For Communications Equipment
MN6153UC
PLL LSI with Built-In Prescaler
Overview
The MN6153UC is a CMOS LSI for a phase-locked
loop (PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (0.5
mW for VDD=1.03 V, F IN= 60 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: V DD=1.0 to 1.4V
Low power consumption: 0.5mW (V DD=V1.03V,
F IN=60MHz)
High-speed operation:
F IN=60MHz
(V DD=1.03V)
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage:
272 to 262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and reference
frequency dividing stages
Pin Assignment
XIN
1
16
OR
XOUT
2
15
OV
FV
3
14
LC
VDD
4
13
FR
DOP
5
12
PS
VSS
6
11
LE
VCP
7
10
DATA
FIN
8
9
(TOP VIEW)
SSOP016-P-0225
CLK
FIN
PS
LE
DATA
CLK
XOUT
XIN
8
12
11
10
9
2
1
Prescaler and
phase matching
Data control
Phase
matching
Swallow
counter
14-bit programmable
counter
18-bit latch
18-bit shift register
17-bit latch
17-bit programmable counter
Control
3
5
7
16
15
14
13
FV
DOP
VCP
OR
OV
LC
FR
MN6153UC
For Communications Equipment
Block Diagram
Phase comparator
For Communications Equipment
MN6153UC
Pin Descriptions
Pin No.
1
Symbol
XIN
Function Description
Crystal oscillator connection pins:
2
XOUT
3
FV
Frequency divider output signal in comparator stage.
4
V DD
Power supply
5
D OP
Low-pass filter connection pin. Use a passive filter.
6
V SS
Ground
7
VCP
Power supply pin for built-in charge pump
8
FIN
Frequency divider input pin in comparator stage.
9
CLK
XIN =Oscillator circuit input pin;
XOUT=Oscillator circuit output pin.
Phase comparator input monitor.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
10
DATA
Shift register data input pin.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
11
LE
Load enable signal input pin.
12
PS
Power save control signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
"H" level input starts the frequency divider and places the chip in operational mode.
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13
FR
Reference frequency divider output signal.
Phase comparator input monitor.
14
LC
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level,
the internal charge pump output is in the high-impedance state, and the loop is
opened.
15
OV
16
OR
Phase comparator output pin for external charge pump.
(OR provides N-channel open drain output.)
MN6153UC
For Communications Equipment
MN6153 Frequency Dividing Data Settings
The following formula shows frequency divider operation.
FIN ={ (16 × N) + A} × (XIN ÷ R)
where
FIN
: VCO output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
XIN
: Reference oscillator frequency
R
: Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB
Test data
3 bits
14 bits
Programmable counter
setting (N)
4 bits
Swallow counter
setting (A)
LSB
For Communications Equipment
MN6153UC
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input
(1) Reference side
Data input direction
Control bits
MSB
LSB
17-bit frequency dividing data
1 bit
1 bit
"L"
Frequencey
Write selection
dividing stage selection "H" level
"H" level
1
2
17
18
19
CLK
DATA
MSB
LSB
LE
(2) Comparating side
Data input direction
Control bits
*1
18-bit frequency dividing data
3-bit test data
3 bits "L" level
1
2
3
4
5
1 bit
1 bit
"L"
Frequencey
Write selection
dividing stage selection "H" level
"L" level
21
22
23
CLK
DATA
MSB
LSB
LE
Notes
1.*1: Preceding the input of the frequency dividing data for the comparating side, input test data consisting of
three "L" level bits to produce normal operation. Never use any other pattern.
2. When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3. When the power is first applied, the data settings are indeterminate. Always write data to the chip before
starting operation.
4. Enter the data to fill the entire latch:
Reference side: 19 bits (17 bits for the frequency divider setting and 2 control bits)
Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2
control bits)
5. Drive the LE pin at "L" level while writing the data.
6. "H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin
are both at "L" level.
7. Writes are possible when the PS pin is either "H" or "L" level.
8. Input the data MSB first.
9. The data are inputted at the rising edge of the CLK signal.
MN6153UC
For Communications Equipment
Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
VDD
Rating
– 0.3 to +3.0
Power supply voltage
VCP
– 0.3 to +4.0
Input pin voltage
VI
VSS – 0.3 to VDD +0.3
Output pin voltage
VO
VSS – 0.3 to VDD +0.3
Power dissipation
PD
20
Operating ambient temperature
Topr
–10 to +60
Storage temperature
Tstg
–55 to +125
Unit
V
mW
˚C
Operating Conditions
VSS=0V, Ta=–10 to +60˚C
Parameter
Power supply voltage
Symbol
VDD
Power supply voltage
VCP
Test Conditions
min
1.0
typ
1.1
max
1.4
Unit
V
2.5
3.0
3.2
V
min
typ
max
Unit
0.5
mA
2.0
µA
Electric Characteristics
VCP=2.5V, Ta=–10 to +60˚C
Parameter
Power supply pin
Symbol
VDD
Power supply current
IDD
Test Conditions
VDD =1.03V
FIN =100MHz, XIN =20MHz,
PS="H"
IDstop
Input Pins
CLK, DATA, LE, PS
PS="L" (at power save operation)
VDD=1.0 to 1.4V
"H" level input voltage
VIH
VDD – 0.2
VDD
"L" level input voltage
VIL
VSS
0.2
Input leakage current
ILI
Input Pin
FIN
±1.0
VIN
Input current
IIF
0.4
Pull-up resistor is present
(PS="L")
Input leakage current
ILIF
FINMAX
VIN =0.4 Vp-p
Minimum operating frequency
FINMIN
VIN =0.4 Vp-p
Vp-p
–100
µA
±20
µA
10
MHz
60
MHz
VDD=1.0 to 1.4V
Input voltage
VIN
Input current
IIX
0.4
Pull-up resistor is present
(PS="L")
Input leakage current
–10
VIN =0 or VDD (PS="H")
Maximum operating frequency
XIN
µA
VDD=1.03 to 1.4V
Input voltage
Input Pin
V
ILIX
VIN=0 or V DD
– 0.2
Vp-p
–1.5
mA
2.0
µA
For Communications Equipment
MN6153UC
Electrical Characteristics (continued)
VCP=2.5V, Ta=–10 to +60˚C
Parameter
Crystal Oscillator Pins
Symbol
Test Conditions
XIN, XOUT VDD=1.03 to 1.4V
Crystal oscillator frequency
fXtal
Output Pins FV, FR, LC, OV
typ
max
12.8
VOH
I OH= –60µA
"L"level output voltage
VOL
I OL=30µA
MHz
VDD– 0.3
VDD
VSS
0.3
VXOH
IXOH= –100µA
VDD– 0.3
VDD
"L"level output voltage
VXOL
I XOL=100µA
VSS
0.3
–250
DOP
V
VDD =1.0 to 1.4V
"H"level output voltage
IDOH
VDop=V CP – 0.3V
"L"level output voltage
IDOL
VDop=0.3V
Output leak current
ILOH
VDop=V CP
2.0
I LOL
VDop=0.0V
–2.0
Output leak current
Output Pin
V
XOUT VDD =1.0 to 1.4V
"H"level output voltage
Output Pin
Unit
VDD=1.0 to 1.4V
"H"level output voltage
Output Pin
min
OR
250
µA
VDD=1.0 to 1.4V
"L"level output voltage
IORL
VOR=0.3V
45
µA
tsul
500
ns
tsu2
500
ns
500
ns
VDD=1.0 to 1.4V
Setup time *1
Hold time *1
tH
Note*1: The following timing chart shows the setup and hold times.
DATA
50%
tsu1
tH
CLK
tsu2
LE
Usage Note
Be particularly careful with this product as it is more sensitive on the static electricity damage than most of
our other products.
VF
*1
Loop filter
0.22µF
10kΩ
VCC
VCO
1µF
35kΩ
100Ω
VDD=1.0V to 1.4V
10µF
390Ω
50 to 60MHz
VCP=3V
Amplifier
VCC=3V
1000pF
0.1µF
0.1µF
8
7
6
5
4
3
2
12pF
12.8MHz
1
12pF
10pF
CLK
DATA
LE
PS
FR
LC
OV
OR
9
10
11
12
13
14
15
16
Frequency dividing
data generation input
Frequency dividing
data generation input
Frequency dividing
data generation input
Intermittent
operation
control
Note *1: VCO characteristics may necessitate
design revisions.
FIN
VCP
VSS
DOP
VDD
FV
XOUT
XIN
MN6153UC
MN6153UC
For Communications Equipment
Application Circuit Example
For Communications Equipment
MN6153UC
Package Dimensions (Unit: mm)
SSOP016-P-0225
6.5±0.2
16
9
+0.10
0.15 -0.05
6.3±0.2
4.3±0.2
1.0±0.1
0.8
0.15
0.35±0.10
1.55±0.30
8
(0.45)
0.1±0.1
1
1.45±0.20
0 to 10°
0.5±0.1
SEATING PLANE