Theory and Applications of the NCP1294, Switching Controller, and Associated Circuits for Lead Acid Battery Charging from a Solar Panel with Maximum Peak Power Tracking (MPPT)

AND8490/D
Theory and Applications of
the NCP1294, Switching
Controller, and Associated
Circuits for Lead Acid
Battery Charging from a
Solar Panel with Maximum
Peak Power Tracking
(MPPT)
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APPLICATION NOTE
Introduction
Background and System Requirements
The following paper describes in detail the principle
operation of the NCP1294, switching controller, and
associated circuits for lead acid battery charging with
MPPT. A design example and test data are included.
The NCP1294 solar controller is a flexible solution used
in Module Level Power Management (MLPM) solutions.
Most of the solar controller battery chargers on the market
today have a large digital content namely to manage
maximum power point tracking and battery charging. The
manipulation of the power stage, MPPT, and battery
management can be controlled with analog circuitry in a cost
effective manner. The solar controller parameters for the
NCP1294 design are listed below in tabular form.
Dusk Dawn
Detection
&
Battery
Discharge
Management
External LED Enable
Solar Panel
and Battery
Enable
Solar
Panel
Reverse
Polarity
Protection
Reverse
Polarity
Protection
Buck
Boost
Stage
Battery
Over Voltage
MPP
Circuit
Battery
Charge
Circuit
Under
Voltage
User Set
Battery
Voltage
Remote
Thermal
Sensor
User Set
Charge
Rate
Figure 1. Block Diagram of ON Semiconductor NCP1294 120W Solar Controller
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 2
1
Publication Order Number:
AND8490/D
AND8490/D
Table 1. ON SEMICONDUCTOR NCP1294 120 W SOLAR CONTROLLER SPECIFICATION
SPECIFICATIONS
Typical Units
Output Current Rating
10 amp maximum (12 V battery controller is limited to 120 W)
Nominal Battery Voltage
12/24/36 VDC
PV Input Voltage
12 V to 60 VDC maximum (Recommended maximum VOC < 50 VDC)
Power Consumption
0.30 W typical standby
Charge Algorithm
3−stage Bulk/Acceptance/Float
Absorption Voltage
14.3 VDC fixed (range 10.0 – 36.0 VDC)
Float Voltage
13.5 VDC fixed (range 10.0 – 36.0 VDC)
Voltage Set Point Limit
17.3 VDC fixed (range 10.0 – 36.0 VDC)
Dusk Dawn Indicator
Positive Logic
Battery Low Indicator
Positive Logic
Temperature Compensation
Optional sensor adjusts charge voltage based on battery temperature
Power Conversion Efficiency
97% Typical 24 V to 14.3 V 8.39 A Output
Physical Configuration and Dimensions
90 mm x 90 mm x 40 mm
Figure 2.
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design should also include safety features such as battery
over voltage detection and solar panel under voltage
detection. The resulting block diagram for the system is
shown below.
The specification described above will be configured in a
block diagram (Figure 1) to aid the design process and
ensure proper understanding of the system. The heart of the
system is the power stage which must accept an input
voltage of 12 V to 60 V and produce an output of 12 V to
36 V. Since the input voltage range spans the required output
voltage, a buck boost topology is required to support the
application. The topologies the designer could choose are
SEPIC, Non Inverting buck boost, flyback, single switch
forward, two switch forward, half bridge, full bridge, or
others not listed. The output power for the converter is 120
W, thus the possibility of a flyback converter is eliminated.
All of the topologies that are suitable for 120 W or greater
have four or more switches and have the added complexity
of a transformer with the exception of a four switch buck
boost. Future work will include isolated topologies as power
demands increase. The output voltage and battery charge
rate should be selectable by the installing technician. The
battery state of charge must be managed by the proper charge
algorithm. Since the controller will be connected to a solar
panel, it must have maximum power point tracking (MPPT)
to provide a high value to the end customer. The controller
should draw no more than 300 mW from either the output or
input while not actively converting so all unnecessary
circuitry should be turned off unless both the battery and the
solar panel are installed. Two positive enable circuits have
to be provided to external circuitry. One circuit detects the
hours of darkness and another detects the state of charge of
the battery so that the external circuit does not discharge the
battery to the point of damage. The controller will be
installed in the field by technicians and novices with varying
degrees of experience, thus it is important to have reverse
polarity protection for both the input and output. Since the
controller and the batteries may be installed in either a hot
or cold location, the controller must accommodate
temperature compensation for charging the battery. The
MPPT Methodology
The power source for the controller specified is a solar
panel. Solar panels have an IV curve that folds over shortly
after the maximum power point where the output voltage
falls as the current is increased beyond the maximum power
point. Unfortunately the IV curves will change with
irradiance, temperature, and age. Irradiance as defined by
[3] is “the density of radiation incident on a given surface
usually expressed in watts per square centimeter or square
meter.” If the solar panel does not have mechanical sun
tracking abilities, the irradiance will change as the sun
moves approximately ±23° over a year. Further, the
irradiance changes daily as the sun moves from horizon to
horizon, resulting in a variation of power output throughout
the day and year.
The output power increases with decreasing temperature
due in large part to the electron and hole mobility of the
semiconductor material. Further, as temperature increases,
the band gap energy of the semiconductor material also
increases. Photons from the sun provide electrons in the
valence band of the semiconductor with the energy to leap
over the band gap into the semiconductor material. The
larger band gap energy means more energy will be required
from the photons in the sun to reach the conduction band. As
a result, fewer electrons will reach the conduction band
resulting in a less efficient solar cell.
To extract the most power out of the variable source, the
solar controller specified must employ MPPT. The MPPT
must first locate the maximum power point and adjust for
environmental conditions in a timely manner to keep the
controller close to the maximum power point.
Figure 3. IV Curve GeneCIS Solar Module 70W WSG0036E070
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Figure 4. Polycrystalline 6” Silicon Cells BP 3220T Temperature Curves [1]
Figure 5. Polycrystalline 6” Silicon Cells BP 3220T Irradiance Curves [1]
VMPP + k * Voc
Many proven methods exist for MPPT for photo voltaic
arrays, but only three will be discussed in this paper for
brevity: Fractional Voc, Hill climber/Perturb and observe,
and dynamic MPPT.
(eq. 1)
The k factor can change with temperature as shown in
Figure 4, it is therefore beneficial to temperature
compensate the fractional Voc circuit so that it is close to the
maximum power point. The advantages to fractional Voc are
that it is simple to implement and can be cost effective. The
drawback is that the method is not good for a wide variety
of solar panels with differing temperature coefficients and
open circuit voltages.
Fractional Open Circuit Voltage or Voc
Fractional Open Circuit Voltage or Voc relies on the linear
relationship between the open circuit voltage of the solar
panel and the maximum power point. The method samples
the voltage of the solar panel when no load is applied and
holds it as a reference for the maximum power point voltage.
Figure 5 shows that the maximum power point is between
71% and 78% [2] of the open circuit voltage or about 3/4.
Therefore, the following equation can be used to calculate
the MPP voltage:
Hill Climber/Perturb and Observe
Hill climber involves incrementing the duty cycle and
calculating the resulting power change, where “perturb and
observe” changes the voltage and observes the power
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change. A PWM converter will be used to control the power
extracted from the solar array which is a power limited
source. Changing the duty cycle also changes the current
draw from the array which in turn decreases the voltage in
a power limited source. The relationship between duty cycle
and voltage is linked so the two concepts will be combined
and explained below. The converter starts by drawing very
small power from the solar panel, the power is calculated,
and the duty cycle is incremented and the power is again
calculated. The previous power calculation is compared to
the current power calculation and depending on the resulting
increase or decrease; the duty cycle is incremented or
decremented respectively as shown in Table 2.
The process continues indefinitely finding the maximum
power point as fast as the algorithm can move. One
drawback to the method is that power is moved from its
current point to another point which may not be the
maximum power point to see if the maximum power point
has changed. The method results in spending half of the time
at the maximum power point, while half of the time remains
at a suboptimal level. If the algorithm is long, this can mean
a significant amount of time is spent not utilizing the
maximum power of a solar panel.
Dynamic MPPT
Dynamic MPPT is applied as a change occurs in the
system. Since the converter is using PWM, a change is
occurring every switching cycle and power drawn from the
solar panel is also changing in an observable way every
cycle. Dynamic MPPT uses the voltage dip on the solar
panel multiplied by the increasing current every switching
cycle to determine the error signal that will be produced to
regulate the duty cycle. The dynamic response detects the
slope of the IV curve, creating a power ramp from which the
error signal intersects creating a power representative duty
cycle. The cycle ends when the ramp changes slope from
positive to negative as shown in Figure 6.
Table 2. HILL CLIMBER DECISION TABLE
Change
Change in Power
Next Change
Positive
Positive
Positive
Positive
Negative
Negative
Negative
Positive
Negative
Negative
Negative
Positive
Solar Panel Voltage
The change in
current is
governed by the
Inductance and
the on time of
the power stage
Error Signal
Error Signal
Duty cycle is
limited by the
power ramp
Solar Panel Current
The ramp is a
multiplication of the
input current and
input voltage. When
the current and
voltage are not at the
MPPT point the slope
is always increasing.
Figure 6. Voltage and Current of a PWM Regulated Converter
soft−start, accurate duty cycle limit control, less than 50 mA
startup current, over and undervoltage protection, and
bidirectional synchronization. [4]
NCP1294 Part Description
The NCP1294 fixed frequency feed forward voltage
mode PWM controller contains all of the features necessary
to be configured in a flyback, boost or forward topology and
can be adapted for use in the buck, buck boost, half bridge,
and full bridge topologies. The PWM controller has been
optimized for high frequency primary side control
operation. In addition, the device includes such features as:
Switch Frequency and Maximum Duty Cycle
Calculations
The frequency of the NCP1294 can be set by using an
oscillator timing capacitor, CT, which is charged by VREF
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input voltage goes up, the rising edge of the ramp signal
increases which reduces duty cycle to counteract the change.
The feed forward feature can also be employed to provide
a volt−second clamp, which limits the maximum product of
input voltage and turn on time. The clamp is used in circuits,
such as forward and flyback converter, to prevent the
transformer from saturating. If the line voltage is much
greater than the FF pin peak voltage, the charge current can
be treated as a constant and is equal to VIN/R. Therefore, the
volt−second value is determined by the following equation:
through RT and discharged by an internal current source.
During the discharge time, the internal clock signal sets the
gate output to the low state, thus providing a user selectable
maximum duty cycle clamp. Charge and discharge times are
determined by following formulas;
ƪ
tc + RT * CT * ln
ƪ
td + RT * CT * ln
tc
td
VPeak
VValley
=
=
=
=
V ref * V Valley
V ref * V Peak
ƫ
V ref * V Peak * IdR T
(eq. 2)
ƫ
V ref * V Valley * IdR T
V IN * T ON + (VCOMP * VFF(d))
charging time
discharging time
peak voltage of the oscillator
valley voltage of the oscillator
VCOMP
VFF(d)
R
C
(eq. 3)
= COMP pin voltage
= FF pin discharge voltage
As shown in the equation, the volt−second clamp is set by
the VCOMP clamp voltage which is equal to 1.8 V. In
forward or flyback circuits, the volt−second clamp value is
designed to prevent transformers from saturation. In a buck
or forward converter, volt−second is equal to:
For the oscillator to function properly, RT has to be greater
than 2.3k.
Feed Forward Voltage Mode Control
In conventional voltage mode control, the ramp signal has
a fixed rising and falling slope. The feedback signal is
derived solely from the output voltage. Consequently,
voltage mode control has inferior line regulation and audio
susceptibility. Feed forward voltage mode control derives
the ramp signal from the input line. Therefore, the ramp of
the slope varies with the input voltage.
At the start of each switch cycle, the capacitor connected
to the FF pin is charged through a resistor connected to the
input voltage. Meanwhile, the gate output is turned on to
drive an external power switching device. When the FF pin
voltage reaches the error amplifier output VCOMP, the
PWM comparator turns off the gate, which in turn opens the
external switch. Simultaneously, the FF capacitor is quickly
discharged to 0.3 V.
Overall, the dynamics of the duty cycle are controlled by
both input and output voltages. For example, an elevated
output voltage reduces VCOMP which in turn causes duty
cycle to decrease. However, if the input voltage varies, the
slope of the ramp signal will react immediately which
provides a much improved line transient response. When the
V IN * T ON +
n
V OUT
Ts
(eq. 4)
n
= transformer turns ratio
The constant, n, is determined by the regulated output
voltage, switching period, and transformer turns ratio (use
1.0 for buck converter). As shown in Equations 3 and 4
during steady state, VCOMP doesn’t change for input
voltage variations, intuitively explaining why FF voltage
mode control has superior line regulation and line transient
response. Knowing the nominal value of VIN and TON, one
can also select the value of RC to place VCOMP at the center
of its dynamic range.
Design Procedure
When selecting a topology for the solar controller, it is
important to understand the converters basic operation and
its limitations. The topology selected is the non−inverting
four switch non−synchronous buck boost topology. The
converter operates with a single control signal from the
NCP1294, which turns on Q1 and Q2 simultaneously
charging L1.
L1
Q1
D2
VSW2
VSW1
D1
Q2
Drive
Figure 7.
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Drive
Drive
VSW 1
VSW 1
VSW 2
VSW 2
Inductor
Current
Inductor
Current
IL2
IL1
IL1
Q1
Q1
Q2
Q2
D1
D1
D2
D2
Figure 8. Buck Boost Operation Time Delayed Left, Ideal Right
DBUCK_BOOST
FSW
T
TOFF
TON
VIN
VOUT
The four switch buck boost topology is show in Figure 8
where a single inductor is used to control the voltage and
current. The four switch non−inverting buck boost has two
modes of operation that will be considered the buck mode
and the buck boost mode. In the buck mode, the converter
produces input voltage pulses that are LC filtered to produce
a lower DC output voltage VOUT. The output voltage can be
changed by modifying the on time relative to the switching
period T or switching frequency. The ratio of high side
switch on time to the switching period is called duty ratio D.
F sw +
D+
D BUCK +
D BUCK_BOOST +
T ON
T
1
T
(1 * D ) +
V OUT
V IN
³ 56.3% +
V OUT
V OUT ) V IN
(eq. 6)
T
13.5 V
24 V
³ 36% +
13.5 V
13.5 V ) 24 V
(eq. 7)
D
DBUCK
Buck boost converter duty cycle
Switching frequency
Switching period
High side switch off time
High side switch on time
Input voltage
Output voltage
The solar controller will operate in buck mode if the
output voltage can be achieved from 1% to 89%. If the
output voltage cannot be reached due to duty cycle
limitations, it will switch to buck boost mode where the
voltage can be achieved. The duty cycle will change from
89% to a lower duty cycle as show in Figure 9. One thing to
note is that when the converters mode switches from buck
to buck boost, the error signal will take time to change the
duty cycle. The instantaneous change of mode will leave a
buck boost converter trying to switch at 89% duty cycle and
trying to slew to 47%; this results in the converter trying to
output 130 V at the trade over region. The NCP1294 is
equipped with a pulse by pulse current limiter and will stop
the converter from building energy in the choke to
dangerous proportions, easing the transition in duty cycle.
(eq. 5)
T OFF
=
=
=
=
=
=
=
= Duty cycle
= Buck converter duty cycle
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Figure 9. Transfer Ratio Between Buck and Boost Mode for Multiple Batteries
Inductor Selection
1*D
11.06 mH +
(eq. 8)
D
=
DBUCK
=
DBUCK_Boost
=
ratio
FSW
=
IOUT
=
=
LOUT_BUCK
LOUT_BUCK_BOOST =
ra
=
= Ripple current
= Output current
= Ripple current ratio
Using the ripple current rule of thumb, the user can
establish acceptable values of inductance for a design using
Equation 9.
L OUT_BUCK +
26.88 mH +
V IN * D BUCK
I OUT
ra
F SW
³
(eq. 9)
24 V * 56%
10 A
25%
I
OUT
200 kHz
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8
ra
BUCK_Boost
³
F SW
24 * 36%
10 A
1*36%
DI
ra +
I out
DI
Iout
ra
V IN * D BUCK_Boost
L OUT_BUCK_BOOST +
When selecting an inductor, the designer may employ a
rule of thumb for the design where the percentage of ripple
current in the inductor should be between 10% and 40%. The
ratio of ripple current to maximum output current is given in
Equation 8.
25%
200 kHz
Duty ratio
Buck converter duty cycle ratio
Buck boost converter duty cycle
Switching frequency
Output current
Buck output inductance
Buck boost output inductance
Ripple current ratio
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3 Batteries
2 Batteries
15 μH
1 Battery
Figure 10. Inductance vs. Current Ripple Ratio
If an inductance of 22 mH is chosen and the converter
charges 1 to 3 batteries, the ripple current requirement is
satisfied in the buck boost mode; however in the buck mode,
the ripple requirement is only met for the case of one battery.
The chart below shows the resulting ripple current from the
selection of 22 mH.
Figure 11. Calculated Ripple Current Ratio with 22 H
When selecting an inductor, the designer must not exceed
the current rating of the part. To keep within the bounds of
the part’s maximum rating, a calculation of the RMS current
and peak current are required.
I DC_Buck + I OUT
10.011 A + 10 A
Ǹ1
ra 2
³
12
Ǹ1 ) 30%
12
I DC_Buck_Boost +
15.63 A +
DBUCK_Boost
IOUT
IDC_Buck
(eq. 10)
2
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I OUT
1 * D BUCK_Boost
³
10 A
1 * 36%
= Buck boost converter duty cycle ratio
= Output current
= Buck converter inductor RMS current
AND8490/D
IDC_Buck _Boost
ra
= Buck boost converter inductor RMS
current
= Ripple current ratio
I PK_BUCK + I OUT
11.55 A + 10 A
I PK_BUCK_Boost +
18.05 A +
DBUCK_Boost
IOUT
IPK_BUCK
IPK_BUCK_Boost
ǒ1 ) raǓ ³
2
ra
(eq. 11)
ǒ1 ) 31%Ǔ
=
=
=
=
Buck boost converter duty cycle ratio
Output current
Buck converter inductor peak current
Buck boost converter inductor peak
current
= Ripple current ratio
2
I OUT
1 * D BUCK_Boost
10
1 * 36%
ǒ1 ) raǓ ³
2
ǒ1 ) 31%Ǔ
2
Figure 12. Calculated DC Current in Inductor for Buck Mode and Buck Boost Mode
Figure 13. Calculated Peak Current in the Inductor for Buck and Buck Boost Mode
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LP tot + LP CU_DC ) LP CU_AC ) LP Core ³
A standard inductor should be found so the inductor will
be rounded to 15 mH. The inductor should support an RMS
current of 20.5 A and a peak current of 22 A. A good design
practice is to select an inductor that has a saturation current
that exceeds the maximum current limit with some margin.
The final selection of an output inductor has both
mechanical and electrical considerations. From a
mechanical perspective, smaller inductor values generally
correspond to smaller physical size. Since the inductor is
often one of the largest components in the regulation system,
a minimum inductor value is particularly important in space
constrained applications. Consequently, output capacitors
must supply the load current until the inductor current
reaches the output load current level. The peak−to−peak
ripple current for NCP1294 is given by the following
equation:
I pp +
V OUT
L OUT
(1 * D )
F SW
D
FSW
Ipp
LOUT
VOUT
=
=
=
=
=
³ 1.02 A +
13.5 V
22 mH
285 mW + 260 mW ) 1 mW ) 24 mW
LPCore
LPCU_AC
LPCU_DC
LPtot
The important factors to consider when selecting an
output capacitor are DC voltage rating, ripple current rating,
output ripple voltage requirements, and transient response
requirements.
The output capacitor must be able to operate properly for
the lifetime of a product. When selecting a capacitor, it is
important to select a voltage rating that is derated to the
guaranteed operating lifetime of a product. Further, it is
important to note that when using ceramic capacitors, the
capacitance decreases as the voltage applied increases; thus
a ceramic capacitor rated at 22 mF 25 V may measure 4.4 mF
with an applied voltage of 13.5 V depending on the type of
capacitor selected. The output capacitor must be rated to
handle the ripple current at full load with proper derating.
Since the load is a battery, the question may arise, isn’t a
battery just like a capacitor? The lead acid battery which is
the load is modeled as a voltage source in series with an RC
network as shown in Figure 14.
(1 * 56%)
200 kHz
(eq. 12)
From Equation 12, it is clear that the ripple current
increases as LOUT decreases, emphasizing the trade−off
between dynamic response and ripple current. The power
dissipation of an inductor falls into two categories: copper
and core losses. Copper losses can be further categorized
into DC losses and AC losses. A good first order
approximation of the inductor losses can be made using the
DC resistance as shown below:
260 mW + 10 2
DCR ³
2
635.2 mW + 15.63 2
DCR
IDC_BUCK
IDC_BUCK Boost
LPCU_DCB
LPCU_DCBB
CF = 1nF
R 10mW
Ro = 20mW
(eq. 13)
2.6 mW
LP CU_DCB + I DC_BUCK_Boost
2
Inductor core power dissipation
Inductor AC power dissipation
Inductor DC power dissipation
Total inductor losses
Output Capacitor Selection
Duty ratio
Switching frequency
Peak−to−peak current of the inductor
Output inductance
Output voltage
LP CU_DCB + I DC_BUCK
=
=
=
=
(eq. 14)
DCR ³
2.6 mW
Figure 14. Thevenin Equivalent Battery Model for
Lead Acid Battery
= Inductor DC resistance
= Buck regulator inductor DC current
= Buck boost regulator inductor DC
current
= Buck inductor DC power dissipation
= Buck boost inductor DC power
dissipation
The series resistance is very low to begin with; therefore
the majority of the pulsed current will go to the battery. The
only time the capacitor is needed is when the current flow
from the battery decreases towards the end of the absorption
stage and in the float stage. Thus a small maintaining
capacitance is needed, but ripple voltage and noise are of
small concern for this type of battery.
The capacitor RMS ratings given in datasheets are
generally for lower switching frequency than used in switch
mode power supplies, but a multiplier is given for higher
The core losses and AC copper losses will depend on the
geometry of the selected core, core material, and wire used.
Most vendors will provide the appropriate information to
make accurate calculations of the power dissipation at which
point the total inductor losses can be captured by the
equation below:
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frequency operation. The RMS current for the output
capacitor can be calculated below:
CO RMS_BUCK + I OUT
CINESR
IinRMS
PCIN
ra
31%
³ 0.294 A + 10 A
Ǹ12
Ǹ12
(eq. 15)
Ǹ
CO RMS−BUCK−Boost + I OUT
11.54 A + 10
CoRMS_BUCK
CoRMS_BUCK_Boost
DBUCK_Boost
IOUT
ra
Ǹ
Due to large di/dt through the input capacitors, electrolytic
or ceramics should be used. If a tantalum capacitor must be
used, it must be surge protected, otherwise capacitor failure
could occur.
2
D BUCK_Boost ) ra12
1 * D BUCK_Boost
56% ) 56%
12
³
Power MOSFET Dissipation
2
Power dissipation, package size, and the thermal
environment drive power supply design. Once the
dissipation is known, the thermal impedance can be
calculated to prevent the specified maximum junction
temperatures from being exceeded at the highest ambient
temperature. Power dissipation has two primary
contributors: conduction losses and switching losses. The
high−side MOSFET will display both switching and
conduction losses. The switching losses of the low side
MOSFET will not be calculated as it switches into nearly
zero voltage and the losses are insignificant. However, the
body diode in the low−side MOSFET will suffer diode
losses during the non−overlap time of the gate drivers.
Starting with the high−side buck and boost MOSFET, the
power dissipation can be approximated from the following
equation:
1 * 56%
= Buck converter output capacitor
RMS current
= Buck boost converter output
capacitor RMS current
= Buck boost converter duty cycle
ratio
= Output current
= Ripple current ratio
Input Capacitor Selection
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize losses and input voltage
ripple. The RMS value of the input ripple current is:
ǸDBuck
Iin RMS_Buck + I OUT
1.34 A + 4.96 A
Iin RMS_Buck_Boost +
Ǹ
P D_HS + P COND ) P SW_TOT
PCOND
PD_HS
(eq. 16)
(1 * 56%)
PSW_TOT
I OUT
1 * D Buck_Boost
D Buck_Boost
11.61 A +
ǒ1 * D BUCKǓ ³
Ǹ56%
10
1 * 56%
ƪ1 * D
Buck_Boost )
Ǹ
56%
ƫ
ra 2
³
12
ƪ1 * 56% ) 56%
ƫ
12
I RMS_BUCK_Boost +
2
DBUCK
=
DBUCK_Boost
=
ra
=
IOUT
=
IRMS_BUCK
=
IRMS_BUCK_Boost =
246 mW + 10 mW
ǒ4.96 AǓ
2
I OUT
1*D
Ǹ
ǒ1 ) ra12 Ǔ
2
D
Ǹ
D
(eq. 19)
ǒ1 ) ra12 Ǔ
2
Buck duty ratio
Buck boost duty ratio
Ripple current ratio
Output current
Buck high side MOSFET RMS current
Buck boost high side MOSFET RMS
current
The first term in Equation 18 is the conduction loss of the
high−side MOSFET while it is on. Since the low side
MOSFET is on at the same time as the boost MOSFET the
conduction loss can be approximated the same.
The equation reaches its maximum value with D = 0.5 at
which point the input capacitance RMS current is half the
output current. Loss in the input capacitors can be calculated
with the following equation:
ǒIin RMSǓ
= Conduction losses
= Power losses in the high side
MOSFET
= Total switching losses
I RMS_BUCK + I OUT
Duty ratio
Buck regulator duty cycle ratio
Buck boost regulator duty cycle ratio
Buck input capacitance RMS current
Buck boost input capacitance RMS
current
= Load current
P CIN + CIN ESR
(eq. 18)
Using the ra term from Equation 8, IRMS becomes:
D
=
DBuck
=
DBuck_Boost
=
IinRMS_Buck
=
IinRMS_Buck_Boost=
IOUT
= Input capacitance Equivalent Series
Resistance
= Input capacitance RMS current
= Power loss in the input capacitor
³
(eq. 17)
2
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12
AND8490/D
P COND_BUCK + ǒI RMS_HS_BUCKǓ
2
R DS(on)
Vth
(eq. 20)
P RMS_BUCK_Boost + ǒI RMS_HS_BUCK_BoostǓ
2
R DS(on)
IRMS_HS_BUCK
= Buck RMS current in the high side
MOSFET
IRMS_HS_BUCK_Boost = Buck boost RMS current in the
high side MOSFET
PCOND_BUCK
= Buck conduction power losses
PCOND_BUCK_Boost = Buck boost conduction power
losses
RDS(ON)
= On resistance of the high side
MOSFET
The second term from Equation 18 is the total switching
loss and can be approximated from the following equations.
P SW_TOT + P SW ) P DS ) P RR
PDS
Figure 15. High Side MOSFET Total Charge
(eq. 21)
t RISE +
= High side MOSFET drain to source
losses
= High side MOSFET reverse recovery
losses
= High side MOSFET switching losses
= High side MOSFET total switching
losses
PRR
PSW
PSW_TOT
ǒI OUT
(eq. 22)
P SW_BUCK_Boost + P TON ) P TOFF +
ǒ
I OUT
1*D
FSW
IOUT
PSW_BUCK
PSW_BUCK_Boost
PTON
PTOFF
tFALL
tRISE
VIN
V IN
Ǔ
F SW
t FALL +
IG12
1
2
QGD
RG
RHSPD
tFALL
VBST
VTH
ǒtRISE ) t FALLǓ
= Switching frequency
= Load current
= Buck high side MOSFET switching
losses
= Buck boost high side MOSFET
switching losses
= Turn on power losses
= Turn off power losses
= MOSFET fall time
= MOSFET rise time
= Input voltage
Q GD
ǒV BST * V THǓńǒR HSPU ) R GǓ
(eq. 23)
= Output current from the high−side gate
drive
= MOSFET gate to drain gate charge
= Drive pull up resistance
= MOSFET gate resistance
= MOSFET rise time
= Boost voltage
= MOSFET gate threshold voltage
QGD
RHSPU
RG
tRISE
VBST
VTH
F SWǓ
V IN
I G1
+
IG1
The first term for total switching losses from Equation 21
are the losses associated with turning the high−side
MOSFET on and off and the corresponding overlap in drain
voltage and current.
1
P SW_BUCK + P TON ) P TOFF +
2
ǒt RISE ) tFALLǓ
Q GD
Q GD
I G2
+
Q GD
ǒVBST * V THǓńǒR HSPD ) R GǓ
(eq. 24)
= Output current from the low−side gate
drive
= MOSFET gate to drain gate charge
= MOSFET gate resistance
= Drive pull down resistance
= MOSFET fall time
= Boost voltage
= MOSFET gate threshold voltage
Next, the MOSFET output capacitance losses are caused
by both the high−side and low−side MOSFETs, but are
dissipated only in the high−side MOSFET.
P DS +
COSS
FSW
PDS
When calculating the rise time and fall time of the high
side MOSFET it is important to know the charge
characteristic shown in Figure 15.
VIN
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13
1
@ C OSS
2
V IN
2
F SW
(eq. 25)
= MOSFET output capacitance at 0 V
= Switching frequency
= MOSFET drain to source charge
losses
= Input voltage
AND8490/D
Finally, the loss due to the reverse recovery time of the
body diode in the low−side MOSFET is calculated as
follows:
P RR + Q RR @ V IN @ F SW
FSW
PRR
NOLLH
(eq. 26)
= Switching frequency
= High side MOSFET reverse recovery
losses
= Reverse recovery charge
= Input voltage
QRR
VIN
PBODY
VFD
Compensation Network
To create a stable power supply, the compensation
network around the error amplifier must be used in
conjunction with the PWM generator and the power stage.
Since the power stage design criteria is set by the
application, the compensation network must correct the
overall output to ensure stability. The NCP1294 is a voltage
mode voltage feed forward part and as such there exists a
voltage loop with an input voltage modified ramp. The
output inductor and capacitor of the power stage form a
double pole and the loop must compensate for that.
The ESR of the output capacitor creates a “zero” at the
frequency as shown in Equation 31:
The NCP1294 demonstration board is setup to use either
a non synchronous or synchronous buck stage depending on
the user’s needs. If a synchronous buck is required, the
calculations and explanation for the dissipation are as
follows. The low−side MOSFET turns on into small
negative voltages so switching losses are negligible. The
low−side MOSFET’s power dissipation only consists of
conduction loss due to RDS(on) and body diode loss during
non−overlap periods. If a non synchronous design is used P
conduction goes to zero and PBODY becomes PDIODE.
P D_LS + P COND ) P BODY
PBODY
PCOND
PD_LS
(eq. 27)
FZ ESR +
= Low side MOSFET body diode losses
= Low side MOSFET conduction losses
= Low side MOSFET losses
IRMS_LS
RDS(ON)_LS
PCOND
(eq. 28)
R DS(on)_LS
=
=
=
=
Ǹǒ
1 * D BUCKǓ
ǒ1 ) ra12 Ǔ
2
F SW
(eq. 29)
2p
640 mF
0.010 mW
1
ǸLOUT
2p
³
Ǹ22 mH
2p
FZ P_BUCK +
2p
= Switching frequency
= Load current
= Dead time between the high−side
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14
ǸLOUT
2p
1 * 47%
COUT
DBUCK_Boost
FP_BUCK
FP_BUCK_Boost
LOUT
(eq. 32)
640 mF
1 * D BUCK_Boost
590 Hz +
ǒNOLLH ) NOLHLǓ
³
C OUT
1
1.34 kHz +
(eq. 30)
FSW
IOUT
NOLHL
(eq. 31)
= Output capacitor ESR
= Output capacitor
= Output capacitor zero ESR frequency
FZ P_BUCK +
Buck duty ratio
Load current
RMS current in the low side
Ripple current ratio
I OUT
³
The frequency of the double pole varies for both a buck
and a buck boost, they can be calculated as shown below:
The body diode losses can be approximated as:
P BODY + V FD
C OUT
1
COESR
COUT
FZESR
= RMS current in the low side
= Low−side MOSFET on resistance
= High side MOSFET conduction losses
I RMS_LS + I OUT @
DBUCK
IOUT
IRMS_LS
ra
2
1
CO ESR
2p
24.87 kHz +
Conduction loss in the low−side MOSFET is calculated as
follows:
P COND + ǒI RMS_LSǓ
MOSFET turning off and the low−side
MOSFET turning on
= Dead time between the low−side
MOSFET turning off and the
high−side MOSFET turning on
= Low−side MOSFET body diode losses
= Body diode forward voltage drop
Ǹ22 mH
=
=
=
=
=
³
³
C OUT
640 mF
³
Output capacitor
Buck boost duty ratio
Buck double pole frequency
Buck boost double pole frequency
Output inductance
AND8490/D
Figure 16. Pole Frequency vs. Input Voltage and Mode
The key is to compensating a combination buck and buck
boost converter is to know where the RHPZ is and how it
changes with load as is defined by the equation above. The
RHPZ is at its lowest point when the load is the highest, for
this application that occurs with one battery and when the
output voltage is at its lowest, as it is a squared term. The
input voltage at its highest voltage will also yield the lowest
RHPZ as shown in the figure below. Note that when the
converter switches to buck mode, RHPZ does not exist, thus
in the figure, buck mode is shown as 1 MHz RHPZ although
it is understood that it does not exist.
The right half plane zero for the buck boost converter can
be calculated with the following equation.
FZ RHPZ_BUCK_Boost +
12.5 kHz +
V IN 2
2p
ǒVOUT ) VINǓ
³
L OUT
(eq. 33)
24 V 2
2p
ǒ13.5 V ) 24Ǔ
FRHPZ_BUCK_Boost
IOUT
LOUT
VIN
VOUT
=
=
=
=
=
I OUT
22 mH
8.89 A
Right half plane zero
Output current
Output inductance
Input Voltage
Output Voltage
Figure 17. Right Half Plane Zero Frequency
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15
AND8490/D
The three equations above define the bode plot that the
power stage has created or open loop response of the system.
The next step is to close the loop by considering the feedback
values. The closed loop crossover frequency should be less
than 1/10 of the switching frequency. The designer must
balance a high crossover frequency with crossing over a
decade before the RHPZ, thus the designer must determine
which frequency is lower. In this application the lowest
RHPZ is at 6.721 kHz, therefore the crossover frequency
will be set to 1.5 kHz. Figure 18 shows type III error
amplifier compensation to make the loop stable. Only the
type III compensation is shown as type II and type I are a
subset.
CP
The relationship between the resistor divider network
above and the output voltage is shown in Equation 34:
(eq. 34)
V OUT * V REF
=
=
=
=
Top resistor divider
Bottom resistor divider
Output voltage
Regulator reference voltage
The most frequently used output voltages and their
associated standard R1 and R2 values are listed in Table 3.
Table 3. OUTPUT VOLTAGE SETTINGS
VOUT
RC
CC
Ǔ
V REF
R1
R2
VOUT
VREF
VOUT(V)
R1(kW)
R2(kW)
13.5
100
10.2
27
100
4.87
40.5
100
3.24
CF
R1
RF
The compensation components for the Type III error
amplifier can be calculated using the method described
below. The method serves to provide a good starting place
for compensation of a power supply. The values can be
adjusted in real time using the compensation tool CompCalc
for the buck portion of the converter but must be checked in
the application
http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP
The integrator for the operation amplifier is set as follows.
The designer should set the voltage feed forward resistor to
the same value as R1 so that the two values cancel out:
FB
COMP
ǒ
R2 + R1
EA
R2
VREF
Figure 18. Type III Error Amplifier Configuration
The compensation network consists of the internal error
amplifier and the impedance networks. The compensation
network has to provide a closed loop transfer function with
the highest 0 dB crossing frequency to have fast response
and the highest gain in DC conditions to minimize load
regulation issues. A stable control loop has a gain crossing
with −20 dB/decade slope and a phase margin greater than
45°. Include worst−case component variations when
determining phase margin. To start the design, a resistor
value should be chosen for R1 from which all other
components can be chosen. A good starting value is 100 kW.
The NCP1294 allows the output of the DC−DC regulator
to be adjusted down to 1.263 V via an external resistor
divider network. The regulator will maintain 1.263 V at the
feedback pin. Thus, if a resistor divider circuit was placed
across the feedback pin to VOUT, the regulator will regulate
the output voltage proportional to the resistor divider
network in order to maintain 1.263 V at the FB pin.
C1 +
V IN
2p * Vramp * Fcross
³
V IN * R * C * F sw
2p * V IN * D * Fcross * R1
³
(eq. 35)
R * C * F sw
2p * D * Fcross * R1
41.2 nF +
C
C1
D
FSW
Fcross
R
R1
VIN
Vramp
100 kW * 1.5 nF * 200 kHz
2p * 89% * 1.3 kHz * 100 kW
=
=
=
=
=
=
=
=
=
Feed forward capacitor
Compensation capacitor
Maximum duty cycle of the converter
Switching frequency
Crossover frequency
Feed forward resistor
Upper resistor divider
Input Voltage
Ramp Voltage
The pole frequency for C1 and R1 should now be
calculated.
FPO +
38.56 Hz +
Figure 19. Feedback Resistor Divider
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16
1
2p * C1 * R1
1
2p * 41.26 nF * 100 kW
(eq. 36)
AND8490/D
C1
FPO
R1
System Turn On and Battery Current Draw
= Compensation capacitor
= Pole frequency
= Upper resistor divider
The system being created is connected to two finite
sources that will supply power to the load at different times
of the day and will more than likely not work at the same
time except for brief periods. The system is not complete
without both the battery and the solar panel installed
therefore, detection of the presence of the battery load and
the solar panel source are advantageous. For instance it
would not be good to dissipate solar panel energy in
providing battery voltage if no battery is connected. If a solar
panel is connected, the battery would be drained looking for
a solar panel to be connected. A simple solution for checking
that both the solar panel is connected and the battery is
connected is a low current draw comparator. Q1 serves as the
comparator and checks to determine if there is a voltage
greater than the base−emitter saturation voltage. If the
resistor divided solar panel voltage is greater than the
VBE(sat) of the NPN transistor, then Q1 becomes saturated
and opens Q2, allowing voltage into power the other
circuits. If a battery is not provided, none of the circuitry
turns on. If a battery is detected and no solar panel is
installed, Q2 remains off as does the circuitry. The solar
panel detection circuit should be set low so it does not
interfere with the operation of the MPPT.
The zero should be placed at the double pole of the plant.
ǒ
2.175 nF +
1
*
³
1
24.87 kHz
(eq. 37)
Ǔ
= Compensation capacitor
= Double pole frequency of buck boost
converter
= ESR frequency
= Upper resistor divider
FZESR
R1
FPO
F P_BUCK_Boost
FP_BUCK
³ 5.425 kW + 100 kW
38.567 Hz
710.9 Hz
(eq. 38)
= Double pole frequency of buck
converter
= Double pole frequency of buck boost
converter
FP_BUCK_Boost
FPO
R1
R2
C3 +
ǒ
1
2p * 100 kW 20 Hz
C2
FP_BUCK_Boost
R2 + R1
Ǔ
1
1
1
*
4pR1 FP _BUCK FZ ESR
C2 +
= Pole frequency of R1 and C1
= Upper resistor divider
= Resistor
2p
Solar
Panel Battery
Voltage Voltage
Q2
Circuit
Power
1
(R2 * Fcross * R1 * FPO)
49.796 nF +
2p
C3
Fcross
FPO
R1
R2
ON
(eq. 39)
1
ǒ5.425 kW * 1.3 kHz * 100 kW * 38.567 HzǓ
=
=
=
=
=
Q1
Compensation pole capacitor
Crossover frequency
Pole frequency of R1 and C1
Upper resistor divider
Resistor
Figure 20. Dual Solar Panel Battery Detection Circuit
If the ESR frequency is greater than the switching
frequency, a CF compensation capacitor may be needed for
stability as the output LC filter is considered high Q and thus
will not give the phase boost at the crossover frequency.
R3 +
2.943 kW +
R1 * F BUCK_Boost
FZ ESR * F P_BUCK_Boost
100 kW * 710 Hz
³
(eq. 40)
24.87 kHz * 710 Hz
CP
Fcross
FP_BUCK_Boost
FZESR
The circuit power comes directly from the output battery
and the intention of system is to be easily adaptable to a
single battery 12 V, dual battery 24 V, or triple battery 36 V
system. Therefore it is necessary to provide a dependable
voltage to the measurement and switching circuitry. In this
application the MC78L08 is used and will provide a steady
8 V supply while handling as much as 40 V.
= Compensation pole capacitor
= Cross over frequency
= Double pole frequency of buck boost
converter
= ESR frequency
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17
AND8490/D
voltage is greater than 2.5 V, D2 pulls down on R3 and Q1
is turned off, pulling up on the LED enable signal. Further,
the circuit in the figure below is linked to the battery and
solar panel detection circuit. The ON node connection
detects daylight and disables the LED string to prevent
operation of the LEDs while the solar panel is charging the
batteries.
Regulated
Circuit
Votlage
Circuit
Power
LDO
Battery
Voltage
Figure 21. LDO Circuit
The system charges batteries during the day time and
discharges them during the night to illuminate a defined
space. The input energy is not guaranteed, but the output
energy remains constant over a long period of time. If a
system is not sized properly, the discharge of the battery can
result in damage. To stop the battery from being damaged,
the LED circuit must be inhibited from operation if the
battery is depleted. The circuit below uses a TL431 to
monitor the battery voltage and provides an enable disable
signal to the LEDs when the battery is below the cutoff
voltage. If the R1 and R2 battery divided voltage is less than
2.5 V, D1 does not pull down on R3. R3 provides greater
than the MOSFET threshold voltage to Q1 giving the LED
a disable signal. Conversely, if the R1 and R2 battery divided
R6
R1
D2
R3
ON
R4
Q1
D1
R5
R2
LED
Enable/Disable
Signal
Figure 22. Battery Discharge and Daylight Detection
Circuit
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18
AND8490/D
Input and Output Current Measurements
and out of the charger. The simplest method of current sense
is low side sensing where the current running in the return
path is sensed by an amplifier as shown in Figure 23.
To implement battery charging and MPPT it is important
to sense the input output currents to control the power into
Battery
Drive
Solar
Panel
Current
Sense
Resistor
Return
Current
−
Amplified Voltage
+
Sense
Amplifier
Figure 23. Low Side Amplifier Current Sensing
The issue with low side sensing is that the solar controller
being produced may be configured in a system with many
other solar controllers and the installer may want to employ
central grounding which will defeat the current sense
employed by diverting the current from the sense resistor in
part or in full. The current sensed by the amplifier then
becomes small in comparison with the actual current being
drawn from the device. While low side current sense is easy
to implement and can be executed inexpensively, it may not
provide a positive user experience as the controller will
cease to function properly when installed by different users.
Figure 24 shows central grounding and how it can affect the
sensed current in low side sensing.
Battery
Drive
Solar
Panel
Current
Sense
Resistor
10mW
Return
Current
1
Return
Current
2
Central
Grounding
Point1mW
Figure 24. Central Grounding Diagram
Implementing high side current sensing allows common
point grounding as the ground path current does not affect
this sensing. Unfortunately the operation amplifier chosen
must have a wide common mode input range. The amplifier
chosen must work at high input voltages and the complexity
of the circuit increases.
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19
AND8490/D
VREF
Sense
Amplifiers
R2 = 10k
+
Amplified Voltage
−
R4 = 10k
R1 = 1k
R3 = 1k
Current
Sense
Resistor
Battery
Drive
Solar
Panel
Figure 25. Amplifier High Side Current Sensing
multiple of 2 of the base current. The next current mirror
considered is the Wilson current mirror, which has relatively
good current parity. The only problem with the Wilson
current mirror is that the number of transistors doubles from
4 to 8, making it unattractive from a cost and circuit
management perspective.
Since the primary aim of the system is making a cost
effective solution, the designer should aim to implement the
solution minimizing current consumption and maximizing
accuracy. One cost effective way to sense high side current
is to use current mirrors to mirror the voltage to ground level.
The simplest current mirror to use is a Windlar, which is
handicapped by the Early effect and the current differs by a
B
Current
Flow
IN
A
Current
Flow
IN
R1= 499 W
R2= 4.9 kW
R1= 499 W
IOUT
IOUT
Current
Sense
Resistor
Current
Sense
Resistor
R3= 4.9 kW
R2= 4.9 kW
R3= 4.9 kW
Figure 26. Left: Windlar High Side Current Sense, Right: Wilson High Current Sense
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20
AND8490/D
Figure 27. Simulated Accuracy of the Windlar Current Sense
Figure 28. Simulated Accuracy of the Wilson Current Sense
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21
AND8490/D
Figure 29. Temperature Error of Windlar and Wilson Current Senses
With the error introduced by the Windlar current sense, it
may first appear that this current sense is not useful, but if a
relative current level is desired, the circuit may still be
useful. For most MPPT algorithms the maxima of a voltage
multiplied by a current is desired. If the current
measurement changes with voltage, the maximum is found
but perhaps not the optimal maximum depending on how the
algorithm is setup. While not the best solution, it may be
good enough for the cost target. If a small output voltage
range is considered, such as the one to a single battery which
varies from 10 V to 15 V, the variation of the Windlar may
be fine but the designer must decide if cost or precision is
more important. The designer must also consider the speed
at which the answer is required. The Wilson current mirror
while accurate had a delay from 500 ns to 2 ms depending on
bias currents where the Windlar had less than 200 ns.
VREF = 3.3V
R1 = 130k
Current limit
100mV = 1A
200mV = 2A
300mV = 3A
400mV = 4A
500mV = 5A
600mV = 6A
700mV = 7A
800mV = 8A
900mV = 9A
1V = 10A
SW1
R2 = 10.7k
R3 = 18.7k
SW2
R4 = 28k
SW3
Figure 30. Output Charge Rate Programming
Input and Output Current Balancing
When building an ideal solar controller, the controller
should protect the batteries or load while extracting the
maximum energy from the solar panels. Unfortunately in the
real world a customer or installer may purchase a large solar
panel and a small battery. If the solar controller were to
charge at the peak power, the battery would charge too fast
and the lifetime of the battery would degrade or an explosion
could occur. What the controller should do is to manage the
needs of the battery and balance them with the peak power
supplied from the solar panel. Thus a maximum battery
charge rate programming as well as a voting scheme is
needed to determine what is limiting the current out of the
system. The programming of the current is accomplished via
a 3.3 V reference provided by the NCP1294 and a resistor
divider network. The shorting of one or multiple headers
will result in a different current limit shown below where
100 mV is 1 A.
1
Short
0
s2
s3
Programmed Current
1
1
1
0.00
0
1
1
2.51
1
0
1
4.15
1
1
0
5.85
0
0
1
6.09
0
1
0
7.57
1
0
0
8.72
0
0
0
10.11
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22
Open
s1
AND8490/D
The user programmed set current is compared to the
measured output current of the system and an error signal is
produced. The error signal results in the voltage level set of
the pulse by pulse current limiter. Likewise, the MPPT finds
the maximum power point and sets the pulse by pulse current
limiter for achieving the maximum power point. The lowest
current set point should govern the system and the two
signals will fight for dominance. If the two designs are
merged into series regulators they can coexist. If a regulator
is not able to achieve its intended higher current, it will keep
opening the pass MOSFET until it is fully on and the other
MOSFET will regulate the current.
VREF = 3.3V
VREF = 3.3V
Output
Current
Amplifier
Output
Current
Amplifier
MPPT Current Limit
+
+
Battery Current Limit
−
−
Pulse by Pulse
Current Limit Set
Output Current
Pulse by Pulse
Current Limit Set
Output Current
VREF = 3.3V
Output
Current
Amplifier
+
Battery Current Limit
−
Output
Current
Amplifier
MPPT Current Limit
Output Current
+
−
Pulse by Pulse
Current Limit Set
Output Current
Figure 31. Voting Scheme
Solar Panel Connection Transients
The operation of the circuit is shown graphically below
where the maximum charge rate of the battery is set below
the MPPT of the solar panel and the system tradeoff between
charging at the maximum battery charge rate and the
maximum power point is achieved.
When connecting a solar panel to a solar controller, load
voltage transient can occur and a designer must take action
to protect the power supply from large transients. The
voltage transients shown below for the panel described are
about 14% above Voc.
Current
Maximum
Power
Point
Current
Limit Set
Battery
Maximum
Charging
Rate
Output
Current
Time
Figure 32. Battery Charging Between MPPT and
Maximum Charge Rate
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23
AND8490/D
Figure 33. Crystal Solar Panel Connection to a 10 kW Resistive Load Positive Terminal Connected Last
Voltage transients can be minimized in some of the
following ways: suppression, filtering, or tolerating. If the
designer chooses to suppress the transients, the power
dissipated to suppress the transient must be calculated. The
inductance of the connection wires can be calculated for a
pair of wires as long d > 5*a using the following equation:
L+
mO * l
4p
ǒ
H
3.95 mH +
4p * 10 −7 m * 9m
a
d
l
L
mo
4p
=
=
=
=
=
ǒd *a aǓǓ
* 1 ) 4 * ln
ǒ
* 1 ) 4 * ln
ǒ
(eq. 41)
ǓǓ
7.5 mm * 1.5 mm
1.5 mm
Wire radius
Wire (center) distance
Length of wire
Wire inductance
4px10−7
Figure 34. Short Circuit Response of the Wurth Solar
panel
The proper part can be selected by looking at the pulse
rating curve for the voltage suppressor. An example pulse
rating curve is shown in Figure 35.
The energy delivered to the load from the wire inductance
is 1/2LI^2. The current delivered to the load will be at
maximum short circuit current or Isc. From the scope
capture shown in Figure 34, the transients do not last longer
than 1 ms, thus the power dissipation needed for the transient
voltage suppressor can be calculated as shown below:
E+
1
2
E
Isc
L
TRTime
* L * Isc 2
TR Time
³ 34.8 W +
=
=
=
=
1
* 3.95
2
2
mH * ǒ4 AǓ
(eq. 42)
1 ms
Energy
Short circuit current
Wire inductance
Transient rise time
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24
AND8490/D
=
=
=
=
LFilter
R1
R2
VSpike
S
Input inductance
DCR of the input inductor
Load resistance
Resulting line spike
LFilter
V1
R1
Figure 36. Simplified Input Diagram
If a reasonable filter is chosen where the inductance is
1 mH, capacitance is 10 mF, R1 is 1 mW and R2 is 1 MW the
time base result of the filter can be calculated as shown in
Figure 37.
The amplitude of the voltage spike can be estimated by
using v = l*di/dt. Assuming the inductance calculated above
and the current is Isc, the remaining value to be obtained is
the dt. The rise time of the current will vary with the
technology, irradiance, and temperature of the solar panel
and the wire inductance, but the reaction time of the Wurth
solar panel with nine meters of wire connected is shown in
Figure 34 and is less than 2 ms.
3.95 mH * 4.2 A * 0 A
L * DI
³ 8.3 V +
Dt
2 ms
V Spike +
DI
L
Dt
VSpike
=
=
=
=
10
1
V2( t ) 0.1
(eq. 43)
Change in current
Wire inductance
Time
Resulting line spike
0.01
3
1.10
0
Since the transients seen on the input are short in duration,
a filter can be used to reduce the amplitude of the voltage that
the rest of the system will see. The worst case scenario is that
the input system is charged up to the open circuit voltage of
the solar panel with no load applied when the transient
pulses are applied. According to [6] the voltage the system
will be subjected to can be approximated by using the
diagram shown in Figure 36 and equations below.
a+
1 R1
1
*
)
2 L Filter R2 * C Filter
b+
Ǹ
R1 ) R2
R2 * L Filter * C Filter
V2(t) +
a
CFilter
(eq. 44)
1*
b * ǸL Filter * C Filter
* e −a*t * sinǒb * t ) qǓ
6
1.5.10
2.10
6
Table 4. INPUT TO OUTPUT CONNECTION
POSSIBILITIES
V Spike * R2
ǒ
6
Aside from normal solar panel transients there also exists
the possibility of four different input to output connections.
b
ǸR1)R2
R2
1.10
t
Reverse Polarity Protection
Case
R1 ) R2
7
5.10
Figure 37. Change in Voltage Over Time at V2
* a2
ǒaǓ
q + a tan
R2
CFilter
Vspike
Figure 35. Pulse Rating Curve for the SMF5.0AT1
Series [5]
V2
Output Voltage
Input Voltage
1
Correct
Correct
2
Correct
Reverse
3
Reverse
Correct
4
Reverse
Reverse
In case 1 there is no need for protection as the input and
output are connected correctly. In case 2, the input voltage
is connected in reverse. If current is allowed to flow in this
case, then all but the output diode will have the possibility
of being damaged. However, by placing a diode in series
with the input either as shown in B or C in Figure 38 all
devices can be protected. One drawback to the series diode
is that it dissipates power continuously in a system. If the
Ǔ
= Exponential time constant
= Input capacitance
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25
AND8490/D
diode is placed in for reverse polarity protection in a high
current system, the losses can be significant. An alternative
way to implement reverse polarity protection is to place a
diode such that it opens a fuse when a reverse voltage is
applied as shown in D in Figure 38. The fuse chosen can be
a user replaceable or a polley thermal fuse. The fuse
provides the necessary protection but can lead to an
unfavorable user experience. A low loss way to implement
the diode reverse polarity protection is to use a MOSFET
that turns on when the voltage is applied in the proper
polarity and turns off when it is not. One example of the
appropriate circuit is shown in E in Figure 38.
Damaged
Damaged
A
Damaged
Damaged
Drive
Protected
Protected
B
Protected
Drive
A
Protected
Protected
Protected
C
Protected
Drive
Protected
Damaged
Protected
Protected
D
Protected
Drive
Protected
Protected
Protected
E
Protected
Drive
Protected
Figure 38. Input Connected in Reverse Polarity
components could be ignited from the large amount of
energy. Figure 39 B shows one way to protect from reverse
output voltage.
In case 3 where the output is connected in reverse polarity
and the input is connected correctly, three of the power
components could be damaged. Since the source is assumed
to be a lead acid battery, the protection is critical as damaged
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AND8490/D
Damaged
A
Damaged
Drive
Damaged
Protected
Protected
B
Protected
Drive
Figure 39. Output Connected in Reverse Polarity
The final case is one in which both the input and output are
connected incorrectly. In case 4, if the designer implemented
both protections from case 2 and case 3 the input and output
would be protected. The designer should not overlook the
voltage suppressors that are installed on the input at the
transient voltages which can be presented in either the
proper polarity or reverse polarity. Therefore it is important
to have bi−directional transient suppressors that can
withstand the normal reverse polarity voltage without
damage.
Protected
Protected
Protected
Protected
Protected
Protected
Drive
Figure 40. Input and Output Connected in Reverse Polarity
One may wonder if the central grounding will affect the
protection in place for reverse polarity protection and the
answer is no. The topology implemented for protection in
the design opens the path even with central grounding.
Although the above methods serve as electrical means of
preventing damage to the power supply, a system designer
should not overlook a mechanical means of preventing
damage such as a keyed connector or dissimilar connections.
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27
AND8490/D
Battery
Drive
Solar
Panel
Current
Sense
Resistor
10mW
Central
Grounding
Point 1mW
Battery
Drive
Solar
Panel
Current
Sense
Resistor
10mW
Central
Grounding
Point 1mW
Figure 41. Reverse Polarity Protection with Central Grounding Scheme
Drive Scheme for Main Switches
appropriate drive scheme to ensure good switching
waveforms.
The basic four switch buck boost converter is shown in
Figure 42 but, Q1 and Q2 must be driven with the
L1
D2
Q1
D1
Q2
Solar
Panel
Drive
Battery
Figure 42. General Schematic for Buck Boost
change from a non−synchronous discrete driver to an
integrated synchronous driver there are very few PMOSFET
synchronous integrated drivers. If the designer manages to
find a PMOSFET that is at cost parity with an NMOSFET
and has the same gate charge, the chances are not good that
there will be many second sources. Therefore, the choice of
a PMOSFET may put the solar controller in a line down
situation after production has started. For all of the
aforementioned reasons, the high side MOSFET will be an
NMOSFET but both a PMOSFET drive scheme and
NMOSFET drive scheme are shown in the Figures 43 and
44 below. In the NMOSFET drive scheme shown in Figure
43, a drive signal is sent to the gate of Q1, in this case a
2N7002. When the drive signal from the NCP1294 is high,
it pulls down on the R1 R2 resistor divider. The resistor
divider in turn pulls down on the gate of Q3, turning it on and
allowing C1 pre−charged 8 V to flow through the switching
The next decision one would have to make is should Q1
be a PMOSFET or an NMOSFET. When making the Q1
design decision one must consider input voltage range,
efficiency, price, and second sources. First, the input voltage
range is 10 V to 60 V so the MOSFET must be able to handle
a minimum of 60 V but keeping with good design practice,
the break down voltage will need to be derated. In order to
have a product with a long lifetime a part that is rated for
100V needs to be found. The converter should have the best
possible efficiency as solar panels are currently expensive
and the energy derived from them is precious. The MOSFET
that should be selected has a low Rdson and low gate charge
as the converter should switch as fast as possible to reduce
the size of L1 which can be the largest part of a controller
design. The price of a PMOSFET can be 2 to 4 times higher
and the gate charge is usually double that of an NMOSFET
with the same Rdson. Further, if the designer decides to
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28
AND8490/D
pulling down on VSW during Q2s off time to ensure C1 is
properly charged. D3 and R5 can be used to change the
nonoverlap time of the synchronous C1 charging. In looking
at the drive scheme for the PMOSFETs, only 3 transistors are
required versus the 7 needed for the N drive, but each
transistor is approximately 0.03 USD in medium quantities,
so quantitatively the P drive is 0.09 USD vs 0.21 USD for the
N drive. The question one must ask is: is the PMOSFET for
the application less than the cost difference of the drivers and
will the efficiency be degraded? Another question is can a
synchronous driver be used for the same cost as it will also
improve efficiency? The answer is no because a driver that
will work at 60 V will cost 0.71 USD and trading a diode for
a MOSFET would double the cost for the switch. The main
design will not be a synchronous design, but if the designer
holds efficiency above cost, a driver has been made
available so that the designer can prototype both circuits to
weigh cost and efficiency.
diode, D2, to the gate of Q2, turning it on and allowing the
switch node to rise. As the switch node rises, so does the
voltage at the gate of Q2 until the solar panel voltage is
presented to the switch node and the solar panel voltage plus
8 V is presented at the gate of Q2. Once the gate signal goes
low, the current ceases to flow through R1 and R2 and the
gate of Q3 is pulled to VSW plus the bias voltage. R3
discharges to the switch node potential and Q4 discharges
the gate of Q2 to the switch node. Upon completion of Q2
discharge the switch node falls and C1 charges up to 9 V
through D1. In this type of drive scenario, there may be a
startup into pre−bias issue where the converter never gets
started. If the battery is connected first to the output, then the
solar panel is connected, there will be 12 V at the switch
node and 8 V on the VC node which will not allow capacitor
C1 to charge properly. Since C1 is not charged properly, Q2
can only turn on linearly and will not start switching. The
purpose of the pink highlighted area is to solve this issue by
C1 = 0.1uF
Q1 Gate
NCP6412AN
Q2
Solar Panel
Voltage =
10V−60V
MMSD4148
VC = 8.0V
VSW
D1
Q1 Drain
R1 = 2k
S
G
Q3
BSS84L
Q3 Gate
D
R1 = 4k
MMSD4148
R4 = 100
0V
D2
2N7002
Q1
NCP1294 Gate
D
R3 = 499
Q4
Q3 Source
MMBT3906
G
0V
S
2N7002
MMSD4148
D3
Q5
Q2 Gate
R5 = 499
Switch Node
NMOS Drive
Figure 43. NMOSFET Drive Scheme
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29
AND8490/D
NCP6412AN
Q2
Solar Panel
Voltage =
10V−60V
VSW
Q1 Gate
Q3
MMBT3904
Q1 Drain
R1 = 400
D1
MMSD4148
Q3 base
0V
R2 = 200
2N7002
Q1
Q2 Gate
D
0V
G
NCP1294 Gate
S
Switch Node
Figure 44. PMOSFET Drive Scheme
the full four switch buck boost will be engaged. The circuit
in Figure 45 looks at the solar panel voltage and the battery
charge voltage and determines when they have hit the
predetermined duty cycle threshold. Once they have passed
the 85% duty cycle, the full buck boost state will begin to
operate.
Q2 is only turned on during buck boost operation unlike
Q1 which is driven continuously during both buck and buck
boost operation. The solar controller should turn on the buck
boost portion (Q2) of the circuit only when the input voltage
falls too far to maintain regulation and that is determined by
the choice of components and allowable max duty cycle.
Therefore, a circuit is needed to determine at what duty cycle
Duty Cycle
Check
Comparator
Solar Panel
R2 = 1.27k
+
LSDRV
R1 = 10k
−
R3 = 1.0k
Battery Voltage
R4 = 10k
L1
D2
Q1
R6 = 10
Battery Voltage
D1
Q2
HSDRV
R5 = 10k
NCP1294 Gate
R5 = 10k
LSDRV
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30
Battery
AND8490/D
Soalr panel Voltage
Battery Votlage
LSDRV
Q4 Gate
Q2 Gate
Figure 45. Buck Boost Mode Detector
Buck Mode Power Saving Option
P MOSFET
+ R DS(on) ³
P MOSFET + I OUT 2R DS(on) ³
I OUT 2
(eq. 46)
7W
70 mW +
10 A 2
During buck mode, Q2 remains off and D2 is always
forward conducting. In buck mode it is advantageous to
short D2 since it does not serve a constructive purpose in this
mode and the tradeoff made is one of efficiency for cost. The
power dissipation of D2 is contained in the following
equations.
P diode + Vf * I OUT ³ 7 W + 0.7 * 10 A
IOUT
Pdiode
Vf
IOUT
PMOSFET
RDS(on)
(eq. 45)
= Output current
= Power dissipation of a diode
= Forward voltage of a diode
= Output current
= Power dissipation of the PMOSFET
= On resistance of the PMOSFET
The trade off is a good one as long as the Rdson is lower
than 70 mW as shown graphically in the Figure 46 below,
where the diode has a constant efficiency drop and the
MOSFET losses have a linear loss factor.
Figure 46. Efficiency Loss of Diode vs. MOSFET
Battery Charging
NCP1294 pulse by pulse current limiting and the current set
circuit. The current will maintain the set charge rate
configured by the designer or user unless the maximum
power point falls below that level, at which time it will
charge to the max power point adjusted rate.
There are three stages to charging a lead acid battery:
constant current or bulk charge, absorption or constant
voltage mode, and float. During the bulk charge, the current
is to be held constant which is accomplished with the
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31
AND8490/D
Figure 47. Lead Acid Battery Charge Profile
the current drops to 5% of the amp hour rating. When the
current drops to 5%, the solar controller will change to float
state and the outer voltage loop will decrease to 13.5 V
where it remains indefinitely or until the current need
changes. Many types of lead acid batteries are suitable for
solar powered street lights, they are: flooded, Valve
Regulated Lead Acid (VRLA), Absorbed Gas Mat (AGM),
and gel. A table of appropriate absorption, float and over
voltage levels are shown in Table 5.
Since the NCP1294 has pulse by pulse current limiting,
nothing needs to change between Stage 1 and Stage 2 as the
output voltage can be set to 14.5 V for both stages. In
Stage 1, the outer voltage loop is never satisfied and the
inner current loop maintains the required current. In Stage
2, the outer voltage loop takes over functionality and the
inner current loop is not used except to maintain the
maximum power point. The result of the voltage loop taking
over is that a constant voltage of 14.5 V is maintained, while
Table 5. CHARGING VOLTAGES OF LEAD ACID BATTERIES
Voltage Range (V)
Flooded
Charging Mode
Sealed VRLA
AGM
GEL
Min
Max
Min
Max
Min
Max
Min
Max
Absorption
14.2
14.8
14.2
14.5
14.4
15
14.4
14.7
Float
13.2
13.5
13.2
13.5
13.2
13.8
13.5
13.8
Over Voltage
15.1
14.9
15.3
While the output voltage is set to 14.5 V for absorption
and 13.5 V for float charge, the designer can place a
potentiometer to dial in the voltage they would like for their
particular battery. The voltage change circuitry is shown in
Figure 48 below.
15.4
Battery Voltage
R1 = 100 k
OR NTC
FB Voltage
Output Current
R2 = 80k
or NTC
R4 = 10k
or NTC
R3 = 69.8k
R5 =330
or NTC
Float
Detection
Comparator
+
−
Float Current Trip
Figure 48. Battery State Control and Internal
Temperature Compensation
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32
AND8490/D
the FB node to be 1.263 V, therefore the resistance of R1
must be decreased or a temperature compensated current
should be injected into the FB node. To determine how the
NTC value changes over temperature, the following
equation is used.
One important thing to know is the affect temperature will
have on battery charge voltage as most solar installations are
not in sheltered environmental conditions. Typical lead acid
battery voltage moves as an exponential. Some variation
exists in the upper and lower battery tolerance at a specific
temperature, the equations to define upper and lower battery
voltages for the standard six cells configuration is shown
below.
Bat UPPER + 15.928617e −0.002479T
Bat LOWER + 15.327247e −0.002582T
BatUPPER
BatLOWER
T
R + Ro
b
R
Ro
To
T
(eq. 47)
(eq. 48)
= Lower battery tolerance
= Upper battery tolerance
= Battery Temperature in degrees C
=
=
=
=
=
e
b
ǒT1*To1 Ǔ
(eq. 49)
Thermistor Constant
Resistance at specified temperature
Resistance at To
298.15 K (25°C)
Current temperature in K
If a NTC is placed in series with R1, the resulting battery
voltage falls within the upper and lower battery limits
established in Equations 47 and 48, except when it gets
extremely cold. However, if a NTC replaces R2, the
resulting curve does no harm in cold temperatures, but
would destroy the battery when hot. When the two curves
are put together, the resulting curve fits between the rails as
shown below in Figures 49 and 50.
To compensate for the battery change with temperature, the
output set point of the solar controller must change with
temperature. If remote sensing is not used, one idea for
compensation is to use a negative temperature coefficient
resistor or NTC as the voltage of the battery decreases as
temperature increases. The NCP1294 regulates voltage at
Figure 49. Temperature Compensated Battery Charged Voltage
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AND8490/D
Figure 50. Temperature Compensated Battery Float Voltage
OOV
The NCT loop should be placed as far away from the
converter heat sources as possible. If the designer does not
want to use an internal NTC, an external diode sense can be
used in conjunction with the NCP1294 3.3 V reference.
When using diodes to monitor the temperature as shown in
Figures 49 and 51, it is important to buffer the 3.3 V
reference voltage as the diode configuration can be remotely
located on the battery or outside the case, where it will be
exposed to ambient temperatures as well as ambient noise.
Buffering the reference will isolate other circuitry which
may be using the reference from the external noise
contamination.
The output battery voltage should be monitored to
determine if the feedback mechanisms have been damaged
or the remote sensing has influenced the battery voltage
beyond the battery temperature compensation. The
NCP1294 is equipped with a OOV comparator, when
tripped the OOV shuts off the system. The comparator can
be used on the input of the system or the output of the system,
but is recommended to be used on the output as a failsafe
mechanism. When using a single battery system, a single trip
point of 18 V can be used or trip points can be set based on
the state of charge. If using the float voltage state, a trip
voltage of 15 V needs to be set. If using the absorption phase
of charge, an 18 V level should be set. If a completely safe
system were to be setup, a trip level could be set to 10%
greater than the battery voltage adjusted for temperature and
state of charge.
External
Remote
Sensing
Solar Controller
OUV
The converter input voltage should be monitored to
determine if the input voltage level will cause a thermal
issue. The NCP1294 is equipped with an under voltage
lockout independent of VIN monitoring to ensure the input
voltage is at the desired level for providing full output
power.
+
3.3V
_
Battery
Votlage
OTP
R1 = 225k
NCP1294
Since the solar controller can be used in an inappropriate
way, it is suggested that the temperature of the buck main
switch be monitored to determine if it has exceed maximum
temperature levels. If the temperature of the main MOSFET
has exceeded appropriate levels, the current can be throttled
back to reduce the power dissipation of the system.
FB
RBIAS = 25k
R2 = 10k
Figure 51. External Diode Temperature Monitoring
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34
AND8490/D
Thermal Management
proper laboratory testing should be performed to ensure the
design will dissipate the required power under worst case
operating conditions. Variables considered during testing
should include maximum ambient temperature, minimum
airflow, maximum input voltage, maximum loading, and
component variations (i.e., worst case MOSFET RDSON).
Several layout tips are listed below for the best electric and
thermal performance.
The NCP1294 is a small source of power dissipation in the
system for which the equations above detailed the loss
mechanisms. The control portion of the IC power
dissipation is determined by the formula below:
P C + I CC
ICC
PC
VIN
V IN
(eq. 50)
= Control circuitry current draw
= Control power dissipation
= Input voltage
The Solar Panel
The solar panel supported by the NCP1294 evaluation
board is between 5 W and 120 W. The industry standard
types of solar panels were considered for this development.
Most common types of solar cells are crystalline silicon in
which there are two primary types: monocrystaline and
polycrystalline silicon. Monacrystalline is the most
efficient, but also more expensive to produce and is usually
limited to commercial and residential applications.
Amorphous solar panels consist of a thin film made from
molten silicon that is spread across a large plate of stainless
steel or similar material. The crystalline structures are very
fragile and usually sandwiched between two sheets of glass
for protection.
• Monocrystalline 18% efficiency
• Polycrystalline 15% efficiency
• Amorphous 10% efficiency
Once the IC power dissipations are determined, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient temperature. The formula for calculating the
junction temperature with the package in free air is:
TJ + TA ) PD
PD
RqJA
TA
TJ
R qJA
(eq. 51)
= Power dissipation of the IC
= Thermal resistance junction to
ambient of the regulator package
= Ambient temperature
= Junction temperature
Thermal performance of the solar controller is strongly
affected by the PCB layout. Extra care should be taken by
users during the design process to ensure that the IC and
power switches will operate under the recommended
environmental conditions. As with any power design,
Figure 52. Solar Controller PCB
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35
36
Z3
Q22
NTD6415ANT4G
HI
www.onsemi.com
Figure 53. Schematic 1Z
GND2-1
Q6
MMBT3904LT1
ON
1k
R57
R48
100k
14V
1k
R56
D8
MMSD4148T3G
12
13
C39
10k
R26
R5
78.7K
1.5nF
C3
R20
100k
1uF
IN
AUX
10k
R25
0.1uF
C2
VC
1uF
560pF
C1
ISETFB
R27
13k
3P3
HI
C8
1
OUT
1uF
GND
MC78L08ACP
2 U11
C4
205 kHz 95.25%
R19
100k
C16
3
ON
680uF 63V
680uF 63V
8
7
6
5
HSSENS
LM5109A
U4
VDD HB
HO
HI
HS
LI
VSS LO
R6
1
2
3
4
10m
C15
VC
C14
UVLO set to 7.86V
OOV set to 17.74V
0.1uF
R46
4.99k
R47
100k
HI
2N7002KT1G
Q20
14V
12V-52V
14
12V-52V
U2-D
+
LM324AM
10k
R53
1
2
3
4
5
6
7
8
0.1uF Q7
C12
VC
PGND
VCC
VREF
LGND
SS
COMP
VFB
U1
NCP1294
GATE
ISENSE
SYNC
FF
UV
OV
RTCT
ISET
10R
R15
VCC
16
15
14
13
12
11
10
9
VC
R17
4k
R13
2k
LO
2N7002KT1G
HB
HO
VSW1
10k
R60
3P3BUFF
330nF
C23
VCC
3P3
200k
1nF
C6
MMSD4148T3G
D7
R41
D2
14V
2N7002KT1G
Q8
Q1
IREG
1R0
10k
R9
2N7002KT1G
Q12
R8
BIPASS
LO
LSDRV
1R0
R59
MMBT3906LT1
MMSD4148T3G
R14
10k
R42
100R0
R18
499R
Q18
HO
Q3
3 BSS84LT1
D
S
2
Q14
AOT414
-20%, +80% 25V
C24 0.1uF
2N7002KT1G
1G
D5
MMSD4148T3G
HB
VC
VSW1
22uH
L1
C11
C7
220nF
AOT414
Q13
150pF
100k
R7
R11
100R0
1nF
3
1
2
R32
680uF 63V
C9
10m
GND1
VFM2
VFM1
R3
20R
FLOAT
NT3
100k NTC
Output Current Sense
2
ATP104
Q21
MBR30H100CT
D6
3
1
BIPASS
C13
SER2918H-223KL
D1
MBR30H100CT
2
10k
R58
G1
S
2
Q10
BSS84LT1 3
D
1
10k
R55
R54
10k
3
VSW1
C10
2N7002KT1G
Q9
R4
69.8k
NT2
80k NTC
R2
499R
1.5nF
R1
330 NTC
NT1
10k NTC
14V
12V-52V
SOALR-
Q19
NTD6415ANT4G
14V
SOLAR+
-
BAT+
BAT
AND8490/D
Z1
AND8490/D
MPP-1
12V-52V
12V-52V
MPP-2
VC
MPP-3
VC
IREG
MPP-4
IREG
3P3
3P3
MPP-5
MPP-6
MPPFB
MPP-7
VC
10k
6
R52
5
R50
U2-B
+
7
LSDRV
LM324AM
10k
R51
1.27k
-
12V-52V
14V
R49
1k
Figure 54. Schematic 2
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37
C20
C19
C18
C17
C26
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
AND8490/D
12V-52V
14V
VOUT_FILT
3P3
R39
49.9
HSSENS
R40
499R
3P3BUFF
BC846BPDW1T1G
Q11
Q4
Q5
Q15
5
5
2
2
3
IMPPDRV
1
IREG
1
BC846BPDW1T1G
1
2
1
2
IBATDRV
6
6
6
6
Q17
2N7002KT1G
BC846BPDW1T1G
5
3
5
3
IMPPDRV
2N7002KT1G
BC846BPDW1T1G
3
1
U2-A
+
LM324AM
4
-
4
3
4
3P3
4
2
Q16
IOUT
ISETFB
C22
3.9nF
R43
4.99k
R21
1k
LM324AM
8
IMPPDRV
10 MPPFB
+
U2-C
9
-
R38
4.99k
R35
3P3BUFF
R10
3.9nF
499R
MPPFB
14V
C5
R33
499R
1k
R29
R16
10k
R45
100k
10k
R31
Q2
3
10k
1uF
C42
D4
R30
MMSD4148T3G
ON
IBATDRV
100k
R37
2
1
LM324AM
1
0R0
ISETFB
U3-A
3
+
10k
R24
5
+
U3-B
6
-
1uF
BSTEN
GND
FLOAT
LM324AM
8
IO3-1
IOUT
C25
0.1uF
R12
C21
2N7002KT1G
2
2.8k
R44
LM324AM
7
D3
0R0
IO3-2
10
+
U3-C
9
-
2% Trip
R36
10.7k
R28
100k
14
U3-D
+
LM324AM
R34
28k
13
12
R23
18.7k
IO2-1
IO2-2
IO1-1
IO1-2
R22
28k
Figure 55. Schematic 3
www.onsemi.com
38
IO1
IO2
IO3
0
0
0.91 11.4
0
0
0
1
V
I
.78
9.7
0
1
0
.67
8.1
0
1
1
.51
6
1
0
0
.55
6.5
1
0
1
0.37 4.1
1
1
1
1
0
1
.22
0
2.0
0
AND8490/D
Figure 56. Layout Bottom
www.onsemi.com
39
AND8490/D
Figure 57. Layout Top
Table 6. BOM
Reference
Qty
Description
Part
Name
Manufacturer
Footprint
Manufacturer
Manufacturer Part #
Q2, Q7 − 9, Q12,
Q16 − 18, Q20
9
Small Signal N
MOSFET
60 V
380 mA
NA
SOT−23
ON Semiconductor
2N7002KT1G
Q21
1
30 V, 72 A, Single
P−Channel MOSFET
8.4 mW
NA
ATPAK
(2leads + tab)
SANYO
ATP104−TL−H
D2, D4 − 5, D7−8
5
Switching Diodes
1V
NA
SOD123
ON Semiconductor
MMSD4148T3G
Q4 − 5, Q11, Q15
4
NPN Dual
65 V
100 mA
NA
SC−88
ON Semiconductor
BC846BPDW1T1G
Q3, Q10
2
NFET
10R 50 V
NA
SOT−23
ON Semiconductor
BSS84LT1
C1
1
SMT Ceramic
Capacitor
560 pF
±5%
603
TDK Corporation
C1608C0G1H561J
C3, C10
2
SMT Ceramic
Capacitor
1.5 nF
±10%
603
TDK Corporation
C1608X7R2A152K
www.onsemi.com
40
AND8490/D
Table 6. BOM
Part
Name
Manufacturer
Footprint
Manufacturer
Manufacturer Part #
SMT Ceramic
Capacitor
1 nF
10%
603
TDK
C1608X7R2A102K
2
SMT Ceramic
Capacitor
1 mF
−20%, +80%
603
Taiyo Yuden
EMK107B7105KA−T
C23
1
SMT Ceramic
Capacitor
330 nF
±10%
603
TDK Corporation
C1608X7R1A334K
C17−20, C25−26
6
SMT Capacitor
0.1 mF
±20%
805
AVX Corporation
08055C104MAT2A
C2, C12, C24
3
Ceramic Chip
Capacitor
0.1 mF
−20%, +80%
603
AVX
06033G104ZAT2A
C11
1
Ceramic Chip
Capacitor
220 nF
10%
603
TDK Corporation
C1608X7R1C224K
C5, C22
2
Ceramic Chip
Capacitor
3.9 nF
10%
603
Murata
GRM188R71H392KA01D
C21, C42
2
Ceramic Chip
Capacitor
1 mF
10%
603
Murata
GRM188R71H392KA01D
C39
1
Ceramic Chip
Capacitor
0.1 mF
±20%
603
TDK Corporation
C1608X7S2A104M
C7
1
Ceramic Chip
Capacitor
150 pF
5%
603
TDK Corporation
C1608C0G1H151J
C16
1
Ceramic Chip
Capacitor
1 mF
±10%
1206
Murata
GRM31MF51E105ZA01L
U1
1
Enhanced Voltage
Mode PWM
Controller
3V
Reference
NA
SOIC 16
ON Semiconductor
NCP1294
C9, C14−15
3
Electrolytic Capacitor
680 mF
63 V
20%
16X25
Nichicon
UPW1J471MHD6
U2−3
2
QUAD, LOW
POWER OP AMP
1 MHz
NA
14−SOIC
ON Semiconductor
LM324ADR2G
U4
1
Half Bridge Driver
1 A 108 V
NA
8−WDFN
National Semiconductor
LM5109AMA
D1, D6
2
Schottky Rectifier
100 V
30 A
NA
TO−220
ON Semiconductor
MBR30H100CTG
U11
1
8.0 V Regulator
4%
TO−92−3
ON Semiconductor
MC78L08ACPRE
Q6
1
General Purpose
NPN Transistor
40 V
200 mA
NA
SOT−23
ON Semiconductor
MMBT3904LT1G
Q1
1
General Purpose
PNP Transistor
PNP
NA
SOT−23
ON Semiconductor
MMBT3906LT1G
Reference
Qty
Description
C6, C13
2
C4, C8
Z1, Z3
2
Q13−14
2
N−MOSFET
100 V
18.2m
NA
TO−220
Alpha & Omega
AOT414
NI
Q19, Q22
2
N MOSFET
100 V
50m
NA
Dpak
ON Semiconductor
NTD6415ANT4G
NT1
1
Resistor
10k NTC
±1.0%
603
EPCOS Inc
B57331V2103J60
NT2
1
Resistor
80k NTC
±1.0%
603
Vishay / Dale
NTHS0603N01N8002JE
NT3
1
Resistor
100k NTC
±1.0%
603
TDK
NTCG164KF104FT1
R1
1
Resistor
330 NTC
±1.0%
603
Murata
NCP18XM331J03RB
R2, R18, R33, R35,
R40
5
Resistor
499R
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT499R
R9, R14, R24−26,
R30−31, R45, R50,
R52 − 55, R58, R60
15
Resistor
10k
±1.0%
603
Panasonic
ERJ−3EKF1002V
RMCF0603FT2K00
R13
1
Resistor
2k
±1.0%
603
Stackpole Electronics Inc
R10, R49, R21
3
Resistor
1k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT1K00
R29, R12
2
Resistor
0R0
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT499R
R16, R37, R7, R47 −
48, R19 − 20, R28
8
Resistor
100k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT100K
R34, R22
2
Resistor
28k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT28K0
R43, R46, R38
3
Resistor
4.99k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT4K99
R44
1
Resistor
2.8k
±1.0%
603
Vishay / Dale
RMCF0603FT2k80
R5
1
Resistor
78.7k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT78K7
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41
AND8490/D
Table 6. BOM
Reference
Qty
Description
Part
Name
Manufacturer
Footprint
R36
1
Resistor
10.7k
±1.0%
R27
1
Resistor
13k
±1.0%
R3
1
Resistor
20R
R51
1
Resistor
R4
1
Resistor
R17
1
R39
1
R41
Manufacturer
Manufacturer Part #
603
STACKPOLE
RMCF0603FT10K7
603
Stackpole Electronics Inc
RMCF0603FT13K0
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT20R0
1.27k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT1K27
69.8k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT69K8
Resistor
4k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT4K99
Resistor
49.9
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT49R9
1
Resistor
200k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT4K99
R56−57
2
Resistor
1k
±1.0%
603
Panasonic
ERJ−3EKF1002V
R23
1
Resistor
18.7k
±1.0%
603
Stackpole Electronics Inc
RMCF0603FT15K0
R15
1
Resistor
10R
±5.0%
603
Stackpole Electronics Inc
RMCF0603JT10R0
RMCF1206JT1R00
R8, R59
2
Resistor
1R0
±5.0%
1206
Stackpole Electronics Inc
R42, R11
2
Resistor
100R0
±5.0%
1206
Stackpole Electronics Inc
RMCF1206JT100R
R6, R32
2
Resistor
10m
±1.0%
2512
Bourns Inc.
CRA2512−FZ−R010ELF
L1
1
Inductor
22 mH
±10%
SMT
Coilcraft
SER2918H−223KL
D3
1
Shunt Reference
ON Semiconductor
TL431ACLPRAG
±1.0%
Bibliography
1. BP 3220T Datasheet.” BP Solar USA. BP Solar, 01 Jan. 2010. Web. 21 Mar. 2011.
<http://www.bp.com/liveassets/bp_internet/solar/bp_solar_usa/STAGING/local_assets/downloads_pdfs/pq/BP3220T
_1−10.pdf>.
2. T. Esram and P. L. Chapman, “Comparison of photovoltaic array maximum power point tracking techniques,” IEEE
Trans. Energy Conv., Vol. 22, pp. 439–449, 2007.
3. [“Irradiance − Definition and More from the Free Merriam−Webster Dictionary.” Dictionary and Thesaurus −
Merriam−Webster Online. Web. 21 Mar. 2011. <http://www.merriam−webster.com/dictionary/irradiance>.
4. “NCP1294 Datasheet.” ON Semiconductor Home Page. ON Semiconductor, July 2090. Web. 21 Mar. 2011.
<http://www.onsemi.com/pub_link/Collateral/NCP1294−D.PDF>.
5. “SMF5.0AT1 Series Datasheet.” ON Semiconductor Home Page. ON Semiconductor, Sept. 2007. Web. 21 Mar. 2011.
<http://www.onsemi.com/pub_link/Collateral/SMF5.0AT1−D.PDF>.
6. Tarter, Ralph E. The RLCR Circuit with a Dc Input. Solid−state Power Conversion Handbook. New York: Wiley,
1993. 26−27. Print.
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