AND9388/D A minimum size, standalone motor application using the LV8907UW Overview www.onsemi.com An example application for LV8907UW (a sensor-less three-phase brushless DC motor controller with gate drivers) is described. The target application is an automotive 60 watt oil pump. The various features of the LV8907UW allow running this pump throughout all application conditions without prior software development. This application note focusses on designing a minimum PCB circuit using the LV8907UWand not on the advanced features of the device. For more information on the capabilities of the IC consult the datasheet. The PCB described consists of the LV8907UW motor controller, three dual power FETs for the power stage, and passive peripheral components. The inputs are power supply and a control PWM, the outputs are the three motor winding terminals. APPLICATION NOTE PICTURE of BOARD ASSEMBLY An SPI interface is featured as well, which is used to setup and program the system parameters. In the present example the SPI is intended to be contacted by test points at the assembly line. Features • Nominal operation voltage range from 5.5V to 20V, transient tolerant from 4.5V to 40V. • Nominal power 60W, max 120W (current limit). • Input: o Power supply and ground. o Low frequency, supply tolerant PWM. o Motor enable line (optional). • Output: o Three motor phases. • Fault feedback through PWM pulldown. • Three NVMFD5852NLT1G MOSFETs. • Single 10mOhm current sense shunt. • On-board thermistor for FET temperature monitoring. • Minimum two layer FR4 board size (40mm × 40mm). The information herein is subject to be change without notice. © Semiconductor Components Industries, LLC, 2016 March 2016- Rev. 1 1 Publication Order Number: AND9388/D AND9388/D SCHEMATICS VM L1 VS V3RI 1 VCC 45 WAKE 15 LIN_PWMIN C11 41 43 42 38 VGL V3RO C10 40 CP2P 47 48 44 VS P7 39 CP2N C8 C31 CHP GND CP1P C29 C9 + CP1N P4 C12 R52 PWMIN P6 R50 COM R14 24 R13 IC 3 TXD 2 RXD UH 36 7 CSB UOUT 35 8 SCLK 9 SI CP1 CP2 CP3 CP4 10 T1a SO R1 T2a R2 R3 R15 T3a P1 U VH 32 VOUT 31 P2 WH 28 WOUT 27 V P3 W EN UL 34 4 PWMIN VL 30 11 FG WL 26 12 DIAG SUL 33 SVL 29 17 TEST C15 CP6 R18 R19 R53 PGND T9 EN AGND R20 R7 46 LGND CP5 R51 TH P8 T1b 19 13 5 37 SWL 25 RF 22 RFSENS 20 R8 T2b R54 R9 R55 VS R17 C7 R16 C27 High current line Figure 1 Schematics www.onsemi.com 2 + C30 Critical line C14 T3b + C28 AND9388/D DETAILED DESCRIPTION Startup and Shutdown Note: For OPT programming the supply voltage must be at least 14V! The layout suggestion of this application note does not provide for a specific SPI connector. It is assumed the necessary pads can be accessed through the assembly line programmer. The location of the SPI pads is marked up in Figure 2. After SPI write and OTP program the connection can be removed, and the power supply voltage can be returned to the nominal 12V. The detailed SPI timing and OTP writing sequence is described in the data sheet. The application described here will be active as soon as power is supplied. If low quiescent current operation (< 100uA) is required, a separate control signal must be connected to the WAKE pin. WAKE is supply voltage tolerant but an in-line 1k filter resistor is recommended. Motor control and Fault handling The motor is controlled by applying a PWM signal to supply voltage tolerant pin LIN_PWMIN. The LV8907UW requires the PWM signal frequency to be less than 1kHz. The PWM input polarity is high active. The input duty cycle 15 to 85% is translated to the output duty cycle 0 to 100%. These configurations can be selected in the system registers of the IC. Power Line Noise Filter To reduce EMC noise, a common mode choke is inserted into the power line. The filter coils (L1) are put in the power lines both plus side and ground side. Its impedance is 850Ω at 100MHz. The capacitor C31 is used for the power supply input. The capacitors C30 and C28 for the motor power node, are necessary to prevent voltage trip due to fly-back of the motor coil as well as noise. In this application, the motor control signal EN is pulled up to the 3.3V on-chip regulator, but can be used as an additional motor enable/disable line: EN open: The motor runs. EN pulled down: Standby Charge pump The required capacitance of the charge pump is defined by the gate capacitance (Ciss) of the output power FET. The charge pump circuit consists of two bucket capacitors at pins CP1P/CP1N and CP2P/CP2N (C9 and C10 in the schematic), and two storage capacitors at pins CHP/VS and VGL/GND (C8 and C11 in the schematic). The following table shows appropriate capacitance values based on FET gate capacitance. When a fault event is detected, the LV8907UW pin DIAG is activated and through transistor T9 will pull down the PWM input to stop the motor. A series resistor may be required to prevent overstressing the external driver of the PWM signal. A multitude of fault scenarios can be selected in the LV8907UW system registers, but it is important to set the IC to NOT latch errors, so the application can recover on its own. ON Suggestions NVD5807N NVMFD5852NL NVD5803N NVMFS5C604NL The sample parameter list on page 5 is a good setup to run most motors. Detailed register usage, is described in the data sheet of LV8907UW. Device configuration via SPI The LV8907UW has register bits for device configuration, feature selection, and parameters. For the type of standalone control system application described here, the settings must be stored in the one-time programmable, non-volatile memory (OTP), and are automatically loaded to the RAM registers at the beginning of each device wake-up. To program and store these parameters, the SPI interface of the LV8907UW must be accessed at least once through the following pins: App. VM CP6 EN CP1 CP2 CP3 CP4 LV8907UW VS AGND EN CSB SCLK SI SO Ciss [nF] 0.6 1.8 3.22 8.9 CP1, CP2 [µF] 0.068 0.1 0.1 0.22 CHP, VGL [µF] 0.1 0.22 0.47 1.5 Output Stage In the schematic (Figure 1), the critical lines are highlighted in light blue, and high current lines are highlighted in light pink. The FET gate lines must be routed as short as possible, as the gate current flows through them. The same is true for the FET source lines which must also be routed away from high current line to prevent VGS bouncing caused by phase current switching. From circuit network point of view, the low side FET source return pins (SUL, SVL, SWL) and current sense resistor are connected to the same node. But, it must be separated geometrically. The FET source lines are highlighted green in Figure 2. The high current path from the source pins of the low side FETs to ground through the current sense resistor, is separated from the source lines as shown in Figure 3. To adjust the switching slew rate, a series resistor is inserted to each gate line of the power MOSFETs. And, to prevent shoot through while the gate driver outputs Purpose Supply ≥14V!! Reference GND must be low for SPI access active low chip select SPI clock Master out slave in Slave out Master in www.onsemi.com 3 AND9388/D In this case 20A is the threshold of the over current protection. R17 and C7 defines a switching noise filter with the cutoff of 160kHz. The cutoff frequency should be higher than output PWM frequency 19.5kHz to reject high frequency noise like a switching spike. 1 2 2 1 3 1 2 1 1 1 2 1 2 1 To monitor the power FET temperature, an NTC thermistor (NCP15XH103F0SRC) is located close to the power FET pair of the phase W. It is connected to the external temperature monitor input pin TH. The threshold of the temperature detection can be adjusted within limits. In this example, the threshold temperature is defined to 127°C. To configure it, 1 1 𝑅𝑅𝑁𝑁𝑁𝑁𝑁𝑁 = 𝑅𝑅0 exp �𝐵𝐵 � − �� 𝑇𝑇 𝑇𝑇0 Where, 𝑅𝑅0 = 10kΩ 𝑇𝑇0 = 298.15K 𝐵𝐵 = 3380 The thermistor resistance at 127°C is, 𝑅𝑅𝑁𝑁𝑁𝑁𝑁𝑁127 = 556Ω 1 1 2 Temperature Monitoring 1 are floating state, a pull down resistor between gate and source of each low side power MOSFET. 1 2 2 3 1 2 1 1 2 1 3 8 3 9 4 0 4 1 2 1 2 1 33 31 6 2 2 1 32 30 3 29 5 26 25 2 11 12 1 27 4 2 3 2 4 2 2 2 1 2 0 1 9 1 5 1 6 1 7 1 8 1 3 1 4 1 2 1 28 1 1 1 34 2 1 1 1 9 MISO GND 35 25 8 10 MOSI 36 SUL SVL SWL 4 5 6 7 SCLK 1 1 2 3 CSB 4 2 4 3 4 4 4 5 4 6 4 7 4 2 4 8 2 1 5 4 3 7 2 2 1 6 1 1 1 5 4 2 1 1 1 3 2 2 1 2 1 1 1 2 1 1 2 6 2 3 2 2 1 2 1 2 1 2 sepalate ground Where, 𝑉𝑉 = 3.3V (LV8907UW internal regulator) 𝑉𝑉𝑇𝑇𝑇𝑇 = 0.35V (register THTH=00) The required resistance of R18 is, 𝑅𝑅18 = 4686 = 4.7kΩ 2 11 2 2 𝑉𝑉 − 1� 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑅𝑅18 = 𝑅𝑅𝑁𝑁𝑁𝑁𝑁𝑁127 � 2 1 thermistor 1 Figure 2 SPI, thermistor and FET routing 1 To measure the temperature of the power FET, the thermistor must be located close to the FET. But, the ground line must be separated from the high current path. See Figure 2 lines marked in purple. 2 3 1 1 1 1 4 1 1 2 2 1 2 2 2 0 1 R F S R E F N S E 1 1 1 2 1 1 1 2 2 The motor current is monitored across the shunt resistor R16 by the IC inputs RFSENS and RF. The traces must be Kelvin connected to the resistor terminals and should be protected from switching signals and high current paths. In this application, the sense traces are separated from the shunt resistor by the different layer. () Shunt resistance RS is determined by the target cycle-by-cycle current limit ILIM. The threshold voltage is 100mV at the pin RF, therefore, 𝑅𝑅𝑆𝑆 = 0.1 ÷ 𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 When the limit current is defined to 10A for instance, the resistance can be obtained by 𝑅𝑅𝑆𝑆 = 0.1 ÷ 10 = 10 [mΩ] The over current threshold voltage is 200mV at the pin RF. Thus, the over current threshold IOCP is automatically defined to be twice of the cycle-by-cycle current limit. 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 = 2𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 1 2 1 2 1 Current sense input 2 1 2 1 1 1 2 1 1 2 1 Figure 3 High current path and current sense www.onsemi.com 4 AND9388/D REGISTER SETTINGS This is a sample register configuration of the LV8907UW to be used for the application board described in this application note. Most motors will start and run with this setting, but may require parameter modification for optimum performance. ADDR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 NAME MRCONF0 MRCONF1 MRCONF2 MRCONF3 MRCONF4 MRCONF5 MRCONF6 MRCONF7 MRCONF8 MRCONF9 BYTE 0x2C 0xC8 0xB1 0x1B 0x50 0x00 0x00 0x58 0x00 0x3E 0x0A MRCONF10 0x01 0x0B 0x0C 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A MRCONF11 MRCONF12 MRSPCT0 MRSPCT1 MRSPCT2 MRSPCT3 MRSPCT4 MRSPCT5 MRSPCT6 MRSPCT7 MRSPCT8 MRSPCT9 MRSPCT10 0x80 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 BITS FRMD=0 FRREN=0 SCEN=1 PWMF=0 REGSEL=1 VCEN=1 LINSLP=0 LINIO=0 FLSEL[1:0]=11 ZPSEL[1:0]=00 PWMFL=1 PWMZP=0 PDTC=0 PWMON=0 SSTEN=1 FGOF[1:0]=01 FDTI[4:0]=10001 PDTSEL[1:0]=00 SSTT[5:0]=011011 STOSC[7:0]= 01010000 CLMASK[3:0]=0000 OCMASK[3:0]=0000 SROFFT[3:0]=0000 CRMASK[3:0]=0000 SYNCEN=0 PPDOSEL=1 FSCDT[1:0]=01 FSCDL[3:0]=1000 SSCG=0 CPTM[3:0]=0000 THTH[1:0]=00 TSTS=0 WDTEN=0 WDTP=0 WDT[5:0]=111110 VCLVPEN=0 CPEN=0 THWEN=0 THPEN=0 FSPEN=0 OVPEN=0 OCPEN=0 DIAGSEL=1 DWNSET[1:0]=10 WDTSEL[1:0]=00 CPLT=0 FSPLT=0 OCPLT=0 DLTO=0 STEPSEL[2:0]=000 SLMD=1 LASET[3:0]=0000 0=0 PX[2:0]=000 0=0 PG[2:0]=000 0=0 IX[2:0]=000 0=0 IG[2:0]=000 FGT0[6:0]=0000000 FGT1[6:0]=0000000 FGT2[6:0]=0000000 FGT3[6:0]=0000000 FGT4[6:0]=0000000 FGT5[6:0]=0000000 FGT6[6:0]=0000000 FGT7[6:0]=0000000 FGT8[6:0]=0000000 www.onsemi.com 5 AND9388/D BILL OF MATERIALS Designator Quantity Type Value Tolerance Footprint Manufacturer Manufacturer Part Number IC R1-3, R7-9 R13-15, R50 R16 R17 R18 R19 R20, R51-52 R53-55 C7, C14, C15 C8, C11, C12 C9, C10 C27, C29 C28,C30-31 L1 T1-3 1 6 4 1 1 1 1 3 3 3 3 2 2 3 1 3 Motor Pre-Driver Thick film Resistor Thick film Resistor Shunt Resistor Thick film Resistor Thick film Resistor Chip Thermistor Thick film Resistor Thick film Resistor Ceramic multilayer Capacitor Ceramic multilayer Capacitor Ceramic multilayer Capacitor Ceramic multilayer Capacitor Electrolytic Capacitor Common mode noise filter Dual N-ch MOSFET 30Ω, 1/10W 1kΩ, 1/10W 10mΩ, 1W 100Ω, 1/16W 4.7kΩ, 1/16W 10kΩ, 1/10W 5.1kΩ, 1/16W 100kΩ, 1/10W 0.01µF, 50V 4.7µF, 25V 1.0µF, 25V 0.1µF, 50V 47µF, 35V 850Ω, 3.5A 40V, 6.9mΩ, 44A ±5% ±1% ±1% ±1% ±1% ±1% ±5% ±5% ±5% ±10% ±10% ±10% ±20% SQFP48K 1608(0603) 1608(0603) 5025(2010) 1608(0603) 1608(0603) 1005(0402) 1005(0402) 1005(0402) 1608(0603) 3225(1210) 3216(1206) 2012(0805) 3X8 7.5X7.5 WDFN-8 ON Semiconductor ROHM ROHM Vishay ROHM ROHM Murata ROHM ROHM TDK TDK TDK TDK Rubycon Sumida ON Semiconductor LV8907UW MCR03EZPJ300 MCR03EZPF1001 WSL2010R0100FEA18 MCR03EZPF1000 MCR03MZPF4701 NCP15XH103F0SRC MCR01MZPJ512 MCR01MZPJ104 CGA3E2NP01H103J080AA CGA6P3X8R1E475K250AB CGA5L2X8R1E105K160AA CGA4J2X8R1H104K125AA 35THV47M6 CPFC74BNP-851 NVMFD5852NLT1G T9 P1-4,P6-8 1 7 NPN Bip-Tr Through-hole SOT-23 ON Semiconductor Mac8 BC846ALT1G ST-1-3 www.onsemi.com 6 AND9388/D 2 1 1 1 1 2 1 2 2 1 1 2 1 1 LAYOUT 1 2 2 3 1 2 5 4 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 2 1 1 6 34 4 33 5 32 49 6 30 8 29 9 28 3 27 26 12 25 5 4 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 5 1 4 1 6 1 1 1 3 1 1 11 2 10 1 6 2 31 1 1 7 1 2 35 3 1 36 2 2 1 1 1 1 2 6 1 1 2 Figure 4 Top layer Figure 5 Silk for top layer www.onsemi.com 7 1 5 4 2 2 1 1 3 2 1 1 1 1 3 1 2 2 1 2 2 2 2 2 2 1 1 1 AND9388/D 1 1 1 3 2 1 1 1 1 1 1 2 1 2 1 1 1 1 1 2 2 4 2 1 2 2 1 1 2 1 2 1 1 1 2 1 1 2 1 Figure 6 Bottom layer Figure 7 Silk for bottom layer www.onsemi.com 8 AND9388/D ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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