Sensor-less Three-phase Brushless DC Motor Controller, with Gate

LV8907UW
Advance Information
Sensor-less Three-phase
Brushless DC Motor Controller,
with Gate Drivers, for Automotive
Overview
The LV8907 is a high performance, AEC-Q100 qualified, sensor-less
three-phase BLDC motor controller with integrated gate drivers for driving
external N-MOSFETs. An on-chip two-stage charge pump provides required
gate current for a wide range of ultra low RDS(ON) type external N-MOSFETs.
The device offers a rich set of system protection and diagnostic functions such
as over-current, over-voltage, short-circuit, under-voltage, over-temperature
and many more. It supports open-loop as well as closed-loop speed control
with user configurable startup, speed setting and proportional/integral (PI)
control coefficients, making it suitable for a wide range of motor and load
combinations. With an in-built linear regulator for powering an external circuit,
a watchdog timer and a Local Interconnect Network (LIN) transceiver, the
LV8907 offers the smallest system solution footprint.
The LV8907 stores system paramerters in embedded one-time programmable
(OTP) non-volatile memory and operates out of system memory. An SPI
interface is provided for parameter setting and monitoring the system health.
With the operating junction temperature tolerance up to 175ºC and electrically
LIN compatible control signals (PWM and Enable), the LV8907 is an ideal
solution stand-alone automotive BLDC motor control systems.
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PACKAGE PICTURE
SPQFP48 7x7 / SQFP48K
7 mm x 7 mm SQFP48K
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified and PPAP capable.
Operating junction temperature up to 175ºC
Operating voltage range from 5.5V to 20V with tolerance from 4.5V to
40V
Embedded proprietary sensor-less commutation control
Integrated gate drivers for driving six N-MOSFETs
Two-stage charge pump for continuous 100% duty-cycle operation
On-chip OTP memory for storing system parameters
In-built LIN transciever and Watchdog timer
SPI interface for real-time parameterization and diagnostic
Integrated 5V/3.3V regulator output for external circuit
Supports open-loop as well as closed-loop speed control
Configurable speed setting and PI control coefficients
Various system protection features including:
o Shoot through protection using configurable dead-time
o Drain-source short detection
o Cycle-by-cycle current limit and over-current shutdown
o Over-voltage and under-voltage shutdown
o Over-temperature warning and shutdown
o Input PWM fault detection
Typical Applications
•
•
•
•
Automotive pumps (Fuel, Oil, and Hydraulic)
Fans (HVAC, Radiator, Battery Cooling, LED Headlight Cooling)
BLDC motor control with or without LIN control
White goods and industial BLDC motor control
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2015
July 2015- Rev. P2
1
Publication Order Number:
LV8907UW/D
LV8907UW
LV8907 BLOCK DIAGRAM
VS
VCC
V3RI
V3RO
LIN_PWMIN
CHP CP1N CP1P CP2N CP2P VGL
LV8907
5V / 3.3V
Regulator
Internal
Regulator
LIN
Transceiver /
PWM Input
TXD
Charge Pump
COM
Back EMF
Detection
Watchdog
Timer
OTP
OSC
System
Registers
RXD
UH
CSB
UOUT
SCLK
VH
SI
System
MOSFET
SO
Control
Pre-driver
EN
and
VOUT
WH
Or
Sensor-less
PWMIN
Commutation
WOUT
Gate Driver
UL
FG
VL
WAKE
WL
SUL
DIAG
VS
CHP
VGL
Voltage
Monitor
TEST
VS
Thermal
Shutdown Logic
VDS
Monitor
SVL
SWL
Protection
Logic
+
+
-
RF
+
-
200 mV 100 mV
RFSENS
TH
LGND
AGND
PGND
FIGURE 1: LV8907 BLOCK DIAGRAM
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2
LV8907UW
APPLICATION BLOCK DIAGRAMS
+
VBAT
VCC
CHP CP1N CP1P CP2N CP2P VGL
VS
V3RI
V3RO
COM
PWMIN
LIN_PWMIN
TXD
UH
RXD
UOUT
CSB
VH
SCLK
VOUT
LV8907
SI
WH
SO
WOUT
EN
UL
PWMIN
VL
FG
WL
DIAG
SUL
WAKE
SWL
SVL
Key
RF
TEST
LGND AGND
TH
PGND
RFSENS
V3RI
FIGURE 2: STAND-ALONE BLDC MOTOR CONTROL USING LV8907
+
VBAT
LIN
VS
LIN_PWMIN
CHP CP1N CP1P CP2N CP2P VGL
V3RI
V3RO
COM
VCC
UH
TXD
Low-end
8-bit MCU
for
LIN Stack
UOUT
RXD
VH
CSB
VOUT
LV8907
SCLK
WH
SI
WOUT
SO
UL
EN
VL
PWMIN
WL
SUL
FG
SVL
DIAG
SWL
Key
WAKE
RF
TEST
TH
LGND AGND
PGND
RFSENS
V3RI
FIGURE 3: LIN BASED BLDC MOTOR CONTROL USING LV8907
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3
LV8907UW
SWL
WL
WOUT
WH
SVL
VL
VOUT
VH
SUL
UL
UOUT
UH
PIN ASSIGNMENTS
36
25
37
24
PGND
COM
VGL
NC
CHP
RF
LV8907
SQFP48K(7×7)
CP1N
CP1P
CP2P
CP2N
VS
NC
RFSENS
TH
NC
TEST
7mm x 7mm
WAKE
NC
EN
LIN_PWMIN
V3RO
NC
V3RI
LGND
48
13
FG
DIAG
SI
SO
CSB
SCLK
NC
AGND
PWMIN
TXD
RXD
12
VCC
1
FIGURE 4: LV8907 PINOUT DETAILS
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LV8907UW
PIN DESCRIPTION
Pin
Name
Pin
No
VCC
1
RXD
2
TXD
3
PWMIN
4
AGND
CSB
SCLK
SI
SO
5
6, 14,
16,18,
21, 23
7
8
9
10
FG
11
DIAG
LGND
LIN_
PWMIN
TEST
12
13
Active low SPI interface chip selection pin. See page 23 for SPI timing details.
SPI interface clock input pin. See page 23 for SPI timing details.
Active high SPI interface serial data input pin. See page 23 for SPI timing details.
Open drain SPI interface serial data output pin. See page 23 for SPI timing details.
Open drain back-EMF transition output pin. The frequency is selectable via register
settings.
Programmable open drain diagnostic output.
LIN Block GND pin.
15
LIN transceiver input/output. Register selectable as PWM input with a VVS/2 threshold.
17
TH
19
RFSENS
20
RF
22
COM
24
Factory test pin. Connect to GND.
Thermistor input pin for FET temperature detection. If the input voltage is below the
threshold voltage, an error is triggered. The error threshold is programmable. To disable
tie to V3RO.
Shunt resistance reference pin. Connect this pin to the GND side of the Shunt resistor
with Kelvin leads.
Output current detect pin. Connect this pin to output side of shunt resistor with Kelvin
leads. The maximum peak motor current is limited to the value calculated by
IOUT=100mV/RF.
COM input pin. Connect this pin to the motor neutral point. This point may be derived from
a resistive network with 1k resistors to the phases.
SUL
SVL
SWL
UL
VL
WL
UOUT
VOUT
WOUT
UH
VH
WH
PGND
33
29
25
34
30
26
35
31
27
36
32
28
37
VGL
38
CHP
39
CP1N
CP1P
CP2P
CP2N
VS
WAKE
40
41
42
43
44
45
NC
Description
5V or 3.3V regulator output pin. (Selected by internal register setting)
Power supply for microcontroller. Connect capacitor to AGND for stability.
Open drain logic level output of LIN_PWMIN received data. Use pullup to a voltage less
than or equal to VS.
Logic level input of transmit data for LIN_PWMIN.
Digital level PWM input pin for direct drive or speed selection. See page 18 for details.
Input polarity can be programmed for either active high or active low.
Analog GND pin.
No Connections
Current return path for low-side gate drive. Short circuit shutoff level is measured
between this pin and its corresponding phase pin.
Gate driver output pin for the low-side Nch Power FET. Use gate resistors for
wave-shaping.
Current return path for high-side gate drive and reference for short circuit shut-off.
Gate driver output pin for the high-side Nch Power FET. Use gate resistors for
wave-shaping.
GND pin for the charge pump output drives.
Power supply pin for low-side gate drive. Connect decoupling capacitor between this pin
and GND.
Power supply pin for high-side gate drive. Connect decoupling capacitor between this pin
and VS.
Charge transfer pin of the Charge pump (1N). Connect capacitor to CP1P-CP1N.
Charge transfer pin of the Charge pump (1P). Connect capacitor to CP1P-CP1N.
Charge transfer pin of the Charge pump (2P). Connect capacitor to CP2P-CP2N.
Charge transfer pin of the Charge pump (2N). Connect capacitor to CP2P-CP2N.
Power supply pin.
WAKE pin. “H” = Operating mode, “L” or “Open” = Sleep mode.
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5
LV8907UW
Pin
Name
EN
V3RO
Pin
No
46
47
V3RI
48
Description
Enable pin. “H” = Normal enabled mode; “L” or “Open” = Standby mode.
3V regulator output pin. Connect capacitor between this pin and AGND.
3V regulator input pin (Control circuit and Logic power supply).
Connect to V3RO pin.
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LV8907UW
PIN CIRCUIT
VS
VS
VS
V3RO
VCC
V3RI
TH
RFSENS
PWMIN
SCLK
SI
TEST
EN
100KΩ
TYPE3: PWMIN, SCLK, SI, TEST,
EN
TYPE1: V3RI, TH, RFSENS
TYPE2: V3RO, VCC
VS
CHP
V3RO
VS
RXD
SO
FG
DIAG
30KΩ
UH
VH
WH
TXD
CSB
60KΩ
TYPE4: RXD, SO, FG, DIAG
TYPE5: TXD, CSB
UOUT
VOUT
WOUT
TYPE6: UH, VH, WH, UOUT, VOUT, WOUT
VGL
VS
VS
UL
VL
WL
WAKE
100KΩ
RF
SUL
SVL
SWL
TYPE8: UL, VL, WL, SUL, SVL,
SWL
TYPE7: WAKE
TYPE9: RF
VGL
CHP
CP1P
CP2P
COM
VGL
VS
VS
60KΩ
CP1N
TYPE10: VGL, CP1P, CP1N
CP2N
TYPE11: COM
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TYPE12: CHP, CP2P, CP2N
LV8907UW
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Parameter
Supply voltage
Charge pump voltage
Ratings
−0.3 to 40
Unit
V
VGL
VR3I, VR3O
−0.3 to 40
−0.3 to 16
−0.3 to 3.6
V
V
V
VCC
−0.3 to 5.5
V
Digital I/O voltage1
WAKE,EN
−0.3 to 40
V
Digital I/O voltage2
CSB, SCLK, SI, PWMIN, TXD,
TEST
−0.3 to 5.5
V
DIAG, FG, SO, RXD
−0.3 to 40
V
LIN_PWMIN
Voltage differential between
Pins are 60V or less
RF
−40 to 40
V
−3 to 3.6
V
RFSENS
−0.3 to 1.0
V
Logic power supply
5V Regulator voltage
Digital output voltage
LIN bus voltage
RF input voltage
RFSENS input voltage
TH input voltage
Voltage Tolerance
High-side output
Pins
VS
CHP
TH
−0.3 to 3.6
V
UOUT, VOUT, WOUT, COM
−3 to 40
V
UH, VH, WH
−3 to 40
V
UL, VL, WL
−3 to 16
V
SUL, SVL, SWL
−3 to 3.6
V
Voltage between HS gate
and phase
UH-UOUT,VH-VOUT,WH-WOUT
−0.3 to 40
V
Voltage between LS gate
and source
UL-SUL, VL-SVL, WL-SWL
−0.3 to 16
V
Regulator output current
Output current
VCC
UH,VH,WH,UL,VL,WL
AC(duty5%)
DIAG, FG, SO, RXD
50
50
400
10
mA
mA
*with Board
TBD
W
Low-side output
Low-side Source output
voltage
Open drain output current
Allowable Power
mA
Storage temperature
−55 to 150
°C
Junction temperature
−40 to 150
°C
*Note 2
150 to 175
°C
Note 1: Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
Note 2: Operation outside the Operating Junction temperature is not guaranteed. Operation above 150°C should not be considered without
a written agreement from ON Semiconductor Engineering staff.
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LV8907UW
ELECTRICAL CHARACTERISTICS
Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 6.0V≤VS≤20V.
Typical values at 25°C and VS=12V unless specified otherwise. (Note 3)
Parameter
Supply-voltage range
Symbol
Condition
VS
Min
Typ
Max
Unit
6
13.5
20
V
Device fully functional.
5.5
20
V
Full logic functionality, driver
stage off.
4.5
40
V
Supply current 1
Is1
V3RO=V3RI
15
25
mA
Supply current 2
Is2
Sleep Mode
40
80
µA
Operational junction
Temperature
Topj
150
°C
−40
OUTPUT BLOCK (UH, VH, WH, UL, VL, WL)
Low-side output
On-resistance 1
Low-side output
On-resistance 2
High-side output
On-resistance 1
High-side output
On-resistance 2
RON(L1)
“L” level Io=10mA
6
15
Ω
RON(L2)
“H” level Io=-10mA
12
22
Ω
RON(H1)
“L” level Io=10mA
6
15
Ω
RON(H2)
“H” level Io=-10mA
12
22
Ω
19.5
20.5
kHz
0.2
%
3.465
V
VS=6.0 to 20V
50
mV
Io=5mA to 25mA
50
mV
5.25
V
DRIVE OUTPUT BLOCK (PWM BLOCK)
Drive output
PWM frequency
fPWMO
Output PWM Duty cycle
minimum resolution
ΔPWMDUTY
PWMF=0
Low frequency mode
PWMF=0
Low frequency mode
*Note 4
Design targeted value:
512 segments
18.5
3V CONSTANT VOLTAGE OUTPUT
Output voltage
V3RO
Voltage regulation
ΔV3R1
Load regulation
ΔV3REG2
3.135
3.3
VCC 5V CONSTANT VOLTAGE OUTPUT
Output voltage
VC5RO
VS=6.0 to 20V
4.75
5.00
Voltage regulation
ΔVC5R1
VS=6.0 to 20V
50
mV
Load regulation
ΔVC5R2
Io=5mA to 25mA
50
mV
3.465
V
VCC 3V CONSTANT VOLTAGE OUTPUT
Output voltage
VC3RO
3.135
3.3
Voltage regulation
ΔVC3R1
VS=6.0 to 20V
50
mV
Load regulation
ΔVC3R2
Io=5mA to 25mA
50
mV
LOW-SIDE GATE VOLTAGE OUTPUT (VGL Pin)
Low-side output
voltage1
Low-side output
voltage2
VGLH1
VGLH2
6.0<VS<8.0V Io=−10mA
8.0<VS<24V Io=−10mA
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8.0
12.0
14.0
V
10.0
12.0
14.0
V
LV8907UW
Parameter
Symbol
Condition
HIGH-SIDE OUTPUT VOLTAGE (CHP Pin)
Internal charge pump
FCP
SSCG=0
oscillator frequency
6.0<VS<8.0V
Boost voltage1
VGHH1
Io=−10mA
8.0<VS<24V
Io=−10mA
Boost voltage2
VGHH2
Min
Typ
Max
Unit
49.6
52.1
54.6
kHz
VS
+6.0
VS
+12.0
VS
+14.0
V
VS
+9.0
VS
+12.0
VS
+14.0
V
1000
Hz
PWMIN INPUT PIN in low frequency mode
Input PWM frequency
range
Input PWM signal
period
fLPWM
TLPWMIN
5.3
fPWM=5.3Hz
188.7
ms
PWMIN INPUT PIN in High frequency mode
Input PWM frequency
range
fHPWM
18.5
kHz
DIGITAL INPUT PIN (CSB, TXD)
High-level input voltage
VIH1
Low-level input voltage
VIL1
Input hysteresis voltage
VIHYS1
0.1
Pull-up resistance.
RDVI1
15
V
0.8×V3RO
0.2×V3RO
V
0.35
0.6×V3RO
V
30
60
KΩ
DIGITAL INPUT PIN (SCLK, SI, PWMIN, TEST)
High-level input voltage
VIH2
Low-level input voltage
VIL2
Input hysteresis voltage
VIHYS2
0.1
Pull-down resistance
RDVI2
50
High-level input voltage
VIH3
2.5
Low-level input voltage
VIL3
V
0.8×V3RO
0.2×V3RO
V
0.35
0.6×V3RO
V
100
200
KΩ
WAKE INPUT PIN
Internal Pull-down
resistance
RDVI3
50
V
100
0.6
V
100
KΩ
EN INPUT PIN
High-level input voltage
VIH4
Low-level input voltage
VIL4
Input hysteresis voltage
VIHYS4
0.1
Pull-down resistance
RDVI4
50
V
0.8×V3RO
0.2×V3RO
V
0.35
0.6×V3RO
V
100
200
KΩ
0.2
V
10
µA
DIGITAL OUTPUT PIN (SO, FG, DIAG,RXD)
Output voltage
VOL
Output leakage current
ILOLK
Io=1mA
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LV8907UW
Parameter
Symbol
Condition
Min
Typ
Max
Unit
90
100
110
mV
180
200
220
mV
+10%
V
0.075
V
CURRENT LIMIT / OVER-CURRENT PROTECTION
Current mode limit voltage VRF1
Over-current detection
Voltage threshold
VRF2
Voltage between RF and
RFSENS
Voltage between RF and
RFSENS
THERMAL SENSING PROTECTION
VTH0
THTH[1:0]=00
Threshold Voltage
VTH1
THTH[1:0]=01
(Thermal error if below)
VTH2
THTH[1:0]=10
VTH3
THTH[1:0]=11
Hysteresis range
VTHHYS
0.35
−10%
0.30
0.25
0.20
0.025
0.05
THERMAL PROTECTION
*Note 4
Thermal
TTW0
warning temperature
TTW1
(Junction temperature)
125
°C
150
TSTS=0
TSTS=1
Thermal warning
temperature hysteresis
TTWHYS
*Note 4
°C
25
(Junction temperature)
*Note 4
Thermal shutdown
TTSD0
(Junction temperature)
150
temperature
TTSD1
TSTS=0
175
°C
TSTS=1
Thermal shutdown
temperature hysteresis
TTSDHYS
*Note 4
°C
25
(Junction temperature)
SUPPLY VOLTAGE DETECTION
Low-voltage detection
Low-voltage detection
hysteresis
Over-voltage detection
Over-voltage detection
hysteresis
CHP Low-voltage
detection
CHP Low-voltage
detection hysteresis
VGL Low-voltage
detection
VGL Low-voltage
detection hysteresis
VCC3.3 Low-voltage
detection
VCC3.3 Low-voltage
detection hysteresis
VCC5.0 Low-voltage
detection
VCC5.0 Low-voltage
detection hysteresis
VSLV
4.8
VSLVHYS
0.1
VSHV
20
VSHVHYS
0.5
CHPLV
0.25
1.0
VS+4.5
CHPLVHYS
0.2
VGLLV
4.5
VGLLVHYS
0.2
VCLV3
REGSEL=0,VCLVPO=0
2.3
VCLVHYS3
REGSEL=0,VCLVPO=0
0.1
VCLV5
REGSEL=1,VCLVPO=0
3.8
VCLVHYS5
REGSEL=1,VCLVPO=0
0.1
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0.4
0.4
0.25
0.25
5.1
V
0.4
V
24
V
1.5
V
VS+5.5
V
0.7
V
5.5
V
0.7
V
2.7
V
0.4
V
4.2
V
0.4
V
LV8907UW
Parameter
Symbol
Condition
Min
Typ
Max
Unit
LIN_PWMIN PIN (LIN TRANSMITTER)
LIN output current bus in
dominant state
LIN output current bus in
recessive state
Short circuit current
limitation
Internal Pull-up resistance
Ibus_pas_dom
Ibus_pas_rec
Ibus_lim
Rslave
Driver OFF
Vbus=0V,VS=7V & 18V
−1
mA
Driver OFF
Vbus=VS,VS=7V & 18V
Driver ON
Vbus=VS, VS=7V & 18V
40
VS=7V & 18V
20
30
20
uA
200
mA
47
kΩ
LIN_PWMIN PIN (LIN RECEIVER & PWMIN)
High-level input voltage
Vbusdom
VS=7V & 18V
0.6×VS
VS
V
Low-level input voltage
Vbusrec
VS=7V & 18V
0
0.4×VS
V
Input hysteresis voltage
Vbushys
VS=7V & 18V
0.05×VS
0.2×VS
V
0.396
0.5
0.5
0.581
0.417
0.5
0.5
0.59
AC characteristics LIN_PWMIN PIN
Duty cycle 1
D1
Duty cycle 2
D2
Duty cycle 3
D3
Duty cycle 4
D4
Propagation delay bus
recessive to RXD=high
Propagation delay bus
dominant to RXD=low
Symmetry of receiver
propagation delay
THrecmax=0.744VS
THdommax=0.581VS
VS=7.0V…18V, tbit=50µs
D1=tBusrecmin/(2*tbit)
THrecmin=0.422VS
THdommin=0.284VS
VS=7.6V…18V, tbit=50µs
D1=tBusrecmax/(2*tbit)
THrecmax=0.778VS
THdommax=0.616VS
VS=7.0V…18V, tbit=96µs
D1=tBusrecmin/(2*tbit)
THrecmin=0.389VS
THdommin=0.251VS
VS=7.6V…18V, tbit=96µs
D1=tBusrecmax/(2*tbit)
Trx_pdr
VS=7V & 18V
6
µs
Trx_pdf
VS=7V & 18V
6
µs
Trx_sym
trx_pdr-Trxpdf
2
µs
22.5
µs
22.5
µs
4
µs
Normal Slope rise time 12
−2
VS=12V,LINSLP=0
T_rise_norm 12
Normal Slope fall time 12
L1,L2(Note 5)
VS=12V,LINSLP=0
T_fall_norm 12
L1,L2(Note 5)
VS=12V,LINSLP=0
symmetry of Normal Slope 12
T_sym_norm 12
L1,L2(Note 5)
−4
Normal Slope rise time 3
T_rise_norm 3
VS=12V,LINSLP=0,L3(Note 5)
27
µs
Normal Slope fall time 3
T_fall_norm 3
VS=12V,LINSLP=0,L3(Note 5)
27
µs
symmetry of Normal Slope 3
T_sym_norm 3
VS=12V,LINSLP=0,L3(Note 5)
5
µs
T_rise_low
VS=12V,LINSLP=1,L3(Note 5)
62
µs
Low Slope rise time
−5
Low Slope fall time
T_fall_low
VS=12V,LINSLP=1,L3(Note 5)
62
µs
Note 3: Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Note 4: Not tested in production. Guaranteed by design.
Note 5: Load conditions Rbus/Cbus: L1=1kΩ/1nF, L2=660Ω/6.8nF, L3=500Ω/10nF Typical Operating Conditions
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LV8907UW
LV8907 CHARACTERISTIC FIGURE
Vcc at 3.3V regulator vs. load current
Vcc at 5.0V regulator vs. load current
3.50
6.00
3.00
5.00
4.00
2.00
1.50
VCC[V]
VCC[V]
2.50
VS=12V
1.00
VS=6V
0.50
VS=4V
50
100
VS=12V
2.00
VS=6V
1.00
0.00
0
3.00
VS=4V
0.00
150
0
Load Current I[mA]
50
100
Load current I[mA]
VCC at 3.3V vs. load current IVCC
VCC at 5V vs. load current IVCC
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150
LV8907UW
DETAILED FUNCTIONAL DESCRIPTON
The LV8907 integrates full sensor-less brushless DC motor commutation and Proportional/Integral (PI) speed control. A
robust startup algorithm combined with OTP registers for important system parameters make this IC a solution of choice
for many BLDC applications wich need uni-directional stand-alone operation of a motor (i.e. pump or fan). No detailed
BLDC commutation knowledge is necessary
Building a BLDC application with the LV8907 is even simpler than building a DC motor application as the IC includes a
speed controller as well. Only a PWM pulse train is necessary to control the motor – either directly or via speed control.
Switch-only applications are also possible. Speed and error information can be fed back to the control unit via FG and
DIAG outputs.
If more complex operation and flexibility are required the LV8907 can be combined with a small microcontroller to build
an externally controlled motor drive. The LV8907 implements motor commutation and includes all necessary support
circuitry for the microcontroller such as:
•
•
•
•
5V/3.3V Power supply.
Integrated watchdog timer.
LIN Transceiver.
External Temperature Sensing.
The LV8907 includes auto-run settings in case of system errors such as a missing control signal, or a watchdog error. If
one of those errors occur and connection to the microcontroller is lost, the motor can continue running at a pre-defined
fixed power level of 25%, 50%, 75% or 100%.
Motor Commutation
Motor position is detected using the BEMF of the un-driven phase of a rotating three-phase motor relative to its neutral
point connected at COM pin. Once an adequate BEMF level has been detected voltages applied via PWM to the other two
phases of the motor maintain rotation. The digital equivalent of the BEMF signal is used to generate FG in one of several
different timing arrangements set with an internal register.
Two different PWM patterns can be selected via register MRCONF12 to match motors with trapezoidal or sinusoidal
BEMF .
Figure 5: Trapezoidal vs. Sinusoidal Drive @ 50% Duty-Cycle
(CH1&3=Phase Voltage, CH2=Phase Current, CH4=Speed signal FG)
Figure 5 shows a comparison of a motor driven with normal trapezoidal commutation (left) vs. one driven with sinusoidal
drive. With sinusoidal drive the actively driven period is extended to 150 electrical degrees with soft transitioning. This
results in sinusoidal drive current with lower total harmonic distortion reducing both torque ripple and noise especially at
low to medium speeds. Trapezoidal drive results in a higher voltage across the motor phases and may be preferable for
high torque and high speed operation.
Commutation Angle Adjustment
In trapezoidal commutation mode it is possible to advance the commutation angle up to 28 electrical degrees by changing
lead angle setting via register LASET. Early commutation adjusts the rotor magnetic field positioning and allows for
higher motor speeds at the expense of efficiency. Advancing commutation is usually done dynamically which needs
active SPI communication during motor operation by a companion microcontroller.
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LV8907UW
Motor Startup
BEMF is used for rotor position sensing but for BEMF generation the motor has to be rotating. A stopped motor will
initially be driven open-loop until BEMF can be detected with minimal rotation. Open-loop operation is motor parameter
dependent. The most critical parameters being the startup frequency and PWM duty cycle (which affects motor flux
density). Both depend on startup load and both load and motor inertia. In the LV8907, the startup commutation
frequency can be programmed with settings in register MRCONF4. Flux density is regulated in this case by limiting rotor
current rather than PWM duty cycle.
To limit high starting currents in stopped motors a current ramp can be enabled with register SSTEN. During this ramp the
current limit is increased in 16 steps from 0 to the maximum current limit defined by the external shunt. A ramp time from
105ms to 6.72s is defined in register SSTT.
The startup algorithm will be applied until a valid BEMF has been detected in all three phases or the startup timer expires.
The startup timer begins after the end of the startup current ramp and can be programmed from 420ms to 6.72s in register
CPTM. If the startup timer expires a locked rotor error is flagged. In auto retry mode the LV8907 will attempt another
open-loop startup after 8 startup timer periods.
Start-up of Rotating Motors
Normally the LV8907 performs free-wheeling detection before applying the open loop startup algorithm described above.
If the motor is already turning in the right direction the IC will continue with closed loop commutation. If the motor is
turning in the wrong direction, the IC will wait for the motor to stop and then perform open-loop startup.
There are two scenarios where this behavior might not be desirable:
1.
Fast Startup is required
Free-wheeling detection takes up to one electrical revolution of the motor, which may be inacceptable for some
applications. In this case free-wheeling detection can be disabled by setting FRREN in MRCONF0[6]. Also see
section “Fast Startup” on page 19.
2.
Wind-milling backwards
Should the motor be driven by some external force as it is freewheeling in the wrong direction the LV8907 will
potentially wait forever. Should start-up under these conditions be required, free-wheeling must be disabled.
Speed Control
For stand-alone operation, the LV8907 offers a PI controller for motor speed which is activated by clearing bit SCEN in
register MRCONF0[5]. In speed control mode the IC uses the PWM inputs LIN_PWMIN or PWMIN as an selector for 9
motor speed values which are stored in 7 bit registers MRSPCT2 to MRSPCT10 as shown in Figure 6.
Figure 6: Relationship PWM Freq. Speed Register
A duty cycle of 50% with a variation band of 6.25% for example will select the motor speed value stored in the 4th speed
register which is MRSPCT6. This allows for non-linear speed curves. When using a companion microcontroller it is
possible to write to the speed register in real time during operation to achieve finer RPM resolution. For more information
see section “Target speed setting” on page 35.
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LV8907UW
The Control algorithm
The LV8907 controls the motor speed by comparing the selected target speed to the actual motor speed and incorporating
a PI controller with configurable gains.
Ramping of Speed Control Values
While tight control is required for optimal speed tracking, it may be undesirable during large input changes as it may lead
to sudden supply loading, increased noise and motor wear. To limit the slope of the control signal, register STEPSEL
(MRCONF12[7-5] imposes a ramp on an input step to slew the speed response of the motor.
Decreasing motor speed too fast results in energy recuperation back into the system. To limit overvoltage during energy
recuperation, the variable DWNSET in register MRCONF11[7,6] allows either 1) to distribute the recuperation energy
over a longer period of time or 2) to prevent energy recuperation entirely.
Motor Drive without Speed Control
In case speed control is not desired, the input PWM can control the power stage open loop if bit SCEN (MRCONF0[5]) is
set. For more information see section “PWM Input” on page 18.
Chip Activation, Shutdown and System States
After power up of VS and WAKE above 2.5V the LV8907 wakes up. Standby mode is entered after VS has exceeded
5.5V(min).
A high level on WAKE >2.5V(max) activates the IC from sleep mode which enables the internal linear regulator at V3RO.
Once the voltage on V3RO as sensed on V3RI has passed the power on reset (POR) threshold the system oscillator starts,
and after 32 counts of the system clock (3.2µs typical) releases the internal digital reset which simultaneously starts the
external regulator VCC and the charge-pump, and loads the system register contents from OTP into internal master
registers. During the entire wake-up sequence of 8ms(typ) DIAG is masked for charge-pump and VCC undervoltage.
After wake-up is complete, the IC enters Standby mode and DIAG is activated to display internal errors. During Standby
mode full SPI access is possible.
A high on EN takes the LV8907 from Standby to Normal mode. Normal mode allows motor control, and SPI access is
limited. A low on EN disables the motor stage regardless of the PWM input and returns the part back to Standby mode.
The IC is shut down by taking WAKE below 0.6V(min). WAKE has priority over the state of EN, if EN hold functionality
is desired; it needs to be implemented with an external diode from EN to WAKE.
System States
LV8907 has three operating modes. The operating modes are controlled by WAKE and EN.
Mode
WAKE
EN
Internal bias
Logic
VCC
Charge pump
Output
Sleep
L
×
Disable
Reset
Disable
Disable
Disable
Standby
H
L
Enable
Active
Enable
Enable
Disable
Normal
H
H
Enable
Active
Enable
Enable
Enable
Figure 7: Operation modes
Sleep mode
Sleep mode is a power saving mode. All circuits are powered down, charge pump is inactive and the SPI port is unusable.
Activating WAKE allows the transition from the sleep mode to either Standby or normal modes.
Standby mode
In Standby mode the OTP content has been transferred into the master-register. In this mode all outputs are turned off.
Any internal writable register that is not locked can be configured by SPI interface.
Normal mode
In normal mode, outputs can be controlled and all blocks are active. All registers can be read through the SPI interface.
Supply Voltage Transients
The LV8907 is well suited to operate during typical automotive transients. It is fully functional during start-stop
transients, as it maintains all specified parameters for supply voltages from 6V < VS < 20V. If the supply voltage falls
below 5V, for example during cold-cranking, under-voltage error is flagged, but digital functionality is maintained until
the internal regulator falls below its under-voltage lockout level of 2.2V. The VCC regulator will go into dropout and
should not be configured for 5V operation if low transient operation is desired.
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LV8907UW
If Overvoltage protection is enabled by in MRCONF10 an overvoltage error is indicated if the supply rises beyond 20V
(min.). In both under- and over-voltage error modes, the power stage drivers UH, VH, WH and UL, VL, and WL go low,
turning the external power stage high-impedance and letting the motor freewheel. The LV8907 will re-engage the motor
after conditions have returned to normal.
System Power Supplies
Three power supplies are integrated into the LV8907:
• An internal 3.3V regulator provides power to the digital and interface section.
•
The VCC regulator can be configured to provide 5V or 3.3V to an external processor and loads.
•
A dual stage charge-pump allows 100% duty-cycle operation and maintains full enhancement to the power stage
at low input voltages.
Internal Regulator V3RO, V3RI
The internal regulator is supplied from VS, provides 3.3V at V3RO, and V3RI is connected to the power supply inputs of
the control circuit blocks and logics. V3RO and V3RI need to be connected externally and bypassed to the GND plane
for stability. V3RO cannot be used for external loads.
VCC Regulator
The VCC regulator may power external loads up to 50mA(max). VCC becomes active during Standby mode and can be
configured via registers to provide 5V or 3.3V. Under-voltage error is flagged if the output voltage drops below 4.2V in
5V operation, or 2.7V in 3.3V operation.
The VCC regulator can be enabled or disabled with an internal register.
Charge Pump Circuit for CHP and VGL
LV8907 has an integrated charge pump circuit for low-side and high-side pre-driver supply. Low side is 12V and high
side is VS+12V. VGL is clamped at 12V maximum. In Normal mode CP2 is charged during switching cycle to VS and
added to VGL to provide the high side voltage supply on Cchp at CHP pin. Under voltage protection threshold for Low
side drive activates if VGL falls below 4.8V in which case the output FET’s will be turned off and an indication shown as
abnormal in an internal register. Over voltage protection threshold for High side drive activates if VS becomes greater
than 20V(min.). In the event of VS rising due to a load dump CHP is discharged to prevent output circuit destruction.
The charge pump circuit operates nominally at 52.1KHz. A SSCG function (MRCONF8[7]) is provided to add a
spread-spectrum component for EMI reduction.
CCP2
CCP1
CCHP
CVGL
Current limitation
Voltage clamping
VS
CP1P
CP1N
CP2P
VGL
CP2N
CHP
VS
Buf
Supply for
LS Pre-Drivers
Buf
Figure 8: Charge Pump circuit
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Supply for
HS Pre-Drivers
LV8907UW
CHP(V)
VGL(V)
CHP
20V
12V
VS
VGL
12V
VS
8V
VS(V)
4.8 6.0
V
V
8.0
V
VS
CP ON
under voltage CHP=VS+VGL
VS(V)
4.8 6.0
V V
21V
CP ON
CHP=VS+VGL
VS
over voltage
VS
under voltage
8.0
V
CP ON
VGL=VS*2
21V
CP ON
VGL=12V
VS
over voltage
Figure 9: High side and Low side gate voltages
PWM Input
The LV8907 will recognize two input PWM frequency ranges. PWMF bit in register MRCONF0[4] selects the input
frequency mode for either low frequency PWM or high frequency PWM.
1.
Low frequency PWM
This is the preferred mode for stand-alone operation. In this mode the input PWM frequency is checked and
minimum and maximum PWM frequency thresholds exist for more robust operation. The input PWM
frequency range is between 5.3Hz and 1kHz. The 0% and 100% duty cycle are detected as the abnormal duty
cycle. The output PWM frequency is
2.
High frequency PWM
The input PWM frequency and duty-cycle are directly fed to the power stage. This allows a companion
microprocessor direct control over duty cycle and output frequency up to 18.5kHz. No input frequency
detection takes place in this mode, so 100% and 0% duty cycle can be applied.
NOTE: It is important not to exceed 18.5kHz to maintain reliable back-EMF detection.
For stand-alone and speed control operation it is advisable to use the low PWM frequency mode. The next section applies
to low-frequency operation only.
There is an inherent delay to detect and utilize the duty cycle information. The delay time is determined by
1
𝑇𝑇𝑃𝑃𝑃𝑃𝑃𝑃 × �1 + �. If faster start-up is necessary, see section “Fast Startup” below. If no frequency is detected after
8
210ms(typ) the PWMPO flag is set in system warning register MRDIAG1. Even without PWM input the LV8907 can run
as described below in section “Fast Startup”.
If a valid frequency was detected, the LV8907 evaluates the input duty-cycle and translates it into an output duty-cycle as
shown in Figure 10Figure . Input duty cycles lower than 15% are considered a motor-off command and will also reset the
error registers.
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LV8907UW
Figure 10: In-direct Drive Mode Dutycycle Translation
Fast Startup
It may be desireable to have the motor start immediately after EN goes high. Two register settings enable motor operation
during this time: bit PDTC (MRCONF1[1]) determines if the motor should be running during this time. PDTSEL
(MRCONF3[7,6]) selects a motor duty cycle of 25, 50, 75 or 100%. This is used as the initial value of the duty cycle
command for the closed loop speed control mode. To guarantee smooth transition to PWM operation it is important to
apply a comparable PWM duty-cycle at startup. Also make sure that free-run detection is disabled (MRCONF0[6]=1) to
improve start-up speed.
Abnormal Duty Cycle Operation (100% or 0%)
For normal duty cycle controlled operation the PWM signal is expected to have a frequency between 5.3Hz and 1kHz. If
no frequency is detected, the LV8907 will flag PWMO error and enter 0% or 100% duty cycle mode depending on the
level of the PWM signal. Operation during this mode can be selected to be either no motor operation, or motor operation
at a fixed motor duty cycle of 25, 50, 75 or 100% as defined by the variables PWMFL and FLSEL or PWMZP and ZPSEL
all located in register MRCONF1.
Speed Feedback FG
The motor speed is shown with an open drain output (FG) where the transitions are direct representations of the BEMF
signal transitions on the motor. The relationship between motor rotation and FG pulses is defined in register MRCONF2 .
Fault Output DIAG
A low on open drain output DIAG indicates a system fault and a shutdown of the driver stage. Per default all system faults
self-recover when the fault condition is removed. For some potentially destructive faults such as Overcurrent, FET-Short
circuit and Locked Rotor conditions it is possible to latch the fault condition. For more information on system diagnostics
see section “System Errors and Warnings” at page 20.
LIN Transceiver
LIN_PWMIN can be used as a local interconnect network (LIN) TBD compatible LIN transceiver by setting the LINIO
bit (MRCONF0[0]) and connecting an external microcontroller to RXD and TXD. The microcontroller must handle the
LIN communication and control the LV8907 through EN, PWMIN and the SPI interface. The LIN transceiver can be
switched to low slope mode to reduce electromagnetic emissions by setting LINSLP=1 (MRCONF0[1]). For more
information on the automotive LIN bus protocol consult publicly available documentation.
Gate Drive Circuit
The gate drive circuit of the LV8907 includes 3 half-bridge drivers which control external N-Channel Fet’s for the motor
phases U, V and W. The high side drivers UH, VH, WH switch their gate connection either to CHP or the respective
phase connection UOUT, VOUT and WOUT. The low-side drivers are switched from VGL to the corresponding source
connection SUL, SVL, SWL. Both high and low side switches are Slope control has to be implemented with external
components.
Current shoot-through protection of the bridge-drivers is implemented by a dead-time counter that delays the turning-on
of the complementary switch. The dead-time can be programmed from 100ns < tFDTI < 3.2us into 5bit parameter FDTI
(MRCONF2[4:0]).
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LV8907UW
To protect against external shorts the drain-source voltage of the active external Power Fets is monitored as well. 4 bit
register FSCDL (MRCONF7[3:0]) selects a short-circuit shutoff voltage 100mV < VFSCLD < 1.6V. For more information
see section “System Errors and Warnings” on page 20. To suppress false triggering during the rising edge of Fet activation,
a four bit masking time can be programmed in FSCDT in register MRCONF7[1:0].
Current Limit and Overcurrent Shutoff
An integrated current sense amplifier implements current limiting and overcurrent shutoff by measuring the motor phase
current across a single shunt between RF and RFSENS.
Current Limit
If the voltage between RF and RFSENS exceeds VRF1=100mV(typ), the active bridge is turned off until the next PWM
period. To suppress switching transients a current limit blanking time 0.1us < tCLMASK < 1.6us can be programmed into
register MRCONF5[7:4].
During open-loop startup this current limit may be ramped from 0 to 100mV in 16 steps during a programmable time
105ms < tSSTT < 6.71s as defined in register MRCONF5[7:4].
Overcurrent Shutoff
If the bit OCPEN (MRCONF10[1]) is set and the voltage between RF and RFSENS exceeds VRF2=200mV(typ), the
LV8907 goes into overcurrent shutoff and all gate drivers are driving low turning the power FETs high-impedance. To
suppress switching transients an overcurrent limit blanking time 0.2us < tOCMASK < 3.2us can be programmed into register
MRCONF5[3:0]. For more information see section “System Errors and Warnings” on page 20.
Temperature Sensing
The LV8907 measures internal die temperature and implements internal thermal warning and shutoff. It is also possible
to protect external devices by monitoring the voltage at TH. Internal and external over-temperature shut down the driver
section. For more information see section “System Errors and Warnings” below.
Internal Over-temperature Measurement
A thermal warning is issued if the internal temperature of the device reaches approximately 25°C below the
over-temperature shutoff level. The shutoff level is selected by bit TSTS (MRCONF8[0]) as 150°C or 175°C(min).
External Over-temperature Shutoff
An analog comparator triggers external over-temperature error if the voltage at TH falls below the two bit programmable
level 0.2V < VTHTH < 0.35V as defined by register MRCONF8[2,1]. For external temperature measurement connect a
resistor between V3RO and TH and an NTC between TH and AGND. The programmed threshold voltage at VTHTH should
be reached at the intended thermal shutdown temperature of the external component to be measured. During the
over-temperature condition, the gate drivers are disabled and a flag, THPO in MRDIAG0 is set.
Watchdog Operation
The LV8907 includes a watchdog timer to monitor a companion microcontroller and disable the motor if the
microcontroller stops working properly. Bit WDTEN in register MRCONF9[7] enables and disables the watchdog timer.
Access to this bit can be blocked – see section “OTP Registers” on page 41 for details. The enabled watchdog will issue
an error whenever the watchdog time 1.64ms < tWDT < 104.96ms expires (MRCONF9[5:0]). A write of 00h to register
MRST (address 32h) resets the watchdog timer.
A watchdog timeout can result in either a motor stop, or motor operation at four predefined duty-cycles (0%, 25%, 50%,
75%, 100%) as defined by WDTP (MRCONF9[6]) and WDTSEL (MRCONF11[5,4]). The duty-cycle is directly applied
to the power stage, not through the speed selection registers. The microprocessor is not re-set.
System Errors and Warnings
All system errors and most warnings cause a transition on DIAG. The polarity of this transition can be selected in bit
DIAGSEL of register MRCONF10[0]. The ability of stand-alone applications without microcontroller to react to errors
and warnings is limited. For this case various auto-retry strategies are implemented (see Table 1).
If a companion microcontroller exists, more complex error handling is possible and DIAG should be connected to an
interrupt input of the microcontroller. Errors that may cause serious damage such as short-circuit, overcurrent and locked
rotor can be latched by enabling the corresponding latch bit in MRCONF10. In this case the LV8907 will keep the output
stage disabled until the latch is cleared by one of the following actions:
• Power on reset.
• EN low.
• Low frequency PWM less than 15% duty cycle.
• SPI write of FFh to MRRST.
If bit DLTO in register MRCONF11[0] is set ONLY latched errors will cause a transition of DIAG. To detect the other
less serious errors and warnings, the diagnostic registers MRDIAG0/MRDIAG1 have to be read regularly via SPI access.
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LV8907UW
Error
OCPO
VSLVPO
VSOVPO
CHPLVPO
VGLLVPO
FSPO
THPO
CPO
Description
Overcurrent Error
VS Undervoltage
VS Overvoltage
CHP Undervoltage
VGL Undervoltage
FET Short Circuit
TH Over-temperature
Locked Rotor
Latchable
Bit
0
1
2
3
4
5
6
7
Maskable
Table 1) Error Register: MRDIAG0[7:0]
X
X
X
X
X
X
X
X
Self Recovery when latch function turned off
After 52.4ms(typ) the motor will re-start.
Motor is re-started when voltage recovers.
Motor is re-started when voltage recovers.
Motor is re-started when voltage recovers.
Motor is re-started when voltage recovers.
After 52.4ms(typ) the motor will re-start.
Motor is re-started when temperature recovers.
Wait 8 tCPTM periods (see page 15 “Motor Startup”)
See register MRCONF10 for error activation and masking and MRCONF11 for latching options.
Warning
THWPO
1
THSPO
2
WDTPO
3
4
5
6
7
STUPO
SPCO
Internal Use
VCLVPO
PWMPO
Description
Junction Temp.
Warning
Junction
Over-temperature
Watchdog Timeout
Blankable
Bit
0
DIAG
Table 2) Warning Register: MRDIAG1[7:0]
X
X
X
X
X
X
X
Startup Operation
Feedback Operation
VCC undervoltage
PWM Input Fault
X
Effect
The IC has exceeded the warning temperature but
stays in Normal operation.
The IC has exceeded the shutoff temperature.
Drivers are shut down during over-temperature.
Driver stage continues with pre-selected
duty-cycle (0, 25, 50, 75, 100%).
The motor is running open loop.
Speed feedback control is active.
Driver stage off.
No PWM signal detected. Driver stage continues
with pre-selected duty-cycle (0, 25, 50, 75, 100%).
*An “X” in column “DIAG Blank” means that it is possible to prevent a warning from triggering DIAG see register
MRCONF10 for details.
SPI Interface
In the LV8907 the SPI Interface is used to perform general communications for status reporting, control and
programming.
Figure 11: SPI Format
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LV8907UW
SPI communications with the LV8907 follows established industry standard practices including the use of WEN and start
and stop bits as shown above. Data is transferred MSB first and both clock and data are transferred as ‘true’ data with the
higher level indicating a logical 1 or true state. When WEN is pulled down to LOW, the register data is transferred from
LV8907 to a microcontroller. And, when WEN is pulled up to HIGH, the register data is transferred from a
microcontroller to LV8907.
There are two items to be especially careful of with the general communication scheme:
(1) Communications must be full duplex and simultaneous. It is not allowed to send one transaction and then read
data on a second transaction as the status register information will be updated on the first transaction and then be
out of date for the second. Some systems break transactions into separate read and write operations which is not
acceptable.
(2) It is important the system master have the clock and data polarities and phases as shown above. Both the clock
and data on some systems can be inverted for various reasons but must arrive at the LV8907 per the above
drawing. Common errors include SCLK inversion such that the leading edge arrives as a downward transition
rather than a rising edge, or having the data to clock phase incorrect. Data phase must be such that the data only
changes during a clock falling edge and is completely stable during a clock rising edge. This means a good
margin of one half a bit time exists to eliminate transmission delay hazards.
The first byte returned on all transactions is always the status register, GSDAT., and contains information such as the busy
flag during programming operations.
GSDAT[7:0]
Bit 7
6
ORBEN
0
STUPO
x
5
4
3
2
SACF
DIAGS
LATCH
OBSY
x
0
0
1
0
0
1
1
x
0
1
Bit 0
SMOD[1:0]
1
1
0
1
0
1
1
0
1
0
1
x
Sleep mode (MRACK[7:0]=FFh)
Device start up time
Standby mode
Normal mode (MRACK [7:0]=55h)
Normal Operation
OTP busy with read/write access
Latched shutdown condition
Failure Condition
Last SPI access OK
Last SPI access failed*
Motor in Startup mode
Motor in Normal drive mode
OTP integrity test mode
The following SPI failures are detectable and reported collectively in GSDAT as general SPI failures:
•
•
•
•
•
•
•
•
Any access to an address which is not assigned.
The number of SCLK clocks is not 16 within one word transfer.
Any access to MRCONF, MRACS, ORCONF, ORACS while OBSY=1,(During write operations)
Write access to MRODL register while OBSY=1, (during write operations.)
Write access to any of the main registers after setting MSAENB=1 (Implies MRxxxx registers are locked).
Write access to any of the OTP registers after OSAENB=1 (Implies ORxxxx registers are locked). .
Write access attempt to a read only or locked register.
SI signal changed at positive edge of SCLK. (Incorrect data/sclk phase setup)
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LV8907UW
SPI Timing
90%
90%
CSB
10 %
10 %
Tcss
1 / Tfck
Tckn
90%
SCLK
10%
SI
Tckp
10 %
10%
Tsis
Tsih
90%
90%
10 %
10%
Tcsh
Tcsp
90 %
Tcssod
SO
90%
Tcksod
90 %
90%
10%
10%
10%
Tcssoz
Tcssoo
Figure 12: SPI Timing Diagram
Tj=-40 to 150°C, VS=4.5 to 20V
Pull up resistance of SO pin=2.4kΩ, Output load of SO pin=30pF
Symbol
Tfck
Tckp
Tckn
Tcss
Tcsh
Tcsp
Tsis
Tsih
Tcssod
Tcksod
Tcssoo
Tcssoz
Comment
SCLK clock frequency
SCLK high pulse width
SCLK low pulse width
CSB setup time
CSB hold time
CSB high pulse width
SI setup time
SI hold time
CSB fall edge to SO delay time
SCLK fall edge to SO delay time
CSB fall edge to SO data out time
CSB rise edge to SO Hi-Z out time
Min
Typ
Max
500
950
950
950
950
1900
450
450
950
950
0
950
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI Register Map
The SPI interface allows read access to the entire address space. Write access to the internal registers is controlled by a
number of factors:
•
System State
tbd
•
Register Access Control
The MASTER registers can only be written in Standby mode and then only if the write lock bit MSAENB has
never been set high.
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23
LV8907UW
Addr
Register
Description
Write
Enable
Standby
Mode
Normal
Mode
IC Setup Register
00h
MRCONF0
Main function
Free-run Detection ON/OFF setup
MSAENB
01h
MRCONF1
PWM Input Specification
MSAENB
02h
MRCONF2
03h
MRCONF3
04h
MRCONF4
Activation frequency setup
MSAENB
05h
MRCONF5
Current limit detection timing setup / Over current
detection setup
MSAENB
06H
MRCONF5
For Internal Use Only
MSAENB
07h
MRCONF7
08h
MRCONF8
09h
MRCONF9
0Ah
MRCONF10
0Bh
MRCONF11
0Ch
MRCONF12
Soft-start EN setup / FG output setup / Dead time
setup
PWM undetected operation mode setup Soft-start
setting
Sync rectification setup
Protection setup
FET short Protection
SSCG Protection setup Locking Protection
Overheat protection
WDT setup
MSAENB
MSAENB
MSAENB
MSAENB
MSAENB
Error / warning masks and
DIAG output setup
Speed FB operation setup at deceleration
WDT protection operation setup
Latch setup
Lead angle setup Silent drive setup
STEP at the time of changing
Speed FB target
revolution
MSAENB
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
MSAENB
Read /
Write
Read
Always OK
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Read /
Write
Speed Control Setup
10h
MRSPCT0
Proportional Gain Setup
Always OK
11h
MRSPCT1
Integral Gain Setup
Always OK
12h
MRSPCT2
3.125% Input PWM
Always OK
13h
MRSPCT3
12.5% Input PWM
Always OK
14h
MRSPCT4
25% Input PWM
Always OK
15h
MRSPCT5
37.5% Input PWM
Always OK
16h
MRSPCT6
50% Input PWM
Always OK
17h
MRSPCT7
62.5% Input PWM
Always OK
18h
MRSPCT8
75% Input PWM
Always OK
19h
MRSPCT9
87.5% Input PWM
Always OK
1Ah
MRSPCT10
96.875% Input PWM
Always OK
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24
LV8907UW
Addr
Register
Description
Write
Enable
Standby
Mode
Normal
Mode
Read
Read
Read
Read
Sytem Diagnostics and Test
20h
MRACS
Lock Bits for OTP and Main Register write
30h
MRACK
SPI Operation Diagnostics
-
31h
MRODL
OTP data READ
Always OK
32h
MRRST
For WDT/Protection Reset
Always OK
33h
MRORB
For OTP Zapping check
Always OK
34h
MRDIAG0
Protection status check
35h
MRDIAG1
Protection status check
38h
TEST1
Production test register 1
…
3C
TEST5
Production test register 5
OTP Memory Section
40h
ORCONF0
Default states of MRCONF0 – MRCONF12
…
4Ch
ORCONF12
transferred upon startup
50h
ORSPCT0
Default states of MRSPCT0 – MRSPCT10
…
5Ah
ORSPCT10
transferred upon startup
60h
ORACS
Default states of MRACS
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25
Read /
Write
Read /
Write
Read /
Write
Read /
Write
-
Read
Read
-
Read
Read
Read
Read
LV8907UW
REGISTER DESCRIPTION
Motor Configuration Register Overview
ADDR[6:0]
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
Register
Name
MRCONF0
MRCONF1
MRCONF2
MRCONF3
MRCONF4
MRCONF5
MRCONF6
MRCONF7
MRCONF8
MRCONF9
MRCONF10
MRCONF11
MRCONF12
D7
D6
D5
D4
D3
D2
D1
FRMD
FRREN
SCEN
PWMF REGSEL
VCEN
LINSLP
FLSEL[1:0]
ZPSEL[1:0]
PWMFL PWMZP PDTC
SSTEN
FGOF[1:0]
FDTI[4:0]
PDTSEL[1:0]
SSTT[5:0]
STOSC[7:0]
CLMASK[3:0]
OCMASK[3:0]
Internal Use Only
SYNCEN PPDOSEL
FSCDT[1:0]
FSCDL[3:0]
SSCG
CPTM[3:0]
THTH[1:0]
WDTEN
WDTP
WDT[5:0]
VCLVPEN
CPEN
THWEN THPEN FSPEN
OVPEN OCPEN
DWNSET[1:0]
WDTSEL[1:0]
CPLT
FSPLT OCPLT
STEPSEL[2:0]
SLMD
LASET[3:0]
D0
LINIO
PWMON
TSTS
DIAGSEL
DLTO
MRCONF0
Address = 00h
Bit 7
FRMD
Standby Mode:
Normal Mode:
6
FRREN
5
SCEN
4
PWMF
3
REGSEL
Read/Write
Read Only
2
VCEN
1
LINSLP
Bit 0
LINIO
FRMD: Forward / reverse selection
The physical motor rotation direction depends on the wiring of the three phases.
FRMD=1 reverses the motor direction.
FRREN: Free-run detection enable
Decides if the LV8907 does a BEMF detection before attempting to start the motor open-loop. See section “Motor Startup”
on page 15.
FRREN=0 Motor will start with a BEMF detection.
FRREN=1 Motor will start open loop with startup parameters.
SCEN: Speed feedback control enable
This bit selects the LV8907 internal speed feedback control or PWM pass through. Speed feedback control is ON when
SCEN=0 Speed feedback loop is active. RPM is selected from input dutycycle as shown in Firgure 6 on page 15.
SCEN=1 Power stage dutycycle is translated from input dutycycle as shown in Figure 10 on page 19.
PWMF: PWM input frequency selection
Decides the PWM input frequency range.
PWMF=0 Valid PWM input frequency from 5.3Hz to 1kHz.
PWMF=1 Valid PWM input frequency from 9.25kHz to 18.5kHz. In this mode the PWM frequency is directly fed to the
power stage. Internal speed control cannot be used.
REGSEL: VCC Voltage selection (5V/3.3V)
REGSEL=0 VCC output set to 3.3V.
REGSEL=1 VCC output set to 5V.
VCEN: VCC regulator enable
VCEN=0 VCC is off.
VCEN=1 VCC is active.
LINSLP: LIN slope mode setup
To improve EMI performance the LIN switching slope can be reduced.
LINSLP=0 Normal LIN rise-time.
LINSLP=1 Rise time increased by 1/3.
LINIO: External input system selection
LV8907 has an embedded LIN physical layer which can also be used as a PWM input channel.
LINIO=0 LIN_PWMIN is in PWM input mode.
LINIO=1 The LIN transceiver is active and the PWM signal is taken from PWMIN.
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26
LV8907UW
MRCONF1
Address = 01h
Standby Mode:
Normal Mode:
Bit 7
6
FLSEL[1,0]
5
4
3
PWMFL
ZPSEL[1,0]
Read/Write
Read Only
2
PWMZP
1
PDTC
Bit 0
PWMON
FLSEL: 100% PWM input duty cycle motor operation
If 100% PWM input duty cycle was detected (no PWM frequency) and PWMFL is set, the motor is driven with the duty
cycle programmed into FLSEL as shown in the following table.
FLSEL[1]
0
0
1
1
FLSEL[0]
0
1
0
1
Motor Duty-Cycle[%]
25
50
75
100
ZPSEL: 0% PWM input duty cycle motor operation
If 0% PWM input duty cycle is detected (no PWM frequency) and PWMZP is set, the motor is driven with the duty cycle
programmed into ZPSEL as shown in the following table.
ZPSEL[1]
0
0
1
1
ZPSEL[0]
0
1
0
1
Motor Duty-Cycle[%]
25
50
75
100
PWMFL: Operation mode selection at PWM input duty-cycle = 100%
If 100% PWM input duty cycle was detected the motor will be
PWMFL=0: turned off.
PWMFL=1: driven with the duty-cycle defined by FLSEL.
PWMZP: Operation mode selection at PWM input duty-cycle = 0%
If 0% PWM input duty cycle is detected the motor will be.
PWMZP=0: turned off.
PWMZP=1: driven with the duty-cycle defined by ZPSEL.
PDTC: Fast Startup operation mode
During the first 200ms after EN high, while the PWM signal is still being measured, the motor can be either
PDTC=0: turned off.
PDTC=1: driven with the duty-cycle defined by PDTSEL (MRCONF3[7,6])
PWMON: PWM input signal level
Decides wether the PWM input signal is active low, or active high.
PWMON=0: PWM input signal is active high.
PWMON=1: PWM input signal is active low.
MRCONF2
Address = 02h
Bit 7
SSTEN
Standby Mode:
Normal Mode:
6
5
4
3
FGOF[1,0]
Read/Write
Read Only
2
1
Bit 0
FDTI[4:0]
SSTEN: Soft-start function enable
Soft-start allows slow startup of motors with higher inertia. The soft-start algorithm ramps the current limit from 0 to max
current in 16 steps during soft-start time tSST which is programmed in register MRCONF3.
SSTEN=0 Soft-start is OFF.
SSTEN=1 Soft-start is active.
Note that soft-start typlically begins after duty-cycle detection. If no duty cycle operation is selected (PDTC=1)
Soft-start will begin after reset.
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27
LV8907UW
FGOF: FG signal output frequency selection
The FG signal is a representation of a successfully detected back-EMF transition which occurs three times during every
electrical revolution. It is possible to divide that frequency as described in the following table.
FGOF[1]
0
0
1
1
FGOF[0]
0
1
0
1
FG output mode
One transition per back-EMF detection.
One pulse per electrical revolution.
One transition every two BEMF det.
One pulse every two elec. Revolutions.
FDTI: Dead time setting
During phase switching between supply and GND it is possible for both low- and high-side drivers to be temporarily on at
the same time causing large current spikes. Register FDTI defines a dead time during which both drivers will be kept off
during these transitions.
FDTI[4]
0
0
FDTI[3]
0
0
FDTI[2]
0
0
1
1
1
1
FDTI
1
1
FDTI[1]
FDTI[0]
0
0
0
1
1
1
0
1
Dead time[us]
3.2
3.1
3.2 - FDTI/10
0.2
0.1
MRCONF3
Address = 03h
Bit 7
6
5
Standby Mode:
Normal Mode:
3
4
PDTSEL[1,0]
Read/Write
Read Only
2
1
Bit 0
SSTT[5:0]
PDTSEL: Fast Start-up motor operation.
If bit PDTC (MRCONF1[1])is set the motor is driven with the duty cycle programmed into PDTSEL as shown in the
following table, as soon as EN is high. This feature is bridging the initial 200ms of operation until a valid PWM
duty-cycle an be decoded,.
PDTSEL[1]
0
0
1
1
PDTSEL[0]
0
1
0
1
Duty[%]
25
50
75
100
SSTT: Soft-start time setting
Soft-start allows startup of motors with higher inertia by ramping the current. The soft-start algorithm divides the current
limit voltage 100mV (Typ) into 16 sections and increases the value from 6.25mV to 100mV to switch over the current
limit value. The soft start can be set from 0.1s < tSSTT < 6.71s as shown in the table below:
SSTT[5]
0
0
SSTT[4]
0
0
SSTT[3]
0
0
1
1
1
1
1
1
SSTT[2]
0
0
SSTT
1
1
SSTT[1]
0
0
SSTT[0]
0
1
1
1
0
1
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Soft-start time[s]
0.105
0.21
0.105 · (1 + SSTT)
6.615
6.72
LV8907UW
MRCONF4
Address = 04h
Bit 7
Standby Mode:
Normal Mode:
6
5
4
3
2
1
Bit 0
STOSC[7:0]
0
0
0
0
0
0
0
0
1
1
1
1
STOSC
1
1
1
1
Read/Write
Read Only
Startup commutation period
[ms]
0.82
0.82×(1+STOSC)
209.92
This register defines the rotation frequency fSTOSC at which the motor should be turned during open-loop startup. If a
BEMF signal can be detected the IC will commutate to the next energization pattern by using the zero-crossing as its
reference. If no BEMF can be detected the IC will commutate to the next energization pattern with the frequency
programmed into STOSC. Open-loop startup continues for the time programmed into CPTM (MRCONF8[6:3]) If no
BEMF is detected during that time a locked rotor error is indicated.
MRCONF5
Address = 05h
Bit 7
Standby Mode:
Normal Mode:
6
5
4
3
Read/Write
Read Only
2
CLMASK[4:0]
1
Bit 0
OCMASK[4:0]
CLMASK: Current limit mask time setting
In order to prevent noise and glitches from causing false current limiting, a mask time can be programmed.
CLMASK[3]
0
0
CLMASK [2]
CLMASK [1]
0
0
0
0
CLMASK
1
1
1
1
1
1
CLMASK [0]
0
1
Mask Time[us]
0.1
0.2
0.1+CLMASK/10
1.5
1.6
0
1
OCMASK: Over-current detection Mask time setting
The time to detect over-current can be programmed with OCMASK.
OCMASK[3]
0
0
OCMASK [2]
OCMASK [1]
0
0
0
0
OCMASK
1
1
1
1
1
1
OCMASK [0]
0
1
Mask Time[us]
0.2
0.4
0.2 · (1+OCMASK)
3.0
3.2
0
1
MRCONF6
Address = 06h
Bit 7
Standby Mode:
Normal Mode:
6
5
4
3
SROFFT[3-0]
Read/Write
Read Only
2
1
Bit 0
CRMASK[3-0]
Internal use only.
MRCONF7
Address = 07h
Standby Mode:
Normal Mode:
Bit 7
6
SYNCEN
PPDOSEL
5
4
3
FSCDT[1:0]
Read/Write
Read Only
2
1
FSCDL[3:0]
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29
Bit 0
LV8907UW
SYNCEN: Synchronous rectification enable
Defines synchronous rectification mode for the output stage. In synchronous rectification the high and low side switches
are always switched in complementary mode = if one switch is on, the other one is off . In a-synchronous rectification
both complementary switches may be off and the motor current is circling through the body diodes.
SYNCEN=0 Synchronous rectification is ON.
SYNCEN=1 Synchronous rectification is OFF.
PPDOSEL: DIAG output selection at PWM input abnormality
D6 of the main register MRCONF7 can be used to reflect abnormal detection result to DIAG pin at the time of PWM
input abnormal detection (0% or 100% detection).
PPDOSEL=0 PWM abnormal input detection result is reflected to DIAG pin when
PPDOSEL=1 and it is not reflected to DIAG pin when.
FSCDT: FET Short protection detection time setting
By monitoring FET Vds, the time from FET’s ON signal output until detecting Shorted status can be set with D5 and D4
of MRCONF7. Please refer to the table below for settable time:
FSCDT[1]
0
0
1
1
FSCDT [0]
0
1
0
1
Detection time[us]
3.2
6.4
9.6
12.8
FSCDL: FET Short protection detection voltage setting
Vds voltage to detect FET Short status can be set with D3~D0 of MRCONF7. Please refer to the table below for available
voltages:
FSCDL [3]
0
0
FSCDL[2]
0
0
1
1
1
1
FSCDL [1]
0
0
FSCDL [0]
0
1
1
1
0
1
Vth[V]
0.1
0.2
0.1+FSCDL/10
1.5
1.6
FSCDL
MRCONF8
Address = 08h
Bit 7
Standby Mode:
Normal Mode:
6
5
SSCG
4
3
CPTM[3-0]
Read/Write
Read Only
2
1
THTH[1,0]
Bit 0
TSTS
SSCG: Charge Pump Spread Spectrum
The Charge pump may have radiation noise issues due to switching at 52.1kHz(typ). By activating SSCG it is possible to
disperse frequency components of the charge pump switching frequency. The frequency will vary 20%.
SSCG=0: Spread spectrum OFF
SSCG=1: Spread spectrum ON
CPTM: Open Loop Startup Timeout
A locked rotor protection circuit is embedded in order to protect IC and Motor during locked rotor conditions. A locked
rotor is detected by counting the time the IC is in Start-up mode (without back-EMF detection) If no back-EMF is detected
for the time programmed into CPTM register the motor is turned off and a locked rotor is flagged.
In Auto recovery mode the motor will remain off for eight times the Open Loop Startup Timeout before another startup is
attempted.
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30
LV8907UW
CPTM [3]
0
0
CPTM [2]
0
0
1
1
1
1
CPTM [1]
0
0
CPTM
1
1
CPTM [0]
0
1
Detection/Restart time[s]
0.42 / 3.36
0.84 / 6.72
0.42 · (1+CPTM) / 3.36 · (1+CPTM)
6.3 / 50.4
6.72 / 53.76
0
1
THTH: External FET Temperature detection voltage setting
LV8907 has an embedded comparator to monitor the external power FET’s temperature using an external thermistor. If
the voltage at TH drops below the threshold level (shown in the table), the external over-temperature protection is
activated, the output gate driver stage is turned off and the THPO error flag is set.
THTH[1]
0
0
1
1
THTH [0]
0
1
0
1
VTH[V]
0.35
0.30
0.25
0.20
TSTS: Junction temperature warning and shutoff levels
The LV8907 monitors it’s own junction temperature to protect against over-temperature damage. Two different warning
and shut-off levels can be selected:
TSTS=0: Over-temperature warning occurs at 125℃(typ), shutdown at 150℃(typ).
TSTS=1: Over-temperature warning occurs at 150℃(typ), shutdown at 175℃(typ).
MRCONF9
Address = 09h
Standby Mode:
Normal Mode:
Bit 7
6
5
WDTEN
WDTP
4
3
Read/Write
Read Only
2
1
Bit 0
WDT[5:0]
WDTEN: Watchdog enable
This bit can enable or disable the watchdog. For increased system robustness it is possible to permanently lock access to
this bit. See OTP section for more details.
WDTEN=1 Watchdog is active.
WDTEN=0 Watchdog is disabled.
WDTP: Operation after a Watchdog error
Operation mode after a Watchdog error.
WDTP=0 Motor off.
WDTP=1 Motor is driven with the PWM duty cycle as defined by WDTSEL (MRCONF11[5,4]).
WDT: Watch dog timer setting
Writing 00h to register MRRST(Address = 32h) resets the watchdog timer. Should the watchdog timer ever reach it’s end
detection time as shown below, a Watchdog error is issued.
WDT [5]
0
0
WDT [4]
0
0
1
1
1
1
WDT [3]
WDT [2]
0
0
0
0
WDT
1
1
1
1
WDT [1]
0
0
WDT [0]
0
1
1
1
0
1
Detection Time[ms]
1.64
3.28
1.64 · (1+WDT)
103.32
104.96
MRCONF10
Address = 0Ah
Bit 7
Standby Mode:
Normal Mode:
6
5
4
3
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31
Read/Write
Read Only
2
1
Bit 0
LV8907UW
VCLVPEN
CPEN
THWEN
THPEN
FSPEN
OVPEN
OCPEN
DIAGSEL
xEN: Error and warning mask
The higher seven bit in this register allows enabling and disabling of various errors and warnings. A one in the register
masks the error, a zero activates the error. The following errors and warnings can be masked:
• VCLVPEN: VCC Undervoltage protection enable
• CPEN: Motor block protection enable
• THWEN: Thermal warning output enable
• THPEN: Thermal protection enable
• FSPEN: FET short protection enable
• OVPEN: Over-voltage protection enable
• OCPEN: Over-current protection enable
DIAGSEL: Diag output polarity selection
This bit selects the polarity of the DIAG signal
DIAGSEL=0 The DIAG pin is active low.
DIAGSEL=1 The DIAG pin is active high and draws pulldown current when off.
MRCONF11
Address = 0Bh
Bit 7
Standby Mode:
Normal Mode:
6
DWNSET[1,0]
5
4
WDTSEL[1,0]
Read/Write
Read Only
3
2
1
Bit 0
CPLT
FSPLT
OCPLT
DLTO
DWNSET: Mode setting at the time of speed feedback deceleration
During speed control mode, motor deceleration can lead to energy recuperation and temporary voltage spikes. DWNSET
allows for various degrees of energy recuperation:
• Normal Mode
Results in a tightest control and maximum energy recuperation. The application circuit has to be able to absorb
the energy generated.
• Sync OFF Mode
The motor is essentially not driven until it has reached the target speed. This does not feed any energy back into
the supply, but may take a long time if motor inertia is high and losses are low.
• Slow Response Mode
This mode is essentially imposing a slow deceleration ramp on the control speed. The energy recuperated is
similar to Normal Mode but spread over a longer period of time reducing the voltage overshoot.
DWNSET[1]
0
0
1
1
DWNSET [0]
0
1
0
1
Mode
Normal Mode
Sync OFF Mode
Slow Response Mode (PROT/32)
Normal Mode
WDTSEL: Operation mode selection after a Watchdog timeout
Bit WDTP (MRCONF9[6]) defines if a Watchdog timeout causes Halt mode (0% drive) or Drive mode. When Drive
mode is selected the motor duty-cycle is defined by WDTSEL as shown in the table below.
WDTSEL[1]
0
0
1
1
WDTSEL[0]
0
1
0
1
Duty[%]
25
50
75
100
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32
LV8907UW
xPLT: Protection Latch selection
The following errors:
Motor block, FET Short, and Over-current can cause intolerable large-current flow in the application. To prevent repeated
current flow during re-try attempts it is possible to latch these errors. The LV8907 will remain disabled until the latch is
cleared as described in section “System Errors and Warnings” on page 20.
CPLT=0 Auto recover after a motor block.
CPLT=1 Latch the IC off after a motor block.
FSPLT=0 Auto recover after a FET short.
FSPLT=1 Latch the IC off after a FET short.
OCPLT=0 Auto recover after over-current.
OCPLT=1 Latch the IC off after over-current.
DLTO: Diagnostic output mode selection
Selects which errors/warnings will actually trigger a DIAG transition.
DLTO=0: Trigger DIAG for any non-masked error or warning.
DLTO=1: Trigger DIAG only for latched errors as defined by xPLT above.
MRCONF12
Address = 0Ch
Bit 7
6
5
Standby Mode:
Normal Mode:
3
4
STEPSEL[2-0]
SLMD
Read/Write
Read/Write*
2
1
Bit 0
LASET[3-0]
*Note: This register is writeable in Normal mode.
STEPSEL: Ramp imposed on speed control changes
Sudden steps in speed targets during speed control can cause excessive current spikes, noise and wear on the mechanical
components. STEPSEL allows to impose a ramp onto the speed input changes. The target frequency is approached by
increasing or decreasing the current speed PROT by a fraction of the current speed once each electrical revolution. The
fractional component is defined by STEPSEL in register MRCONF12[7-5]. Figure 13 shows the RPM ramping response
to an input step for six different ramp settings.
Target Speed Transistion by Setting of the Register DWNSET
Example Case of 1000rpm to 5000rpm Vice Versa
PROT
PROT/2
PROT/4
PROT/8
PROT/16
PROT/32
6000
Target Speed (rpm)
5000
4000
3000
2000
1000
0
0
20
40
60
80
100
the Number of Electrical Cycle (FG counts)
120
Figure 13: Speed Control Input Ramp for different STEPSEL Settings
.
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140
LV8907UW
STEPSEL[2]
0
0
0
0
1
1
1
1
STEPSEL[1]
0
0
1
1
0
0
1
1
STEPSEL[0]
0
1
0
1
0
1
0
1
Step Mode
PROT (Current electrical speed at FG)
PROT/2
PROT/4
PROT/8
PROT/16
PROT/32
PROT
PROT
SLMD: Sinusoidal vs. trapezoidal drive mode selection
This bit selects wether the motor phases are driven with a trapezoidal or pseudo-sinosoidal signal.
SLMD=0 Trapezoidal drive with 120 degrees energization.
SLMD=1 Sinusoidal drive with 150 degrees energization.
LASET: Lead angle setting
In trapezoidal drive mode it is possible to advance the commutation point towards zero-crossing of the back-EMF singal.
This helps to achieve back-EMF field-weakening for higher rotational speeds and to compensate for delays in high speed
operation.
LASET [3]
0
0
LASET [2]
0
0
1
1
1
1
LASET [1]
0
0
LASET [0]
0
1
1
1
0
1
Lead Angle[deg]
0
1.875
LASET · 1.875
26.25
28.125
LASET
Speed Control Register Overview
ADDR[6:0]
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Register
Name
MRSPCT0
MRSPCT1
MRSPCT2
MRSPCT3
MRSPCT4
MRSPCT5
MRSPCT6
MRSPCT7
MRSPCT8
MRSPCT9
MRSPCT10
D7
-
D6
D5
D4
PX[2:0]
IX[2:0]
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D3
FGT0[6:0]
FGT1[6:0]
FGT2[6:0]
FGT3[6:0]
FGT4[6:0]
FGT5[6:0]
FGT6[6:0]
FGT7[6:0]
FGT8[6:0]
D2
D1
PG[2:0]
IG[2:0]
D0
LV8907UW
Speed control loop gain setting
Speed feedback is controlled by a PI controller, and each component of the gain can be set with MRSPCT0 and
MRSPCT1 of the main register as shown in Figure 14.
PI Controller
Pg
Reference Speed
Px
Speed Error
To Duty_Cycle Controller
Value
Actual Speed
Ig
Ix
Integrator
Gain
Value
Gain
X 1
0
1
X 7/8
1
X2
2
X 6/8
2
X4
0
X1
3
X 5/8
3
X8
4
X 4/8
4
X 16
5
X 3/8
5
X 32
6
X 2/8
6
X 64
7
X 1/8
7
CUT
Figure 14: Speed Control Algorithm
Proportional Gain can be set with PX and PG of MRSPCT0 where the total gain is the product of both components PG and
PX. Integral Gain can be set with IX, and IG of MRSPCT1 respectively.
PX, IX [2]
0
0
0
0
1
1
1
1
PX, IX [1]
0
0
1
1
0
0
1
1
PX, IX [0]
0
1
0
1
0
1
0
1
Gain
1
2
4
8
16
32
64
0
PG, IG [2]
0
0
0
0
1
1
1
1
PG, IG [1]
0
0
1
1
0
0
1
1
PG, IG [0]
0
1
0
1
0
1
0
1
Gain
1
7/8
6/8
5/8
4/8
3/8
2/8
1/8
Target speed setting
There are two ways of setting a target speed with speed control active (SCEN=0):
1. By using a companion microprocessor to write the speed value directly into the Speed Control Register via SPI.
2. By applying a low frequency PWM input which selects a target speed from the Speed Control Register.
SPI Speed Control
For SPI speed control the companion microprocessor should apply a fixed duty-cycle PWM signal to the LV8907
PWMIN pin. An input duty cycle of 12.5% would then select speed register MRSPCT3 as shown in the table below. By
writing RPM values to register MRSPCT3 via SPI, the speed can be controlled directly.
PWM Speed Control
PWM input frequency must be in Low frequency mode (PWMF=0). In this mode the PWM input duty cycle is measured
and used to select a target speed from the Speed Control Registers MRSPCT2..10. Note that 0% and 100% input duty
cycle will be flagged as a “PWM Input Fault”
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LV8907UW
Input Duty Cycle(%)
Register
(center value of the range)
0
0% Duty Operation*
(3.125)
MRSPCT2
12.5
MRSPCT3
25
MRSPCT4
37.5
MRSPCT5
50
MRSPCT6
62.5
MRSPCT7
75
MRSPCT8
87.5
MRSPCT9
(96.875)
MRSPCT10
100
100% Duty Operation*
*See page 19: Abnormal Duty Cycle Operation (100% or 0%)
There is a hysteresis of 6.25% duty cycle around each typical value resulting in the duty cycle thresholds depicted in
Figure 15.
Figure 15: Speed register vs. Input Duty Cycle
The motor speed is defined as ERPM (Electrical Revolutions Per Minute). To calculate the physical rotational speed
RPM of the motor divide ERPM by the number of pole pairs of the motor. Each of the registers selected by the input
PWM above has 7 bits to program ERPM in a piecewise exponential function as follows. To get the register values
FGT from electrical RPM use the following formulas:
•
FGT=ERPM/200 for ERPM values from 0 to 14400RPM.
•
FGT=23·Ln(ERPM)-147 for ERPM values from 14400RPM upwards.
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LV8907UW
FGT[7]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FGT[6]
0
0
0
FGT [5]
0
0
0
FGT [4]
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
X
FGT [3]
0
0
0
…
0
0
0
…
1
1
0
…
0
0
1
…
1
1
X
FGT [2]
0
1
1
FGT [1]
X
0
0
FGT [0]
X
0
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
0
1
0
1
1
X
1
1
X
0
1
X
Electrical RPM
Output Off
400
600
200 rpm steps
13000
13200
13600
400 rpm steps
17200
17600
18400
800 rpm steps
23200
24000
26000
2000 rpm steps
38000
40000
100% duty cycle
Figure 16: Speed Register Contents vs. Electrical RPM
MRACS
Address = 20h
Standby Mode:
Normal Mode:
Read Only
Read Only
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
OSAENB
MSAENB
This read-only register controls SPI access to the Master Registers and OTP Registers. Its contents are transferred from
OTP Register ORACS at device startup.
OSANEB: OTP Register access enable
Controls write access to the OTP registers.
OSAENB=0: Write access permitted.
OSAENB=1: Write access denied.
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LV8907UW
MSANEB: Master Register access enable
Controls write access to the Master registers.
OSAENB=0: Write access permitted.
OSAENB=1: Write access denied.
MRACK
Address = 30h
Standby Mode:
Normal Mode:
Read Only
Read Only
Bit 7
6
5
4
3
2
1
Bit 0
0
1
0
1
0
1
0
1
This read only register is used to check IC and SPI interface. 55h is read from this register in standby and normal mode,
FFh during sleep mode.
MRODL
Address = 31h
Standby Mode:
Normal Mode:
Bit 7
6
5
0
0
0
4
3
MRODL[7:0]
0
0
2
1
Bit 0
0
0
0
Read/Write
Read Only
OTP download
A write access of 00h to this register initiates a copy operation of OTP data to the Master Register. This register is
blocked if OBSY is high.
MRRST
Address = 32h
Bit 7
0
1
Standby Mode:
Normal Mode:
6
0
1
5
4
3
2
1
Bit 0
0
1
MRRST[7:0]
0
0
1
1
0
1
0
1
0
1
Read/Write
Read/Write
Reset Watchdog Timer
Reset Error Latch
This register is used to reset the watch dog timer or the error latch.
• Writing 00h to this register will reset the watch dog timer.
• Writing FFh will reset the Protection latch.
MRORB
Address = 33h
Standby Mode:
Normal Mode:
read/write
read Only
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
ORBEN
ORBLV
This register modifies the OTP readout threshold. After programming the OTP registers should be verified by reading
them with the readout thresholds set low and high to detect false zeros and ones. See “OTP Programming” on page 42.
ORBEN: Selects the margin read mode.
ORBEN = 0: Normal mode.
ORBEN = 1: Margin read mode.
ORBLV: Selects the OTP readout threshold.
ORBLV = 0: Low level margin check
ORBLV = 1: High level margin check
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LV8907UW
MRDIAG0
Address = 34h
Bit 7
CPO
Standby Mode:
Normal Mode:
6
THPO
5
FSPO
4
VGLLVPO
3
CHPLVPO
Read Only
Read Only
2
VSOVPO
1
VSLVPO
Bit 0
OCPO
Registers MRDIAG[0,1] contain system errors or warnings.
CPO: Locked rotor protection output
No back EMF was detected during the entire open-loop startup time as programmed in CPTM on page 30. Either the rotor
is blocked, or startup parameters are not correct. The drivers are disabled.
THPO: Thermal protection output
The external temperature sensor input TH threshold was triggered. If the voltage at pin TH is lower than programmed in
THTH on page 31 the drivers will shut down. Tie TH to V3RO to disable this function.
FSPO: FET Short protection output
The drain-source voltage threshold across one of the external power FETs has been exceeded during operation. The
threshold voltage is programmed in register FSCDL. Errors are suppressed for a blanking time as programmed in register
FSCDT, both in register MRCONF7.
For the high-side FETs this voltage is measured between pinVS and the corresponding phase connection UOUT, VOUT,
WOUT. For the low-side FETs it is measurend between the phase connection and the pins SUL, SVL and SWL. Make
sure to minimize potential voltage drops in the sense paths.
VGLLVPO: VGL Low voltage protection output
The voltage at VGL has dropped below 5.5V(max). The drivers are disabled to protect agains low gate enhancement.
CHPLVPO: CHP Low voltage protection output
The voltage between VS and VCP has dropped below 5.5V(max). The drivers are disabled to protect agains low gate
enhancement.
VSOVPO: VS Over-voltage protection output
The voltage at VS has exceeded 20V(min). The driver stage and the charge pump are disabled to protect against
overvoltage at the charge-pump.
VSLVPO: VS Low voltage protection output
The voltage at VS has fallen below 5.1V(max). The driver stage is disabled to protect against internal threshold issues.
VOCPO: Over-current protection output
The voltage between current sense pins RFSENS and RF has exceeded 200mV for longer than the overcurrent limit mask
time programmed in OCMASK in register MRCONF5 on page 29. The driver stage is disabled to protect agains damage.
MRDIAG1
Address = 35h
Standby Mode:
Normal Mode:
Read Only
Read Only
Bit 7
6
5
4
3
2
1
Bit 0
PWMPO
VCLVPO
-
SPCO
STUPO
WDTPO
THSPO
THWPO
More errors and warnings…
PWMPO: PWM input abnormal protection output
The PWM input does not oscillate with the appropriate frequency or is steady high (100%) or low (0%). Depending on the
settings in register MRCONF1 on page 27 the driver stage will turn off, or operate at a predefined duty-cycle (emergency
mode).
VCLVPO: VCC reduced voltage protection output
VCC undervoltage error. Depending on the setting of MRCONF0 on page 26 VCC is either 5V(typ) or 3.3V(typ).
Undervoltage is flagged if VCC falls below 4.2V(max) or 2.7V(max) respectively.
SPCO:
Speed error out of the range
1
SPCO = 0, when the absolute value of the speed error is equal to or less than target × 16
1
SPCO = 1, when the absolute value of the speed error is greater than target × 16
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LV8907UW
STUPO: Start-up status output
This flag indicates open-loop startup operation. No back EMF has been detected, yet.
WDTPO: Watch dog timer protection output
The watchdog has timed out. This flag will be high if the watchdog was not re-set during the time defined by MRCONF9
on page 31. If the watchdog is enabled the driver stage will either be off or run in emergency mode with the settings
defined by MRCONF11 on page 32.
Flag WDTPO is high even if the watchdog is disabled.
THSPO: Junction temperature thermal protection output
The IC temperature is too high and the drivers are shut off. The overtemperature shutoff level is defined by MRCONF8 on
page 30 to be either 150ºC(min.) or 175ºC(min.).
THWPO: Junction temperature thermal warning output
The IC temperature has exceeded the warning level. The overtemperature warning level is defined by MRCONF8 on page
30 to be either 125ºC(min.) or 150ºC(min.).
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LV8907UW
OTP Registers
The OTP Registers contain the default values of the system registers. These registers are always readable via SPI in either
Standby or Normal modes. During device startup these default values are copied from the OTP bank (SPI addresses 40h to
60h) to the Master register bank (SPI addresses 00h to 20h). The OTP registers should only be programmed once during
IC initialization, during normal operation only the Master Registers are accessed and modified. It is possible to block
programming of the OTP section by setting the OSANB bit in the ORACS Register of the OTP.
For detailed information on the content of the OTP see the corresponding Master Register descriptions in the previous
section. Master registers from 30h to 35h shown below are autonomous and have no equivalent position in the OTP as
they report various internal data and status information.
ADDR[6:0]
Bank
OTP Register
40h
0d[0]
41h
Master Register
ADDR[6:0]
ORCONF0
MRCONF0
00h
0d[1]
ORCONF1
MRCONF1
01h
42h
0d[2]
ORCONF2
MRCONF2
02h
43h
0d[3]
ORCONF3
MRCONF3
03h
44h
0d[4]
ORCONF4
MRCONF4
04h
45h
1d[0]
ORCONF5
MRCONF5
05h
47h
1d[2]
ORCONF7
MRCONF7
07h
48h
1d[3]
ORCONF8
MRCONF8
08h
49h
1d[4]
ORCONF9
MRCONF9
09h
4Ah
2d[0]
ORCONF10
MRCONF10
0Ah
4Bh
2d[1]
ORCONF11
4Ch
2d[2]
ORCONF12
50h
2d[3]
51h
Function
MRCONF11
0Bh
MRCONF12
0Ch
ORSPCT0
MRSPCT0
10h
2d[4]
ORSPCT1
MRSPCT1
11h
52h
3d[0]
ORSPCT2
MRSPCT2
12h
53h
3d[1]
ORSPCT3
MRSPCT3
13h
54h
3d[2]
ORSPCT4
MRSPCT4
14h
55h
3d[3]
ORSPCT5
MRSPCT5
15h
56h
3d[4]
ORSPCT6
MRSPCT6
16h
57h
4d[0]
ORSPCT7
MRSPCT7
17h
58h
4d[1]
ORSPCT8
MRSPCT8
59h
4d[2]
ORSPCT9
MRSPCT9
18h
19h
5Ah
4d[3]
ORSPCT10
MRSPCT10
1Ah
60h
4d[4]
ORACS
WRITE protection
MRACS
20h
_
_
_
SPI Status Register
MRACK
30h
_
_
_
Initiates a bank write
MRODL
31h
_
_
_
Watchdog Reset
MRRST
32h
_
_
_
Margin read checks
MRORB
33h
_
_
_
Diagnostic Flags
MRDIAG0
34h
_
_
_
Diagnostic Flags
MRDIAG1
35h
…corresponds to…
OTP data download
The OTP register data is typically transferred into the main registers at device startup (From sleep to standby transition).
This operation takes up to 110us. A high OBSY flag in the first returned byte during a SPI transaction indicates this.
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LV8907UW
Figure 17: OTP data download timing at startup
An OTP download can also actively be initiated by writing 00h to register MRODL. This command requires monitoring
the OBSY flag. Don't perform specific register access (MRCONF, MRSPCT, ORCONF, ORSPCT, ORACS) until the
OBSY flag is cleared.
Figure 18: OTP data download timing after an MRODL command
OTP Programming
The OTP registers can only be programmed in Standby mode and then only if the write lock bit OSAENB in the ORACS
register has never been set high. Unwritten OTP bits “zeroes” can always be programmed, but once a bit has been
programmed to a “one” it can never be erased.
Programming the OTP registers takes place in groups of 5 via 5 SPI writes to fill an OTP bank. As soon as the last of 5
bytes are received the OBSY flag will be set and and those 5 bytes are programmed permanently into the corresponding
OTP bank. The OBSY flag will de-assert at the end of the write cycle. During programming the GSDAT register should
be examined via repeated SPI accesses (MRACK is suggested) until the completion of the programming can be observed.
MRCONF, MRSPCT, ORCONF, ORSPCT, ORACS registers cannot be accessed during an OTP write cycle.
Figure 19: OTP programming timing
In order to verify that the OTP programming operation was successful. It is strongly recommended to do an OTP margin
check: To do this, the OTP Registers are uploaded manually into the Master Register bank with minimum and maximum
readout thresholds. The readout thresholds are set in register MRORB.
OTP Margin read check sequence:
1. Program OTP
2. Set OTP readout threshold “low” by setting ORBEN=1 and ORBLV=0 in register MRORB
3. Execute OTP download command by writing 00h to MRODL.
4. Verify that the Master Register contents are consistent with the programmed OTP data.
5. Set OTP readout threshold “high” by setting ORBEN=1 and ORBLV=1 in register MRORB
6. Execute OTP download command by writing 00h to MRODL.
7. Verify that the Master Register contents are consistent with the programmed OTP data.
8. Return OTP threshold to normal by setting ORBEN=0 and ORBLV=0.
9. Execute OTP download command.
10. Verify that the Master Register contents are consistent with the programmed OTP data.
Locking OTP register contents
MSAENB bit and OSAENB bit of ORACS register are used in order to prevent write-access of Main- and OTP Registers
respectively.
CAUTION: Inadvertent writing of these bits will permanently lock the corresponding register blocks from any
further write access. Should only be set at end of development cycles.
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LV8907UW
ORACS
Address = 60h
Bit 7
0
Standby Mode:
Normal Mode:
6
0
5
0
4
0
3
0
Read/Write
Read Only
2
0
1
OSAENB
Bit 0
MSAENB
This register is used in order to permanently prevent write access to the OTP and/or main registers. This register data is
transferred into MRACS register.
OSAENB D[1]:
Controls write access to the OTP registers.
OSAENB=0:
Write access permitted.
OSAENB=1:
Write access denied.
MSAENBD[0]:
This bit is used in order to prevent write access to the main registers.
MSAENB=0:
Write access permitted.
MSAENB=1:
Write access denied.
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LV8907UW
APPLICATION INFORMATION
Output drive circuit
LV8907 design is based on the assumption that the high side and low side outputs use Nch FET’s in a saturated PWM
Mode. The output FET is always in saturation when turned on eliminating operation in linear regions other than
transitions and thus minimizing power losses. Motor torque is adjusted by changing the duty cycle of the output. A
capacitor of around 0.1uF must be placed at each FET output to prevent high frequency oscillation due to layout parasitics.
If the switching speed of FET is too fast, insert serial resistors in the gate drive for slew rate control. Excessively fast turn
on of the FET can cause destructive shoot thru currents. However, if the resistors for the gate are too high, the waveform
of the gate is weakened and can lead to insufficient gate voltage even when duty cycle of the PWM is low. This may lead
to excess heat generation or breakdown of lower FET’s. Even without resistors, the same phenomenon may occur if the
gate capacitance of the FET is large. In this case, the minimum duty cycle needs to be controlled with the SOA (Safe
Operating Area) of the FET in mind. Some FETs may cause shoot thru current when the PWM duty cycle is very low.
This can be prevented by connecting a capacitor between gate and source of the high-side FET. Large capacitances may
slow down the switching speed. Both cases must be considered.
Current limit circuit
Current limit circuit threshold is determined as follows: Ithreshold = Vrf / Rf.
(Vrf = 100 mV Typ.).
Rf, the shunt resistor value, sets this limit. When (RF-RFGND) voltage is higher than 100 mV, PWM turns off to limit
peak current. By connecting RF pin and RFGND pin to both ends of nearby shunt resistor with Kelvin leads a precise
current limit value is obtained for operation. Poor layouts without Kelvin lead consideration can lead to motor vibration
and noise.
In the current limit circuit a filter circuit is embedded to prevent erroneous operation of current limit during reverse
recovery current of output diode during PWM operation. Normally the internal filter circuit is sufficient for typical
applications. In the case of abnormal operation due to reverse recovery current of diode flow for 1uSec or longer add an
external filter circuit (R, C low pass filter, etc.). Care must be taken as if this filter is too large it may delay the current
limit detection and subsequently result in circuit damage.
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LV8907UW
PACKAGE DIMENSIONS
The exposed pad must not to connect GND. It must be electrical floading node. It can contact a
heatsink.
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
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