SC420A Datasheet

SC420A
TM
High Speed, Combi-Sense , Synchronous
Power MOSFET Driver for Mobile Applications
POWER MANAGEMENT
Description
Features
The SC420A is a cost effective Dual MOSFET Driver, incorporating Semtech’s patented Combi-SenseTM technology, designed for switching High and Low side Power
MOSFETs
Step-down Switching regulators. A 30ns max
POWERinMANAGEMENT
propagation delay from input transition to the gate of
the power FET’s guarantees operation at high switching
frequencies. Internal overlap protection circuit prevents
shoot-through from Vin to GND in the main and synchronous MOSFETs.
u High efficiency
u Shutdown mode for increased power saving
u Fast rise and fall times (10ns typical with 3000pF
reducing switching losses at high frequencies without
causing thermal stress on the driver.
inductors and low cost ceramic capacitors
u Under-voltage lockout
u Low quiescent current
u MLP packaging provides superior thermal performance in a small footprint
load)
u 5V gate drive
u Ultra-low (<30ns) propagation delay (BG going low)
u Adaptive and programmable non-overlapping gate
drives provide shoot-through protection
u Floating top drive switches up to 27V
High current drive capability allows fast switching, thus u High frequency operation allows use of small
The high voltage CMOS process allows operation up to
27 Volts, making the SC420A suitable for adaptor powered applications. Under-voltage-lockout and over-temperature shutdown features are included for proper and
safe operation. The SC420A is offered in a space saving
MLP-12 package.
Applications
u High efficiency portable and notebook computers
u Battery powered applications
Conceptual Application Circuit
VIN2
D1
VIN
M1
VIN2
VIN
TG
PWM
FB
EN
Combi-Sense TM
Controller IC
GND
VIN
CO
BST
CBST
SC420A
EN
L1
VOUT
DRN
CS- CS+
BG
CDELAY
VPN
M2
CL
RVPN
CVPN
CDELAY
Figure 1
Revision: April 1, 2004
1
United States Patent No. 6,441,597
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SC420A
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
VIN2 Supply Voltage
Conditions
Min
VIN2
BST to PGND
BST to DRN
DRN to PGND
Max
Units
30
V
40
V
VIN + 2
V
V
tPULSE<100ns
-5
34
static
-2
30
TG
DRN - 0.3
BST + 0.3
V
BG
- 0.3
VIN + 0.3
V
VPN to PGND
VPN
30
V
VIN to PGND
VIN
7
V
VIN + 0.3
V
Tamb = 25 oC,TJ = 125 oC
0.66
W
Tcase = 25 oC, TJ = 125oC
2.56
EN, CO, CDELAY
- 0.3
Continuous Power Dissipation
PD
Thermal Resistance Junction to Case
θJC
3
o
C/W
Thermal Resistance Junction to
Ambient (1)
θJA
48
o
C/W
Operating Junction Temperature
Range
TJ
- 40
125
o
C
Storange Temperature Range
TSTG
- 65
150
o
C
Peak IR Reflow (10 - 40 sec)
TIRreflow
260
o
C
Note:
(1) Performance when used according to manufacturing guidelines, refer to Applications Information section for more information
Electrical Characteristics
Unless specified: -40oC < TJ < 125°C; VIN = 5V; 0V < VDRN < 25V
Parameter
Symbol
Conditions
Min
Typ
Max
Units
4.75
5
6
V
27
V
Power Supply
Supply Voltage
VIN
VIN2
Quiescent Current, Operating
(static)
IQop
CO = 0V, EN >
2.2V
2.3
Quiescent Current, Shutdown
IQsd
CO = 0V, EN = 0V
0.2
 2004 Semtech Corp.
2
mA
20
µA
United States Patent No. 6,441,597
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SC420A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: -40oC < TJ < 125°C; VIN = 5V; 0V < VDRN < 25V
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Under Voltage Lockout
Start Threshold (ramping up)
VIN
4.1
4.3
4.55
V
Hysteresis
Vhys
100
200
350
mV
Under-Voltage Lockout
Time Delay
VIN ramping up (2)
VIN ramping down
(2)
tpdhUVLO
2
µs
tpdLUVLO
2
µs
EN
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
2.0
V
0.8
V
CO
High Level Input Voltage
2.0
V
Low Level Input Voltage
0.8
V
Thermal Shutdown
Over Temperature Trip Point
(2)
Hysteresis (2)
TOTP
165
o
C
THYST
10
o
C
High Side Driver (TG)
Peak Output Current
Output Resistance(3)
(3)
IPKH
RSRC_TG
RSINK_TG
Rise Time
Fall Time
(3)
(3)
 2004 Semtech Corp.
trTG
I=
100mA
VBST-VDRN = 5V
VBST-VDRN = 5V
CL = 3nF,V BST - VDRN = 5V
tfTG
3
1.5
1.7
1.9
A
1.8
2.2
2.6
0.6
0.8
1.0
12
16
20
ns
10
14
18
ns
Ω
United States Patent No. 6,441,597
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SC420A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: -40oC < TJ < 125°C; VIN = 5V; 0V < VDRN < 25V
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Propagation Delay, TG Going
High (3)
tpdhTG
CTG = 3nF,BG = 0V
30
36
42
ns
Propagation Delay, TG Going
Low (3)
tpdlTG
CTG = 3nF,DRN = 0V
20
28
36
ns
1.8
2.0
2.2
A
1.8
2.2
2.6
0.55
0.7
0.95
Low-Side Driver (BG)
Peak Output Current
Output Resistance
(3)
(3)
IPKL
RSRC_BG
Ω
I = 100mA
RSINK_BG
Rise Time (3)
trBG
CBG = 3nF
5
10
15
ns
Fall Time (3)
tfBG
CBG = 3nF
2
5
8
ns
Propagation Delay,BG Going
High (3)
tpdhBG
C BG=3nF, DRN = 0V
21
28
35
ns
Propagation Delay,BG Going
Low (3)
tpdlBG
CBG = 3nF
20
25
30
ns
tspd
CCDELAY open
15
20
30
ns
Shoot-thru Protection (CDELAY)
Shoot-thru Protection Delay
Time (2)
Programmed Delay
CDELAY charge current
1
ICDELAY
350
500
ns/pF
650
µA
Virtual Phase Node (VPN)
Output Resistance
Leakage
RSRC_VPN
65
RSINK_VPN
90
ILEAK_VPN
VIN2=27V
Ω
600
nA
Notes:
(2) Guaranteed by design
(3) Temperature = 25OC
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SC420A
POWER MANAGEMENT
Pin Configuration
N.C.
DRN
12
TG
BST
CO
11
PGND
Top View
Ordering Information
9
2
8
3
7
5
6
Package
Temp Range (TJ)
SC420AIMLTRT(3)
MLP-12
-40° to 125°C
Note:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
10
1
4
Device (1)
BG
VIN
CDELAY
(2) This device is ESD sensitive. Use of standard ESD
handling precautions is required.
VPN
EN
VIN2
(3) Lead Free package compliant with J-STD-020B.
Qualified to support maximum IR reflow temperature of
260oC for 30 seconds.
(MLP-12)
Pin Descriptions
Pin
#
Pin
Name
1
TG
2
BST
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap
voltage for the high-side MOSFET. The capacitor value is typically between 0.1µF and 1µF (ceramic).
3
CO
Logic level PWM input signal to the SC420 supplied by external controller.
4
VIN2
Input power (VBAT) to the DC/DC converter. Used as supply reference for internal Combi-Sense TM
circuitry. Connect as close as possible to Drain of TOP switching MOSFET.
5
EN
Active high logic level input signal. A logic High enables TG and BG switching. A low level disables
outputs and reduces quiescent current to IQ SD
6
VPN
Virtual Phase Node. Connect an RC between this pin and the output sense point to Enable CombiSense TM operation.
7
Pin Function
Output gate drive for the switching (high-side) MOSFET.
The capacitance connected between this pin and GND sets the additional propagation delay for BG
CDELAY going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no capacitor is connected, the
propragation delay = 20ns.
8
VIN
Input supply for the bottom drive and the Logic. A 1µF-10µF Ceramic Capacitor must be connected
from this pin to PGND, placed less than 0.5" from SC420.
9
BG
Output drive for the synchronous (bottom) MOSFET.
10
PGND
11
N.C.
No Connect
12
DRN
This pin connects to the junction of the switching and synchronous MOSFETs . This pin can be subjected
to a -2V minimum relative to PGND without affecting operation.
Ground. Keep this pin close to the synchronous MOSFETs source.
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SC420A
POWER MANAGEMENT
Block Diagram
VIN2
VIN
VIN
VPN
VIN
VIN
VIN
BST
TG
CDELAY
STEERING/
LOGIC
OVERLAP
PROTECTION
CO
DRN
VIN
BG
PGND
Vref
BANDGAP
Vref
EN
Timing Diagram
CO
tpdl
TG
tfTG
tpdhTG
tr TG
TG
tpdh BG
tr BG
tpdl BG
tf BG
tspd
BG
tri - state
tri - state
VPN
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SC420A
POWER MANAGEMENT
Applications Information
Fig 1: Typical Applications Schematic
Fig 2: Typical SC420A components
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SC420A
POWER MANAGEMENT
Applications Information
Combi-Sense (Lossless current sense)
input supply and ground, a shoot-through condition during which both the top and bottom FET’s could be on
Combi-Sense is a method to sense the output current momentarily. The top FET is also prevented from turnon a combination of power devices. There is no sense ing on until the bottom FET is off. The top FET turn-on
resistor and the current is sensed on: Top MOSFET, bot- delay is internally set to 30ns (typical) and may be
tom MOSFET and output inductor.
programmably extended by an external capacitor on the
Cdelay pin, the delay is increased by 1ns/pf.
An internal phase node VPN sends a signal which is integrated by the Combi-Sense network. This network con- The EN (enable) pin may be used to turn both TG and BG
sists of a resistor and capacitor in series, connected drives off. This lowers power consumption by reducing
between VPN and the DRN pins. The resulting signal is the quiescent current draw of the SC420A to IQsd.
large, clean and not duty cycle sensitive. It can be used
directly for close loop current mode control and current CO Undriven
limit.
If the CO pin is undriven it will be pulled to GND by an
Fast Switching Drives
internal pull down resistor. This will switch the BG pin
high and the TG pin low.
As the switching frequency of PWM controllers is increased
to reduce power supply volume and cost, fast rise and Over Temperature Shutdown
fall times are necessary to minimize switching losses (TOP
MOSFET) and reduce dead-time (BOTTOM MOSFET) The SC420A will shutdown by pulling both driver’s low if
losses. While low Rds_On MOSFET’s present a power its junction temperature, T , exceeds 165°C. The drivJ
saving, the MOSFETs die area is larger and the effective ers will resume operation when T declines below 155oC.
J
input capacitance of the MOSFET is increased. Often a
50% decrease in Rds_On doubles the effective input Supply Voltage
gate charge, which must be supplied by the driver. The
Rds_On power savings can be offset by the switching The SC420A can operate from 4.75V to 6V. The V pin
IN
and dead-time losses with a suboptimum driver. While bypass capacitor must also be less than 0.5in away from
discrete solution can achieve reasonable drive capabil- the SC420A. The ground node of this capacitor, the
ity, implementing shoot-through, programmable delay and SC420A PGND pin and the Source of the bottom FET
other housekeeping functions necessary for safe opera- must be very close to each other, preferably with comtion can become cumbersome and costly. The SC420A mon PCB copper land with multiple vias to the ground
presents a total solution for the high-speed, high power plane (if used). The parallel Schottky (if used) must be
density applications. Wide input supply range of 4.5V- physically next to the Bottom FET’s drain and source pins.
25V allows use in battery powered applications, new high Any trace or lead inductance in these connections will drive
voltage, distributed power supplies.
current away from the Schottky and allow it to flow through
the FET’s Body diode, thus reducing efficiency.
Shoot Through Protection
Preventing Inadvertent Bottom Gate Turn-on
The control input (CO) to the SC420A is typically supplied
by a PWM controller that regulates the power supply out- At high VIN2 input voltages, (12V and greater) a fast turnput. The timing diagram demonstrates the sequence of on of the top FET creates a positive going spike on the
events by which the top and bottom drive signals are Bottom FET’s gate through the Miller capacitance, Crss of
applied. The shoot-through protection is implemented the bottom FET. The voltage appearing on the gate due to
by holding the bottom FET off until the voltage at the this spike is:
phase node (intersection of top FET source, the output
inductor and the bottom FET drain) has dropped below
Vin * Crss
1V. This assures that the top FET has turned off and
VSPIKE =
(Crss + Ciss )
that a direct current path does not exist between the
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SC420A
POWER MANAGEMENT
Applications Information (Cont.)
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous impedance of the capacitors, since dV/dT and thus the effective
frequency is very high. If the BG pin of the SC420A is very
close to the bottom FET, Vspike will be reduced depending
on trace inductance, rate of rise of current, etc.
far negative, thus causing improper operation, double pulsing or at worst driver damage. On the SC420A, the drain
node, DRN, can go as far as 2V below ground without
affecting operation or sustaining damage.
The bottom MOSFET must be selected with attention
paid to the Crss/Ciss ratio. A low ratio reduces the Miller
feedback and thus reduces Vspike. Also MOSFETs with
higher Turn-on threshold voltages will conduct at a higher
voltage and will not turn on during the spike. A zero ohm
bottom FET gate resistor will obviously help keeping the
gate voltage low during off time.
The negative voltage spikes on the phase node adds to
the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. This is of special importance
if higher boost voltages are used. If the phase node
negative spikes are too large, the voltage on the boost
capacitor could exceed device’s absolute maximum rating of 7V. To eliminate the effect of the ringing on the
boost capacitor voltage, place a 1 - 10 Ohm resistor between boost Schottky diode and VIN to filter the negative
spikes on DRN Pin. Initially populate it by 0 ohm. Alternately, a Silicon diode, such as the commonly available
1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor.
The ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 10002000pf, in parallel with Coss of the bottom FET will ofA capacitor may be added from the gate of the Bottom ten eliminate the EMI issue.
FET to its source, preferably less than 0.5in away. This
capacitor will be added to Ciss in the above equation to
Prevent Driver Overvoltage
reduce the effective spike voltage.
Ultimately, slowing down the top FET by adding boost resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the
BG driver to hold the bottom gate voltage low. It does this
at the expense of increased switching times (and switching losses) for the top FET.
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is determined by:
Fring =
Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of surface
mount MOSFETs, while increasing thermal resistance,
will reduce lead inductance as well as radiated EMI.
1
1
=
( 2 Π * Sqrt ( LST * Coss )
2π LST * COSS
-Where:
LST = The effective stray inductance of the top FET added to
trace inductance of the connection between top FET’s source
and the bottom FET’s ground connection.
COSS = Drain to Source capacitance of the bottom FET. If
there is a Schottky used, the capacitance of the Schottky is
added to this value
Although this ringing does not pose any power losses due
to a fairly high Q, it could cause the phase node to go too
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SC420A
POWER MANAGEMENT
Applications Information (Cont.)
Start-up Sequencing
Manufacturing Guidlines
Proper sequencing of the Combi-SenseTM controller and
SC420A driver during both start-up and shut-down is very
important. In general, the design must ensure that the
driver powers up (during start-up) before the controller does,
and that the driver powers down last during shut-down.
This ensures that the driver will never issue gate drive
pulses that are not well-controlled.
Detailed information on manufacturing and rework
of PCBs using the MLP package can be found in the
MLP application note “Comprehensive User’s Guide
- Micro Lead Frame Package”. Please contact your
local Semtech representative to obtain a copy of this
application note.
In general it is recommended that the Vcc’s for the CombiSense Controller and SC420A be connected to the same
(5V) supply. If the EN controls are not used (tied high)
then the UVLO settings for the controller and driver will
guarantee the proper sequencing (the SC420A maximum
UVLO value is guaranteed to be lower than the CombiSenseTM Controller minimum UVLO value).
For absolute guarantee of proper sequencing it is recommended that the EN controls be used as shown in the
following block diagram. With this arrangement the delayed PWRGD signal from the VccVID regulator is used to
enable both ICs. The Soft-Start time established for the
controller ensures it will come up well after the SC420A.
During power-down de-assertion of VID_PWRGD will ensure simultaneous disabling of the Combi-SenseTM Controller and SC420A.
V5
SYS_PWRGD
SC1403
V3
VR_ON
Vcc-CORE
VccVID Regulator
VID_PWRGD
CombiTM
Sense
Controller
EN
CO
SC420A
EN
VccPWRGD
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SC420A
POWER MANAGEMENT
Applications Information (Cont.)
COMPONENT SELECTION FOR SC420A APPLICATION:
Top Gate Resistor (Rtg)
High Side MOSFET (LSFET)
TG resistance is not generally required, as Rbst can take
care of the rising edge. We recommend one Rtg for each
HSFET only when the maximum length of the TG trace > 2
inches. Populate with 0 Ω initially.
The SC420A is usually used for low duty cycle ( ~ 10% )
applications. So the Rds (ON) of the high side MOSFET is
not a parameter of significant importance. A 10 – 25
mÙ Rds for the HSFET is acceptable depending on the
load current. Minimum Qg for the HSFET is important for
component selection. Typical range is 10 – 25 nC.
Low Side MOSFET (LSFET)
Boost Diode (Dbst)
Boost Diode as shown in the above figure is required and
should have a very low forward voltage drop. This increases
the amount of charge on Cbst capacitor.
Rds is the critical selection parameter for LSFET. IT should
be as low as possible for reduction of conduction losses
and hence increase efficiency. Typical range is 1 – 3 mÙ.
Rg is another important parameter for LSFET. It should
be as low as possible as this will give better efficiency.
Typical range 0.1 – 2 Ω. Ratio of Qgd/Qgs is third
parameter of consideration.
Delay Capacitor (Cdly)
As the duty cycle for the application increases, requirements for the two FETs become more similar; however,
switching charge will always be more important to the
HSFET since it switches into the full voltage, and the LSFET
always switching into the near zero voltage.
Decoupling capacitors (C1,C3)
Delay capacitor is not added in a typical application. This
option is useful to control the delay between the BG falling
and TG rising edges. Cdly is used for very high capacitance
LSFETs to ensure BG is below Vth of the FET before TG
turns on.
These are de-coupling capacitors present in the circuit.
Place as close to SC420A as possible. Typical rating is 1uF/
10V for C1 and 0.1uF /25V for C3.
Boost Capacitor (Cbst)
Boost capacitor is important for SC420A application as
shown in the above figure. It is a good design rule to have
boost capacitance at least 100 X the Cgs for the HSFET.
Boost Resistor (Rbst)
Boost resistance is important and depends on the layout.
We recommend always designing with the resistor as shown
in the above circuit to help minimize EMI when the HSFET
turns on. The value required is layout dependant.
Bottom Gate Resistor (Rbg)
BG resistance is normally not required, but may be needed
for damping for long BG trace runs. We recommend one
Rbg for each LSFET only when the maximum length of the
BG trace is > 1 inch. Populate with 0 Ω initially.
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SC420A
POWER MANAGEMENT
Applications Information (Cont.)
Critical Component Recommendations for SC420A application
Component
Manufacturer
Series or Part Number
High Side MOSFET, HSFET
International Rectifier
Fairchild Semiconductor
Siliconix
Infenion Technologies
Depends on Application
Low Side MOSFET, LSFET
International Rectifier
Fairchild Semiconductor
Siliconix
Infenion Technologies
Depends on Application
Boost Capacitor, Cbst
Various
X5R or better
Boost Diode, Dbst
Various
Schottky, 200mA or greater
Delay Capacitor, Cdly
Various
NPO Ceramic
Decoupling Capacitors,
C1,C3
Various
X5R or better
Critical Supplier Contacts
Company
Contact
International Rectifier
Web: http://www.irf.com/product-info/
Phone: (310) 726-8000
Panasonic
Web: http://www.panasonic.com/pic/ecg/
Phone: (201) 348-7522
IRC
Web: http://www.irctt.com
Phone: (888) 472-4376
Kernet
Web: http://www.kernet.com/
Phone: (864) 963-6300
Sanyo
Web: http://www.sanyovideo.com/
Phone: (619) 661-6835
TDK
Web: http://www.component.tdk.com/components/components.html
Phone: (847) 390-4373
Vishay/Dale
Web: http://www.vishay.com/brands/dale
Phone: (402) 564-3131
Vishay/Siliconix
Web: http://www.vishay.com/brands/siliconix
Phone: (800) 554-5565
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SC420A
POWER MANAGEMENT
Applications Information (Cont.)
result, run the TG and BG connections with a
minimum aspect ratio (length to width) of 20:1. This
results in a 50 mil trace for a one inch connection.
In addition, minimize the loop area of the gate drive
loop. This is easy with BG, since the return path for
the current is GND. In the case of TG, the return
path for drivercurrent is DRN, so run these traces
together, as closely as possible.
Fig 3: Typical Layout schematic for SC420A
Layout Guidelines
As shown in the above layout the traces used for
interconnections are not identical to each. The layout
using the above traces has significant advantages.
The traces used to interconnect C1, Dbst, Cbst, Rbst,
Vcc, GND, and Vbat are wider and heavy. This is done to
reduce the resistance and inductance of the current path.
As a result the voltage drop of the traces is significantly
reduced. This arrangement charges the Cbst capacitor
faster. Because of this, the FET gate capacitances are
also charged and discharged faster, improving the
efficiency of the system. Ceramic X7R capacitors are a
good choice for supply bypassing near the chip.
Vias represent significant inductance and are to be
avoided wherever possible. BG is especially important
because when the HSFET switches off, the high dV/
dt of the DRN node will force current into the LSFET
gate via Cgd. A large inductance in the BG trace will
prevent the driver from holding BG down at this time.
The signal level traces are not critical because the
current levels are much smaller.
Wider traces are also used for TG and BG connects. This
is essential to decrease the delay of signal through the
trace and allow rapid charge and discharge of the FET
capacitance. Inductance is usually the dominant
impedance in the time range of interest (~10ns). As a
 2004 Semtech Corp.
We can also see vias (circular dots) present in the
layout. The vias are important for interconnection
between different layers of the PCB. Also they are
important in heat transfer and aid in running the
system cooler.
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SC420A
POWER MANAGEMENT
Applications Information (Cont.)
Timing Waveforms measured in a system
The following waveforms were noted using a 3-phase SC2647 Combi-Sense™ PWM controller system. Typical operating
conditions for this system are
Input Voltage, Vin = 10 – 25V
Output Current, Iout = 0 – 52A
Output Voltage, Vout = 0.8 – 1.85V
Timing Diagram, Vin = 10V, Iout = 0, Vout = 1.45V
Timing Diagram, Vin = 10V, Iout = 10A, Vout = 1.45V
Timing Diagram, Vin = 10V, Iout = 20A, Vout = 1.45V
Timing Diagram, Vin = 10V, Iout = 30A, Vout = 1.45V
Component
Manufacturer
Series or Part Number
High Side MOSFET (each
phase)
International Rectifier
2 IRF7811AV's, total gate capacitance = 3.602 nF
Low Side MOSFET (each phase)
Fairchild Semiconductor
2 FDS7066's, total gate capacitance = 9.946 nF
Output inductor (each phase)
Panasonic
Series 2334Q, L= 700nH, RL~ 1mohm
Controller
Semtech
SC2647
List of components used for above application
 2004 Semtech Corp.
14
United States Patent No. 6,441,597
www.semtech.com
SC420A
POWER MANAGEMENT
Outline Drawing - MLP-12
 2004 Semtech Corp.
15
United States Patent No. 6,441,597
www.semtech.com
SC420A
POWER MANAGEMENT
PCB FOOTPRINT - MLP-12
SC420A Footprint
Note:
This land pattern is for reference purposes only. Consult your manufacturing group to ensure you meet your
company’s manufacturability guidelines.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2004 Semtech Corp.
16
United States Patent No. 6,441,597
www.semtech.com