SC1205H Datasheet

SC1205H
High Speed Synchronous Power
MOSFET Driver
PRELIMINARY
POWER MANAGEMENT
Description
Features
K Higher efficiency (>90%)
K Fast rise and fall times (15ns typical with 3000pf
The SC1205H is a cost effective, High Drive Voltage,
Dual MOSFET Driver designed for switching High and Low
side Power MOSFETs. Each driver is capable of Ultrafast rise/fall times as well as a 20ns max propagation
delay from input transition to the gate of the power FET’s.
An internal Overlap Protection circuit prevents shootthrough from Vin to GND in the main and synchronous
MOSFETs. The Adaptive Overlap Protection circuit ensures the Bottom FET does not turn on until the Top FET
source has reached a voltage low enough to prevent
cross-conduction.
load)
KHigher gate drive voltage (8V) for optimum
MOSFET RDS_ON at minimum switching loss
K Ultra-low (<20ns) propagation delay (BG going low)
K 5 Amp peak drive current
K Adaptive non-overlapping gate drives provide
K
K
K
K
K
Higher gate voltage drive capability of 8V (top and
bottom) optimally reduces Rds_on of power MOSFETs
without excessive driver and FET switching losses. The
high current drive capability (5A peak) allows fast switching, thus reducing switching losses at high (up to 1MHz)
frequencies without causing thermal stress on the driver.
shoot-through protection
Floating top drive switches up to 18V
Under-voltage lock-out
Over-temperature shutdown
Less than 10µA supply current when EN is low
Low cost
Applications
K
K
K
K
K
The high voltage CMOS process allows operation from 518 Volts at top MOSFET drain, thus making SC1205H
suitable for battery powered applications. Connecting
Enable pin (EN) to logic low shuts down both drives and
reduces operating current to less than 10µA.
Intel PentiumTM power supplies
AMD AthlonTM and K8TM power supplies
High efficiency portable and notebook computers
Battery powered applications
High frequency (to 1.0 MHz) operation allows use
of small inductors and low cost caps in place of
electrolytics
An under-voltage-lock-out and overtemperature shutdown feature is included to guarantee proper and safe
operation. The SC1205H is offered in a standard SO-8
package.
Typical Application Circuit
2.5m
Vin 5-12V
2200uf
10u,CER
10nf
+8V
10
70N03
1
VID4
VCC
16
BST
TG
2
VID3
BGOUT
+8V
15
VS
DRN
70N03
3
VID2
OC+
14
EN
BG
4
VID1
OUT1
13
CO
SC1205H
5
6
VID0
OUT2
ERROUT
OC-
12
GND
1.5V,40A
11
70N03
7
Rf
8
FB
UVLO
RREF
GND
10
BST
+8V
9
TG
VS
DRN
70N03
EN
Rref
BG
SC2422B
CO
Ri
Revision 2, June 2002
SC1205H
1
GND
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
VCC Supply Voltage
Maximum
Units
VIMAXSW
11
V
BST to PGND
VMAXBST-PGND
30
V
BST to DRN
VMAXBST-DRN
11
V
DRN to PGND
VMAXDRN-PGN
-2 to 25
V
tPULSE < 100ns
-5 to 25
V
tPULSE < 20ns
-10 to 25
DRN to PGND Pulse
Conditions
VMAXPULSE
VMAXOVP S-PGND
12
V
Input Pin
CO
-0.3 to 12
V
Continuous Power Dissipation
PD
0.66
2.56
W
Thermal Resistance Junction to Case
θJ C
40
°C/W
Thermal Resistance Junction to Ambient
θJ A
150
°C/W
Operating Temperature Range
TJ
0 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 Sec.
TLEAD
300
°C
EN to PGND
Tamb = 25°C, TJ = 125°C
Tcase = 25°C, TJ =125°C
Note:
(1) Specification refers to application circuit in Figure 1.
Electrical Characteristics
Unless specified: -0 < θJ < 125°C; VCC = 5V; 4V < VBST < 26V
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V CC
V CC
4.2
5
9.0
V
Iq_op
VCC = 5V, CO = OV
Iq_stby
EN = OV
Pow er Supply
Supply Voltage
Quiescent Current, Operating
Quiescent Current
1
mA
10
µA
4.75
V
Under Voltage Lockout
Start Threshold
Hysteresis
 2002 Semtech Corp.
4.2
VSTART
4.4
0.05
VhysUVLO
2
V
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: -0 < θJ < 125°C; VCC = 5V; 4V < VBST < 26V
Parameter
Symbol
Conditions
Min
Typ
Max
Units
CO
High Level Input Voltage
VIH
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
V C C = 9V
2.0
V
2.65
V
0.8
V
EN
High Level Input Voltage
VIH
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
V C C = 9V
2.0
V
2.2
V
0.8
V
Thermal Shutdow n
Over Temperature Trip Point
TOTP
165
°C
Hysteresis
THYST
10
°C
IPKH
3
A
High Side Driver
Peak Output Current
Output Resistance
RsrcTG
RsinkTG
duty cycle < 2%, tpw < 100 µs,
TJ = 125°C, VBST - VDRN = 4.5V,
VTG = 4.0V (src) +VDRN
or VTG = 0.05V (sink) +VDRN
1
Ω
.7
Low -Side Driver
Peak Output Current
Output Resistance
IPKL
RsrcBG
RsinkBG
duty cycle < 2%, tpw < 100 µs,
TA = 25°C,
VV S = 4.6V, VBG = 4V (src),
or VLOWDR = 0.5V (sink)
3
A
1.2
Ω
1.0
Ω
AC Operating Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Rise Time
trTG1
CI = 3nF, VBST - VDRN = 8V
14
ns
Fall Time
tfTG
CI = 3nF, VBST - VDRN = 8V
12
ns
Propagation Delay Time,
TG Going High
tpdhTG
CI = 3nF, VBST - VDRN = 8V
20
ns
Propagation Delay Time,
TG Going Low
tpdlTG
CI = 3nF, VBST - VDRN = 8V
15
ns
High Side Driver
 2002 Semtech Corp.
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SC1205H
PRELIMINARY
POWER MANAGEMENT
AC Operating Specifications (Cont.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Low -Side Driver
Rise Time
trBG
CI = 3nF, V
V S
= 8V
15
ns
Fall Time
trBG
CI = 3nF, V
V S
= 8V
13
ns
Propagation Delay Time
BG Going High
tpdhBGHI
CI = 3nF, V
V S
= 8V
12
ns
Propagation Delay Time
BG Going Low
tpdlBGHI
CI = 3nF, V
V S
= 8V
7
ns
Under-Voltage Lockout
V_5 ramping up
tpdhUVLO
EN is High
10
µs
V_5 ramping down
tpdLUVLO
EN is High
10
µs
Note:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Timing Diagrams
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Top View
(1)
P ackag e
Temp Range (TJ)
SO-8
0° to 125°C
SC1205HSTR
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(SO-8)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
DRN
2
TG
3
BST
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the
floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically
between 0.1µF and 1µF (ceramic).
4
CO
TTL-level input signal to the MOSFET drivers.
5
EN
When high, this pin enables the internal circuitry of the device. When low, TG and BG
are forced low and the supply current (5V) is less than 10µA.
6
VS
5V-9.0V supply. A .22-1µF ceramic capacitor should be connected from 5V to PGND
very close to this pin.
7
BG
Output drive for the synchronous (bottom) MOSFET.
8
PGND
This pin connects to the junction of the switching and synchronous MOSFETs . This pin
can be subjected to a -2V minimum relative to PGND without effecting operation.
Output gate drive for the switching (high-side) MOSFET.
Ground. Keep this pin close to the synchronous MOSFETs source.
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Block Diagram
Applications Information
Theory of Operation
SC1205H is the higher gate drive voltage version of it
predecessor, the SC1205. It is designed for optimum
enhancement of Low Rds_On power MOSFET’s with ultra-low rise/fall times and propagation delays. Higher
MOSFET enhancement has been made possible by optimally increasing the gate drive voltage while maintaining
low switching losses at minimum RDS_ON. The SC1205H
is designed for a gate drive voltage of 8V, without compromising features that allow fast switching and low propagation delays.
costly. The SC1205H presents a total solution for the
high-speed, high power density applications. Wide input
supply range of 4.5V-18V allows use in battery powered
applications, new high voltage, distributed power servers.
Shoot Through Protection
The control input (CO) to the SC1205H is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 6). The timing diagram demonstrates the sequence
of events by which the top and bottom drive signals are
applied. The shoot-through protection is implemented
by holding the bottom FET off until the voltage at the
phase node (intersection of top FET source, the output
inductor and the bottom FET drain) has dropped below
1V. This assures that the top FET has turned off and
that a direct current path does not exist between the
input supply and ground, a shoot-through condition during which both the top and bottom FET’s could be on
momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally
set to 20ns (typical).
The EN (enable) pin may be used to turn both TG and BG
drives off. This would allow lower power operation by
reducing the quiescent current draw of the SC1205H to
less than 10µA.
Fast Switching Drives
As the switching frequency of PWM controllers is increased
to reduce power supply volume and cost, fast rise and
fall times are necessary to minimize switching losses (TOP
MOSFET) and reduce dead-time (BOTTOM MOSFET)
losses. While low Rds_On MOSFET’s present a power
saving in I2R losses, the MOSFETs die area is larger and
the effective input capacitance of the MOSFET is increased. Often a 50% decrease in Rds_On doubles the
effective input gate charge, which must be supplied by
the driver. The Rds_On power savings can be offset by
the switching and dead-time losses with a suboptimum
driver. While discrete solution can achieve reasonable
drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Applications Information (Cont.)
LAYOUT GUIDELINES
Preventing Inadvertent Bottom FET Turn-on
As with any high speed , high current, switching regulator
circuit, proper layout is critical in achieving optimum performance of the SC1205H. The Evaluation board schematic (Refer to figure 6) shows a two-phase synchronous
design with all surface mountable components.
At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the Bottom FET’s gate through the Miller capacitance, Crss of
the bottom FET. The voltage appearing on the gate due
to this spike is:
Tight placement and short, wide traces must be used in
layout of The gate drives, DRN, and especially PGND pin.
The top gate driver supply voltage is provided by
bootstrapping the boost supply and adding it to the phase
node (DRN) voltage. Since the bootstrap capacitor supplies the charge to the top gate, it must be less than .5”
away from the SC1205H. Ceramic X7R capacitors are a
good choice for supply bypassing near the chip.
Supply Voltage
The Vcc supply must be derived from a voltage that does
not vary significantly with output load. This is especially
true if the MOSFET drain voltage is a +5V supply bus and
the Vcc of the SC1205H is connected to +5V. As the
load increases, or during sudden load transients, the 5V
supply dips significantly due to trace resistance and inductance. If the Vcc of the SC1205H is derived from
the end of this +5V bus, the drop in the +5V can cause
the Vcc to fall lower than the required under voltage lockout threshold of the SC1205H and cause intermittent
drive shutdown. To avoid this occurrence, connect the
Vcc of the SC1205H to the beginning point of the +5V
bus with a separate trace, directly to the input connector.
The Vcc pin bypass capacitor must also be less than .5”
away from the SC1205H. The ground node of this capacitor, the SC1205H PGND pin and the Source of the
bottom FET must be very close to each other, preferably
with common PCB copper land with multiple vias to the
ground plane (if used). The parallel Schottky (if used)
must be physically next to the Bottom FET’s drain and
source pins. Any trace or lead inductance in these connections will drive current way from the Schottky and
allow it to flow through the FET’s Body diode, thus reducing efficiency.
 2002 Semtech Corp.
V SPIKE =
Vin * crss
( Crss + ciss
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1205H
is very close to the bottom FET, Vspike will be reduced
depending on trace inductance, rate of rise of current,
etc.
While not shown in Figure 6, a capacitor may be added
from the gate of the Bottom FET to its source, preferably
less than .5” away. This capacitor will be added to Ciss
in the above equation to reduce the effective spike voltage.
The bottom MOSFET must be selected with attention
paid to the Crss/Ciss ratio. A low ratio reduces the Miller
feedback and thus reduces Vspike. Also MOSFETs with
higher Turn-on threshold voltages will conduct at a higher
voltage and will not turn on during the spike. The MOSFET
shown in the schematic (Figure 6) has a 2 volt threshold
and will require approximately 4.5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A
zero ohm bottom FET gate resistor will obviously help
keeping the gate voltage low during off time.
Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. It
does this at the expense of increased switching times
(and switching losses) for the top FET.
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Applications Information (Cont.)
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is determined by:
Fring =
Prevent Driver Overvoltage
The negative voltage spikes on the phase node adds to
the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. This is of special importance
if higher boost voltages are used. If the phase node
negative spikes are too large, the voltage on the boost
capacitor could exceed device’s absolute maximum rating of 12V. To eliminate the effect of the ringing on the
boost capacitor voltage, place a 4.7 - 10 Ohm resistor
between boost Schottky diode and Vcc to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such
as the commonly available 1N4148 can substitute for
the Schottky diode and eliminate the need for the series
resistor.
Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or
other surface mount MOSFETs while increasing thermal
resistance, will reduce lead inductance as well as radiated EMI.
1
( 2 Π * Sqrt (L ST * Coss )
-Where:
Lst = The effective stray inductance of the top FET added
to trace inductance of the connection between top FET’s
source and the bottom FET’s drain added to the trace
resistance of the bottom FET’s ground connection.
Coss = Drain to source capacitance of bottom FET. If
there is a Schottky used, the capacitance of the Schottky
is added to this value.
Although this ringing does not pose any power losses due
to a fairly high Q, it could cause the phase node to go too
far negative, thus causing improper operation, double
pulsing or at worst driver damage. On the SC1205H,
the drain node, DRN, can go as far as 2V below ground
without affecting operation or sustaining damage.
Over Temperature Shutdown
The SC1205H will shutdown by pulling both driver if its
junction temperature, TJ, exceeds 165°C.
The ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 10002000pf, in parallel with Coss of the bottom FET can often eliminate the EMI issue.
 2002 Semtech Corp.
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Typical Performance Plots
Figure 1: Rise and fall time and propagation delay of SC1205H
SC1205H Rise Time and Fall Time
Vin = 5V
Vcc/Vbst = 8V
I out = 20A
Chan. 1 = CO pin
Chan. 2 = Top gate
Chan. 3 = Phase node
Chan. 4 = Bottom gate
See Schematic, Figure 6
Figure 2: Rise and fall time and propagation delay of SC1205H
SC1205H Rise Time and Fall Time
Vin = 5V
Vcc/Vbst = 8V
I out = 20A
Chan. 1 = CO pin
Chan. 2 = Top gate
Chan. 3 = Phase node
Chan. 4 = Bottom gate, Propagation
delay between CO pin and Bottom
Gate = 14ns
See Schematic, Figure 6
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Figure 3: Rise and fall time and propagation delay of SC1205H, driving two top
and two bottom FETs, All FETS , FDB7030BL
Rise and fall time of gate drives of the SC1205H with
VCC = VBST = +8V.
Ch1:Top gate drive, Ch2:Bottom Gate drive
Note that these rise and fall times are achieved while
driving 2X FDB7030BL MOSFETs on top and 2X
FDB7030BL on the bottom (synchronous).
Vin = 5V
Vcc = Vbst = 8V
Iout = 20A/phase
All gate drive resistors are set to zero for this test.
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SC1205H
POWER MANAGEMENT
Figure 4: SC1205H driving a 3nF capacitive load. VCC = VBOOST = 8V.
PRELIMINARY
SC1205H
Timing Delay
Chan. 1 = Top gate
Fall time
Chan. 2 = Bott. Gate rise time
Chan. 3 = CO pin going low
Figure 5: SC1205H driving a 3nF capacitive load. VCC = VBOOST = 8V.
SC1205H
Propagation Delay
Chan. 1 = Top gate
Fall time
Chan. 3 = CO pin going low
 2002 Semtech Corp.
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 2002 Semtech Corp.
S1
12
820uf,16V
C34
10k
100K
C6
6.49k
R17
R19
26.7k
C25
100pf
R11
R10
ENABLE
EN
820uf,16V
C10
10u,CER
RREF
FB
U2
local gnd
SC2422A
ERROUT
VID0
VID1
VID2
VID3
VID4
11.5k
R14
8
7
6
5
4
3
2
1
C13
1uf
R2
10
VCC
R1
.005
GND
UVLO
OC-
OUT2
OUT1
OC+
BGOUT
^
Install resistor to limit voltage rise on boost
capacitor due to large phase node negative
spikes.
8
7
6
5
4
3
2
1
820uf,16V
C7
Vout/Clk switch
9
10
11
12
13
14
15
16
1u,16V
C9
INPUT
1
2
3
4
5
6
J1
+5V
9
10
11
12
13
14
15
16
X
*
10
C21
10.0K
R33
R32
24.3K
C11
R30
133
R31
100
22nf
.1
C18
1uf
R3
VIN
4
5
6
C26
1uf
4
E N5
6
10k
R20
4.7-10 ohm
^
EN
+8V
4.7-10 ohm
^
3
8
1
R18
8
SC1205H
CO
EN
VS
U3
LL42
D6
SC1205H
CO
EN
VS
LL42
U1
3
D7
C1
1uf
GND
BG
TG
BST
DRN
GND
BG
TG
BST
DRN
7
1
2
7
1
2
C4
1uf
VCORE
R13
0
0
R9
R8
0
R5
0
Q5
FDB7030BL
Q4
FDB7030BL
Vin
Q3
FDB7030BL
Q1
FDB7030BL
Vin
L2
TTIB1106-708
C22
1uf
L1
1uf
C15
TTIB1106-708
1.7V
10u,CER
C31
10u,CER
C29
10u,CER
C28
10u,CER
C24
10u,CER
C23
10u,CER
C20
10u,CER
C19
10u,CER
C17
10u,CER
C16
820uf,16V
C35
820uf,16V
C14
820uf,16V
C12
820uf,16V
C5
820uf,OS
C33
SC1205H
POWER MANAGEMENT
Evaluation Board Schematic - SC1205H
PRELIMINARY
Figure 6: Microprocessor Core Supply
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SC1205H
PRELIMINARY
POWER MANAGEMENT
Outline Drawing - SO-8
Land Pattern - SO-8
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2002 Semtech Corp.
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