SEMTECH SC1405B

SC1405B
High Speed Synchronous Power
MOSFET Smart Driver
POWER MANAGEMENT
Description
Features
The SC1405B is a Dual-MOSFET Driver with an internal
Overlap Protection Circuit to prevent shoot-through. Each
driver is capable of driving a 3000pF load in 15ns rise/
fall time and has ULTRA-LOW propagation delay from input transition to the gate of the power FET’s. Adaptive
Overlap Protection circuit ensures that the synchronous
FET does not turn on until the top FET source has reached
a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate
transitioning high is externally programmable via a capacitor to minimize dead time. The bottom FET may be
disabled at light loads by keeping S_MOD low to trigger
asynchronous operation, thus saving the bottom FET’s
gate drive current and inductor ripple current. An internal voltage reference allows threshold adjustment for
an Output Over-Voltage protection circuitry, independent
of the PWM controller.
Under-Voltage-Lock-Out circuit is included to guarantee
that both driver outputs are off when Vcc is less than or
equal to 4.4V (typ) at supply ramp up (4.35V at supply
ramp down). A CMOS output provides status indication
of the 5V supply. A low enable input places the IC in standby mode, reducing supply current to less than 10µA.
SC1405B is offered in a high pitch (.025” lead spacing)
TSSOP package.
‹ Fast rise and fall times (15ns with 3000pf load)
‹ 14ns max. Propagation delay (BG going low)
‹ Adaptive and programmable shoot-through
protection
Wide input voltage range (4.5-25V)
Power saving asynchronous mode control
Output overvoltage protection/overtemp shutdown
Under-Voltage lock-out and power ready signal
Less than 10µA stand-by current (EN=low)
Improved drive version of SC1405TS
High frequency (to 1.2MHz) operation allows use of
small inductors and low cost capacitors in place of
electrolytics
‹
‹
‹
‹
‹
‹
‹
Applications
‹ High Density/Fast transient microprocessor power
supplies
‹ Motor Drives/Class-D amps
‹ High efficiency portable computers
Typical Application Circuit
INPUT POWER, 5-20V
+
+
MTB75N03
75A,30V
Vcc
10uF,6.3V
5817
+
.1uF
8
3
<<
P_READY
>>
PWM IN
(20KHz-1MHz)
+
47pF
7
2
4
6
1
.22uF
14
13
[email protected]
2.2
12
SC1405
11
10
5
+
+
+
MTB75N03
75A,30V
9
2.2
<< DSPS_DR
Over-Voltage Sense
<<< Output Feedback to PWM
Controller
Revision: January 13, 2004
1
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SC1405B
POWER MANAGEMENT
Absolute Maximum Ratings
Parameter
Symbol
Maximum
Units
VMAXSV
7
V
BST to PGND
VMAXBST-PGND
30
V
BST to DRN
VMAXBST-DRN
8
V
DRN to PGND
VMAXDRN-PGN
-2 to 25
V
-5 to 25
V
VMAXOVP SPGND
10
V
Input Pin
CO
-0.3 to 8.3
V
Continuous Power Dissipation
Pd
0.66
2.56
W
Thermal Impedance Junction to Case
θJ C
40
°C/W
Thermal Impedance Junction to Ambient
θJ A
150
°C/W
Operating Temperature Range
TJ
0 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 Sec.
TLEAD
300
°C
VCC Supply Voltage
DRN to PGND Pulse
Conditions
VMAXPULSE
OVP_S to PGND
tPULSE < 100ns
TAMB = 25°C, TJ = 125°C
TCASE = 25°C, TJ = 125°C
NOTE:
(1) Specification refers to application circuit in Figure 1.
Electrical Characteristics - DC Operating Specifications
Unless specified: -0 < θJ < 125°C; VCC = 6V; 4V < VBST < 26V
Parameter
Symbol
Conditions
Min
Typ
Max
Units
4.15
5
6.0
V
10
µA
Pow er Supply
Supply Voltage
Quiescent Current
V CC
Iq_stby
E N = 0V
Iq_op
VCC = 5V, CO = 0V
High Level Output Voltage
VOH
VCC = 4.6V, lload = 10mA
Low Level Output Voltage
VOL
VCC < UVLO threshold,
lload = 10µA
IO_SINK
VPRDY = 0.4V
Quiescent Current, operating
1
mA
4.55
V
PR D Y
Sink Current
 2004 Semtech Corp.
2
4.5
0.1
5
10
0.2
V
mA
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SC1405B
POWER MANAGEMENT
Electrical Characteristics - DC Operating Specifications
Parameter
Symbol
Conditions
Min
High Level Output Voltage
VOH
VCC = 4.6V, Cload = 100pF
4.15
Low Level Output Voltage
VOL
VCC = 4.6V, Cload = 100pF
Typ
Max
Units
D S P S _D R
V
0.05
V
4.6
V
Under Voltage Lockout
Start Threshold
Hysteresis
Logic Active Threshold
VSTART
4.2
VhysUVLO
4.4
0.05
V AC T
V
1.5
V
1.255
V
Overvoltage Protection
Trip Threshold
Hysteresis
VTRIP
1.145
1.2
0.8
VhysOVP
V
S_MOD
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
2.0
V
0.8
V
Enable
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
2.0
V
0.8
V
CO
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
2.0
V
0.8
V
Thermal Shutdow n
Over Temperature Trip Point
TOTP
165
o
C
Hysteresis
THYST
10
o
C
IPKH
3
A
1
Ω
High-Side Driver
Peak Output Current
Output Resistance
RsrcTG
RsinkTG
duty cycle < 2%, tpw < 100µs,
TJ = 125°C, VBST - VDRN = 4.5V,
VTG = 4.0V (src)+VDRN
or VTG = 0.5V (sink)+VDRN
.7
Low -Side Drive
Peak Output Current
Output Resistance
IPKL
RsrcBG
RsinkBG
 2004 Semtech Corp.
duty cycle < 2%, tpw < 100µs,
TJ = 125°C,
VV S = 4.6V,
VBG = 4V (src)
or VLOWDR = 0.5V (sink)
3
3
A
1.2
Ω
1.0
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SC1405B
POWER MANAGEMENT
Electrical Characteristics - AC Operating Specifications
Parameter
Symbol
Conditions
rise time
trTG1
fall time
Min
Typ
Max
Units
CI = 3nF, VBST - VDRN = 4.6V,
14
23
ns
tfTG
CI = 3nF, VBST - VDRN = 4.6V,
12
19
ns
propagation delay time,
TG going high
tpdhTG
CI = 3nF, VBST - VDRN = 4.6V,
C-delay=0
20
32
ns
propagation delay time,
TG going low
tpdlTG
CI = 3nF, VBST - VDRN = 4.6V,
15
24
ns
High Side Driver
Low -Side Driver
rise time
trBG
CI = 3nF, V
V S
= 4.6V,
15
24
ns
fall time
trBG
CI = 3nF, V
V S
= 4.6V,
13
21
ns
propagation delay time,
BG going high
tpdhBGHI
CI = 3nF, VBST - VDRN = 4.6V,
C-delay=0
12
19
ns
propagation delay time,
TG going low
tpdlBG
CI = 3nF, V V S = 4.6V,
DRN <1V
7
12
ns
V_5 ramping up
tpdhUVLO
EN is High
10
us
V_5 ramping down
tpdhUVLO
EN is High
10
us
EN is transitioning from low to
high
tpdhPRDY
V_5 >UVLO threshold, Delay
measured from EN > 2.0V to
PRDY > 3.5V
10
µs
EN is transitioning fro high to low
tpdhUVLO
V_5 >UVLO threshold, Delay
measured from EN < 0.8V to
PRDY < 10% of V_5V
500
µs
trDSPS DR.
CI = 100 pf, V_5 = 4.6V
20
ns
propagation delay, DSPS_DR
going high
tpdhDSPS DR
S_MOD goes high and BG
goes high or S_MOD goes low
10
ns
propagation delay, DSPS_DR
goes low
tpdlDSPS DR
S_MOD goes high and BG
goes low
10
ns
tpdhOVP S
V_5 + 4.6V, TJ = 125OC,
OVP_S > 1.2V to BG > 90%
of V _5
1
µs
Under-Voltage Lockout
PR D Y
D S P S _D R
rise/fall time
Overvoltage Protection
propagation delay
Note:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
 2004 Semtech Corp.
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SC1405B
POWER MANAGEMENT
Timing Diagrams
 2004 Semtech Corp.
5
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SC1405B
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
Top View
(1)
SC1405BTS.TR
P ackag e
Temp Range (TJ)
TSSOP-14
0 to 125°C
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(14-Pin TSSOP)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
OVP_S
2
EN
3
GND
4
CO
5
S_MOD
6
DELAY_C
The capacitance connected between this pin and GND sets the additional propagation
delay for BG going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no
capacitor is connected, the propragation delay = 20ns.
7
PRDY
This pin indicates the status of VCC. When VCC is less than the UVLO threshold, this
output is driven low. When VCC is greater than or equals to the UVLO threshold this
output goes high.
8
VC C
Input supply of 5V - 6V. A .22-1µF ceramic capacitor should be connected from VCC to
PGND very close to the chip.
9
BG
10
PGND
11
D S P S _D R
Dynamic Set Point Switch Drive. TTL level output signal. When S-MOD is high, this pin
follows the BG driver pin voltage.
12
DRN
This pin connects to the junction of the switching and synchronous MOSFET's. This pin
can be subjected to a -2V minimum relative to PGND without affecting operation.
13
TG
14
BST
Overvoltage protection sense. External scaling resistors required to set protection
threshold.
When high, this pin enables the internal circuitry of the device. When low, TG, BG, and
PRDY are forced low and the supply current (5V) is less than 10µA.
Logic GND.
TTL-level input signal to the MOSFET drivers.
When low, this signal forces BG to be low, triggering asynchronous operation. When
high, BG is not a function of this signal.
Output drive for the synchrounous (bottom) MOSFET.
Power ground. Connect to the synchronous FET source pin (power ground).
Output gate drive for the switching (high-side) MOSFET.
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the
floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically
between 0.1µF and 1µF (ceramic).
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
 2004 Semtech Corp.
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SC1405B
POWER MANAGEMENT
Block Diagram
Applications Information
SC1405B is the higher speed version of the SC1405.
It is designed to drive Low Rds_On power MOSFET’s with
ultra-low rise/fall times and propagation delays. As the
switching frequency of PWM controllers is increased to
reduce power supply and Class-D amplifier volume and
cost, fast rise and fall times are necessary to minimize
switching losses (TOP MOSFET) and reduce Dead-time
(BOTTOM MOSFET) losses. While Low Rds_On MOSFET’s
present a power saving in I2R losses, the MOSFET’s die
area is larger and thus the effective input capacitance
of the MOSFET is increased. Often a 50% decrease in
Rds_On more than doubles the effective input gate
charge, which must be supplied by the driver. The Rds_On
power savings can be offset by the switching and deadtime losses with a suboptimum driver. While discrete
solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other
housekeeping functions necessary for safe operation can
become cumbersome and costly. The SC1405 family of
parts presents a total solution for the high-speed, high
power density =applications. Wide input supply range of
4.5V-25V allows use in battery powered applications, new
high voltage, distributed power servers as well as ClassD amplifiers.
of events by which the top and bottom drive signals are
applied. The shoot-through protection is implemented
by holding the bottom FET off until the voltage at the
phase node (intersection of top FET source, the output
inductor and the bottom FET drain) has dropped below
1V. This assures that the top FET has turned off and
that a direct current path does not exist between the
input supply and ground, a condition which both the top
and bottom FET’s are on momentarily. The top FET is
also prevented from turning on until the bottom FET is
off. This time is internally set to 20ns (typical) and may
be increased by adding a capacitor from the C-Delay pin
to GND. The delay is approximately 1ns/pf in addition to
the internal 20ns delay. The external capacitor may be
needed if multiple High input capacitance MOSFET’s are
used in parallel and the fall time is substantially greater
than 20ns.
Theory of Operation
As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the
SC1405B. The Evaluation board schematic (Refer to
figure 3) shows a dual phase synchronous design with all
surface mountable components.
It must be noted that increasing the dead-time by high
values of C-Delay capacitor will reduce efficiency since
the parallel Schottky or the bottom FET body diode will
have to conduct during dead-time.
Layout Guidelines
The control input (CO) to the SC1405B is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, Figure 3). The timing diagram demonstrates the sequence
 2004 Semtech Corp.
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SC1405B
POWER MANAGEMENT
Applications Information
MOSFETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the
spike. The MOSFET shown in the schematic (figure 4)
has a 2 volt threshold and will require approximately 5
volts Vgs to be conducting, thus reducing the possibility
of shoot-through. A zero ohm bottom FET gate resistor
will obviously help keeping the gate voltage low.
While components connecting to C-Delay, OVP_S, EN,SMOD, DSPS_DR and PRDY are relatively non-critical, tight
placement and short,wide traces must be used in layout
of The Drives, DRN, and especially PGND pin. The top
gate driver supply voltage is provided by bootstrapping
the +5V supply and adding it the phase node voltage
(DRN). Since the bootstrap capacitor supplies the charge
to the TOP gate, it must be less than .5” away from the
SC1405. Ceramic X7R capacitors are a good choice for
supply bypassing near the chip. The Vcc pin capacitor
must also be less than .5” away from the SC1405. The
ground node of this capacitor, the SC1405 PGND pin
and the Source of the bottom FET must be very close to
each other, preferably with common PCB copper land
and multiple vias to the ground plane (if used). The parallel Shottkey must be physically next to the Bottom FETS
Drain and source. Any trace or lead inductance in these
connections will drive current way from the Shottkey and
allow it to flow through the FET’s Body diode, thus reducing efficiency.
Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low.
Ringing on the Phase Node
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is determined by:
FRING =
Where:
Preventing Inadvertent Bottom FET Turn-on
VIN * CRSS
(CRSS + CISS
Coss=Drain to source capacitance of bottom FET. If there
is a Shottkey used, the capacitance of the Shottkey is
added to the value.
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1405B
is very close to the bottom FET, Vspike will be reduced
depending on trace inductance, rate if rise of current,etc.
Although this ringing does not pose any power losses
due to a fairly high Q, it could cause the phase node to
go too far negative, thus causing improper operation,
double pulsing or at worst driver damage. This ringing is
also an EMI nuisance due to its high resonant frequency.
Adding a capacitor, typically 1000-2000pf, in parallel with
Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10
ohm resistor between the phase node and the DRN pin
of the SC1405 should eliminate the double pulsing.
While not shown in Figure 4, a capacitor may be added
from the gate of the Bottom FET to its source, preferably
less than .5” away. This capacitor will be added to Ciss
in the above equation to reduce the effective spike voltage, Vspike.
The negative voltage spikes on the phase node adds to
the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. If the phase node negative
spikes are too large, the voltage on the boost capacitor
could exceed device’s absolute maximum rating of 8V.
The selection of the bottom MOSFET must be done with
attention paid to the Crss/Ciss ratio. A low ratio reduces
the Miller feedback and thus reduces Vspike. Also
 2004 Semtech Corp.
(2Π * (L ST * COSS
Lst = The effective stray inductance of the top FET added
to trace inductance of the connection between top FET’s
source and the bottom FET’s drain added to the trace
resistance of the bottom FET’s ground connection.
At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the Bottom FET’s gate through the Miller capacitance, Crss of
the bottom FET. The voltage appearing on the gate due
to this spike is:
VSPIKE =
1
8
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SC1405B
POWER MANAGEMENT
Applications Information (Cont.)
To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between
boost Schottky diode and Vcc to filter the negative spikes
on DRN Pin. Alternately, a Silicon diode, such as the
commonly available 1N4148 can substitute for the
Schottky diode and eliminate the need for the series resistor.
At that point, the inductor core and wire losses, depending on the magnitude of the ripple current, can be quite
significant. Operating in asynchronous mode at light loads
effectively only charges the inductor by as much as
needed to supply the load current, since the inductor
never completely discharges at light loads. DC regulation can be an issue when operating in asynchronous
mode, depending on the type of controller used and minimum load required to maintain regulation. If there are
no Shottkey diodes used in parallel with bottom FET, the
FET’s body diode will need to conduct in asynchronous
mode. The high voltage drop of this diode must be considered when determining the criteria for this mode of
operation.
Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or
other surface mount MOSFETs will reduce lead inductance and their parasitic effects.
ASYNCHRONOUS OPERATION
The SC1405B can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus disabling
the bottom FET drive. This has the effect of saving power
at light loads since the bottom FET’s gate capacitance
does not have to charged at the switching frequency.
There can be a significant savings since the bottom driver
can supply up to 2A pulses to the FET at the switching
frequency. There is an additional efficiency benefit to
operating in asynchronous mode. When operating in synchronous mode, the inductor current can go negative
and flow in reverse direction when the bottom FET is on
and the DC load is less than 1/2 inductor ripple current.
 2004 Semtech Corp.
DSPS DR
This pin produces an output which is a logical duplicate
of the bottom FET’s gate drive, if S-MOD is held LOW.
OVP_S/OVER TEMP SHUTDOWN
Output over-voltage protection may be implemented on
the SC1405 independent of the PWM controller . A voltage divider from the output is compared with the internal bandgap voltage of 1.2V (typical). Upon exceeding
this voltage, the overvoltage comparator disables the top
FET, while turning on the bottom FET to allow discharge
of the output capacitors excessive voltage through the
output inductor. There should be sufficient RC time constant as well as voltage headroom on the OVP_S pin to
assure it does not enter overvoltage mode inadvertently.
The SC1405 will shutdown if its Tj exceeds 165°C.
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SC1405B
POWER MANAGEMENT
Typical Characteristics
Performance diagrams, Application Evaluation Board.
Figure 1: PWM input and Gate drive switching
waveforms. The MOSFETs driven are shown
on Figure 4 (Evaluation Board Schematic)
Ch1: PWM input signal
Ch2: Top Gate Drive
Ch3: Phase (Switching) Node
Ch4: Bottom Gate
PIN Descriptions
Figure 2: PWM input and Gate drive and phase
node switching waveforms with time scale expanded. The MOSFETs driven are shown on
Figure 4 (Evaluation Board Schematic)
Ch1: PWM input signal
Ch2: Top Gate Drive
Ch3: Phase (Switching) Node
Ch4: Bottom Gate
Figure 3: PWM input and Gate drive and phase
node switching waveforms with time scale
expanded. The MOSFETs driven are shown
on Figure 4 (Evaluation Board Schematic)
Ch1: PWM input signal
Ch2: Top Gate Drive
Ch3: Phase (Switching) Node
Ch4: Bottom Gate
 2004 Semtech Corp.
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 2004 Semtech Corp.
C7
INPUT
6
5
4
3
2
1
J1
1u,16V
All VIDs OFF disables the
SC2422 Controller.
1000uf,16V
11
7.5K
R16
26.1k
R15
C24
220pf
1K
5
Vid0
120K
4
Vid1
R11
3
Vid2
R10
2
Vid3
RRE F
FB
13K
R2
U?
10
GND
UVLO
OC-
OUT2
OUT1
OC+
BGOUT
VCC
.002
R1
VCORE
C11
1uf
SC2422-P
ERROUT
VID0
VID1
VID2
VID3
VID4
R14
8
7
6
1
33u f,OS
C2
Vid4
C8
10u,CE R
C1
+12V
5-7V
9
10
11
12
13
14
15
16
10k
R4
EN
3.6K
R20
C26
C21
7.5K
5
7
2
4
6
1
8
3
5
7
2
4
6
1
8
3
OVP
Vcc
10uf
Vcc
C12
10uf
10nf
10
R3
R8
C9
10nf
TG
BS T
TG
BS T
1
R17
SC1 405B
PRDY
EN
DRN
CO
DELA Y_ C
BG
OVP_S
DSPS_DR
S_MO D PGND
Vcc
GND
U3
5819
D4
SC1 405B
11
10
9
12
13
14
11
10
9
12
13
14
10u,CE R
C4
PRDY
DRN
EN
CO
DELA Y_ C
BG
OVP_S
DSPS_DR
S_MO D PGND
Vcc
GND
5819
U1
D2
1uf
C3
R19
7.5K
10u,CE R
C5
R13
0
R9
0
VIN
Q4
FDB 7030
Q3
FDB 6035
Q2
FDB 7030
Q1
C30
.1
R6
0
R5
0
Vin
FDB 6035
1uf
C6
7.5K
R18
.1
C20
.1
C14
C27
.01
2.2
R12
L2
PIT1103 _1uh
R7
2.2
L1
C16
.01
PIT1103 _1uh
10u,CE R
C29
10u,CE R
C28
10u,CE R
C25
10u,CE R
C23
10u,CE R
C22
10u,CE R
C19
10u,CE R
C18
10u,CE R
C17
10u,CE R
C15
820u f,OS
C13
820u f,OS
C10
SC1405B
POWER MANAGEMENT
Evaluation Board Schematic
Figure 4 - APPLICA
TION EV
AL
U ATION BO
ARD SCHEMA
TIC
APPLICATION
EVAL
ALU
BOARD
SCHEMATIC
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SC1405B
POWER MANAGEMENT
Evaluation Board Bill of Materials
Item
Qty.
Reference
Value
Manufacturer
1
12
C 1, C 4, C 5, C 15, C 17, C 18, C 19, C 22, C 23,
C 25, C 28, C 29
01u, Cer.
Murata, TDK
2
1
C2
33uf, OS
Sanyo
3
3
C3, C6, C11
1uF
4
1
C7
1u, 16V
5
1
C8
1000uf, 16V
6
2
C 9, C 26
10nf
7
2
C 10, C 13
820uf, OS
8
2
C 21, C 12
10uf
9
3
C 14, C 20, C 30
.1
10
2
C 16, C 27
.01
11
1
C 24
220pf
12
2
D 4, D 2
5819
13
1
J1
INPUT
14
2
L2, L1
PIT1103_luh
Falco (Falcousa.com)
15
2
Q1, Q3
F D B 6035
Fairchild
16
2
Q2, Q4
F D B 7030
Fairchild
17
1
R1
.002
Dale
18
2
R3, R2
10
19
1
R4
10k
20
4
R5, R6, R9, R13
0
21
2
R12, R7
2.2
22
4
R8, R16, R18, R19
7.5K
23
1
R10
120K
24
1
R11
1K
25
1
R14
13K
26
1
R15
26.1k
27
1
R17
1
28
1
R20
3.6K
29
1
U2
S C 2422
Semtech
30
2
U1, U3
S C 1405B
Semtech
 2004 Semtech Corp.
12
Panasonic
Sanyo
www.semtech.com
SC1405B
POWER MANAGEMENT
Outline Drawing -TSSOP-14
Land Pattern - TSSOP-14
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
 2004 Semtech Corp.
13
www.semtech.com