SC1405D High Speed Synchronous Power MOSFET Smart Driver POWER MANAGEMENT Description Features The SC1405D is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through. Each driver is capable of driving a 3000pF load in 15ns rise/ fall time and has ULTRA-LOW propagation delay from input transition to the gate of the power FETs. Adaptive Overlap Protection circuit ensures that the synchronous FET does not turn on until the top FET source has reached a voltage low enough to prevent shoot-through. The delay between the bottom gate going low to the top gate transitioning high is externally programmable via a capacitor to minimize dead time. The bottom FET may be disabled at light loads by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FET’s gate drive current and inductor ripple current. Fast rise and fall times (15ns withPRELIMINARY 3000pf load) 14ns max. Propagation delay (BG going with low) Adaptive and programmable shoot-through protection Adaptive overvoltage protection Wide input voltage range (4.5V - 25V) Programmable delay between FETs Power saving asynchronous mode control Output overvoltage protection/overtemp shutdown Under-Voltage lock-out and power ready signal Less than 10µA stand-by current (EN=low) Power ready output signal High frequency (to 1.2MHz) operation allows use of small inductors and low cost caps in place of electrolytics TSSOP-14 package An internal voltage reference allows threshold adjustment for an Output Over-Voltage protection circuitry, independent of the PWM controller. The device provides overvoltage protection independent of the PWM feedback loop with a unique “adaptive OVP” comparator which rejects noise but responds quickly to a true OVP situation. Applications High Density/Fast transient microprocessor power supplies Motor Drives/Class-D amps High efficiency portable computers Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are off when Vcc is less than or equal to 4.4V (typ) at supply ramp up (4.35V at supply ramp down). A CMOS output provides status indication of the 5V supply. A low enable input places the IC in standby mode, reducing supply current to less than 10µA. Typical Application Circuit Revision: June 8, 2005 1 www.semtech.com SC1405D POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Minimum Maximum Units VCCMAX -0.3 7 V BST to PGND VMAXBST-PGND -0.3 30 V BST to DRN VMAXBST-DRN -0.3 8 V DRN to PGND VMAXDRN-PGN DC -2 25 V VMAXPULSE tPULSE < 100nS -5 25 V -0.3 10 V -0.3 VCC + 0.3 V -1 +1 V 0.66 2.56 W VCC Supply Voltage DRN to PGND Pulse OVP_S to PGND Conditions VMAXOVP S-PGND EN, CO, DSPS, MODE, PRDY, DELAY to AGND AGND to PGND Tamb = 25°C, TJ = 125°C Tcase = 25°C, TJ = 125°C Continuous Power Dissipation Pd Thermal Impedance Junction to Case θJ C 40 °C/W Thermal Impedance Junction to Ambient θJ A 150 °C/W Junction Temperature Range TJ -40 +125 °C Storage Temperature Range TSTG -65 +150 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C NOTE: (1) Specification refers to application circuit. Electrical Characteristics - DC Operating Specifications Unless otherwise specified: -40 < TJ < 125°C; VCC = 6V; 4V < VBST < 26V Parameter Symbol Conditions Min Typ Max Units 4.6 5 6.0 V 10 µA Pow er Supply Supply Voltage Quiescent Current V CC Iq_stby E N = 0V Iq_op VCC = 5V, CO = 0V High Level Output Voltage VOH VCC = 4.7V, lload = 10mA Low Level Output Voltage VOL VCC < UVLO threshold, lload = 10µA IO_SINK VPRDY = 0.4V Quiescent Current, operating 1 mA 4.55 V PR D Y Sink Current 2005 Semtech Corp. 2 4.5 0.1 5 10 0.2 V mA www.semtech.com SC1405D POWER MANAGEMENT Electrical Characteristics - DC Operating Specifications Parameter Symbol Conditions Min High Level Output Voltage VOH VCC = 4.6V, Cload = 100pF 4.15 Low Level Output Voltage VOL VCC = 4.6V, Cload = 100pF Typ Max Units D S P S _D R V 0.05 V 4.6 V Under Voltage Lockout Start Threshold Hysteresis 4.2 Vhys Logic Active Threshold 4.4 0.05 EN is low V 1.5 V 1.28 V Overvoltage Protection Trip Threshold Hysteresis VTRIP 1.17 1.225 0.8 VhysOVP V Trip Delay, 50mV Overdrive TJ = 0 to 125oC 300 470 800 ns Trip Delay, 100mV Overdrive TJ = 0 to 125oC 125 225 400 ns S_MOD High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V Enable High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V CO High Level Input Voltage VIH Low Level Input Voltage VIL 2.0 V 0.8 V Thermal Shutdow n Over Temperature Trip Point TOTP 165 o C Hysteresis THYST 10 o C IPKH 3 A 1 Ω High-Side Driver Peak Output Current Output Resistance RsrcTG RsinkTG duty cycle < 2%, tpw < 100µs, TJ = 125°C, VBST - VDRN = 4.5V, VTG = 4.0V (src)+VDRN or VTG = 0.5V (sink)+VDRN .7 Low -Side Drive Peak Output Current Output Resistance IPKL RsrcBG RsinkBG 2005 Semtech Corp. duty cycle < 2%, tpw < 100µs, TJ = 125°C, VV S = 4.6V, VBG = 4V (src) or VLOWDR = 0.5V (sink) 3 3 A 1.2 Ω 1.0 www.semtech.com SC1405D POWER MANAGEMENT Electrical Characteristics - AC Operating Specifications Parameter Symbol Conditions rise time trTG1 fall time Min Typ Max Units CI = 3nF, VBST - VDRN = 4.6V, 14 23 ns tfTG CI = 3nF, VBST - VDRN = 4.6V, 12 19 ns propagation delay time, TG going high tpdhTG CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 20 32 ns propagation delay time, TG going low tpdlTG CI = 3nF, VBST - VDRN = 4.6V, 15 24 ns High Side Driver Low -Side Driver rise time trBG CI = 3nF, V V S = 4.6V, 15 24 ns fall time trBG CI = 3nF, V V S = 4.6V, 13 21 ns propagation delay time, BG going high tpdhBGHI CI = 3nF, VBST - VDRN = 4.6V, C-delay=0 12 19 ns propagation delay time, TG going low tpdlBG CI = 3nF, V V S = 4.6V, DRN <1V 7 12 ns V_5 ramping up tpdhUVLO EN is High 10 µs V_5 ramping down tpdhUVLO EN is High 10 µs EN is transitioning from low to high tpdhPRDY V_5 >UVLO threshold, Delay measured from EN > 2.0V to PRDY > 3.5V 10 µs EN is transitioning fro high to low tpdhUVLO V_5 >UVLO threshold, Delay measured from EN < 0.8V to PRDY < 10% of V_5V 500 µs trDSPS DR. CI = 100 pf, V_5 = 4.6V 20 ns propagation delay, DSPS_DR going high tpdhDSPS DR S_MOD goes high and BG goes high or S_MOD goes low 10 ns propagation delay, DSPS_DR goes low tpdlDSPS DR S_MOD goes high and BG goes low 10 ns Under-Voltage Lockout PR D Y D S P S _D R rise/fall time NOTE: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. 2005 Semtech Corp. 4 www.semtech.com SC1405D POWER MANAGEMENT Application Circuit - TSSOP-14 INPUT POWER + + P_READY >> PWM IN (20KHz-1MHz) 47pF 7 2 4 6 1 5 << DSPS_DR MTB75N03 75A,30V 1N5819 .1uF 8 3 << + D1 +5V 10uF,6.3V + Vcc GND BST TG PRDY EN DRN CO DELAY _C BG OVP_S DSPS_DR S_MOD PGND .22uF 14 13 2.2 12 + + + MTB75N03 75A,30V 9 11 10 2.2 SC1405D Ov er-Voltage Sense <<< Output Feedback to PWM Controller Timing Diagram 2005 Semtech Corp. 5 www.semtech.com SC1405D POWER MANAGEMENT Pin Configuration Ordering Information Top View Device P ackag e Temp Range (TJ) SC1405DITSTRT TSSOP-14 -40° to 125°C Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. (14-Pin TSSOP) Pin Descriptions Pin # Pin Name Pin Function 1 OVP_S 2 EN 3 GND 4 CO 5 S_MOD 6 DELAY_C The capacitance connected between this pin and GND sets the additional propagation delay for BG going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no capacitor is connected, the propragation delay = 20ns. 7 PRDY This pin indicates the status of VCC. When VCC is less than the UVLO threshold, this output is driven low. When VCC is greater than or equals to the UVLO threshold this output goes high. 8 VC C Input supply of 5 - 8V. A .22-1µF ceramic capacitor should be connected from VCC to PGND very close to the chip. 9 BG 10 PGND 11 D S P S _D R Dynamic Set Point Switch Drive. TTL level output signal. When S-MOD is high, this pin follows the BG driver pin voltage. 12 DRN This pin connects to the junction of the switching and synchronous MOSFET's. This pin can be subjected to a -2V minimum relative to PGND without affecting operation. 13 TG 14 BST Overvoltage protection sense. External scaling resistors required to set protection threshold. When high, this pin enables the internal circuitry of the device. When low, TG, BG, and PRDY are forced low and the supply current (5V) is less than 10µA. Logic GND. TTL-level input signal to the MOSFET drivers. When low, this signal forces BG to be low, triggering asynchronous operation. When high, BG is not a function of this signal. Output drive for the synchrounous (bottom) MOSFET. Power ground. Connect to the synchronous FET source pin (power ground). Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1µF and 1µF (ceramic). NOTE: (1) All logic level inputs and outputs are open collector TTL compatible. 2005 Semtech Corp. 6 www.semtech.com SC1405D POWER MANAGEMENT Block Diagram Applications Information SC1405D is designed to drive Low Rds_On power FETs with ultra-low rise/fall times and propagation delays. As the switching frequency of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP FET) and reduce Dead-time (BOTTOM FET) losses. While Low Rds_On FETs present a power saving in I2R losses, the FET’s die area is larger and thus the effective input capacitance of the FET is increased. Often a 50% decrease in Rds_On more than doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a suboptimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and costly. The SC1405 family of parts presents a total solution for the highspeed, high power density applications. Wide input supply range of 4.5V-25V allows use in battery powered applications, new high voltage, distributed power servers as well as Class-D amplifiers. by holding the bottom FET off until the voltage at the phase node (intersection of top FET source, the output inductor and the bottom FET’s drain) has dropped below 1V. This assures that the top FET has turned off and that a direct current path does not exist between the input supply and ground, a condition which both the top and bottom FETs are on momentarily. The top FET is also prevented from turning on until the bottom FET is off. This time is internally set to 20ns (typical) and may be increased by adding a capacitor from the C-Delay pin to GND. The delay is approximately 1ns/pF in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance FETs are used in parallel and the fall time is substantially greater than 20ns. Theory of Operation As with any high speed , high current circuit, proper layout is critical in achieving optimum performance of the SC1405D. The Evaluation board schematic on page 12 shows a dual phase synchronous design with all surface mountable components. It must be noted that increasing the dead-time by high values of C-Delay capacitor will reduce efficiency since the parallel Schottky or the bottom FET’s body diode will have to conduct during dead-time. Layout Guidelines The control input (CO) to the SC1405D is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic on page 12). The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented 2005 Semtech Corp. While components connecting to C-Delay, OVP_S, EN,SMOD, DSPS_DR and PRDY are relatively noncritical, tight 7 www.semtech.com SC1405D POWER MANAGEMENT Applications Information the Miller feedback and thus reduces Vspike. Also FETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The FET shown in the schematic has a 2 volt threshold and will require approximately 5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom FET gate resistor will obviously help keeping the gate voltage low. placement and short, wide traces must be used in layout of The Drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it the phase node voltage (DRN). Since the bootstrap capacitor supplies the charge to the TOP gate, it must be less than 0.5” away from the SC1405. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. The Vcc pin capacitor must also be less than 0.5” away from the SC1405. The ground node of this capacitor, the SC1405 PGND pin and the Source of the bottom FET must be very close to each other, preferably with common PCB copper land and multiple vias to the ground plane (if used). The parallel Schottky (if used) must be physically next to the Bottom FET’s drain and source. Any trace or lead inductance in these connections will drive current way from the Schottky and allow it to flow through the FET’s body diode, thus reducing efficiency. Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. Ringing on the Phase Node The top FET source must be close to the bottom FET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by: Preventing Inadvertent Bottom FET Turn-on Fring = At high input voltages, (12V and greater) a fast turn-on of the top FET creates a positive going spike on the Bottom FET’s gate through the Miller capacitance, Crss of the bottom FET. The voltage appearing on the gate due to this spike is: Vspike = Where: Lst = The effective stray inductance of the top FET added to trace inductance of the connection between top FET’s source and the bottom FET’s drain added to the trace resistance of the bottom FET’s ground connection. Vin * Crss Crss + Ciss Coss=Drain to source capacitance of bottom FET. If there is a Schottky used, the capacitance of the Schottky is added to the value. Where Ciss is the input gate capacitance of the bottom FET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1405D is very close to the bottom FET, Vspike will be reduced depending on trace inductance, rate if rise of current, etc. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. This ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 1000-2000pf, in parallel with Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10 ohm resistor between the phase node and the DRN pin of the SC1405 should eliminate the double pulsing. While not shown in Application Evaluation Board Schematic on page 12, a capacitor may be added from the gate of the bottom FET to its source, preferably less than 0.5” away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage, Vspike. The negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. If the phase node negative spikes are too large, the voltage on the boost capacitor The selection of the bottom FET must be done with attention paid to the Crss/Ciss ratio. A low ratio reduces 2005 Semtech Corp. 1 2Π L st * Coss 8 www.semtech.com SC1405D POWER MANAGEMENT Applications Information (Cont.) could exceed device’s absolute maximum rating of 8V. To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between boost Schottky diode and Vcc to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such as the commonly available 1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor. DSPS DR This pin produces an output which is a logical duplicate of the bottom FET’s gate drive, if S-MOD is held High. OVP_S/OVER TEMP SHUTDOWN Output over-voltage protection (OVP) may be implemented on the SC1405D independent of the PWM controller . A voltage divider from the output is compared with the internal bandgap voltage of 1.2V (typical). Upon exceeding this voltage, the overvoltage comparator disables the top FET, while turning on the bottom FET to allow discharge of the output capacitors excessive voltage through the output inductor. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or other surface mount FETs will reduce lead inductance and their parasitic effects. ASYNCHRONOUS OPERATION The SC1405D can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus disabling the bottom FET drive. This has the effect of saving power at light loads since the bottom FET’s gate capacitance does not have to charged at the switching frequency. There can be a significant savings since the bottom driver can supply up to 2A pulses to the FET at the switching frequency. There is an additional efficiency benefit to operating in asynchronous mode. When operating in synchronous mode, the inductor current can go negative and flow in reverse direction when the bottom FET is on and the DC load is less than 1/2 inductor ripple current. At that point, the inductor core and wire losses, depending on the magnitude of the ripple current, can be quite significant. Operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed to supply the load current, since the inductor never completely discharges at light loads. DC regulation can be an issue when operating in asynchronous mode, depending on the type of controller used and minimum load required to maintain regulation. If there are no Shottkey diodes used in parallel with bottom FET, the FET’s body diode will need to conduct in asynchronous mode. The high voltage drop of this diode must be considered when determining the criteria for this mode of operation. 2005 Semtech Corp. The SC1405D has a unique adaptive OVP circuit. Short noise pulses, less than ~100ns are rejected completely; longer pulses will trigger OVP if only of sufficient magnitude. A long term transient will trigger OVP with a smaller magnitude. To assure proper tripping, bypass the resistor from OVP_S pin to GND with a capacitor. The value of this capacitor must be selected to achieve a time constant equal to one switching period. Leave at least 250mV headroom on the OVP pin to prevent false OVP events. The SC1405D will shutdown if its TJ exceeds 165°C. 9 www.semtech.com SC1405D POWER MANAGEMENT Typical Characteristics Performance diagrams, Application Evaluation Board. PIN Descriptions PIN Descriptions Timing diagram: Ch1: CO input Ch2: TG drive Ch3: BG non-overlap drive Ch4: phase node Iout = 20A (10A/phase) Refer to Eval. Schematic (fig.3) Timing diagram: Rise/Fall times Ch1: TG drive Ch2: BG drive Cursor: TpdhTG Iout = 20A (10A/phase) Refer to Eval. Schematic (fig.3) VIN = 12V, VOUT = 1.6V. Top FET = IR7811 FDB7030(BL) Qgd = 23nc 2005 Semtech Corp. 10 www.semtech.com SC1405D POWER MANAGEMENT Typical Characteristics (Cont.) SC1405D OVP Delay vs. Temperature 600.00 500.00 Delay (nS) 400.00 300.00 200.00 100.00 0.00 -25 -5 15 35 55 75 95 115 135 Temperature (C) 50mV Overdrive 100mV Overdrive Typical Delay vs. Overdrive (T=25C) Delay (nS) 10000 1000 100 10 1000 Overdrive (mV) 2005 Semtech Corp. 11 www.semtech.com VR_ON CORESW V_GATE 12 VID0 DPRSLPVR 9 11 8 VID1 DPSLP# 7 VID2 10 6 VID3 GMUXSEL 5 4 VID4 OSB O SB R9 69.8k 1 2 3 OSD O SD 1 R7 21.5k 1 2 HYS OSDR 2 2 HYS R5 6.8k O S D R 1 2 R2 51k 1 DPRSLPVR DPSLP# EN SS CORE DAC GND CO VCC CMP CMPREF CL CLREF PWRGOOD SC1471 GMUXSEL VID0 VID1 VID2 VID3 VID4 OSB OSD OSDR HYS U1 13 14 15 16 17 18 19 20 21 22 23 24 71_ON SS CORE DAC CO VCCC CMP 1 R11 620 1 620 1.24k 1 2 1 10 DAC R16 1.8nF C13 2 1 C11 1nF 2 2 R24 CMPREF CL CLREF 1 2 R1 1 2 1 1 1nF C24 100 R17 C10 2 0.1uF 120pF 1 C7 1 2 2 2 2 1 2 NO_POP C21 1 2 CMP PRDY DRN TG BST VCC BG PGND DSPSDR SC1405D DELAYC SMOD CO GND EN 10.0k R12 1 8 9 10 11 12 13 14 1uF NOTE: Populate R12, C12, and R14 for redundant OVP. Ground Pin 1 if redundant OVP is not required. 7 6 5 4 3 2 OVPS U2 470pF C12 OVPS 1 OH C O RE 2 DELAYC R8 787 R6 787 1 BA L C LO H +VCORE 1 180pF 1 180pF C8 C9 2 2 R4 750 R3 750 1 2 BG TG BST 1 2 1 2 1uF C22 1.0u C14 1 R13 1 R10 10uF C2 Q1 IRF7811A 2 TG14 2 1 2 10uF C3 1 2 10uF C4 1 2 10uF C5 Q3 D FDS6674A 4 PHASE 1 Q4 D 2 Q2 R15 D 1 Q5 D 10uF/1206 2 CS+ L-R 1 2 0.002 C33 FDS7764A 4 4 IRF7811A L1 0.6uH TG2 D 1 2 CS- Rout CS+, CS- as a differential pair. 1 2 PHASE FDS6674A 4 1 1 MBR0530 D1 8 7 6 5 C1 8 7 6 5 3 2 1 + R14 150uF C18 6.65k 150uF C15 MBRS130L D2 + 10uF C6 1 2 8 7 6 5 3 2 1 8 7 6 5 3 2 1 1 2 3 2 1 8 7 6 5 3 2 1 1 2 1 2 1 2 2 2 1 + 150uF C16 + 150uF C19 GND +V_IN +5Vcc 1 2 1 2 12 + 150uF C17 + 150uF C20 +VCORE 1 2005 Semtech Corp. 2 +3_3V SC1405D POWER MANAGEMENT Evaluation Board Schematic www.semtech.com SC1405D POWER MANAGEMENT Outline Drawing -TSSOP-14 A DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX D A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc 2X E/2 E1 E PIN 1 INDICATOR ccc C 2X N/2 TIPS 1 2 3 e B aaa C SEATING PLANE .047 .006 .002 .042 .031 .007 .012 .007 .003 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 14 8° 0° .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.20 0.09 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 14 0° 8° 0.10 0.10 0.20 D A2 A A1 C c GAGE PLANE bxN bbb H C A-B D 0.25 L (L1) DETAIL SIDE VIEW SEE DETAIL 01 A A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB-1. 2005 Semtech Corp. 13 www.semtech.com SC1405D POWER MANAGEMENT Land Pattern - TSSOP-14 X DIM (C) G DIMENSIONS INCHES MILLIMETERS C G P X Y Z Z Y (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 14 www.semtech.com