PCS1P2192A VDP Multiple Pixel Clock Generator Features Product Description • Generates multiple clock outputs from 20MHz external reference clock • Input frequency: 20MHz • Output frequencies: o Selectable CLKOUT: 108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz, 25MHz, 45MHz, and 40MHz o REFOUT: 20MHz • Operating Supply Voltage: 3.3V ± 0.3V • Zero ppm frequency synthesis error on all clock outputs The PCS1P2192A is a clock generator that generates multiple selectable pixel clock outputs for Video Display Panel applications from an external 20MHz reference clock. The PLL based clock generator is specifically designed to provide zero ppm frequency synthesis error on all clock outputs. Various pixel clock rates are selectable through frequency selection pins S[2:0] (Refer to Frequency Selection Table) The device provides a reference clock output additionally. Operating Supply Voltage for this device is 3.3V ± 0.3V. The device is available in an 8-pin SOIC package. Application • 8-pin SOIC package PCS1P2192A is targeted towards Video Display Panel (VDP) applications like VGA, SVGA, XGA, WXGA, UXGA. Block Diagram VDD CLKIN [S2: S0] PLL CLKOUT REFOUT GND ©2010 SCILLC. All rights reserved. NOVEMBER 2010 – Rev. 2.1 Publication Order Number: PCS1P2192/D PCS1P2192A Pin Configuration 8 VDD 7 CLKOUT S0 3 6 REFOUT S1 4 5 S2 CLKIN 1 GND 2 PCS1P2192A Pin Description Pin# Pin Name Type Description 1 CLKIN I 20MHz external reference clock input. 2 GND P Ground Connection. 3 S0 I 4 S1 I 5 S2 I 6 REFOUT O Reference clock output. 7 CLKOUT O Clock output. 8 VDD P Device Power Supply . Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer to Frequency Selection Table.) Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer to Frequency Selection Table.) Frequency select. Digital logic input used to select output frequency. Has an internal pull up resistor. (Refer to Frequency Selection Table.) Frequency Selection Table S2 S1 S0 CLKOUT (MHz) 0 0 0 108 0 0 1 27 0 1 0 33.2 0 1 1 85 1 0 0 65 1 0 1 25 1 1 0 45 1 1 1 40 Rev. 2 | Page 2 of 7 | www.onsemi.com PCS1P2192A Absolute Maximum Ratings Symbol VDD, VIN TSTG Rating Unit Voltage on any input pin with respect to Ground Parameter -0.5 to +4.6 V Storage temperature -65 to +125 °C Ts Max. Soldering Temperature (10 sec) 260 °C TJ Junction Temperature 150 °C 2 KV Static Discharge Voltage TDV (As per JEDEC STD22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Recommended Operating Conditions Parameter Description Min Typ 3.0 3.3 Max Unit 3.6 V +85 °C VDD Operating Voltage TA Operating Temperature CL Load Capacitance 15 pF CIN Input Capacitance 7 pF 0 DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VIL Input low voltage (For CLKIN) GND-0.3 0.8 V VIH Input high voltage (For CLKIN) 2.0 VDD+0.3 V IIL Input low current 50 µA IIH Input high current -50 µA Output low voltage (VDD = 3.3V, IOL = 8mA) 0.4 V 5 mA VOL VOH Output high voltage (VDD = 3.3V, IOH = -8mA) IDD Static supply current ICC Dynamic supply current (3.3V and no load) VDD Operating Voltage tON Power-up time (first locked cycle after power-up) 1 mS Output impedance 40 Ω ZOUT 2.4 V 1 9 3.0 Note: 1. CLKIN pulled low. Rev. 2 | Page 3 of 7 | www.onsemi.com 3.3 mA 3.6 V PCS1P2192A AC Electrical Characteristics Symbol fIN fOUT Min Typ Max 20 108, 27, 33.2, 85, 65, 25, 45, 40 Output frequency Unit MHz MHz 1 Output rise time (Measured from 20% to 80%) 1.2 2.5 nS 1 Output fall time (Measured from 80% to 20%) 0.8 1.6 nS tLH tHL Parameter Input frequency tJC Period Jitter tD Output duty cycle ±150 Frequency Synthesis Error (All Outputs) pS 0 40 Note: 1. Measured with a capacitive load of 15pF. Rev. 2 | Page 4 of 7 | www.onsemi.com 50 ppm 60 % PCS1P2192A Typical Application Schematic VDD CLKIN 2 VDD 0Ω 0Ω VDD 0Ω 0Ω VDD 1 CLKIN GND 8 GND CLKOUT 7 3 S0 REF 6 S1 S2 5 4 0.01uF VDD 0Ω 0Ω Use either pull-up or pull-down 0Ω Resistor with [S2:S0] for selection of CLKOUT frequencies. PCB Layout Recommendation For optimum device performance, following guidelines are recommended. used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible. All the VDD pins should • Dedicated VDD and GND planes. • The device must be isolated from system power supply noise. A 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be have decoupling capacitors. • In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. A typical layout is shown in the figure below. As short as possible VDD GND Rev. 2 | Page 5 of 7 | www.onsemi.com PCS1P2192A Package Information 8-Pin SOIC Package H E D A2 A θ C D e A1 L B Dimensions Symbol Inches Min Max Millimeters Min Max A1 0.004 0.010 0.10 0.25 A 0.053 0.069 1.35 1.75 A2 0.049 0.059 1.25 1.50 B 0.012 0.020 0.31 0.51 C 0.007 0.010 0.18 0.25 D 0.193 BSC 4.90 BSC E 0.154 BSC 3.91 BSC e 0.050 BSC 1.27 BSC H 0.236 BSC 6.00 BSC L 0.016 0.050 θ 0° 8° 0.41 1.27 0° 8° Rev. 2 | Page 6 of 7 | www.onsemi.com PCS1P2192A Ordering Code Part Number PCS1P2192AG-08SR Marking ACZ Package Type 8-Pin SOIC, TAPE & REEL, Green Temperature 0°C to +85°C A “microdot” placed at the end of last row of marking or just below the last row toward the center of package indicates Pb-free. are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes ON Semiconductor and without further notice to any products herein. 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