PULSECORE PCS1P2192A

PCS1P2192A
June 2009
rev 1.0
VDP Multiple Pixel Clock Generator
Product Description
Features
• Generates multiple clock outputs from 20MHz
The PCS1P2192A is a clock generator that generates
external reference clock
multiple selectable pixel clock outputs for Video Display
• Input frequency: 20MHz
Panel applications from an external 20MHz reference
• Output frequencies:
clock. The PLL based clock generator is specifically
•
•
Selectable CLKOUT:
designed to provide zero ppm frequency synthesis error
108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz,
on all clock outputs. Various pixel clock
rates are
25MHz, 45MHz, and 40MHz
selectable through frequency selection pins S[2:0] (Refer
REFOUT: 20MHz
Frequency Selection Table) The device provides a
• Operating Supply Voltage: 3.3V ± 0.3V
reference clock output additionally. Operating Supply
• Zero ppm frequency synthesis error on all clock
Voltage for this device is 3.3V± 0.3V. The device is
outputs
available in an 8 pin SOIC package, in commercial
• Commercial temperature: 0°C to +85°C
temperature grade.
• 8-pin SOIC package
Applications
PCS1P2192A is targeted towards Video Display Panel
(VDP) applications like VGA, SVGA, XGA, WXGA,
UXGA.
Block Diagram
VDD
CLKIN
[S2: S0]
PLL
CLKOUT
REFOUT
GND
PulseCore Semiconductor Corporation
2105 S. Bascom Ave Suite 210, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PCS1P2192A
June 2009
rev 1.0
Pin Configuration
8
VDD
7
CLKOUT
S0 3
6
REFOUT
S1 4
5
S2
CLKIN
1
GND 2
PCS1P2192A
Pin Description
Pin#
Pin Name
Type
Description
1
CLKIN
I
20MHz external reference clock input.
2
GND
P
Ground Connection.
3
S0
I
4
S1
I
5
S2
I
6
REFOUT
O
Reference clock output
7
CLKOUT
O
Clock output
8
VDD
P
Device Power Supply
Frequency select. Digital logic input used to select output frequency. Has an internal
pull up resistor. (Refer Frequency Selection Table)
Frequency select. Digital logic input used to select output frequency. Has an internal
pull up resistor. (Refer Frequency Selection Table)
Frequency select. Digital logic input used to select output frequency. Has an internal
pull up resistor. (Refer Frequency Selection Table)
Frequency Selection Table
S2
S1
S0
CLKOUT (MHz)
0
0
0
108
0
0
1
27
0
1
0
33.2
0
1
1
85
1
0
0
65
1
0
1
25
1
1
0
45
1
1
1
40
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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PCS1P2192A
June 2009
rev 1.0
Absolute Maximum Ratings
Symbol
Parameter
VDD, VIN
TSTG
Rating
Unit
Voltage on any input pin with respect to Ground
-0.5 to +4.6
V
Storage temperature
-65 to +125
°C
Ts
Max. Soldering Temperature (10 sec)
260
°C
TJ
Junction Temperature
150
°C
2
KV
Static Discharge Voltage
TDV
(As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Recommended Operating Conditions
Parameter
Description
Min
Typ
3.0
3.3
Max
Unit
3.6
V
+85
°C
VDD
Operating Voltage
TA
Operating Temperature
CL
Load Capacitance
15
pF
CIN
Input Capacitance
7
pF
0
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
V
VIL
Input low voltage (For CLKIN)
GND - 0.3
0.8
VIH
Input high voltage (For CLKIN)
2.0
VDD + 0.3
V
IIL
Input low current
50
µA
IIH
Input high current
-50
µA
VOL
Output low voltage (VDD = 3.3V, IOL = 8mA)
0.4
V
VOH
Output high voltage (VDD = 3.3V, IOH = -8mA)
IDD
Static supply current *
ICC
Dynamic supply current (3.3V and no load)
VDD
Operating Voltage
tON
Power-up time (first locked cycle after power-up)
1
mS
Output impedance
40
Ω
ZOUT
2.4
V
5
9
3.0
3.3
mA
mA
3.6
V
* CLKIN pulled low
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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PCS1P2192A
June 2009
rev 1.0
AC Electrical Characteristics
Symbol
fIN
Parameter
Min
Input frequency
Output frequency
tLH*
Output rise time ( Measured from 20% to 80% )
1.2
tHL*
Output fall time ( Measured from 80% to 20% )
0.8
tJC
Period Jitter
Frequency Synthesis Error (All Outputs)
Output duty cycle
Max
20
108, 27,
33.2, 85, 65,
25, 45, 40
fOUT
tD
Typ
40
Unit
MHz
MHz
2.5
nS
1.6
nS
±150
pS
0
ppm
50
60
%
* measured with a capacitive load of 15pF
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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PCS1P2192A
June 2009
rev 1.0
Typical Application Schematic
VDD
CLKIN
1
CLKIN
VDD
8
0.01uF
VDD
2
GND
3
S0
GND
CLKOUT 7
0Ω
0Ω
VDD
0Ω
4
S1
REF 6
VDD
0Ω
S2
5
0Ω
0Ω
Use either pull-up or pull-down
0Ω Resistor with [S2:S0] for selection of
CLKOUT frequencies
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power supply noise. A 0.01µF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be
used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via
should be kept as short as possible. All the VDD pins should have decoupling capacitors.
• In an optimum layout all components are on the same side of the board, minimizing vias through other
signal layers.
A typical layout is shown in the figure
As short
as possible
VDD
GND
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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PCS1P2192A
June 2009
rev 1.0
Package Information
8-Pin SOIC Package
H
E
D
A2
A
C
A1
D
θ
e
L
B
Dimensions
Symbol
Inches
Min
Max
Min
Max
A1
0.004
0.010
0.10
0.25
A
0.053
0.069
1.35
1.75
A2
0.049
0.059
1.25
1.50
B
0.012
0.020
0.31
0.51
C
0.007
0.010
0.18
0.25
Millimeters
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L
0.016
0.050
0.41
1.27
θ
0°
8°
0°
8°
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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PCS1P2192A
June 2009
rev 1.0
Ordering Code
Part Number
Marking
Package Type
Temperature *
PCS1P2192AG-08ST
PCS 1P2192AG
8-Pin SOIC, TUBE, Green
Commercial
PCS1P2192AG-08SR
PCS 1P2192AG
8-Pin SOIC, TAPE & REEL, Green
Commercial
*VDP commercial temperature range (0°C to +85°C)
Device Ordering Information
P C S 1 P 2 1 9 2 A G - 0 8 S R
R = Tape & Reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under U.S Patent Nos 5,488,627 and 5,631,921
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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PCS1P2192A
June 2009
rev 1.0
PulseCore Semiconductor Corporation
2105 S. Bascom Ave Suite 210
Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Copyright © PulseCore Semiconductor
All Rights Reserved
Part Number: PCS1P2192A
Document Version: 1.0
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
Many PulseCore Semiconductor products are protected by issued patents or by applications for patent
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks
of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves
the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors
that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance.
PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive
information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and
disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to
fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively
according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any
patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore
does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be
expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the
manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
VDP Multiple Pixel Clock Generator
Notice: The information in this document is subject to change without notice.
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