DN05011/D Design Note – DN05011/D High Efficiency 3A Buck Regulator w/ Light Load Efficiency Device Application NCP3170A Consumer Electronic Circuit Description This circuit is proposed for a wide varying +12V input (4.5V-18V) where there is a need to step-down the voltage to various low voltage outputs from 1.0V to 5.0V. The requirement specified using two 22uF ceramic output capacitors. Target efficiency is >80% with a thermally acceptable board temperature. The NCP3170A is a synchronous PWM switching buck regulator which utilizes current mode control for simple power supply design. The NCP3170A operates from 4.5 V to 18 V, producing up to 3 A, and is capable of producing output voltages as low as 0.8 V. To reduce the number of external components, a number of features are internally set including soft start, power good detection, and switching frequency. The NCP3170A is currently available in an SOIC−8 package. Input Voltage Output Voltage Output Current Topology 5V & 12V 0.8V-5.0V 3.0A Buck High Efficiency (90mΩ/25mΩ MOSFETs) 4.5 V to 18 V Operating Input Voltage Range FMEA Fault Tolerant During Pin Short Test Fixed 500 kHz and 1 MHz PWM Operation Cycle−by−Cycle Current Monitoring PowerGood Pin for Power Sequencing Dedicated ENABLE pin Turn on Into Pre−bias Short Circuit Protection Fixed Switching Frequency Enhanced Light Load Efficiency Figure 1: NCP3170A Demonstration PCB Key Features Rev 0 - July, 2011 DN05011/D Figure 2: NCP3170A Pinout Table 1: Pin Description PIN PIN NAME 1 PGND 2 VIN 3 AGND 4 FB 5 COMP 6 EN 7 PG 8 VSW DESCRIPTION The power ground pin is the high current path for the device. The pin should be soldered to a large copper area to reduce thermal resistance. PGND needs to be electrically connected to AGND. The input voltage pin powers the internal control circuitry and is monitored by multiple voltage comparators. The VIN pin is also connected to the internal power PMOS switch and linear regulator output. The VIN pin has high di/dt edges and must be decoupled to ground close to the pin of the device. The analog ground pin serves as small-signal ground. All small-signal ground paths should connect to the AGND pin and should also be electrically connected to power ground at a single point, avoiding any high current ground returns. Inverting input to the OTA error amplifier. The FB pin in conjunction with the external compensation serves to stabilize and achieve the desired output voltage with current mode compensation. The loop compensation pin is used to compensate the transconductance amplifier which stabilizes the operation of the converter stage. Place compensation components as close to the converter as possible. Connect a RC network between COMP and AGND to compensate the control loop. Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. Do not leave it open. Power good is an open drain 500uA pull down indicating output voltage is within the power good window. If the power good function is not used, it can be connected to the VSW node to reduce thermal resistance. Do not connect PG to the VSW node if the application is turning on into pre-bias. The VSW pin is the connection of the drains of the internal N and P MOSFETS. At switch off, the inductor will drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt. Rev 0 - July, 2011 DN05011/D Figure 3: NCP3170A Block Diagram Rev 0 - July, 2011 DN05011/D Performance Information The following figures show typical performance of the evaluation board. 5V NCP3170 Efficiency 100 90 80 60 50 40 30 20 10 Output Current (A) 1.2V Figure 4: NCP3170 5V Efficiency Rev 0 - July, 2011 1.8V 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 Efficiency (%) 70 3.3V DN05011/D 12V NCP3170 Efficiency 100 90 80 60 50 40 30 20 10 Output Current (A) 1.2V 1.8V Figure 5: NCP3170 12V Efficiency Schematic Rev 0 - July, 2011 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 Efficiency (%) 70 3.3V 5.0V DN05011/D Schematic Figure 6: NCP3170 1.2V Schematic Rev 0 - July, 2011 DN05011/D Table 2: BOM for the NCP3170 1.2V Design Reference Qty C3 1 CF 1 CC 1 CHF 1 CP 1 C2 C4-5 3 C6 1 C1 1 C7 1 LOUT 1 U1 1 R2 1 R3 1 R4 1 RC 1 R1 1 RF 1 Description SMT Ceramic Capacitor SMT Ceramic Capacitor SMT Ceramic Capacitor SMT Ceramic Capacitor SMT Ceramic Capacitor SMT Ceramic Capacitor SMT Ceramic Capacitor Surface Mount E-Cap Surface Mount E-Cap SMT Inductor Switching PWM Regulator SMT Resistor SMT Resistor SMT Resistor SMT Resistor SMT Resistor SMT Resistor Value Tolerance 0.01uF ±5% 150pF ±5% 10nF ±5% 820pF ±5% NI ±5% 22uF ±20% NI ±10% NI ±20% NI ±20% 2.5uH 20% 500kHz NA 49.9k ±1.0% 100k ±1.0% 20R ±1.0% 2k ±1.0% 24.9k ±1.0% 1k ±1.0% Footprint 603 603 603 603 603 1210 1210 (8mm x 6.2)mm (8.3 x 8.3)mm (10.2x 10.2 x 6.4)mm SOIC8 603 603 603 603 603 603 Rev 0 - July, 2011 Manufacturer TDK Murata TDK AVX Manufacturer Part Number C1608C0G1E103J GRM1885C1H151JA01D C1608C0G1E103J 06035A821JAT2A AVX 12103D226MAT2A Wurth ON Semiconductor Vishay / Dale Vishay / Dale Vishay / Dale Vishay / Dale Vishay / Dale Vishay / Dale 7447798250 NCP3170 CRCW060349K9FKEA CRCW0603100KFKEA CRCW060320R0FKEA CRCW06032K00FKEA CRCW060324K9FKEA CRCW06031K00FKEA DN05011/D Table 3: BOM changes to achieve desired output VIN (V) 12 12 12 12 12 12 12 12 12 12 18 5 5 5 5 5 5 5 5 Vout (V) 0.8 1.0 1.1 1.2 1.5 1.8 2.5 3.3 5.0 10.68 14.8 0.8 1.0 1.1 1.2 1.5 1.8 2.5 3.3 Lout (μF) 1.8 2.5 2.5 2.5 3.6 3.6 4.7 4.7 7.2 7.2 7.2 1.8 2.5 2.5 2.5 3.6 3.6 3.6 3.6 R1 (kΩ) 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 24.9 R2 (kΩ) NI 100 66.5 49.9 28.7 20 11.8 7.87 4.75 2.05 1.43 NI 100 66.5 49.9 28.7 20 11.8 7.87 Rf (kΩ) NI 1 1 1 1 1 1 1 1 1 1 NI 1 1 1 1 1 1 1 Cf (pF) NI 150 150 150 150 150 150 150 150 150 150 NI 150 150 150 150 150 150 150 Rev 0 - July, 2011 Cc (nF) NI 15 10 10 10 10 8.2 6.8 3.9 3.9 6.8 NI 15 10 10 10 10 6.8 6.8 Rc (kΩ) NI .825 2 2 2.49 2.49 3.74 4.99 10 10 6.98 NI .825 2 2 2.49 2.49 4.99 4.99 Cp (nF) 15 NI NI NI NI NI NI NI NI NI NI 15 NI NI NI NI NI NI NI DN05011/D Figure 7: Layout Top Rev 0 - July, 2011 DN05011/D Figure 8: Layout Bottom Rev 0 - July, 2011 DN05011/D Figure9: Output Ripple Voltage 12 V to 3.3 V with 0.3 A Load Figure10: Output Ripple Voltage 12 V to 3.3 V with 3.0 A Load Figure11: Output Ripple Voltage 12 V to 1.2 V with 0.3 A Load Figure12: Output Ripple Voltage 12 V to 1.2 V with 3.0 A Load Rev 0 - July, 2011 DN05011/D Figure13: 12 V to 3.3 V with Soft start Figure14: 12 V to 3.3 V Short Figure15: 12 V to 3.3 V Release From Short Figure16: 12 V to 3.3 V Transient Response 50% to 100% Rev 0 - July, 2011 DN05011/D Figure17: 12 V to 3.3 V 3A Load Frequency Response Figure18: 12 V to 1.2 V 3A Load Frequency Response Rev 0 - July, 2011 DN05011/D Disclaimer: ON Semiconductor is providing this design note “AS IS” and does not assume any liability arising from its use; nor does ON Semiconductor convey any license to its or any third party’s intellectual property rights. This document is provided only to assist customers in evaluation of the referenced circuit implementation and the recipient assumes all liability and risk associated with its use, including, but not limited to, compliance with all regulatory standards. ON Semiconductor may change any of its products at any time, without notice. Design note created by Bryan McCoy, e-mail: [email protected] Rev 0 - July, 2011