Features • Serial EEPROM Family for Configuring Altera FLEX® Devices • Simple Interface to SRAM FPGAs • EE Programmable 512-Kbit and 1-Mbit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) • Cascadable Read Back to Support Additional Configurations or Future Higher-density Arrays • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in the Space-efficient Surface-mount PLCC and PDIP Packages for the • • • • 512-Kbit device and PLCC, PDIP and TQFP Packages for the 1-Mbit Device In-System Programmable via 2-wire Bus Emulation of Atmel’s AT24CXXX Serial EEPROMs Available in 3.3V ± 10% LV and 5V ± 5% C Versions System-friendly READY Pin Description The AT17C512A/010A and AT17LV512A/010A (high-density AT17A Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for programming Altera FLEX® devices. The AT17C512A/LV512A devices are packaged in the popular 8-lead PDIP and the 20-lead PLCC; the AT17C010A/LV010A are packaged in the popular 8-lead PDIP, the 20-lead PLCC and the 32-lead TQFP. The AT17A Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a feature of the AT17A Series, the user can select the polarity of the reset function by programming four EEPROM bytes. The AT17A parts generate their own internal clock by default and can be used as a system “master” for loading the FPGA devices. The internal clock can be disabled by the industrial programmer to allow the AT17A parts to be used as system “slave”, so that the external devices will provide the clock for loading the FPGA devices. The Atmel devices also support a system-friendly READY pin for the 20-lead PLCC package and a write protect mechanism for all packages. The READY pin is used to simplify system power-up considerations. The WP1 pin is used to protect part of the Configurator memory during in-system programming. FPGA Configuration EEPROM Memory 512-kilobit and 1-megabit Altera Pinout AT17C512A AT17LV512A AT17C010A AT17LV010A The AT17A Series Configurator can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP cable. Rev. 0974E–08/01 1 Pin Configuration 20-lead PLCC DCLK WP1 NC NC OE 4 5 6 7 8 3 2 1 20 19 VCC SER_EN (A2) nCASC GND 18 17 16 15 14 9 10 11 12 13 8 7 6 5 1 2 3 4 SER_EN NC NC READY NC nCS GND NC (A2) nCASC NC DATA DCLK OE nCS NC DATA NC VCC NC 8-lead PDIP 32 31 30 29 28 27 26 25 NC DATA NC NC NC VCC NC NC 32-lead TQFP(1) 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 NC SER_EN NC NC READY NC NC NC NC nCS NC GND NC NC (A2) nCASC NC 9 10 11 12 13 14 15 16 NC DCLK NC WP1 NC NC OE NC Note: 2 1. The 32-lead TQFP package is not available for AT17C512A/LV512A devices. AT17C/LV512A/010A 0974E–08/01 AT17C/LV512A/010A Block Diagram SER_EN WP1 PROGRAMMING DATA SHIFT REGISTER PROGRAMMING MODE LOGIC OSC CONTROL ROW ADDRESS COUNTER ROW DECODER OSC BIT COUNTER POWER ON RESET EEPROM CELL MATRIX COLUMN DECODER TC DCLK READY (Optional) Device Configuration OE nCS nCASC (A2) DATA The control signals for the configuration EEPROM (nCS, OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17A Series Configurator. If nCS is held High after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven Low, the counter and the DATA output pin are enabled. When OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS. When the Configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin to avoid contention with other Configurators. Upon power-up, the address counter is automatically reset. 3 0974E–08/01 The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. This document discusses the EPF10K device interface. For more details or information on other Altera applications, please reference the “AT17A Series Conversions from Altera FPGA Serial Configuration Memories” application note. FPGA Device Configuration FPGA devices can be configured with an AT17A Series EEPROM (see Figure 1). The AT17A Series device stores configuration data in its EEPROM array and clocks the data out serially with its internal oscillator. The OE, nCS and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The AT17A Series device sends a serial bitstream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the FPGA device. When configuration data for an FPGA device exceeds the capacity of a single AT17A Series device, multiple AT17A Series devices can be serially linked together (see Figure 2). When multiple AT17A Series devices are required, the nCASC and nCS pins provide handshaking between the cascaded EEPROMs. The position of an AT17A Series device in a chain determines its operation. The first AT17A Series device in a Configurator chain is powered up or reset with nCS Low and is configured for the FPGA device’s protocol. This AT17A Series device supplies all clock pulses to one or more FPGA devices and to any downstream AT17A Series Configurator during configuration. The first AT17A Series Configurator also provides the first stream of data to the FPGA devices during multi-device configuration. Once the first AT17A Series device finishes sending configuration data, it drives its nCASC pin Low, which drives the nCS pin of the second AT17A Series device Low. This activates the second AT17A Series device to send configuration data to the FPGA device. The first AT17A Series device clocks all subsequent AT17A Series devices until configuration is complete. Once all configuration data is transferred and nCS on the first AT17A Series device is driven High by CONF_DONE on the FPGA devices, the first AT17A Series device clocks 16 additional cycles to initialize the FPGA device before going into zero-power (idle) state. If nCS on the first AT17A Series device is driven High before all configuration data is transferred–or if the nCS is not driven High after all configuration data is transferred– nSTATUS is driven Low, indicating a configuration error. The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. It can be used to hold the FPGA device in reset while it is completing its power-on reset but it cannot be used to effectively delay configuration (i.e., the output is released well before the system VCC has stabilized). 4 AT17C/LV512A/010A 0974E–08/01 AT17C/LV512A/010A Figure 1. Configuration with a Single AT17A Series Configurator(1)(2)(3) VCC VCC 1 kW VCC 1 kW 1 kW VCC EPF6K/EPF10K nCONFIG 0.1 mF nCE MSEL0 MSEL1 AT17C512A/010A/020A AT17LV512A/010A/020A DCLK DCLK DATA0 DATA CONF_DONE nSTATUS SER_EN nCS OE READY GND Notes: 1. The use of the READY pin is optional for the 20-lead PLCC and the 32-lead TQFP packages. The 8-lead PDIP package does not have a READY pin. 2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.) 3. Reset polarity of EEPROM must be set active Low (OE active High) 5 0974E–08/01 Figure 2. Configuration with Multiple AT17A Series Configurators(1)(2)(3) VCC VCC VCC 1 kW AT17C512A/010A/020A AT17LV512A/010A/020A DEVICE 1 1 kW EPF10K nCONFIG 1 kW AT17C512A/010A/020A V AT17LV512A/010A/020A CC DEVICE 2 DCLK DCLK DCLK DATA0 DATA DATA SER_EN 0.1 mF nCE CONF_DONE MSEL0 nSTATUS nCS nCASC OE nCS OE READY MSEL1 GND Notes: 1. The use of the READY pin is optional for the 20-lead PLCC and the 32-lead TQFP packages. The 8-lead PDIP package does not have a READY pin. 2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.) 3. Reset polarity of EEPROM must be set active Low (OE active High). AT17A Series Reset Polarity The AT17A Series Configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. For more details, please reference the “Programming Specification for Atmel’s FPGA Configuration EEPROMs” application note. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial interface. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. See the “Programming Specification for Atmel’s Configuration EEPROMs” application note for further information. The AT17A Series parts are read/write at 5V nominal. The AT17LVA Series parts are read/write at 3.3V nominal. Standby Mode The AT17A Series Configurator enters a low-power standby mode whenever nCS is asserted High. In this mode, the configuration consumes less than 0.5 mA of current at 5V. The output remains in a high-impedance state regardless of the state of the OE input. 6 AT17C/LV512A/010A 0974E–08/01 AT17C/LV512A/010A Pin Configurations 8 PDIP Pin 20 PLCC Pin 32 TQFP Pin Name I/O Description 1 2 31 DATA I/O Three-state data output for configuration. Open-collector bi-directional pin for programming. 2 4 2 DCLK I/O Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The counter is incremented only if the OE input is held High, the nCS input is held Low, and all configuration data has not been transferred to the target device (otherwise, as the master device, the DCLK pin drives Low). 5 4 WP1 I WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during FPGA loading operations. See programming specifications for details. 3 8 7 OE I Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level resets the address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and must be programmed active High (RESET active Low) by the user during programming for Altera applications. 4 9 10 nCS I Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the address counter and enables DATA to drive out. If the AT17A Series is reset with nCS Low, the device initializes as the first (and master) device in a daisy-chain. If the AT17A Series is reset with nCS High, the device initializes as a subsequent AT17A Series device in the chain. 5 10 12 GND 6 12 Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND pins. nCASC O Cascade select output (active Low). This output goes Low when the address counter has reached its maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device is usually connected to the nCS input pin of the next device in the chain, which permits DCLK from the master Configurator to clock data from a subsequent AT17A Series device in the chain. A2 I Device selection input, A2. This is used to enable (or select) the device during programming, (i.e., when SER_EN is Low; please refer to the “Programming Specification” application note for more details). 15 15 20 READY(1) O Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated) when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used). 7 18 23 SER_EN I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low, enables the 2-wire serial programming mode. 8 20 27 VCC Note: +3.3V/+5V power supply pin 1. READY is an optional pin. It is not available in the 8-lead PDIP package. 7 0974E–08/01 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +7.0V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260°C Operating Conditions AT17CXXXA Symbol VCC 8 Description AT17LVXXXA Min Max Min Max Units Commercial Supply voltage relative to GND -0°C to +70°C 4.75 5.25 3.0 3.6 V Industrial Supply voltage relative to GND -40°C to +85°C 4.5 5.5 3.0 3.6 V Military Supply voltage relative to GND -55°C to +125°C 4.5 5.5 3.0 3.6 V AT17C/LV512A/010A 0974E–08/01 AT17C/LV512A/010A DC Characteristics VCC = 5V ± 5% Commercial/5V ± 10% Industrial/Military Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0.0 0.8 V VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) VOH High-level Output Voltage (IOH = -4 mA) VOL Low-level Output Voltage (IOL = +4 mA) 0.4 V ICCA Supply Current, Active Mode (at FMAX) 10 mA IL Input or Output Leakage Current (VIN = VCC or GND) 10 µA Commercial 0.5 mA ICCS Supply Current, Standby Mode AT17C512A/010A Industrial/Military 0.5 mA 3.86 V Commercial 0.32 3.76 V V Industrial 0.37 3.7 V V Military -10 DC Characteristics VCC = 3.3V ± 10% Symbol Description Min Max Units VIH High-level Input Voltage 2.0 VCC V VIL Low-level Input Voltage 0.0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +2.5 mA) 0.4 V ICCA Supply Current, Active Mode (at FMAX) 5 mA IL Input or Output Leakage Current (VIN = VCC or GND) 10 µA Commercial 100 µA ICCS Supply Current, Standby Mode Industrial/Military 100 µA 2.4 V Commercial 0.4 2.4 V V Industrial 0.4 2.4 V V Military -10 9 0974E–08/01 AC Characteristics nCS TSCE TSCE THCE OE TLC THOE THC DCLK TOE TCAC TOH TDF TCE DATA TOH AC Characteristics When Cascading OE nCS DCLK TCDF DATA LAST BIT TOCK FIRST BIT TOCE TOOE nCASL TOCE 10 AT17C/LV512A/010A 0974E–08/01 AT17C/LV512A/010A . AC Characteristics for AT17C512A/010A VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Industrial/Military Commercial Symbol Description TOE(2) OE to Data Delay TCE (2) TCAC (2) Min Max Industrial/Military(1) Max Units 30 35 ns nCS to Data Delay 45 45 ns DCLK to Data Delay 50 55 ns TOH Data Hold From nCS, OE, or DCLK TDF(3) nCS or OE to Data Float Delay TLC DCLK Low Time Slave Mode 20 20 ns THC DCLK High Time Slave Mode 20 20 ns TSCE nCS Setup Time to DCLK (to guarantee proper counting) 20 25 ns THCE nCS Hold Time from DCLK (to guarantee proper counting) 0 0 ns TLOE OE Low Time (guarantees counter is reset) 20 20 ns FMAX Maximum Input Clock Frequency Slave Mode 15 15 MHz TLC DCLK Low Time Master Mode 30 250 30 250 ns DCLK High Time Master Mode 30 250 30 250 ns THC Notes: 0 Min 0 50 ns 50 ns 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±=200 mV from steady state active levels. AC Characteristics for AT17C512A/010A When Cascading VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Industrial/Military Commercial Symbol TCDF (3) Description Min Max Industrial/Military(1) Min Max Units DCLK to Data Float Delay 50 50 ns TOCK(2) DCLK to nCASC Delay 35 40 ns TOCE(2) nCS to nCASC Delay 35 35 ns TOOE(2) OE to nCASC Delay 30 30 ns FMAX Maximum Input Clock Frequency Notes: 12.5 12.5 MHz 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ±=200 mV from steady state active levels. 11 0974E–08/01 . AC Characteristics for AT17LV512A/010A VCC = 3.3V ± 10% Commercial/VCC = 3.3V ± 10% Industrial/Military Commercial Symbol Description TOE(2) OE to Data Delay TCE (2) TCAC (2) Min Max Industrial/Military(1) Max Units 50 55 ns nCS to Data Delay 55 60 ns DCLK to Data Delay 60 65 ns TOH Data Hold From nCS, OE, or DCLK TDF(3) nCS or OE to Data Float Delay TLC DCLK Low Time Slave Mode 25 25 ns THC DCLK High Time Slave Mode 25 25 ns TSCE nCS Setup Time to DCLK (to guarantee proper counting) 35 40 ns THCE nCS Hold Time from DCLK (to guarantee proper counting) 0 0 ns TLOE OE Low Time (guarantees counter is reset) 20 20 ns FMAX Maximum Input Clock Frequency Slave Mode 15 10 MHz TLC DCLK Low Time Master Mode 30 300 30 300 ns THC DCLK High Time Master Mode 30 300 30 300 ns VRDY Ready Pin Open Collector Voltage 1.2 2.4 1.2 2.4 V Notes: 0 Min 0 50 ns 50 ns 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for AT17LV512A/010A When Cascading VCC = 3.3V ± 10% Commercial/VCC = 3.3V ± 10% Industrial/Military Commercial Symbol Description TCDF(3) DCLK to Data Float Delay TOCK(2) TOCE(2) TOOE(2) FMAX Notes: 12 Max Units 50 50 ns DCLK to nCASC Delay 50 55 ns nCS to nCASC Delay 35 40 ns OE to nCASC Delay 35 35 ns Maximum Input Clock Frequency Slave Mode Min 12.5 Max Industrial/Military(1) Min 10 MHz 1. Preliminary specifications for military operating range only. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AT17C/LV512A/010A 0974E–08/01 AT17C/LV512A/010A Ordering Information – 5V Devices Memory Size (1) 512-Kbit 1-Mbit(2) Notes: Ordering Code Package Operation Range AT17C512A-10PC AT17C512A-10JC 8P3 20J Commercial (0°C to 70°C) AT17C512A-10PI AT17C512A-10JI 8P3 20J Industrial (-40°C to 85°C) AT17C010A-10PC AT17C010A-10JC AT17C010A-10QC 8P3 20J 32A Commercial (0°C to 70°C) AT17C010A-10PI AT17C010A-10JI AT17C010A-10QI 8P3 20J 32A Industrial (-40°C to 85°C) 1. Use 512-Kbit density parts to replace Altera EPC1441. 2. Use 1-Mbit density parts to replace Altera EPC1. Ordering Information – 3.3V Devices Memory Size (1) 512-Kbit 1-Mbit(2) Notes: Ordering Code Package Operation Range AT17LV512A-10PC AT17LV512A-10JC 8P3 20J Commercial (0°C to 70°C) AT17LV512A-10PI AT17LV512A-10JI 8P3 20J Industrial (-40°C to 85°C) AT17LV010A-10PC AT17LV010A-10JC AT17LV010A-10QC 8P3 20J 32A Commercial (0°C to 70°C) AT17LV010A-10PI AT17LV010A-10JI AT17LV010A-10QI 8P3 20J 32A Industrial (-40°C to 85°C) 1. Use 512-Kbit density parts to replace Altera EPC1441. 2. Use 1-Mbit density parts to replace Altera EPC1. Package Type 8P3 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 32A 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 13 0974E–08/01 Packaging Information 8P3, 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AA JEDEC STANDARD MS-018 AA 32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat package (TQFP) Dimensions in Millimeters and (Inches) PIN 1 ID 9.00 (0.354) BSC 0.45 (0.018) 0.30 (0.012) 0.80 (0.031) BSC 9.00 (0.354) BSC 7.00 (0.276) BSC 0.20 (0.008) 0.10 (0.004) 0.75 (0.030) 0.45 (0.018) 14 1.20 (0.047) MAX 0˚ 7˚ 0.15 (0.006) 0.05 (0.002) AT17C/LV512A/010A 0974E–08/01 Atmel Headquarters Atmel Product Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atme l® is the registered trademark of Atmel. FLEX ® is the registered trademark of Altera Corporation. Other terms and product names may be the trademarks of others. Printed on recycled paper. 0974E–08/01/xM