SAM D20 - Summary

Atmel SAM D20J / SAM D20G / SAM D20E
SMART ARM-Based Microcontroller
DATASHEET SUMMARY
Description
The Atmel® | SMART™ SAM D20 is a series of low-power microcontrollers using the 32-bit
ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and
32KB of SRAM. The SAM D20 devices operate at a maximum frequency of 48MHz and
reach 2.14 Coremark/MHz. They are designed for simple and intuitive migration with
identical peripheral modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All devices include
intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and
support for capacitive touch button, slider and wheel user interfaces.
The Atmel | SMART SAM D20 devices provide the following features: In-system
programmable Flash, eight-channel Event System, programmable interrupt controller, up to
52 programmable I/O pins, 32-bit real-time clock and calendar, up to eight 16-bit
Timer/Counters (TC). The timer/counters can be configured to perform frequency and
waveform generation, program execution timing or input capture with time and frequency
measurement of digital signals. The TCs can operate in 8- or 16-bit mode, or be cascaded
to form a 32-bit TC. The series provide up to six Serial Communication Modules (SERCOM)
that each can be configured to act as an USART, UART, SPI and I2C up to 400kHz; up to
twenty-channel 350ksps 12-bit ADC with programmable gain and optional oversampling
and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog
comparators with window mode, Peripheral Touch Controller supporting up to 256 buttons,
sliders, wheels, and proximity sensing; programmable Watchdog Timer, brown-out detector
and power-on reset, and two-pin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can
be used as a source for the system clock. Different clock domains can be independently
configured to run at different frequencies while enabling power saving by running each
peripheral at its optimal clock frequency.
The Atmel | SMART SAM D20 devices have two software-selectable sleep modes, idle and
standby. In idle mode the CPU is stopped while all other functions can be kept running. In
standby all clocks and functions are stopped expect those selected to continue running. The
device supports SleepWalking. This feature allows the peripheral to wake up from sleep
based on predefined conditions, and thus allows the CPU to wake up only when needed,
e.g. when a threshold is crossed or a result is ready. The Event System supports
synchronous and asynchronous events, allowing peripherals to receive, react to and send
events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface.
The same interface can be used for non-intrusive on-chip debug of application code. A boot
loader running in the device can use any communication interface to download and upgrade
the application program in the Flash memory.
The Atmel | SMART SAM D20 devices are supported with a full suite of program and system
development tools, including C compilers, macro assemblers, program
debugger/simulators, programmers and evaluation kits.
Atmel-42129NS–SAM-D20_Summary–01/2015
SMART
Features
z Processor
ARM Cortex-M0+ CPU running at up to 48MHz
z Single-cycle hardware multiplier
Memories
z 16/32/64/128/256KB in-system self-programmable flash
z 2/4/8/16/32KB SRAM
System
z Power-on reset (POR) and brown-out detection (BOD)
z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)
z External Interrupt Controller (EIC)
z 16 external interrupts
z One non-maskable interrupt
z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
z Idle and standby sleep modes
z SleepWalking peripherals
Peripherals
z 8-channel Event System
z Up to eight 16-bit Timer/Counters (TC), configurable as either:
z
z
z
z
z
z
One 16-bit TC with compare/capture channels
One 8-bit TC with compare/capture channels
z One 32-bit TC with compare/capture channels, by using two TCs
z
z
z
z
z
z
z
z
z
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
z USART with full-duplex and single-wire half-duplex configuration
2
z I C up to 400kHz
z SPI
One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
z Differential and single-ended channels
z 1/2x to 16x gain stage
z Automatic offset and gain error compensation
z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
10-bit, 350ksps Digital-to-Analog Converter (DAC)
Two Analog Comparators with window compare function
Peripheral Touch Controller (PTC)
z
256-Channel capacitive touch and proximity sensing
z I/O
z
Up to 52 programmable I/O pins
z Packages
64-pin TQFP, QFN
64-ball UFBGA
z 48-pin TQFP, QFN
z 45-ball WLCSP
z 32-pin TQFP, QFN
z Operating Voltage
z 1.62V – 3.63V
z Power Consumption
z Down to 70µA/MHz in active mode
z Down to 8µA running the Peripheral Touch Controller
z
z
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
2
1.
Configuration Summary
Table 1-1.
Configuration Summary
SAM D20J
SAM D20G
SAM D20E
Number of pins
64
48
32
General Purpose I/O-pins (GPIOs)
52
38
26
Flash
256/128/64/32/16KB
256/128/64/32/16KB
256/128/64/32/16KB
SRAM
32/16/8/4/2KB
32/16/8/4/2KB
32/16/8/4/2KB
Maximum CPU frequency
48MHz
Event System channels
8
8
8
Timer Counter (TC)
8
6
6
Waveform output channels for TC
2
2
2
Serial Communication Interface
(SERCOM)
6
6
4
Analog-to-Digital Converter (ADC)
channels
20
14
10
Analog comparators
2
2
2
Digital-to-Analog Converter (DAC)
channels
1
1
1
Yes
Yes
Yes
1
1
1
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
16
16
16
16x16
12x10
10x6
QFN
TQFP
UFBGA
QFN
TQFP
WLCSP
QFN
TQFP
Real-Time Counter (RTC)
RTC alarms
RTC compare values
External Interrupt lines
Peripheral Touch Controller (PTC) X
and Y lines
Packages
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHzinternal oscillator (OSC32K)
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
Oscillators
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
3
2.
Ordering Information
SAMD 20 E 14 A - M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
20 = Cortex M0+ CPU, Basic Feature Set
Package Grade
O
Pin Count
U = -40 - 85 C Matte Sn Plating
N = -40 - 105 C Matte Sn Plating
O
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
Flash Memory Density
A = TQFP
M = QFN
C = UFBGA
U = WLCSP
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Default Variant
2.1
SAM D20E
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20E14A-AU
Tray
ATSAMD20E14A-AN
TQFP32
ATSAMD20E14A-AUT
Tape & Reel
ATSAMD20E14A-ANT
16K
2K
ATSAMD20E14A-MU
Tray
ATSAMD20E14A-MN
QFN32
ATSAMD20E14A-MUT
Tape & Reel
ATSAMD20E14A-MNT
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
4
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20E15A-AU
Tray
ATSAMD20E15A-AN
TQFP32
ATSAMD20E15A-AUT
Tape & Reel
ATSAMD20E15A-ANT
32K
4K
ATSAMD20E15A-MU
Tray
ATSAMD20E15A-MN
QFN32
ATSAMD20E15A-MUT
Tape & Reel
ATSAMD20E15A-MNT
ATSAMD20E16A-AU
Tray
ATSAMD20E16A-AN
TQFP32
ATSAMD20E16A-AUT
Tape & Reel
ATSAMD20E16A-ANT
64K
8K
ATSAMD20E16A-MU
Tray
ATSAMD20E16A-MN
QFN32
ATSAMD20E16A-MUT
Tape & Reel
ATSAMD20E16A-MNT
ATSAMD20E17A-AU
Tray
ATSAMD20E17A-AN
TQFP32
ATSAMD20E17A-AUT
Tape & Reel
ATSAMD20E17A-ANT
128K
16K
ATSAMD20E17A-MU
Tray
ATSAMD20E17A-MN
QFN32
ATSAMD20E17A-MUT
Tape & Reel
ATSAMD20E17A-MNT
ATSAMD20E18A-AU
Tray
ATSAMD20E18A-AN
TQFP32
ATSAMD20E18A-AUT
Tape & Reel
ATSAMD20E18A-ANT
256K
32K
ATSAMD20E18A-MU
Tray
ATSAMD20E18A-MN
QFN32
ATSAMD20E18A-MUT
Tape & Reel
ATSAMD20E18A-MNT
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
5
2.2
SAM D20G
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20G14A-AU
Tray
ATSAMD20G14A-AN
TQFP48
ATSAMD20G14A-AUT
Tape & Reel
ATSAMD20G14A-ANT
16K
2K
ATSAMD20G14A-MU
Tray
ATSAMD20G14A-MN
QFN48
ATSAMD20G14A-MUT
Tape & Reel
ATSAMD20G14A-MNT
ATSAMD20G15A-AU
Tray
ATSAMD20G15A-AN
TQFP48
ATSAMD20G15A-AUT
Tape & Reel
ATSAMD20G15A-ANT
32K
4K
ATSAMD20G15A-MU
Tray
ATSAMD20G15A-MN
QFN48
ATSAMD20G15A-MUT
Tape & Reel
ATSAMD20G15A-MNT
ATSAMD20G16A-AU
Tray
ATSAMD20G16A-AN
TQFP48
ATSAMD20G16A-AUT
Tape & Reel
ATSAMD20G16A-ANT
64K
8K
ATSAMD20G16A-MU
Tray
ATSAMD20G16A-MN
QFN48
ATSAMD20G16A-MUT
Tape & Reel
ATSAMD20G16A-MNT
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
6
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20G17A-AU
Tray
ATSAMD20G17A-AN
TQFP48
ATSAMD20G17A-AUT
Tape & Reel
ATSAMD20G17A-ANT
ATSAMD20G17A-MU
128K
16K
Tray
ATSAMD20G17A-MN
QFN48
ATSAMD20G17A-MUT
Tape & Reel
ATSAMD20G17A-MNT
ATSAMD20G17A-UUT
WLCSP45
Tape & Reel
ATSAMD20G18A-AU
Tray
ATSAMD20G18A-AN
TQFP48
ATSAMD20G18A-AUT
Tape & Reel
ATSAMD20G18A-ANT
ATSAMD20G18A-MU
256K
32K
Tray
ATSAMD20G18A-MN
QFN48
ATSAMD20G18A-MUT
Tape & Reel
ATSAMD20G18A-MNT
ATSAMD20G18A-UUT
2.3
WLCSP45
Tape & Reel
Package
Carrier Type
SAM D20J
Ordering Code
FLASH (bytes)
SRAM (bytes)
ATSAMD20J14A-AU
Tray
ATSAMD20J14A-AN
TQFP64
ATSAMD20J14A-AUT
Tape & Reel
ATSAMD20J14A-ANT
16K
2K
ATSAMD20J14A-MU
Tray
ATSAMD20J14A-MN
QFN64
ATSAMD20J14A-MUT
Tape & Reel
ATSAMD20J14A-MNT
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
7
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J15A-AU
Tray
ATSAMD20J15A-AN
TQFP64
ATSAMD20J15A-AUT
Tape & Reel
ATSAMD20J15A-ANT
32K
4K
ATSAMD20J15A-MU
Tray
ATSAMD20J15A-MN
QFN64
ATSAMD20J15A-MUT
Tape & Reel
ATSAMD20J15A-MNT
ATSAMD20J16A-AU
Tray
ATSAMD20J16A-AN
TQFP64
ATSAMD20J16A-AUT
Tape & Reel
ATSAMD20J16A-ANT
64K
8K
ATSAMD20J16A-MU
Tray
ATSAMD20J16A-MN
QFN64
ATSAMD20J16A-MUT
Tape & Reel
ATSAMD20J16A-MNT
ATSAMD20J17A-AU
Tray
ATSAMD20J17A-AN
TQFP64
ATSAMD20J17A-AUT
Tape & Reel
ATSAMD20J17A-ANT
ATSAMD20J17A-MU
128K
16K
Tray
ATSAMD20J17A-MN
QFN64
ATSAMD20J17A-MUT
Tape & Reel
ATSAMD20J17A-MNT
ATSAMD20J17A-CU
Tray
UFBGA64
ATSAMD20J17A-CUT
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
8
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD20J18A-AU
Tray
ATSAMD20J18A-AN
TQFP64
ATSAMD20J18A-AUT
Tape & Reel
ATSAMD20J18A-ANT
ATSAMD20J18A-MU
256K
32K
Tray
ATSAMD20J18A-MN
QFN64
ATSAMD20J18A-MUT
Tape & Reel
ATSAMD20J18A-MNT
ATSAMD20J18A-CU
Tray
UFBGA64
ATSAMD20J18A-CUT
Tape & Reel
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
9
3.
Block Diagram
ARM SINGLE CYCLE IOBUS
SWCLK
ARM CORTEX-M0+
PROCESSOR
Fmax 48MHz
SERIAL
WIRE
SWDIO
DEVICE
SERVICE
UNIT
M
M
HIGH SPEED
BUS MATRIX
S
S
AHB-APB
BRIDGE A
32/16/8/4/2KB
RAM
S
AHB-APB
BRIDGE C
S
NVM
256/128/64/32/16KB
CONTROLLERFLASH
S
PERIPHERAL
ACCESS CONTROLLER
AHB-APB
BRIDGE B
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
PORT
SYSTEM CONTROLLER
VREF
BOD33
66xxSERCOM
SERCOM
PIN[3:0]
8 x TIMER COUNTER
8 x(See
Timer
Counter
Note1)
WO[1:0]
OSCULP32K
OSC32K
OSC8M
XIN
XOUT
XOSC
DFLL48M
POWER MANAGER
AIN[19:0]
ADC
RESET
RESET
CONTROLLER
GCLK_IO[7:0]
SLEEP
CONTROLLER
WATCHDOG
TIMER
EXTINT[15:0]
NMI
Notes:
1.
AIN[3:0]
2 ANALOG
COMPARATORS
GENERIC CLOCK
CONTROLLER
REAL TIME
COUNTER
EXTERNAL INTERRUPT
CONTROLLER
VREFA
VREFB
CLOCK
CONTROLLER
PORT
XOSC32K
EVENT SYSTEM
XIN32
XOUT32
CMP1:0]
VOUT
DAC
VREFA
PERIPHERAL
TOUCH
CONTROLLER
X[15:0]
Y[15:0]
Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. Refer to “Configuration Summary” on
page 3 for details.
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
10
Pinout
4.1
SAM D20J
4.1.1
QFP64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
4.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
11
4.1.2
UFBGA64
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
12
SAM D20G
4.2.1
QFP48
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
4.2
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
13
4.2.2
WLCSP45
"
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
14
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
SAM D20E
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
4.3
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel | SMART SAM D20 [DATASHEET Summary]
Atmel-42129NS–SAM-D20_Summary–01/2015
15
5.
I/O Multiplexing and Considerations
5.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the
peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable
bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written
to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in
the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins.
Table 5-1.
PORT Function Multiplexing
Pin
B(1)
A
SAM SAM SAM I/O
Pin
D20E D20G D20J Pin Supply Type
EIC
REF
ADC
AC
C
PTC DAC
D
E
SERCOM(2)
F
TC(3)
1
1
1
PA00 VDDANA
EXTINT[0]
2
2
2
PA01 VDDANA
EXTINT[1]
SERCOM1/
PAD[1]
TC2/
WO[1]
3
3
3
PA02 VDDANA
EXTINT[2]
AIN[0]
Y[0]
4
PA03 VDDANA
ADC/VREFA
EXTINT[3]
AIN[1]
DAC/VREFA
Y[1]
5
PB04 VDDANA
EXTINT[4]
AIN[12]
Y[10]
6
PB05 VDDANA
EXTINT[5]
AIN[13]
Y[11]
4
H
AC/GCLK
SERCOM1/
PAD[0]
4
G
TC2/
WO[0]
VOUT
9
PB06 VDDANA
EXTINT[6]
AIN[14]
Y[12]
10
PB07 VDDANA
EXTINT[7]
AIN[15]
Y[13]
7
11
PB08 VDDANA
EXTINT[8]
AIN[2]
Y[14]
SERCOM4/
PAD[0]
TC4/
WO[0]
8
12
PB09 VDDANA
EXTINT[9]
AIN[3]
Y[15]
SERCOM4/
PAD[1]
TC4/
WO[1]
5
9
13
PA04 VDDANA
EXTINT[4]
AIN[4] AIN[0] Y[2]
SERCOM0/
PAD[0]
TC0/
WO[0]
6
10
14
PA05 VDDANA
EXTINT[5]
AIN[5] AIN[1] Y[3]
SERCOM0/
PAD[1]
TC0/
WO[1]
7
11
15
PA06 VDDANA
EXTINT[6]
AIN[6] AIN[2] Y[4]
SERCOM0/
PAD[2]
TC1/
WO[0]
8
12
16
PA07 VDDANA
EXTINT[7]
AIN[7] AIN[3] Y[5]
SERCOM0/
PAD[3]
TC1/
WO[1]
11
13
17
PA08
VDDIO
I2C
NMI
AIN[16]
X[0]
SERCOM0/ SERCOM2/
PAD[0]
PAD[0]
TC0/
WO[0]
12
14
18
PA09
VDDIO
I2C
EXTINT[9]
AIN[17]
X[1]
SERCOM0/ SERCOM2/
PAD[1]
PAD[1]
TC0/
WO[1]
13
15
19
PA10
VDDIO
EXTINT[10]
AIN[18]
X[2]
SERCOM0/ SERCOM2/
PAD[2]
PAD[2]
TC1/
WO[0]
GCLK_O[4]
14
16
20
PA11
VDDIO
EXTINT[11]
AIN[19]
X[3]
SERCOM0/ SERCOM2/
PAD[3]
PAD[3]
TC1/
WO[1]
GCLK_IO[5]
19
23
PB10
VDDIO
EXTINT[10]
SERCOM4/
PAD[2]
TC5/
WO[0]
GCLK_IO[4]
20
24
PB11
VDDIO
EXTINT[11]
SERCOM4/
PAD[3]
TC5/
WO[1]
GCLK_IO[5]
25
PB12
VDDIO
I2C
EXTINT[12]
X[12]
SERCOM4/
PAD[0]
TC4/
WO[0]
GCLK_IO[6]
26
PB13
VDDIO
I2C
EXTINT[13]
X[13]
SERCOM4/
PAD[1]
TC4/
WO[1]
GCLK_IO[7]
27
PB14
VDDIO
EXTINT[14]
X[14]
SERCOM4/
PAD[2]
TC5/
WO[0]
GCLK_IO[0]
28
PB15
VDDIO
EXTINT[15]
X[15]
SERCOM4/
PAD[3]
TC5/
WO[1]
GCLK_IO[1]
ADC/
VREFB
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Table 5-1.
PORT Function Multiplexing (Continued)
Pin
B(1)
A
SAM SAM SAM I/O
Pin
D20E D20G D20J Pin Supply Type
EIC
REF
ADC
AC
C
PTC DAC
D
E
SERCOM(2)
F
G
TC(3)
H
AC/GCLK
21
29
PA12
VDDIO
I2C
EXTINT[12]
SERCOM2/ SERCOM4/
PAD[0]
PAD[0]
TC2/
WO[0]
AC/CMP[0]
22
30
PA13
VDDIO
I2C
EXTINT[13]
SERCOM2/ SERCOM4/
PAD[1]
PAD[1]
TC2/
WO[1]
AC/CMP[1]
15
23
31
PA14
VDDIO
EXTINT[14]
SERCOM2/ SERCOM4/
PAD[2]
PAD[2]
TC3/
WO[0]
GCLK_IO[0]
16
24
32
PA15
VDDIO
EXTINT[15]
SERCOM2/ SERCOM4/
PAD[3]
PAD[3]
TC3/
WO[1]
GCLK_IO[1]
17
25
35
PA16
VDDIO
I2C
EXTINT[0]
X[4]
SERCOM1/ SERCOM3/
PAD[0]
PAD[0]
TC2/
WO[0]
GCLK_IO[2]
18
26
36
PA17
VDDIO
I2C
EXTINT[1]
X[5]
SERCOM1/ SERCOM3/
PAD[1]
PAD[1]
TC2/
WO[1]
GCLK_IO[3]
19
27
37
PA18
VDDIO
EXTINT[2]
X[6]
SERCOM1/ SERCOM3/
PAD[2]
PAD[2]
TC3/
WO[0]
AC/CMP[0]
20
28
38
PA19
VDDIO
EXTINT[3]
X[7]
SERCOM1/ SERCOM3/
PAD[3]
PAD[3]
TC3/
WO[1]
AC/CMP[1]
39
PB16
VDDIO
I2C
EXTINT[0]
SERCOM5/
PAD[0]
TC6/
WO[0]
GCLK_IO[2]
40
PB17
VDDIO
I2C
EXTINT[1]
SERCOM5/
PAD[1]
TC6/
WO[1]
GCLK_IO[3]
29
41
PA20
VDDIO
EXTINT[4]
X[8]
SERCOM5/ SERCOM3/
PAD[2]
PAD[2]
TC7/
WO[0]
GCLK_IO[4]
30
42
PA21
VDDIO
EXTINT[5]
X[9]
SERCOM5/ SERCOM3/
PAD[3]
PAD[3]
TC7/
WO[1]
GCLK_IO[5]
21
31
43
PA22
VDDIO
I2C
EXTINT[6]
X[10]
SERCOM3/ SERCOM5/
PAD[0]
PAD[0]
TC4/
WO[0]
GCLK_IO[6]
22
32
44
PA23
VDDIO
I2C
EXTINT[7]
X[11]
SERCOM3/ SERCOM5/
PAD[1]
PAD[1]
TC4/
WO[1]
GCLK_IO[7]
23
33
45
PA24
VDDIO
EXTINT[12]
SERCOM3/ SERCOM5/
PAD[2]
PAD[2]
TC5/
WO[0]
24
34
46
PA25
VDDIO
EXTINT[13]
SERCOM3/ SERCOM5/
PAD[3]
PAD[3]
TC5/
WO[1]
37
49
PB22
VDDIO
EXTINT[6]
SERCOM5/
PAD[2]
TC7/
WO[0]
GCLK_IO[0]
38
50
PB23
VDDIO
EXTINT[7]
SERCOM5/
PAD[3]
TC7/
WO[1]
GCLK_IO[1]
25
39
51
PA27
VDDIO
EXTINT[15]
GCLK_IO[0]
27
41
53
PA28
VDDIO
EXTINT[8]
GCLK_IO[0]
31
45
57
PA30
VDDIO
EXTINT[10]
SERCOM1/
PAD[2]
TC1/
WO[0]
32
46
58
PA31
VDDIO
EXTINT[11]
SERCOM1/
PAD[3]
TC1/
WO[1]
59
PB30
VDDIO
I2C
EXTINT[14]
SERCOM5/
PAD[0]
TC0/
WO[0]
60
PB31
VDDIO
I2C
EXTINT[15]
SERCOM5/
PAD[1]
TC0/
WO[1]
61
PB00 VDDANA
EXTINT[0]
AIN[8]
Y[6]
SERCOM5/
PAD[2]
TC7/
WO[0]
62
PB01 VDDANA
EXTINT[1]
AIN[9]
Y[7]
SERCOM5/
PAD[3]
TC7/
WO[1]
47
63
PB02 VDDANA
EXTINT[2]
AIN[10]
Y[8]
SERCOM5/
PAD[0]
TC6/
WO[0]
48
64
PB03 VDDANA
EXTINT[3]
AIN[11]
Y[9]
SERCOM5/
PAD[1]
TC6/
WO[1]
Note:
1.
2.
3.
4.
SWCLK GCLK_IO[0]
SWDIO(4)
All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.
Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode.
Note that TC6 and TC7 are not supported on the SAM D20G. Refer to “Configuration Summary” on page 3 for details.
This function is only activated in the presence of a debugger
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5.2
Other Functions
5.2.1
Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL).
Oscillator
Supply
XOSC
VDDIO
XOSC32K
5.2.2
Signal
I/O Pin
XIN
PA14
XOUT
PA15
XIN32
PA00
XOUT32
PA01
VDDANA
Serial Wire Debug Interface Pinout
After reset, SWCLK functionality is selected for pin PA30 to allow for debugger probe detection. The application software
can switch the SWCLK functionality of PA30 to GPIO (or other peripherals) during runtime. PA31, by default, is configured like other normal I/O pins and will automatically switch to SWDIO function when a debugger cold-plugging or hotplugging is detected. When the device is put in debug mode, application software accesses to PA30 and PA31 PORT
registers are ignored.
Signal
Supply
I/O Pin
SWCLK
VDDIO
PA30
SWDIO
VDDIO
PA31
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6.
Product Mapping
Figure 6-1. SAM D20 Product Mapping
Global Memory Space
0x00000000
Code
0x00000000
Internal flash
Code
0x20000000
0x00040000
Reserved
SRAM
0x1FFFFFFF
SRAM
0x20008000
0x20000000
Undefined
0x40000000
AHB-APB Bridge C
Internal SRAM
0x42000000
PAC2
0x20008000
0x42000400
Peripherals
Peripherals
0x40000000
0x43000000
SERCOM0
AHB-APB
Bridge A
Reserved
AHB-APB
Bridge B
Undefined
0x42000000
0x60000200
Reserved
System
SERCOM1
SERCOM2
0x42001400
SERCOM3
0x42001800
AHB-APB
Bridge C
0xE0000000
0x42000C00
0x42001000
0x41000000
0x60000000
EVSYS
0x42000800
SERCOM4
0x42001C00
SERCOM5
0x42FFFFFF
0x42002000
0xFFFFFFFF
System
0xE0000000
TC0
0x42002400
TC1
Reserved
0x42002800
0xE000E000
TC2
SCS
0x42002C00
0xE000F000
TC3
Reserved
AHB-APB Bridge A
0x40000000
PAC0
0x42003000
0xE00FF000
0x42003400
0xE0100000
TC5
Reserved
0xFFFFFFFF
0x40000400
TC4
ROM Table
0x42003800
TC6
PM
0x40000800
SYSCTRL
AHB-APB Bridge B
0x42004800
0x41004000
0x41004400
0x42004C00
PORT
EIC
0x41004800
0x40001C00
DAC
NVMCTRL
RTC
0x40001800
AC
DSU
WDT
Reserved
0x40FFFFFF
0x42004400
0x41002000
0x40001400
ADC
PAC1
GCLK
0x40001000
TC7
0x42004000
0x41000000
0x40000C00
0x42003C00
PTC
0x42005000
Reserved
0x41FFFFFF
Reserved
0x42FFFFFF
This figure represents the full configuration of the Atmel® SAM D20 with maximum flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 3 for details.
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7.
Processor and Architecture
7.1
Cortex-M0+ Processor
The Atmel® SAM D20 implements the ARM® Cortex®-M0+ processor, which is based on the ARMv6 architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and
upward compatible with the Cortex-M3 and Cortex-M4 processors. The ARM Cortex-M0+ implemented is revision r0p1.
For more information, refer to www.arm.com.
7.1.1
Cortex-M0+ Configuration
Feature
Configurable Option
SAM D20 Configuration
Interrupts
External interrupts 0-32
32
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint comparators
0, 1, 2
2
Number of breakpoint comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Absent
Memory Protection Unit
Not present or 8-region
Not present
Reset all registers
Present or absent
Absent(1)
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
Note:
1.
All software run in privileged mode only
The ARM Cortex-M0+ processor has two bus interfaces:
z
Single 32-bit AMBA® 3 AHB-Lite™ system interface that provides connections to peripherals and all system
memory, including flash and RAM
z
Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores
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8.
Packaging Information
8.1
Thermal Considerations
8.1.1
Thermal Resistance Data
Table 8-1 summarizes the thermal resistance data depending on the package.
Table 8-1.
8.1.2
Thermal Resistance Data
Package Type
θJA
θJC
32-pin TQFP
68°C/W
25.8°C/W
48-pin TQFP
78.8°C/W
12.3°C/W
64-pin TQFP
66.7°C/W
11.9°C/W
32-pin QFN
37.2°C/W
3.1°C/W
48-pin QFN
33°C/W
11.4°C/W
64-pin QFN
33.5°C/W
11.2°C/W
64-ball UFBGA
67.4°C/W
12.4°C/W
45-ball WLCSP
37.0°C/W
0.36°C/W
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following equations:
Equation 1
T J = T A + ( P D × θ JA )
Equation 2
T J = T A + ( P D × ( θ HEATSINK + θ JC ) )
where:
z
θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1
z
θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 8-1
z
θHEATSINK = cooling device thermal resistance (°C/W), provided in the manufacturer datasheet
z
PD = device power consumption (W)
z
TA = ambient temperature (°C)
From “Equation 1” , the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or
not. If a cooling device is to be fitted on the chip, “Equation 2” should be used to compute the resulting average chipjunction temperature TJ in °C.
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8.2
Package Drawings
8.2.1
64-pin TQFP
Table 8-2.
Device and Package Maximum Weight
300
Table 8-3.
mg
Package Characteristics
Moisture Sensitivity Level
Table 8-4.
MSL3
Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
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8.2.2
64-pin QFN
Note:
The exposed die attached pad is not connected inside the device.
Table 8-5.
Device and Package Maximum Weight
200
Table 8-6.
mg
Package Characteristics
Moisture Sensitivity Level
Table 8-7.
MSL3
Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
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8.2.3
64-ball UFBGA
Table 8-8.
Device and Package Maximum Weight
27.4
Table 8-9.
mg
Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-10. Package Reference
JEDEC Drawing Reference
MO-280
JESD97 Classification
E8
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8.2.4
48-pin TQFP
Table 8-11. Device and Package Maximum Weight
140
mg
Table 8-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-13. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
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8.2.5
48-pin QFN
Note:
The exposed die attached pad is not connected inside the device.
Table 8-14. Device and Package Maximum Weight
140
mg
Table 8-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-16. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
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8.2.6
45-ball WLCSP
Note:
The exposed die attached pad is not connected inside the device.
Table 8-17. Device and Package Maximum Weight
7.3
mg
Table 8-18. Package Characteristics
Moisture Sensitivity Level
MSL1
Table 8-19. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E1
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8.2.7
32-pin TQFP
Table 8-20. Device and Package Maximum Weight
100
mg
Table 8-21. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-22. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
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8.2.8
32-pin QFN
Note:
The exposed die attached pad is connected inside the device to GND and GNDANA connected together.
Table 8-23. Device and Package Maximum Weight
90
mg
Table 8-24. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-25. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
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8.3
Soldering Profile
Table Table 8-26 gives the recommended soldering profile from J-STD-20.
Table 8-26. Soldering Profile
Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
___REV___287610
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Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
2.2
2.3
SAM D20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SAM D20G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SAM D20J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
SAM D20J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SAM D20G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SAM D20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
5.2
Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7. Processor and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1
Cortex-M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
8.2
8.3
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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