SAM D21 - Summary

SMART ARM-based Microcontroller
SAM D21E / SAM D21G /SAM D21J Summary
DATASHEET SUMMARY
Introduction
®
™
Atmel | SMART SAM D21 is a series of low-power microcontrollers using
®
®
the 32-bit ARM Cortex -M0+ processor, and ranging from 32- to 64-pins
with up to 256KB Flash and 32KB of SRAM. The SAM D21 devices operate
®
at a maximum frequency of 48MHz and reach 2.46 CoreMark /MHz. They
are designed for simple and intuitive migration with identical peripheral
modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All
devices include intelligent and flexible peripherals, Atmel Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and
wheel user interfaces.
Features
•
•
•
This is a summary document. A
complete document is available
on our Web site at
www.atmel.com
•
Processor
– ARM Cortex-M0+ CPU running at up to 48MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer (MTB)
Memories
– 32/64/128/256KB in-system self-programmable Flash
– 4/8/16/32KB SRAM Memory
System
– Power-on reset (POR) and brown-out detection (BOD)
– Internal and external clock options with 48MHz Digital Frequency
Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional Digital
Phase Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– 16 external interrupts
– One non-maskable interrupt
– Two-pin Serial Wire Debug (SWD) programming, test and
debugging interface
Low Power
– Idle and standby sleep modes
– SleepWalking peripherals
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
•
Peripherals
– 12-channel Direct Memory Access Controller (DMAC)
– 12-channel Event System
– Up to five 16-bit Timer/Counters (TC), configurable as either:
• One 16-bit TC with two compare/capture channels
• One 8-bit TC with two compare/capture channels
• One 32-bit TC with two compare/capture channels, by using two TCs
– Three 24-bit Timer/Counters for Control (TCC), with extended functions:
•
•
•
–
–
–
–
–
–
–
–
–
–
•
•
•
•
Up to four compare channels with optional complementary output
Generation of synchronized pulse width modulation (PWM) pattern across port pins
Deterministic fault protection, fast decay and configurable dead-time between
complementary output
• Dithering that increase resolution with up to 5 bit and reduce quantization error
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
• Embedded host and device function
• Eight endpoints
Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as
either:
• USART with full-duplex and single-wire half-duplex configuration
• I2C up to 3.4MHz
• SPI
• LIN slave
One two-channel Inter-IC Sound (I2S) interface
One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
• Differential and single-ended input
• 1/2x to 16x programmable gain stage
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
10-bit, 350ksps Digital-to-Analog Converter (DAC)
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
• 256-Channel capacitive touch and proximity sensing
I/O
– Up to 52 programmable I/O pins
Drop in compatible with SAM D20
Packages
– 64-pin TQFP, QFN, UFBGA
– 48-pin TQFP, QFN, WLCSP
– 32-pin TQFP, QFN, WLCSP
Operating Voltage
– 1.62V – 3.63V
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
2
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description.................................................................................................................4
2. Configuration Summary............................................................................................. 5
3. Ordering Information..................................................................................................7
3.1.
3.2.
3.3.
3.4.
SAM D21E....................................................................................................................................7
SAM D21G................................................................................................................................... 9
SAM D21J...................................................................................................................................11
Device Identification................................................................................................................... 13
4. Block Diagram......................................................................................................... 15
5. Pinout.......................................................................................................................16
5.1.
5.2.
5.3.
SAM D21J.................................................................................................................................. 16
SAM D21G................................................................................................................................. 18
SAM D21E..................................................................................................................................20
6. Product Mapping......................................................................................................22
7. Processor And Architecture..................................................................................... 23
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
Cortex M0+ Processor................................................................................................................23
Nested Vector Interrupt Controller..............................................................................................25
Micro Trace Buffer...................................................................................................................... 26
High-Speed Bus System............................................................................................................ 27
AHB-APB Bridge........................................................................................................................ 30
PAC - Peripheral Access Controller............................................................................................31
8. Packaging Information............................................................................................. 49
8.1.
8.2.
8.3.
Thermal Considerations............................................................................................................. 49
Package Drawings......................................................................................................................50
Soldering Profile......................................................................................................................... 59
1.
Description
®
™
®
®
The Atmel | SMART SAM D21 is a series of low-power microcontrollers using the 32-bit ARM Cortex M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and 32KB of SRAM. The SAM
D21 devices operate at a maximum frequency of 48MHz and reach 2.46 CoreMark/MHz. They are
designed for simple and intuitive migration with identical peripheral modules, hex compatible code,
identical linear address map and pin compatible migration paths between all devices in the product
series. All devices include intelligent and flexible peripherals, Atmel Event System for inter-peripheral
signaling, and support for capacitive touch button, slider and wheel user interfaces.
The SAM D21 devices provide the following features: In-system programmable Flash, twelve-channel
direct memory access (DMA) controller, 12 channel Event System, programmable interrupt controller, up
to 52 programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC)
and three 24-bit Timer/Counters for Control (TCC), where each TC can be configured to perform
frequency and waveform generation, accurate program execution timing or input capture with time and
frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be
cascaded to form a 32-bit TC, and three timer/counters have extended functions optimized for motor,
lighting and other control applications. The series provide one full-speed USB 2.0 embedded host and
device interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act
as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN slave; two-channel I2S interface;
up to twenty-channel 350ksps 12-bit ADC with programmable gain and optional oversampling and
decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with
window mode, Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels and proximity
sensing; programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire
Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a
source for the system clock. Different clock domains can be independently configured to run at different
frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus
maintaining a high CPU frequency while reducing power consumption.
The SAM D21 devices have two software-selectable sleep modes, idle and standby. In idle mode the
CPU is stopped while all other functions can be kept running. In standby all clocks and functions are
stopped expect those selected to continue running. The device supports SleepWalking. This feature
allows the peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to
wake up only when needed, e.g. when a threshold is crossed or a result is ready. The Event System
supports synchronous and asynchronous events, allowing peripherals to receive, react to and send
events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same
interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the
device can use any communication interface to download and upgrade the application program in the
Flash memory.
The SAM D21 devices are supported with a full suite of program and system development tools, including
C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
4
2.
Configuration Summary
SAM D21J
SAM D21G
SAM D21E
Pins
64
48
32
General Purpose I/O-pins
(GPIOs)
52
38
26
Flash
256/128/64/32KB
256/128/64/32KB
256/128/64/32KB
SRAM
32/16/8/4KB
32/16/8/4KB
32/16/8/4KB
Timer Counter (TC)
instances
5
3
3
Waveform output channels 2
per TC instance
2
2
Timer Counter for Control
(TCC) instances
3
3
Waveform output channels 8/4/2
per TCC
8/4/2
8/4/2
DMA channels
12
12
12
USB interface
1
1
1
Serial Communication
Interface (SERCOM)
instances
6
6
4
Inter-IC Sound (I2S)
interface
1
1
1
Analog-to-Digital Converter 20
(ADC) channels
14
10
Analog Comparators (AC)
2
2
2
Digital-to-Analog Converter 1
(DAC) channels
1
1
Real-Time Counter (RTC)
Yes
Yes
Yes
RTC alarms
1
1
1
RTC compare values
One 32-bit value or
One 32-bit value or
One 32-bit value or
two 16-bit values
two 16-bit values
two 16-bit values
16
16
16
12x10
10x6
External Interrupt lines
3
Peripheral Touch Controller 16x16
(PTC) X and Y lines
Maximum CPU frequency
48MHz
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
5
Packages
Oscillators
SAM D21J
SAM D21G
SAM D21E
QFN
QFN
QFN
TQFP
TQFP
TQFP
UFBGA
WLCSP
WLCSP
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
32KHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
12
12
12
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
6
3.
Ordering Information
SAMD 21 E 15 A - M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0 + CPU, Basic Feature Set
+ DMA + USB
Package Grade
Pin Count
U = -40 - 85 C Matte Sn Plating
F = -40 - 125 C Matte Sn Plating
O
O
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
Flash Memory Density
A = TQFP
M = QFN
U = WLCSP
C = UFBGA
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
Device Variant
A = Default Variant
B = Added RWW support for 32KB and 64KB memory options
3.1.
SAM D21E
Table 3-1. Device Variant A
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21E15A-AU
32K
4K
TQFP32
Tray
ATSAMD21E15A-AUT
Tape & Reel
ATSAMD21E15A-AF
Tray
ATSAMD21E15A-AFT
Tape & Reel
ATSAMD21E15A-MU
QFN32
Tray
ATSAMD21E15A-MUT
Tape & Reel
ATSAMD21E15A-MF
Tray
ATSAMD21E15A-MFT
Tape & Reel
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
7
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21E16A-AU
64K
8K
TQFP32
Tray
ATSAMD21E16A-AUT
Tape & Reel
ATSAMD21E16A-AF
Tray
ATSAMD21E16A-AFT
Tape & Reel
ATSAMD21E16A-MU
QFN32
Tray
ATSAMD21E16A-MUT
Tape & Reel
ATSAMD21E16A-MF
Tray
ATSAMD21E16A-MFT
Tape & Reel
ATSAMD21E17A-AU
128K
16K
TQFP32
Tray
ATSAMD21E17A-AUT
Tape & Reel
ATSAMD21E17A-AF
Tray
ATSAMD21E17A-AFT
Tape & Reel
ATSAMD21E17A-MU
QFN32
Tray
ATSAMD21E17A-MUT
Tape & Reel
ATSAMD21E17A-MF
Tray
ATSAMD21E17A-MFT
Tape & Reel
ATSAMD21E18A-AU
256K
32K
TQFP32
Tray
ATSAMD21E18A-AUT
Tape & Reel
ATSAMD21E18A-AF
Tray
ATSAMD21E18A-AFT
Tape & Reel
ATSAMD21E18A-MU
QFN32
Tray
ATSAMD21E18A-MUT
Tape & Reel
ATSAMD21E18A-MF
Tray
ATSAMD21E18A-MFUT
Tape & Reel
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
8
Table 3-2. Device Variant B
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21E15B-AU
32K
4K
TQFP32
Tray
ATSAMD21E15B-AUT
Tape & Reel
ATSAMD21E15B-AF
Tray
ATSAMD21E15B-AFT
Tape & Reel
ATSAMD21E15B-MU
QFN32
ATSAMD21E15B-MUT
Tape & Reel
ATSAMD21E15B-MF
Tray
ATSAMD21E15B-MFT
Tape & Reel
ATSAMD21E16B-AU
64K
8K
TQFP32
Tray
ATSAMD21E16B-AUT
Tape & Reel
ATSAMD21E16B-AF
Tray
ATSAMD21E16B-AFT
Tape & Reel
ATSAMD21E16B-MU
QFN32
Tray
ATSAMD21E16B-MUT
Tape & Reel
ATSAMD21E16B-MF
Tray
ATSAMD21E16B-MFT
Tape & Reel
ATSAMD21E16B-UUT
3.2.
Tray
64K
8K
WLCSP35
Tape & Reel
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21G15A-AU
32K
4K
TQFP48
Tray
SAM D21G
Table 3-3. Device Variant A
ATSAMD21G15A-AUT
Tape & Reel
ATSAMD21G15A-AF
Tray
ATSAMD21G15A-AFT
Tape & Reel
ATSAMD21G15A-MU
QFN48
Tray
ATSAMD21G15A-MUT
Tape & Reel
ATSAMD21G15A-MF
Tray
ATSAMD21G15A-MFT
Tape & Reel
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
9
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21G16A-AU
64K
8K
TQFP48
Tray
ATSAMD21G16A-AUT
Tape & Reel
ATSAMD21G16A-AF
Tray
ATSAMD21G16A-AFT
Tape & Reel
ATSAMD21G16A-MU
QFN48
Tray
ATSAMD21G16A-MUT
Tape & Reel
ATSAMD21G16A-MF
Tray
ATSAMD21G16A-MFT
Tape & Reel
ATSAMD21G17A-AU
128K
16K
TQFP48
Tray
ATSAMD21G17A-AUT
Tape & Reel
ATSAMD21G17A-AF
Tray
ATSAMD21G17A-AFT
Tape & Reel
ATSAMD21G17A-MU
QFN48
Tray
ATSAMD21G17A-MUT
Tape & Reel
ATSAMD21G17A-MF
Tray
ATSAMD21G17A-MFT
Tape & Reel
ATSAMD21G17A-UUT
ATSAMD21G18A-AU
256K
32K
WLCSP45
Tape & Reel
TQFP48
Tray
ATSAMD21G18A-AUT
Tape & Reel
ATSAMD21G18A-AF
Tray
ATSAMD21G18A-AFT
Tape & Reel
ATSAMD21G18A-MU
QFN48
Tray
ATSAMD21G18A-MUT
Tape & Reel
ATSAMD21G18A-MF
Tray
ATSAMD21G18A-MFT
Tape & Reel
ATSAMD21G18A-UUT
WLCSP45
Tape & Reel
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
10
Table 3-4. Device Variant B
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21G15B-AU
32K
4K
TQFP48
Tray
ATSAMD21G15B-AUT
Tape & Reel
ATSAMD21G15B-AF
Tray
ATSAMD21G15B-AFT
Tape & Reel
ATSAMD21G15B-MU
QFN48
ATSAMD21G15B-MUT
Tape & Reel
ATSAMD21G15B-MF
Tray
ATSAMD21G15B-MFT
Tape & Reel
ATSAMD21G16B-AU
64K
8K
TQFP48
Tray
ATSAMD21G16B-AUT
Tape & Reel
ATSAMD21G16B-AF
Tray
ATSAMD21G16B-AFT
Tape & Reel
ATSAMD21G16B-MU
3.3.
Tray
QFN48
Tray
ATSAMD21G16B-MUT
Tape & Reel
ATSAMD21G16B-MF
Tray
ATSAMD21G16B-MFT
Tape & Reel
SAM D21J
Table 3-5. Device Variant A
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21J15A-AU
32K
4K
TQFP64
Tray
ATSAMD21J15A-AUT
Tape & Reel
ATSAMD21J15A-AF
Tray
ATSAMD21J15A-AFT
Tape & Reel
ATSAMD21J15A-MU
QFN64
Tray
ATSAMD21J15A-MUT
Tape & Reel
ATSAMD21J15A-MF
Tray
ATSAMD21J15A-MFT
Tape & Reel
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
11
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21J16A-AU
64K
8K
TQFP64
Tray
ATSAMD21J16A-AUT
Tape & Reel
ATSAMD21J16A-AF
Tray
ATSAMD21J16A-AFT
Tape & Reel
ATSAMD21J16A-MU
QFN64
Tray
ATSAMD21J16A-MUT
Tape & Reel
ATSAMD21J16A-MF
Tray
ATSAMD21J16A-MFT
Tape & Reel
ATSAMD21J16A-CU
UFBGA64
ATSAMD21J16A-CUT
ATSAMD21J17A-AU
Tray
Tape & Reel
128K
16K
TQFP64
Tray
ATSAMD21J17A-AUT
Tape & Reel
ATSAMD21J17A-AF
Tray
ATSAMD21J17A-AFT
Tape & Reel
ATSAMD21J17A-MU
QFN64
Tray
ATSAMD21J17A-MUT
Tape & Reel
ATSAMD21J17A-MF
Tray
ATSAMD21J17A-MFT
Tape & Reel
ATSAMD21J17A-CU
UFBGA64
ATSAMD21J17A-CUT
ATSAMD21J18A-AU
Tray
Tape & Reel
256K
32K
TQFP64
Tray
ATSAMD21J18A-AUT
Tape & Reel
ATSAMD21J18A-AF
Tray
ATSAMD21J18A-AFT
Tape & Reel
ATSAMD21J18A-MU
QFN64
Tray
ATSAMD21J18A-MUT
Tape & Reel
ATSAMD21J18A-MF
Tray
ATSAMD21J18A-MFT
Tape & Reel
ATSAMD21J18A-CU
ATSAMD21J18A-CUT
UFBGA64
Tray
Tape & Reel
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
12
Table 3-6. Device Variant B
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAMD21J15B-AU
32K
4K
TQFP64
Tray
ATSAMD21J15B-AUT
Tape & Reel
ATSAMD21J15B-AF
Tray
ATSAMD21J15B-AFT
Tape & Reel
ATSAMD21J15B-MU
QFN64
ATSAMD21J15B-MUT
Tape & Reel
ATSAMD21J15B-MF
Tray
ATSAMD21J15B-MFT
Tape & Reel
ATSAMD21J16B-AU
64K
8K
TQFP64
Tray
ATSAMD21J16B-AUT
Tape & Reel
ATSAMD21J16B-AF
Tray
ATSAMD21J16B-AFT
Tape & Reel
ATSAMD21J16B-MU
QFN64
Tray
ATSAMD21J16B-MUT
Tape & Reel
ATSAMD21J16B-MF
Tray
ATSAMD21J16B-MFT
Tape & Reel
ATSAMD21J16B-CU
UFBGA64
ATSAMD21J16B-CUT
3.4.
Tray
Tray
Tape & Reel
Device Identification
The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification
register (DID.DEVSEL) in order to identify the device by software. The SAM D21 variants have a reset
value of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the device
selection ('xx').
Table 3-7. SAM D21 Device Identification Values
Device Variant
DID.DEVSEL
Device ID (DID)
SAMD21J18A
0x00
0x10010000
SAMD21J17A
0x01
0x10010001
SAMD21J16A
0x02
0x10010002
SAMD21J15A
0x03
0x10010003
Reserved
0x04
SAMD21G18A
0x05
0x10010005
SAMD21G17A
0x06
0x10010006
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
13
Device Variant
DID.DEVSEL
Device ID (DID)
SAMD21G16A
0x07
0x10010007
SAMD21G15A
0x08
0x10010008
Reserved
0x09
SAMD21E18A
0x0A
0x1001000A
SAMD21E17A
0x0B
0x1001000B
SAMD21E16A
0x0C
0x1001000C
SAMD21E15A
0x0D
0x1001000D
Reserved
0x10 - 0x1F
SAMD21J16B
0x20
0x10011420
SAMD21J15B
0x21
0x10011421
Reserved
0x22
SAMD21G16B
0x23
0x10011423
SAMD21G15B
0x24
0x10011424
Reserved
0x25
SAMD21E16B
0x26
0x10011426
SAMD21E15B
0x27
0x10011427
Reserved
0x28 - 0xFF
Note: The device variant (last letter of the ordering number) is independent of the die revision. The
device variant denotes functional differences, whereas the die revision marks evolution of the die.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
14
Block Diagram
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SERIAL
WIRE
SWDIO
DEVICE
SERVICE
UNIT
M
256/128/64/32KB
NVM
32/16/8/4KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
S
S
PERIPHERAL
ACCESS CONTROLLER
S
AHB-APB
BRIDGE B
S
USB FS
DEVICE
MINI-HOST
S
AHB-APB
BRIDGE A
DMA
66xxSERCOM
SERCOM
VREF
OSC32K
XOSC32K
DMA
OSC8M
5 x TIMER / COUNTER
8 x Timer Counter
XOSC
FDPLL96M
POWER MANAGER
CLOCK
CONTROLLER
RESET
CONTROLLER
SLEEP
CONTROLLER
EVENT SYSTEM
DMA
RESETN
PAD0
PAD1
PAD2
PAD3
OSCULP32K
DFLL48M
XIN
XOUT
DM
SOF 1KHZ
PERIPHERAL
ACCESS CONTROLLER
SYSTEM CONTROLLER
XIN32
XOUT32
DP
AHB-APB
BRIDGE C
PERIPHERAL
ACCESS CONTROLLER
BOD33
DMA
M
HIGH SPEED
BUS MATRIX
3x TIMER / COUNTER
FOR CONTROL
WO0
WO1
WO0
WO1
PORT
SWCLK
MICRO
TRACE BUFFER
IOBUS
PORT
4.
(2)
WOn
AIN[19..0]
DMA
20-CHANNEL
12-bit ADC 350KSPS
VREFA
VREFB
CMP[1..0]
GCLK_IO[7..0]
2 ANALOG
COMPARATORS
GENERIC CLOCK
CONTROLLER
REAL TIME
COUNTER
DMA
EXTINT[15..0]
NMI
VOUT
10-bit DAC
WATCHDOG
TIMER
EXTERNAL INTERRUPT
CONTROLLER
AIN[3..0]
PERIPHERAL
TOUCH
CONTROLLER
DMA
INTER-IC
SOUND
CONTROLLER
VREFA
X[15..0]
Y[15..0]
MCK[1..0]
SCK[1..0]
SD[1..0]
FS[1..0]
1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals
and ADC signals. Refer to #unique_12 for details.
2. The three TCC instances have different configurations, including the number of Waveform Output (WO)
lines. Refer to TCC Configuration Summary in the Overview of TCC – Timer/Counter for Control
Applications for details.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
15
Pinout
5.1.
SAM D21J
5.1.1.
QFN64 / TQFP64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
16
5.1.2.
UFBGA64
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
17
SAM D21G
5.2.1.
QFN48 / TQFP48
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.2.
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
18
5.2.2.
WLCSP45
A
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
19
SAM D21E
5.3.1.
QFN32 / TQFP32
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
5.3.
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
20
5.3.2.
WLCSP35
A
B
1
00
PA
30
PA
2
01
PA
3
PA
3
GN
4
D
VD
DA
1
NA
A
VD
OR
DC
N
DI
D
E
D
GN
E
F
T
SE
25
PA
RE
VD
2
PA
27
PA
24
PA
2
03
PA
D
GN
2
PA
2
23
PA
4
0
PA
5
11
PA
17
PA
19
PA
7
08
PA
09
PA
1
PA
6
18
PA
D
1
PA
4
1
PA
0
PA
AN
0
PA
5
06
PA
0
PA
6
VD
O
DI
C
1
PA
0
8
GN
5
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
21
6.
Product Mapping
Figure 6-1. Atmel SAM D21 Product Mapping
Code
Device Variant B
Device Variant A
Global Memory Space
0x00000000
0x00000000
0x00000000
Internal Flash
Internal Flash
0x00010000
0x00040000
Code
Internal
RWW section
Reserved
0x1FFFFFFF
0x1FFFFFFF
AHB-APB Bridge C
0x20000000
SRAM
0x20008000
0x40000000
0x40000000
Peripherals
0x41000000
0x43000000
Reserved
0x60000000
0x42000000
Reserved
0xE000E000
0xE0000000
System
0xE000F000
0xE00FF000
0xFFFFFFFF
0xE0100000
AHB-APB Bridge A
0x40000800
0x40000C00
0x40001000
0x40001400
0x40001800
0x40001C00
0x40FFFFFF
0x42000400
AHB-APB
0x42000800
AHB-APB
Bridge A
0x42000C00
0x42001000
AHB-APB
Bridge B
0x42001400
AHB-APB
Bridge C
0x42001800
0xFFFFFFFF
PAC0
0x41002000
PM
0x41004000
SYSCTRL
0x41004400
GCLK
0x41004800
WDT
0x41005000
RTC
Reserved
0x42002000
Reserved
0x42002400
SCS
0x42002800
Reserved
0x42002C00
ROMTable
0x42003000
Reserved
0x42003400
AHB-APB Bridge B
0x41000000
EIC
0x42001C00
System
0xE0000000
0x40000400
Internal SRAM
0x42FFFFFF
Undefined
0x40000000
0x42000000
0x20007FFF
Undefined
0x60000200
SRAM
0x20000000
0x41006000
0x41007000
0x41FFFFFF
PAC1
DSU
NVMCTRL
PORT
DMAC
USB
MTB
Reserved
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
0x42004C00
0x42005000
0x42005400
0x42FFFFFF
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
SERCOM5
TCC0
TCC1
TCC2
TC3
TC4
TC5
TC6
TC7
ADC
AC
DAC
PTC
I2S
Reserved
This figure represents the full configuration of the Atmel® SAM D21 with maximum flash and SRAM
capabilities and a full set of peripherals. Refer to the Configuration Summary for details.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
22
7.
Processor And Architecture
7.1.
Cortex M0+ Processor
®
®
The SAM D21 implements the ARM Cortex -M0+ processor, based on the ARMv6 Architecture and
®
Thumb -2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0
core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision
r0p1. For more information refer to http://www.arm.com.
7.1.1.
Cortex M0+ Configuration
Table 7-1. Cortex M0+ Configuration
Features
Configurable option
Enter Title of Manual
configuration
Interrupts
External interrupts 0-32
28
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint
comparators
0, 1, 2
2
Number of breakpoint
comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Absent(1)
Memory Protection Unit
Not present or 8-region
Not present
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
DAP AHB slave
Debug access port type supported
DAP-Specific
Architectural clock gating
Implement Architectural Clock Gating
Implemented
Debug Interface
Serial wire and/or JTAG debug interface Serial Wire
Multi-drop serial wire
Serial wire multi-drop support
Not implemented
Note: 1. All software run in privileged mode only.
The ARM Cortex-M0+ core has two bus interfaces:
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
23
•
•
7.1.2.
Cortex-M0+ Peripherals
•
•
•
•
•
7.1.3.
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all
system memory, which includes flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.
System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+
Technical Reference Manual for details (www.arm.com).
System Timer (SysTick)
– The System Timer is a 24-bit timer that extends the functionality of both the processor and the
NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
Nested Vectored Interrupt Controller (NVIC)
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.
Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core
are closely coupled, providing low latency interrupt processing and efficient processing of late
arriving interrupts. Refer to Nested Vector Interrupt Controller and the Cortex-M0+ Technical
Reference Manual for details (www.arm.com).
System Control Block (SCB)
– The System Control Block provides system implementation information, and system control.
This includes configuration, control, and reporting of the system exceptions. Refer to the
Cortex-M0+ Devices Generic User Guide for details (www.arm.com).
Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the CortexM0+ processor. Refer to section Micro Trace Buffer and the CoreSight MTB-M0+ Technical
Reference Manual for details (www.arm.com).
Cortex-M0+ Address Map
Table 7-2. Cortex-M0+ Address Map
7.1.4.
7.1.4.1.
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0x41006000 (see also Product Mapping)
Micro Trace Buffer (MTB)
I/O Interface
Overview
Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently,
the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single
cycle I/O accesses to be sustained for as long as needed. Refer to CPU Local Bus for more information.
7.1.4.2.
Description
Direct access to PORT registers.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
24
7.2.
Nested Vector Interrupt Controller
7.2.1.
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM D21 supports 32 interrupt lines with four
different priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual
(www.arm.com).
7.2.2.
Interrupt Line Mapping
Each of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Each
peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear
(INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in the
peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s
Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the
peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the
peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests
for one peripheral are ORed together on system level, generating one interrupt request for each
peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt
pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it
must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC
interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
Table 7-3. Interrupt Line Mapping (Continued)
Peripheral Source
NVIC Line
EIC NMI – External Interrupt Controller
NMI
PM – Power Manager
0
SYSCTRL – System Control
1
WDT – Watchdog Timer
2
RTC – Real Time Counter
3
EIC – External Interrupt Controller
4
NVMCTRL – Non-Volatile Memory Controller
5
DMAC - Direct Memory Access Controller
6
USB - Universal Serial BusReserved
7
EVSYS – Event System
8
SERCOM0 – Serial Communication Interface 0
9
SERCOM1 – Serial Communication Interface 1
10
SERCOM2 – Serial Communication Interface 2
11
SERCOM3 – Serial Communication Interface 3
12
SERCOM4 – Serial Communication Interface 4
13
SERCOM5 – Serial Communication Interface 5Reserved
14
TCC0 – Timer Counter for Control 0
15
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
25
Peripheral Source
NVIC Line
TCC1 – Timer Counter for Control 1
16
TCC2 – Timer Counter for Control 2
17
TC3 – Timer Counter 3
18
TC4 – Timer Counter 4
19
TC5 – Timer Counter 5
20
TC6 – Timer Counter 6Reserved
21
TC7 – Timer Counter 7Reserved
22
ADC – Analog-to-Digital Converter
23
AC – Analog Comparator
24
DAC – Digital-to-Analog ConverterReserved
25
PTC – Peripheral Touch ControllerReserved
26
I2S - Inter IC SoundReservedReserved
27
7.3.
Micro Trace Buffer
7.3.1.
Features
•
•
•
•
7.3.2.
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over
the execution trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+.
This information is stored as trace packets in the SRAM by the MTB. An off-chip debugger can extract the
trace information using the Debug Access Port to read the trace information from the SRAM. The
debugger can then reconstruct the program flow from this information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the
SRAM. The MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the
processor PC value changes non-sequentially. A non-sequential PC change can occur during branch
instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more
details on the MTB execution trace packet format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various
ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical
Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s
MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a
specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
26
watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around
overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM
Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTBM0+ Technical Reference Manual. The MTB has 4 programmable registers to control the behavior of the
trace features:
•
•
POSITION: Contains the trace write pointer and the wrap bit,
MASTER: Contains the main trace enable bit and other trace control fields,
•
•
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
BASE: Indicates where the SRAM is located in the processor memory map. This register is
provided to enable auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
7.4.
High-Speed Bus System
7.4.1.
Features
The High-Speed Bus System combines a Bus Interconnection Matrix for standard Master/Slave
communication, and a unified FlexRAM System Memory area with multiple access capabilities.
High-Speed Bus Matrix has the following features:
•
Symmetric crossbar bus switch implementation
•
Allows concurrent accesses from different masters to different slaves
•
32-bit data bus
•
Operation at a one-to-one clock frequency with the bus masters
FlexRAM Memory has the following features:
l Unified System Memory area
l Allows concurrent accesses from different masters
l Offers privileged accesses from specific masters
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
27
Configuration
Multi-Slave
MASTERS
CM0+
0
DSU DSU
1
DMACDSU
Data
2
2
DSU
1
DMAC Data
0
CM0+
3
DMAC WB
AHB-APB Bridge C
2
USB
AHB-APB Bridge B
1
MTB
AHB-APB Bridge A
0
SRAM
DMAC Fetch
MASTER ID
Internal Flash
High-Speed Bus SLAVES
Priviledged SRAM-access
MASTERS
7.4.2.
3
4
4
5
5
6
6
SLAVE ID
SRAM PORT ID
MTB
USB
DMAC WB
DMAC Fetch
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
28
Priviledged
SRAM-access
MASTERS
Multi-Slave
MASTERS
CM0+
0
DSU DSU
1
DMACDSU
Data
2
DMAC Data
DSU
MASTER ID
CM0+
3
DMAC Fetch
AHB-APB Bridge C
2
DMAC WB
AHB-APB Bridge B
1
Reserved
AHB-APB Bridge A
0
SRAM
MTB
Internal Flash
High-Speed Bus SLAVES
0
1
2
3
4
4
5
5
6
6
SLAVE ID
SRAM PORT ID
MTB
DMAC WB
DMAC Fetch
Table 7-4. Bus Matrix Masters
Bus Matrix Masters
Master ID
CM0+ - Cortex M0+ Processor
0
DSU - Device Service Unit
1
DMAC - Direct Memory Access Controller / Data Access
2
Table 7-5. Bus Matrix Slaves
Bus Matrix Slaves
Slave ID
Internal Flash Memory
0
AHB-APB Bridge A
1
AHB-APB Bridge B
2
AHB-APB Bridge C
3
SRAM Port 4 - CM0+ Access
4
SRAM Port 5 - DMAC Data Access
5
SRAM Port 6 - DSU Access
6
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
29
Table 7-6. SRAM Port Connection
7.4.3.
SRAM Port Connection
Port ID
Connection Type
MTB - Micro Trace Buffer
0
Direct
USB - Universal Serial Bus
1
Direct
DMAC - Direct Memory Access Controller - Write-Back Access
2
Direct
DMAC - Direct Memory Access Controller - Fetch Access
3
Direct
CM0+ - Cortex M0+ Processor
4
Bus Matrix
DMAC - Direct Memory Access Controller - Data Access
5
Bus Matrix
DSU - Device Service Unit
6
Bus Matrix
SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different
masters can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any
access to the RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit
values for the QoS level configuration is shown in Table. Quality of Service.
Table 7-7. Quality of Service
Value
Name
Description
00
DISABLE
Background (no sensitive operation)
01
LOW
Sensitive Bandwidth
10
MEDIUM
Sensitive Latency
11
HIGH
Critical Latency
If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the
RAM access.
The priority order for concurrent accesses are decided by two factors. First the QoS level for the master
and then a static priority given by table nn-mm (table: SRAM port connection) where the lowest port ID
has the highest static priority.
The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.
The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
7.5.
AHB-APB Bridge
The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and
the low-power APB domain. It is used to provide access to the programmable control registers of
peripherals (see Product Mapping).
AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:
•
Wait state support
•
Error reporting
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
30
•
•
Transaction protection
Sparse data transfer (byte, half-word and word)
Additional enhancements:
•
Address and data cycles merged into a single cycle
•
Sparse data transfer also apply to read access
to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See PM – Power
Manager for details.
Figure 7-1. APB Write Access.
T0
T1
T2
T3
PCLK
T0
T1
T2
T3
T4
T5
T4
T5
PCLK
PADDR
Addr 1
PADDR
PWRITE
PWRITE
PSEL
PSEL
PENABLE
PENABLE
PWDATA
Addr 1
PWDATA
Data 1
PREADY
Data 1
PREADY
No wait states
Wait states
Figure 7-2. APB Read Access.
T0
T1
T2
T3
PCLK
PADDR
T0
T2
T3
PCLK
Addr 1
PADDR
PWRITE
PWRITE
PSEL
PSEL
PENABLE
PENABLE
PRDATA
T1
Data 1
Addr 1
PRDATA
PREADY
Data 1
PREADY
No wait states
Wait states
7.6.
PAC - Peripheral Access Controller
7.6.1.
Overview
There is one PAC associated with each AHB-APB bridge. The PAC can provide write protection for
registers of each peripheral connected on the same bridge.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
31
The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager.
CLK_PAC0_APB and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset.
Refer to PM – Power Manager for details. The PAC will continue to operate in any sleep mode where the
selected clock source is running. Write-protection does not apply for debugger access. When the
debugger makes an access to a peripheral, write-protection is ignored so that the debugger can update
the register.
Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a
read-modify-write operation. These registers are mapped into two I/O memory locations, one for clearing
and one for setting the register bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will
clear the corresponding bit in both registers (WPCLR and WPSET) and disable the write-protection for
the corresponding peripheral, while writing a one to a bit in the Write Protect Set (WPSET) register will set
the corresponding bit in both registers (WPCLR and WPSET) and enable the write-protection for the
corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when read.
If a peripheral is write-protected, and if a write access is performed, data will not be written, and the
peripheral will return an access error (CPU exception).
The PAC also offers a safety feature for correct program execution, with a CPU exception generated on
double write-protection or double unprotection of a peripheral. If a peripheral n is write-protected and a
write to one in WPSET[n] is detected, the PAC returns an error. This can be used to ensure that the
application follows the intended program flow by always following a write-protect with an unprotect, and
vice versa. However, in applications where a write-protected peripheral is used in several contexts, e.g.,
interrupts, care should be taken so that either the interrupt can not happen while the main application or
other interrupt levels manipulate the write-protection status, or when the interrupt handler needs to
unprotect the peripheral, based on the current protection status, by reading WPSET.
7.6.2.
Register Description
Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Refer to Product Mapping for PAC locations.
7.6.2.1.
PAC0 Register Description
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
32
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
6
5
4
3
2
1
EIC
RTC
WDT
GCLK
SYSCTRL
PM
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 6 – EIC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 5 – RTC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 4 – WDT
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
33
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 3 – GCLK
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 2 – SYSCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 1 – PM
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
34
Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x000000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
6
5
4
3
2
1
EIC
RTC
WDT
GCLK
SYSCTRL
PM
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit 6 – EIC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 5 – RTC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 4 – WDT
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
35
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 3 – GCLK
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 2 – SYSCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 1 – PM
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
7.6.2.2.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
PAC1 Register Description
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
36
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x000002
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
6
5
4
3
2
1
MTB
USB
DMAC
PORT
NVMCTRL
DSU
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
Bit 6 – MTB
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 5 – USB
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 4 – DMAC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
37
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 3 – PORT
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 2 – NVMCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 1 – DSU
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
38
Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x000002
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
Access
Reset
6
5
4
3
2
1
MTB
USB
DMAC
PORT
NVMCTRL
DSU
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
Bit 6 – MTB
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 5 – USB
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 4 – DMAC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
39
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 3 – PORT
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 2 – NVMCTRL
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 1 – DSU
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
7.6.2.3.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
PAC2 Register Description
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
40
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00800000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
14
13
I2S
PTC
DAC
AC
ADC
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
12
11
10
9
8
TC4
TC3
TC2
TC1
TC0
TCC2
TCC1
TCC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 20 – I2S
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 19 – PTC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 18 – DAC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
41
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 17 – AC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 16 – ADC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 15 – TC4
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 14 – TC3
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 13 – TC2
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
42
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 12 – TC1
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 11 – TC0
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 1 – EVSYS
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bits 10,9,8 – TCCx
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bits 7,6,5,4,3,2 – SERCOMx
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
43
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
44
Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00800000
Property: –
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Access
Reset
Bit
Access
Reset
Bit
15
Access
Reset
Bit
Access
Reset
14
13
I2S
PTC
DAC
AC
ADC
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
12
11
10
9
8
TC4
TC3
TC2
TC1
TC0
TCC2
TCC1
TCC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 20 – I2S
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 19 – PTC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 18 – DAC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
45
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 17 – AC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 16 – ADC
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 15 – TC4
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 14 – TC3
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 13 – TC2
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
46
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 12 – TC1
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 11 – TC0
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bit 1 – EVSYS
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bits 10,9,8 – TCCx
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Bits 7,6,5,4,3,2 – SERCOMx
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
47
Value
Description
0
Write-protection is disabled.
1
Write-protection is enabled.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
48
8.
Packaging Information
8.1.
Thermal Considerations
Related Links
Junction Temperature on page 49
8.1.1.
Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 8-1. Thermal Resistance Data
8.1.2.
Package Type
θJA
θJC
32-pin TQFP
64.7°C/W
23.1°C/W
48-pin TQFP
63.6°C/W
12.2°C/W
64-pin TQFP
60.9°C/W
12.2°C/W
32-pin QFN
40.9°C/W
15.2°C/W
48-pin QFN
32.0°C/W
10.9°C/W
64-pin QFN
32.5°C/W
10.7°C/W
35-pin WLCSP
TBD
TBD
45-pin WLCSP
TBD
TBD
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal
Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling
device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be
used to compute the resulting average chip-junction temperature TJ in °C.
Related Links
Thermal Considerations on page 49
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
49
8.2.
Package Drawings
8.2.1.
64 pin TQFP
Table 8-2. Device and Package Maximum Weight
300
mg
Table 8-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-4. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
50
8.2.2.
64 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 8-5. Device and Package Maximum Weight
200
mg
Table 8-6. Package Charateristics
Moisture Sensitivity Level
MSL3
Table 8-7. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
51
8.2.3.
64-ball UFBGA
Table 8-8. Device and Package Maximum Weight
27.4
mg
Table 8-9. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-10. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E8
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
52
8.2.4.
48 pin TQFP
Table 8-11. Device and Package Maximum Weight
140
mg
Table 8-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-13. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
53
8.2.5.
48 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 8-14. Device and Package Maximum Weight
140
mg
Table 8-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 8-16. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
54
8.2.6.
45-ball WLCSP
Table 8-17. Device and Package Maximum Weight
7.3
mg
Table 8-18. Package Characteristics
Moisture Sensitivity Level
MSL1
Table 8-19. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E1
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
55
8.2.7.
32 pin TQFP
Table 8-20. Device and Package Maximum Weight
100
mg
Table 8-21. Package Charateristics
Moisture Sensitivity Level
MSL3
Table 8-22. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
56
8.2.8.
32 pin QFN
Note: The exposed die attach pad is connected inside the device to GND and GNDANA.
Table 8-23. Device and Package Maximum Weight
90
mg
Table 8-24. Package Characteristics
Moisture Sensitivity Level
MSL3
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
57
Table 8-25. Package Reference
8.2.9.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
35 ball WLCSP
Table 8-26. Device and Package Maximum Weight
6.2
mg
Table 8-27. Package Characteristics
Moisture Sensitivity Level
MSL1
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
58
Table 8-28. Package Reference
8.3.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E1
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 8-29. Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
Atmel SAM D21E / SAM D21G /SAM D21J Summary [DATASHEET]
Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
59
Atmel Corporation
©
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
2016 Atmel Corporation. / Rev.: Atmel-42181I-SAM D21_Datasheet_Summary-03/2016
®
®
Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
®
®
other countries. ARM , ARM Connected logo, and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be
trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND
CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS
INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED
OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to
update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive
applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any
applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without
an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the
operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments
unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically
designated by Atmel as automotive-grade.