AT28HC256N - Mature

Features
• Fast Read Access Time – 90 ns
• Automatic Page Write Operation
•
•
•
•
•
•
•
•
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms Maximum
– 1 to 64-byte Page Write Operation
Low Power Dissipation: 300 µA Standby Current (CMOS)
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 105 Cycles
– Data Retention: 10 Years
Single 5V ±10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
256 (32K x 8)
High-speed
Parallel
EEPROM
Description
The AT28HC256N is a high-performance electrically erasable and programmable read
only memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256N offers
access times to 90 ns with power dissipation of just 440 mW. When the AT28HC256N
is deselected, the standby current is less than 3 mA.
AT28HC256N
The AT28HC256N is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64
bytes of data are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the
latched data using an internal control timer. The end of a write cycle can be detected
by DATA Polling of I/O7 . Once the end of a write cycle has been detected a new
access for a read or write can begin.
Atmel’s AT28HC256N has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and
improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra
64 bytes of EEPROM for device identification or tracking.
LCC, PLCC
Top View
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
4
3
2
1
32
31
30
A0 - A14
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
Function
I/O1
I/O2
GND
NC
I/O3
I/O4
I/O5
Pin Name
A7
A12
A14
NC
VCC
WE
A13
Pin Configurations
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
3446B–PEEPR–4/04
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2
AT28HC256N
3446B–PEEPR–4/04
AT28HC256N
Device Operation
READ: The AT28HC256N is accessed like a Static RAM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state when either
CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system.
BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and
OE high initiates a write cycle. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a
byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will
effectively be a polling operation.
PAGE WRITE: The page write operation of the AT28HC256N allows 1 to 64 bytes of
data to be written into the device during a single internal programming period. A page
write operation is initiated in the same manner as a byte write; the first byte written can
then be followed by 1 to 63 additional bytes. Each successive byte must be written
within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28HC256N
will cease accepting data and commence the internal programming operation. All bytes
during a page write operation must reside on the same page as defined by the state of
the A6 - A14 inputs. That is, for each WE high to low transition during the page write
operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within the page are to be written.
The bytes may be loaded in any order and may be altered within the same load period.
Only bytes which are specified for writing will be written; unnecessary cycling of other
bytes within the page does not occur.
DATA POLLING: The AT28HC256N features DATA Polling to indicate the end of a
write cycle. During a byte or page write cycle an attempted read of the last byte written
will result in the complement of the written data to be presented on I/O7. Once the write
cycle has been completed, true data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write cycle.
TOGGLE BIT: In addition to DATA Polling the AT28HC256N provides another method
for determining the end of a write cycle. During the write operation, successive attempts
to read data from the device will result in I/O6 toggling between one and zero. Once the
write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle
bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes to any 5-volt-only
nonvolatile memory may occur during transition of the host system power supply. Atmel
has incorporated both hardware and software features that will protect the memory
against inadvertent writes.
HARDWARE PROTECTION: Hardware features protect against inadvertent writes to
the AT28HC256N in the following ways: (a) VCC sense – if VCC is below 3.8V (typical)
the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the
device will automatically time out 5 ms typical) before allowing a write; (c) write inhibit –
holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter
– pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled data protection feature has
been implemented on the AT28HC256N. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by
the user; the AT28HC256N is shipped from Atmel with SDP disabled.
3
3446B–PEEPR–4/04
SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data
Protection” algorithm). After writing the 3-byte command sequence and after tWC the
entire AT28HC256N will be protected against inadvertent write operations. It should be
noted, that once protected the host may still perform a byte or page write to the
AT28HC256N. This is done by preceding the data to be written by the same 3-byte command sequence.
Once set, SDP will remain active unless the disable command sequence is issued.
Power transitions do not disable SDP and SDP will protect the AT28HC256N during
power-up and power-down conditions. All command sequences must conform to the
page write timing specifications. It should also be noted that the data in the enable and
disable command sequences is not written to the device and the memory addresses
used in the sequence may be written with data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the three byte command
sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the
user for device identification. By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array.
OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details.
4
AT28HC256N
3446B–PEEPR–4/04
AT28HC256N
DC and AC Operating Range
AT28HC256N-90
AT28HC256N-12
-40°C - 85°C
-40°C - 85°C
5V ±10%
5V ±10%
Operating Industrial Temperature (Case)
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
VIL
VIH
VIL
DIN
VIH
X(1)
X
High Z
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
Chip Erase
VIL
VH(3)
VIL
High Z
Write
(2)
Standby/Write Inhibit
Notes:
1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V ±0.5V.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Min
Max
Units
VIN = 0V to VCC + 1V
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ISB2
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
300
µA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
30
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 6.0 mA
VOH
Output High Voltage
IOH = -4 mA
2.0
V
0.45
2.4
V
V
5
3446B–PEEPR–4/04
AC Read Characteristics
AT28C256N-90
Symbol
tACC
Parameter
Min
AT28HC256N-12
Max
Min
Max
Units
Address to Output Delay
90
120
ns
(1)
CE to Output Delay
90
120
ns
(2)
OE to Output Delay
0
40
0
50
ns
tDF(3)(4)
CE or OE to Output Float
0
40
0
50
ns
tOH
Output Hold from OE, CE or Address,
whichever occurred first
0
tCE
tOE
0
ns
AC Read Waveforms(1)(2)(3)(4)
tCE
tOE
tDF
tACC
Notes:
tOH
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
6
1. This parameter is characterized and is not 100% tested.
AT28HC256N
3446B–PEEPR–4/04
AT28HC256N
AC Write Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Setup Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Setup Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tDV
Notes:
Min
Max
Units
(1)
Time to Data Valid
NR
1. NR = No Restriction.
AC Write Waveforms
WE Controlled
tOES
tAS
tOEH
tAH
tCH
tCS
tWPH
tWP
tDH
tDS
CE Controlled
tOEH
tOES
tAS
tCH
tAH
tCS
tWPH
tWP
tDV
tDS
tDH
7
3446B–PEEPR–4/04
Page Mode Write Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tWC
Write Cycle Time
3
ms
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
100
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
50
µs
ns
Page Mode Write Waveforms(1)(2)
tWPH
tWP
tAS
tAH
tBLC
tDH
tDS
tWC
Notes:
1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tH
tS
tS = tH = 5 µs (min.)
tW = 10 ms (min.)
tW
8
VH = 12.0V ±0.5V
AT28HC256N
3446B–PEEPR–4/04
AT28HC256N
Software Data Protection
Enable Algorithm(1)
Software Data Protection Disable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
Notes:
LOAD DATA 55
TO
ADDRESS 2AAA
ENTER DATA
PROTECT STATE
LOAD DATA 20
TO
ADDRESS 5555
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of write
even if no other data is loaded.
3. Write Protect state will be deactivated at end of
write period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Write Cycle Waveforms(1)(2)
tWPH
tWP
tAS
tAH
tBLC
tDH
tDS
tWC
Notes:
1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
9
3446B–PEEPR–4/04
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
0
ns
0
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
Data Polling Waveforms
tOEH
tDH
tWR
tOE
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
Max
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics” on page 6.
Toggle Bit Waveforms
tOEH
tDH
tOE
tWR
Notes:
10
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT28HC256N
3446B–PEEPR–4/04
AT28HC256N
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
90
30
0.3
AT28HC256N-90JI
32J
Industrial
(-40°C to 85°C)
120
30
0.3
AT28HC256N-12JI
32J
Industrial
(-40°C to 85°C)
Note:
1. See “Valid Part Numbers” table below.
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
Valid Part Numbers
The following table lists standard Atmel products that can be ordered:
Device Numbers
Speed
Package and Temperature Combinations
AT28HC256N
90
JI
AT28HC256N
12
JI
11
3446B–PEEPR–4/04
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT28HC256N
3446B–PEEPR–4/04
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3446B–PEEPR–4/04