Data Sheet

BGA7350
50 MHz to 250 MHz high linearity Si variable gain amplifier;
24 dB gain range
Rev. 1 — 21 December 2011
Product data sheet
1. Product profile
1.1 General description
The BGA7350 MMIC is a dual independently digitally controlled IF Variable Gain
Amplifier (VGA) operating from 50 MHz to 250 MHz. Each IF VGA amplifies with a gain
range of 24 dB and at its maximum gain setting delivers 17 dBm output power at 1 dB gain
compression and a superior linear performance.
The BGA7350 Dual IF VGA is optimized for a differential gain error of less than 0.1 dB
for accurate gain control and has a total integrated gain error of less than 0.4 dB.
The gain controls of each amplifier are separate digital gain-control word, which is
provided externally through two sets of 5 bits.
The BGA7350 is housed in a 32 pins 5 mm  5 mm leadless HVQFN32 package.
1.2 Features and benefits
 Dual independent digitally controlled 24 dB gain range VGAs, with 5-bit control
interface
 50 MHz to 250 MHz frequency operating range
 Gain step size: 1 dB  0.1 dB
 18.5 dB power gain
 Fast gain stage switching capability
 17 dBm output power at 1 dB gain compression
 5 V single supply operation with power-down control
 Logic-level shutdown control pin reduces supply current
 Excellent ESD protection at all pins
 Moisture sensitivity level 2
 Unconditionally stable
 Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
 Compatible with W-CDMA / WiMAX / LTE base-station infrastructure / multi carrier
systems
 Multi channel receivers
 General use for ADC driver applications
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
1.4 Quick reference data
Table 1.
Quick reference data
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC = 5 V; ICC = 245 mA;
Tuned for fIF = 172 MHz; B = 28 MHz; Tcase = 25 C; Differential input resistance matched to 140 ;
Differential output resistance matched to 200 ; unless otherwise specified; see Section 11
“Application information”.
Symbol
Parameter
Conditions
Min
VCC
supply voltage
VCC(A) + VCC(B)
4.75 5
ICC
supply current
ICC(A) + ICC(B)
power gain
Gp
Product data sheet
Max Unit
5.25 V
A_EN = "0"; B_EN = "0"
-
3
5
mA
A_EN = "1"; B_EN = "1"
-
245
280
mA
maximum gain
[1]
17.5 18.5 19.5 dB
minimum gain
[2]
7
5.5 4
dB
Ri(dif)
differential input
resistance
100
140
180

Ro(dif)
differential output
resistance
160
200
240

NF
noise figure
maximum gain
[1]
increased rate per gain step
BGA7350
Typ
-
6
8
dB
-
0.8
1
dB
IP3O
output third-order
intercept point
upper 5 gain steps
[1]
-
43
-
dBm
PL(1dB)
output power at 1 dB
gain compression
upper 5 gain steps
[1]
-
17
-
dBm
EG(dif)
differential gain error
-
 0.1 -
dB
E(dif)
differential phase error
upper 12 dB gain range
-
1.5
-
deg
per gain step (for all
consecutive gain steps)
-
0.5
-
deg
[1]
Maximum gain; gain code = 00000.
[2]
Minimum gain; gain code = 11000.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
2 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
2. Pinning information
25 A_OUT_N
26 A_OUT_P
27 VCCA
28 GNDA
29 A_IN_N
30 A_IN_P
terminal 1
index area
31 A_D0
32 A_D1
2.1 Pinning
A_D2
1
24 A_OUT_P
A_D3
2
23 A_OUT_N
A_D4
3
22 A_EN
n.c.
4
n.c.
5
B_D4
6
19 B_EN
B_D3
7
18 B_OUT_N
B_D2
8
17 B_OUT_P
21 GNDA
B_OUT_N 16
20 GNDB
B_OUT_P 15
VCCB 14
GNDB 13
B_IN_N 12
B_IN_P 11
9
B_D1
B_D0 10
BGA7350
aaa-001223
Transparent top view
Fig 1.
Pin configuration SOT617-1
2.2 Pin description
Table 2.
BGA7350
Product data sheet
Pin description
Symbol
Pin
Description
A_D2
1
MSB  2 for gain control interface of channel A
A_D3
2
MSB  1 for gain control interface of channel A
A_D4
3
MSB for gain control interface of channel A
n.c.
4
not connected [1]
n.c.
5
not connected [1]
B_D4
6
MSB for gain control interface of channel B
B_D3
7
MSB  1 for gain control interface of channel B
B_D2
8
MSB  2 for gain control interface of channel B
B_D1
9
LSB + 1 for gain control interface of channel B
B_D0
10
LSB for gain control interface of channel B
B_IN_P
11
channel B positive input [2]
B_IN_N
12
channel B negative input [2]
GNDB
13, 20
ground for channel B
VCCB
14
supply voltage for channel B
B_OUT_P
15, 17
channel B positive output [2]
B_OUT_N
16, 18
channel B negative output [2]
B_EN
19
power enable pin for channel B
GNDA
21, 28
ground for channel A
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
3 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
Table 2.
Pin description …continued
Symbol
Pin
Description
A_EN
22
power enable pin for channel A
A_OUT_N
23, 25
channel A negative output [2]
A_OUT_P
24, 26
channel A positive output [2]
VCCA
27
supply voltage for channel A
A_IN_N
29
channel A negative input [2]
A_IN_P
30
channel A positive input [2]
A_D0
31
LSB for gain control interface of channel A
A_D1
32
LSB + 1 for gain control interface of channel A
GND
GND paddle
RF ground and DC ground [3]
[1]
Pin to be left open.
[2]
Each channel should be independently enabled with logic HIGH and disabled with logic LOW.
[3]
The center metal base of the SOT617-1 also functions as heatsink for the VGA.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
BGA7350
BGA7350
Product data sheet
Description
Version
HVQFN32 plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5  5  0.85 mm
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
SOT617-1
© NXP B.V. 2011. All rights reserved.
4 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
A_VCOM
VCC
IN+
A_OUT_N
A_OUT_P
EN
A_D4
GAIN
CONTROL
GAIN
CONTROL
A_D3
VDD
A_D2
VCCA
GNDA
A_IN_N
A_IN_P
A_D0
A_D1
4. Functional diagram
A_OUT_P
OUT+
CM
A_OUT_N
INVCC
OUT-
REGULATOR
VDD
A_EN
VEE
VEE
GNDA
IN-
VEE
B_VCOM
B_EN
CM
IN+
B_OUT_P
OUT+
B_OUT_N
A_OUT_P
GNDB
B_IN_N
B_IN_P
B_D0
VCCB
VEE
GAIN
CONTROL
B_D1
B_D2
B_OUT_N
OUT-
B_D4
B_D3
EN
VDD
REGULATOR
GNDB
VCC
VDD
VCC
GAIN
CONTROL
BGA7350
aaa-001224
Fig 2.
Functional diagram
5. Enable control
Table 4.
Mode
Enable / disable control settings
Function description
Mode description Enable
VEN (V)
Ien (A)
A_EN B_EN Min Max Min Max
A_EN, B_EN VGA function off
BGA7350
Product data sheet
Disable
"0"
"0"
0
0.8
-
1
A_EN, B_EN VGA in operating mode Enable
"1"
"1"
1.6
5.25 -
1
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
6. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min Max Unit
supply voltage (A)
[1]
-
6
VCC(B)
supply voltage (B)
[1]
-
6
V
VAEN
voltage on pin A_EN
0.6 6
V
VBEN
voltage on pin B_EN
0.6 6
V
VAD0
voltage on pin A_D0
0.6 6
V
VAD1
voltage on pin A_D1
0.6 6
V
VAD2
voltage on pin A_D2
0.6 6
V
VAD3
voltage on pin A_D3
0.6 6
V
VAD4
voltage on pin A_D4
0.6 6
V
VBD0
voltage on pin B_D0
0.6 6
V
VBD1
voltage on pin B_D1
0.6 6
V
VBD2
voltage on pin B_D2
0.6 6
V
VBD3
voltage on pin B_D3
0.6 6
V
VBD4
voltage on pin B_D4
0.6 6
V
VAIN
voltage on pin A_IN
0.6 6
V
VBIN
voltage on pin B_IN
0.6 6
V
Pi(RF)
RF input power
-
20
dBm
Tcase
case temperature
40
+85
C
Tj
junction temperature
-
150
C
VESD
electrostatic discharge
voltage
Human Body Model (HBM);
According JEDEC standard 22-A114E
-
4000 V
Charged Device Model (CDM);
According JEDEC standard 22-C101B
-
2000 V
Machine Model (MM);
According JEDEC standard 22-A115
-
400
VCC(A)
[1]
V
V
All digital pins may not exceed VCC as the internal ESD circuit can be damaged. To prevent this it is
recommended that VAEN and VBEN are limited to a maximum of 5 mA.
7. Thermal characteristics
Table 6.
Thermal characteristics
Symbol Parameter
Rth(j-sp)
BGA7350
Product data sheet
thermal resistance from junction to solderpoint
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
Conditions
Typ Unit
Tcase = 85 C; VCC = 5 V;
ICC = 245 mA
17
K/W
© NXP B.V. 2011. All rights reserved.
6 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
8. Static characteristics
Table 7.
Characteristics
A_EN = "1"; B_EN = "1" (both channels enabled). Typical values at VCC = 5 V; Tcase = 25 C;
unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
4.75
5
5.25
V
-
3
5
mA
VCC
supply voltage
VCC(A) + VCC(B)
ICC
supply current
ICC(A) + ICC(B)
A_EN = "0"; B_EN = "0"
A_EN = "1"; B_EN = "1"
VIH
HIGH-level input voltage
[1]
VIL
LOW-level input voltage
[1]
PL
power dissipation
[1]
-
245
280
mA
1.6
-
5.25
V
-
-
0.8
V
-
1.2
1.5
W
Voltage on the control pins.
9. Dynamic characteristics
Table 8.
Characteristics
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC = 5 V; ICC = 245 mA;
Tuned for fIF = 172 MHz; B = 28 MHz; Tcase = 25 C; Differential input resistance matched to 140 ;
Differential output resistance matched to 200 ; unless otherwise specified; see Section 11
“Application information”.
Symbol
Parameter
Conditions
Gp
power gain
maximum gain
Min
Typ
Max Unit
f = 50 MHz; B = 15 MHz
-
19.5
-
f = 172 MHz; B = 28 MHz
17.5 18.5
19.5 dB
-
18.0
-
dB
f = 50 MHz; B = 15 MHz
-
4.5
-
dB
f = 172 MHz; B = 28 MHz
7
5.5
4
dB
[1]
f = 250 MHz; B = 28 MHz
minimum gain
[2]
f = 250 MHz; B = 28 MHz
Gadj
gain adjustment range
Gstep
gain step
Gflat
gain flatness
EG(dif)
differential gain error
EG(itg)
integrated gain error
E(dif)
ts(step)G
BGA7350
Product data sheet
differential phase error
gain step settling time
dB
[1]
[1]
-
6.0
-
dB
-
24
-
dB
-
1
-
-
0.1
-
dB
-
 0.1 -
dB
upper 12 dB gain range
-
 0.3 -
dB
full gain range
-
 0.4 -
dB
upper 12 dB gain range
-
1.5
-
deg
per gain step (for all
consecutive gain steps)
-
0.5
-
deg
per 1.5 dB of steady state
-
5
15
ns
per 0.1 dB of steady state
-
20
40
ns
td(grp)
group delay time
-
150
-
ps
tpu
power-up time
-
-
1
s
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
7 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
Table 8.
Characteristics …continued
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at VCC = 5 V; ICC = 245 mA;
Tuned for fIF = 172 MHz; B = 28 MHz; Tcase = 25 C; Differential input resistance matched to 140 ;
Differential output resistance matched to 200 ; unless otherwise specified; see Section 11
“Application information”.
Symbol
Parameter
Min
Typ
Max Unit
Ri(dif)
differential input
resistance
100
140
180

Ro(dif)
differential output
resistance
160
200
240

isol(ch-ch) isolation between
channels
50
-
-
dB
CMRR
common-mode
rejection ratio
40
-
-
dB
IP3O
output third-order
intercept point
IP2O
PL(1dB)
Conditions
output second-order
intercept point
output power at 1 dB
gain compression
Upper 5 gain steps
[3]
f = 50 MHz
[4]
-
43
-
dBm
f = 172 MHz
[5]
-
43
-
dBm
f = 250 MHz
[6]
-
41
-
dBm
Upper 5 gain steps
[3]
f = 50 MHz
[7]
-
85
-
dBm
f = 172 MHz
[8]
-
70
-
dBm
f = 250 MHz
[9]
-
70
-
dBm
f = 50 MHz
-
17
-
dBm
f = 172 MHz
-
17
-
dBm
Upper 5 gain steps
[3]
f = 250 MHz
2H
NF
second harmonic level
noise figure
-
17
-
dBm
maximum gain
[1][10]
-
80
-
dBc
gain step 12
[2][10]
-
80
-
dBc
[1]
-
6
8
dB
-
0.8
1
dB
maximum gain
increase rate per gain step
[1]
Maximum gain; gain code = 00000.
[2]
Minimum gain; gain code = 11000.
[3]
Gain code = 00000, 00001, 00010, 00011, 00100.
[4]
PL = 2 dBm per tone; spacing = 2 MHz (f1 = 49 MHz; f2 = 51 MHz)
[5]
PL = 2 dBm per tone; spacing = 2 MHz (f1 = 171 MHz; f2 = 173 MHz)
[6]
PL = 2 dBm per tone; spacing = 2 MHz (f1 = 249 MHz; f2 = 251 MHz)
[7]
PL = 2 dBm per tone (f1 = 30 MHz; f2 = 80 MHz; fmeas = 50 MHz)
[8]
PL = 2 dBm per tone (f1 = 82 MHz; f2 = 90 MHz; fmeas = 172 MHz)
[9]
PL = 2 dBm per tone (f1 = 120 MHz; f2 = 130 MHz; fmeas = 250 MHz)
[10] PL = 5 dBm one tone (f = 86 MHz; fmeas = 172 MHz)
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
8 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
Table 9.
Gain control
gain step
input to either A_D0 to A_D4 pins
or B_D0 to B_D4 pins
nominal power gain (dB)
0
00000
18.5
1
00001
17.5
2
00010
16.5
3
00011
15.5
4
00100
14.5
5
00101
13.5
6
00110
12.5
7
00111
11.5
8
01000
10.5
9
01001
9.5
10
01010
8.5
11
01011
7.5
12
01100
6.5
13
01101
5.5
14
01110
4.5
15
01111
3.5
16
10000
2.5
17
10001
1.5
18
10010
0.5
19
10011
0.5
20
10100
1.5
21
10101
2.5
22
10110
3.5
23
10111
4.5
24
11000
5.5
-
> 11000
5.5
10. Moisture sensitivity
Table 10.
BGA7350
Product data sheet
Moisture sensitivity level
Test methodology
Class
JESD-22-A113
2
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
9 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
11. Application information
aaa-001225
0.5
5
Ven
(V)
Vo
(V)
(1)
(2)
aaa-001226
0.5
(1)
Vo
(V)
5
(2)
Ven
(V)
4
0.3
4
0.1
3
0.1
3
-0.1
2
-0.1
2
-0.3
1(1)
-0.3
1
0.3
-0.5
0
40
0
120
80
-0.5
0
40
t (ns)
t (ns)
(1) VO
(1) VO
(2) Ven
(2) Ven
Fig 3.
Enable time response
BGA7350
Product data sheet
0
120
80
Fig 4.
Gain step response
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
10 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001227
20
aaa-001228
20
(1)
(1)
Gp
(dB)
Gp
(dB)
10
10
0
0
(24)
(24)
-10
-10
60
100
140
180
220
80
120
160
200
f (MHz)
Fig 5.
240
280
f (MHz)
Tuned for fIF = 140 MHz; PL = 5 dBm; step size 1 dB.
Tuned for fIF = 172 MHz; PL = 5 dBm; step size 1 dB.
(1) gain step 0 (maximum gain)
(1) gain step 0 (maximum gain)
(25) gain step 24 (minimum gain)
(25) gain step 24 (minimum gain)
Power gain as a function of frequency
Fig 6.
Power gain as a function of frequency
aaa-001229
20
(1)
Gp
(dB)
10
0
(24)
-10
140
180
220
260
300
340
f (MHz)
Tuned for fIF = 230 MHz; PL = 5 dBm; step size 1 dB.
(1) gain step 0 (maximum gain)
(25) gain step 24 (minimum gain)
Fig 7.
Power gain as a function of frequency
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
11 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001230
0
phase S11
(deg)
mag S11
(dB)
-10
aaa-001231
0
110
90
-10
70
-20
180
phase S11
(deg)
mag S11
(dB)
phase S11
170
phase S11
-20
160
mag S11
-30
50
-30
150
30
-40
140
10
220
-50
mag S11
-40
-50
60
100
140
180
80
120
160
f (MHz)
f (MHz)
Tuned for fIF = 140 MHz; measured at gain step 0
(maximum gain).
Fig 8.
130
240
200
Tuned for fIF = 172 MHz; measured at gain step 0
(maximum gain).
S11 as a function of frequency
Fig 9.
S11 as a function of frequency
aaa-001232
0
150
phase S11
mag S11
(dB)
phase S11
(deg)
-20
90
mag S11
-40
30
-60
140
180
220
-30
300
260
f (MHz)
Tuned for fIF = 230 MHz; measured at gain step 0 (maximum gain).
Fig 10. S11 as a function of frequency
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
12 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001233
0
aaa-001234
0
mag S12
(dB)
mag S12
(dB)
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
60
100
140
180
220
80
120
160
200
f (MHz)
240
f (MHz)
Tuned for fIF = 140 MHz; measured at gain step 0
(maximum gain).
Tuned for fIF = 172 MHz; measured at gain step 0
(maximum gain).
Fig 11. S12 as a function of frequency
Fig 12. S12 as a function of frequency
aaa-001235
0
mag S12
(dB)
-10
-20
-30
-40
-50
140
180
220
260
300
f (MHz)
Tuned for fIF = 230 MHz; measured at gain step 0 (maximum gain).
Fig 13. S12 as a function of frequency
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
13 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001236
0.5
aaa-001237
0.5
EG(dif)
(dB)
EG(dif)
(dB)
0.3
0.3
0.1
0.1
(1)
-0.1
-0.1
(2)
(1)
(3)
(2)
(3)
-0.3
-0.3
-0.5
-0.5
0
5
10
15
20
25
0
5
10
Gstep
15
20
25
Gstep
Tuned for fIF = 140 MHz.
Tuned for fIF = 172 MHz.
(1) Tamb = 40 C
(1) Tamb = 40 C
(2) Tamb = +25 C
(2) Tamb = +25 C
(3) Tamb = +85 C
(3) Tamb = +85 C
Fig 14. Differential gain error as a function of gain
step
Fig 15. Differential gain error as a function of gain
step
aaa-001238
0.5
EG(dif)
(dB)
0.3
0.1
-0.1
(1)
(2)
(3)
-0.3
-0.5
0
5
10
15
20
25
Gstep
Tuned for fIF = 230 MHz.
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 16. Differential gain error as a function of gain step
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
14 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001239
20
aaa-001240
20
PL(1dB)
(dBm)
PL(1dB)
(dBm)
19
19
18
18
17
17
(1)
(1)
(2)
16
16
(2)
(3)
(3)
15
15
0
1
2
3
4
5
0
1
2
Gstep
3
4
5
Gstep
Tuned for fIF = 140 MHz.
Tuned for fIF = 172 MHz.
(1) Tamb = 40 C
(1) Tamb = 40 C
(2) Tamb = +25 C
(2) Tamb = +25 C
(3) Tamb = +85 C
(3) Tamb = +85 C
Fig 17. output power at 1 dB gain compression as a
function of gain step
Fig 18. output power at 1 dB gain compression as a
function of gain step
aaa-001241
20
PL(1dB)
(dBm)
19
18
17
(1)
(2)
(3)
16
15
0
1
2
3
4
5
Gstep
Tuned for fIF = 230 MHz.
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 19. output power at 1 dB gain compression as a function of gain step
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
15 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
55
lP3o
(dBm)
(1)
50
aaa-001242
55
lP3o
(dBm)
(1)
50
gain step 12
(2)
(1)
(3)
(2)
45
gain step 12
gain step 0
(1)
(2)
(2)
(3)
(3)
45
(3)
40
aaa-001243
40
gain step 0
35
35
30
30
25
25
20
20
-4
-2
0
2
4
6
PL (dBm) per tone
-4
Tuned for fIF = 140 MHz.
-2
0
2
4
6
PL (dBm) per tone
Tuned for fIF = 172 MHz.
(1) Tamb = 40 C
(1) Tamb = 40 C
(2) Tamb = +25 C
(2) Tamb = +25 C
(3) Tamb = +85 C
(3) Tamb = +85 C
Fig 20. Output third order intercept point as a function
of output power per tone
Fig 21. Output third order intercept point as a function
of output power per tone
aaa-001244
55
lP3o
(dBm)
50
(1)
(1)
45
gain step 12
gain step 0
(2)
(2)
(3)
(3)
40
35
30
25
20
-4
-2
0
2
4
6
PL (dBm) per tone
Tuned for fIF = 230 MHz.
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 22. Output third order intercept point as a function of output power per tone
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
16 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001245
55
lP3o
(dBm)
aaa-001246
55
lP3o
(dBm)
(2)
45
(1)
45
(1)
(2)
35
35
25
25
15
15
-4
-2
0
2
4
6
PL (dBm) per tone
-4
Tuned for fIF = 140 MHz.
-2
0
2
4
6
PL (dBm) per tone
Tuned for fIF = 172 MHz.
(1) gain step 0
(1) gain step 0
(2) gain step 12
(2) gain step 12
Fig 23. Output third order intercept point as a function
of output power per tone
Fig 24. Output third order intercept point as a function
of output power per tone
aaa-001247
55
lP3o
(dBm)
45
(1)
(2)
35
25
15
-4
-2
0
2
4
6
PL (dBm) per tone
Tuned for fIF = 230 MHz.
(1) gain step 0
(2) gain step 12
Fig 25. Output third order intercept point as a function of output power per tone
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
17 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001248
50
lP3o
(dBm)
aaa-001249
50
lP3o
(dBm)
(2)
45
(2)
45
(3)
(1)
40
40
35
35
30
30
25
(1)
25
(3)
20
20
15
100
150
200
250
15
100
150
200
f (MHz)
PL = 3 dB per tone; Tamb = 25 C.
PL = 3 dB per tone; gain step 12.
(1) gain step 0
(1) Tamb = 40 C
(2) gain step 12
(2) Tamb = +25 C
(3) gain step 24
(3) Tamb = +85 C
Fig 26. Output third order intercept point as a function
of frequency
BGA7350
Product data sheet
250
f (MHz)
Fig 27. Output third order intercept point as a function
of frequency
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
18 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001250
-70
α2H
(dBc)
(1)
(2)
(3)
-80
-70
aaa-001251
-70
α3H
(dBc)
α2H
(dBc)
-90
α3H
-90
-90
α2H
-80
-90
(1)
(2)
(3)
-110
-2
-80
(1)
(2)
(3)
-100
-6
-80
α3H
(dBc)
(1)
(2)
(3)
α2H
2
-100
-100
-110
-110
6
α3H
-100
-110
-6
-2
PL (dBm)
2
6
PL (dBm)
Tuned for fIF = 86 MHz; f2H = 172 MHz; f3H = 258 MHz;
gain step 0 (maximum gain).
Tuned for fIF = 140 MHz; f2H = 280 MHz; f3H = 420 MHz;
gain step 0 (maximum gain).
(1) Tamb = 40 C
(1) Tamb = 40 C
(2) Tamb = +25 C
(2) Tamb = +25 C
(3) Tamb = +85 C
(3) Tamb = +85 C
Fig 28. Second harmonic level and third harmonic
level as a function of output power
Fig 29. Second harmonic level and third harmonic
level as a function of output power
aaa-001252
-70
(1)
(2)
(3)
α2H
(dBc)
-70
-70
α3H
(dBc)
α2H
-80
-80
(1)
(2)
(3)
-90
α3H
-90
-100
-100
-110
-110
-6
-2
2
6
PL (dBm)
Tuned for fIF = 230 MHz; f2H = 460 MHz; f3H = 690 MHz; gain step 0 (maximum gain).
(1) Tamb = 40 C
(2) Tamb = +25 C
(3) Tamb = +85 C
Fig 30. Second harmonic level and third harmonic level as a function of output power
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
19 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
aaa-001253
-30
-30
α3H
(dBc)
α2H
(dBc)
aaa-001254
-50
α2H
(dBc)
α3H
(dBc)
-50
-50
-50
(3)
-70
-70
(2)
α2H
(1)
(1)
(2)
(3)
-70
α3H
-70
(3)
-90
-90
α2H
-90
-110
(1)
-110
-6
-2
2
-110
6
-110
-6
-2
PL (dBm)
2
6
PL (dBm)
Tuned for fIF = 86 MHz; f2H = 172 MHz; f3H = 358 MHz;
Tamb = 25 C.
Tuned for fIF = 140 MHz; f2H = 280 MHz; f3H = 420 MHz;
Tamb = 25 C.
(1) gain step 0
(1) gain step 0
(2) gain step 12
(2) gain step 12
(3) gain step 24
(3) gain step 24
Fig 31. Second harmonic level and third harmonic
level as a function of output power
Fig 32. Second harmonic level and third harmonic
level as a function of output power
aaa-001255
-50
(3)
α2H
(dBc)
-90
α3H
(2)
(1)
(2)
(3)
-50
α3H
(dBc)
α2H
-70
-70
(2)
(1)
(1)
(2)
(3)
-90
α3H
-90
-110
-110
-6
-2
2
6
PL (dBm)
Tuned for fIF = 230 MHz; f2H = 460 MHz; f3H = 690 MHz; Tamb = 25 C.
(1) gain step 0
(2) gain step 12
(3) gain step 24
Fig 33. Second harmonic level and third harmonic level as a function of output power
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
20 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
11.1 Schematic dual VGA
C6
C7
C1
A_IN_N
C2
A_IN_P
A_D0
A_D0
A_D1
A_D1
18
B_OUT_P
B_OUT_N
GNDA
GNDB
19
17
16
26
15
27
14
28
13
BGA7350
29
12
30
11
31
10
B_OUT_N
L3
B_OUT_P
L4
R2
C11
C1
VCCB
GNDB
B_IN_N
C3
B_IN_P
C4
B_D0
B_D0
32
9
1
2
A_D2
33
3
4
5
6
7
B_D1
B_D1
8
B_D2
GNDA
20
B_D3
VCCA
21
B_D4
C10
22
n.c.
C9
A_OUT_P
23
n.c.
L2
24
VCCB
25
A_D4
A_OUT_N
A_D3
L1
R1
C8
B_EN
A_EN
A_OUT_P
VCCA
A_OUT_N
A_EN
B_EN
C5
A_D2
B_D2
A_D3
B_D3
A_D4
B_D4
aaa-001256
For a list of components see Table 11.
Fig 34. Schematic dual VGA
Table 11. List of components
For schematic see Figure 34.
Component
Description
C1, C2, C3, C4, C5, C6, C7, C8, C9, C11
capacitor
1 nF
C10, C12
capacitor
100 pF
L1, L2, L3, L4
inductor
R1, R2
BGA7350
Product data sheet
resistor
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
Conditions
Value
Remarks
f = 50 MHz
1200 nH
0603LS
f = 172 MHz
120 nH
0603LS
f = 250 MHz
56 nH
0603LS
0
© NXP B.V. 2011. All rights reserved.
21 of 31
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
NXP Semiconductors
BGA7350
R17
10 kΩ
JP13
1
C9
100 pF
R1
10 kΩ
GND
R3
10 kΩ
R15
10 kΩ
GND
2
R2
10 kΩ
VCMinA
1
C11
R14
10 kΩ
GND
R16
10 kΩ
4
2
1
P03
P04
P05
P06
P07
GND
21
4
5
20
6
19
7
PCF8575
18
8
17
9
16
10
15
11
14
12
13
A0
GND
P17
P14
2
3
n.c.
1
n.c.
B_D4
JP7
GND
219-05
B_D3
BG
5
10
P13
7
4
8
7
P12
8
3
6
5
6
9
P11
9
2
4
3
P10
10
1
2
1
GND
A_D3
A_D4
VCM
4
GND
P16
P15
A_D2
1
JP1
S2
B_D2
A_OUT_N
A_OUT_P
2
1 32 31 30 29 28 27 26 25
24
2
23
3
22
4
21
BGA7350
5
20
I1
6
19
7
18
8
17
33
9 10 11 12 13 14 15 16
GND
R18
0Ω
GND
JP9
GND n.m.
2
GND
1
A_OUT_P
R6
10 kΩ
2
1
TR4
4
R8
10 kΩ
SMA-142-0701851/861
X3
6
GND
GNDB
GND
B_EN
GND
GND
JP3
GND
1
4
3
1
4
3
2
S3
GND
10 Ω
GND
1
219-02
JP11
2
R20
0Ω
R24
GND
0Ω
C21
1 μF
2
VCMB
R19
0Ω
L4
180 nH
1
1
R25
0Ω
GND
C7
1 nF
C8
100 pF
SMA-142-0701851/861
6
GND
2
R26
n.m.
C18 100 nF 3
X2
GND
4
TR3
ADT4-1T+
GND
C22
1 μF
R10
GND
1
1
2
JP4
3
JP16
GND
VoutB
GND
GND
aaa-001257
JP12
GND
1
GND
2
BGA7350
22 of 31
© NXP B.V. 2011. All rights reserved.
Fig 35. Schematic
2
3
B_OUT_P
GND
For a list of components see Table 12.
EN
4
B_OUT_N
VCCB
GND
GND
1
VCMA
GNDA
C4
10 nF
C3
100 pF
2
4
JP10
A_EN
C16
100 nF
3
2
GND
L3
180 nH
ADT3-1T
X5
SMA-142-0701851/861
3
GND
A_OUT_N
GND
VCMinB
R9
10 kΩ
6
2
0Ω
GND
C14
n.m.
C13
R7
10 kΩ
1
C17 100 nF
R23
n.m.
R22
JP2
R5
10 kΩ
ADT4-1T+ GND
TR2
R21
R12
0Ω
B_OUT_N
1
S1
VCCA
10
SCL
VCCB
SDA
A_IN_N
3
GNDA
5
4
A_IN_P
6
2
A_D1
3
9
A_D0
8
B_OUT_P
P02
22
7
GNDB
P01
3
8
C23
1 μF
C6
100 pF
L1
180 nH
0Ω
9
B_IN_P
P00
23
2
4
C5
1 nF
GND
B_IN_N
A2
7
L2
180 nH
C2
C20
10 nF 1 μF
50 MHz to 250 MHz high linearity Si variable gain amplifier
Rev. 1 — 21 December 2011
All information provided in this document is subject to legal disclaimers.
A1
24
1
10
B_D0
INT_B
AG
5
VCC
lC1
GND
219-05
3
GND
10 Ω
C1
100 pF
C15
JP8 GND 100 nF
B_D1
MKS18546-0-404
6
2
R13
3
GND
4
3
2
1
JP15
1
2
GND
TR1
ADT3-1T
2
GND n.m.
X1
1
JP5
SMA-142-0701851/861
6
R4
10 kΩ
n.m.
C12
GND
X4
GND
JP6
1
VoutA
VCCA
C10
C19
1 μF 100 nF
VCCdig
2
11.2 Application PCB
Product data sheet
GND
R11
10 kΩ
BGA7350
NXP Semiconductors
LSB
+
1
+
22
R
1 2
L3
3
R
26
B OUT
+
+
1 2 3 4 5
X3
21
6
C
5
C
JP3
L4
1 2
C13 C11
C14 C12
R17
JP2
24
1 2 3
25
VCM IN B
JP9
JP6
R
R
R9
4
S2
R10 JP16 GND
VCCB GND
TR
LSB
8
R7
R8
C4
JPA
JP11
C
R6
GND
S3
C
R5
I1
C3
C9
MSB
VCC I2C
JP10
7
R11
R14
R16
JP7
B VDD25ext
X5
A OUT
L1
C10
L2
A VDD25ext
GND
2 3
R
TR
C2
C1
S1
X1
R13 1
TR
1 2 3 4 5
VCCA
JP15 GND
23
MSB
JP5 GND
R
R4
JP1
R3
JP13
VCM IN A
2
R1
R2
C19
GND
TR
R15
VCC
GND
GND
JP8
X4
50 MHz to 250 MHz high linearity Si variable gain amplifier
GND
GND
X2
JP12
aaa-001258
For a list of components see Table 12.
Fig 36. Components top side
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
23 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
C
15
17
C
C20
C
R20
R19
C
22
R18
R12
23
C
C
18
16
C21
aaa-001259
For a list of components see Table 12.
Fig 37. Components bottom side
Table 12. List of components
See Figure 35, Figure 36 and Figure 37.
Component
Description
C1, C3, C6, C8, C9
Value
Size
capacitor
100 pF
0603
C2, C4
capacitor
10 nF
0603
C5, C7
capacitor
1 nF
0603
C10, C15, C16, C17, C18
capacitor
100 nF
0603
C11
capacitor
-
0603
not mounted
C12
capacitor
-
0603
not mounted
C13
capacitor
-
0603
not mounted
C14
capacitor
-
0603
not mounted
C19, C20, C21, C22, C23
capacitor
1 F
0603
I1
BGA7350
-
JP1
jumper
-
JP5
AG
JP2
jumper
-
JP5
BG
JP3
jumper
-
JP2
EN
JP4
jumper
-
JP2
VCCB
JP5
jumper
-
JP2
VCCA
JP6
jumper
-
JP2
VCCdig
JP7
jumper
-
JP2
VCM
JP8
jumper
-
JP2
VCMinA
BGA7350
Product data sheet
Conditions
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
Remarks
© NXP B.V. 2011. All rights reserved.
24 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
Table 12. List of components
See Figure 35, Figure 36 and Figure 37.
Component
Description
JP9
JP10
Conditions
Value
Size
Remarks
jumper
-
JP2
VCMinB
jumper
-
JP2
VCMA
JP11
jumper
-
JP2
VCMB
JP12
jumper
-
JP2
GND
JP13
jumper
-
JP2
GND
JP15
jumper
-
JP3
VoutA
JP16
jumper
L1, L2, L3, L4
inductor
-
JP3
VoutB
fIF = 140 MHz
150 nH
0603
dependent on PCB layout
fIF = 172 MHz
100 nH
0603
dependent on PCB layout
fIF = 230 MHz
56 nH
0603
dependent on PCB layout
R1
resistor
10 
0402
R2
resistor
10 
0402
R3
resistor
10 
0402
R4
resistor
10 
0402
R5
resistor
10 
0402
R6
resistor
10 
0402
R7
resistor
10 
0402
R8
resistor
10 
0402
R9
resistor
10 
0402
R10
resistor
10 
1206
R11
resistor
10 
0402
R12
resistor
0
0402
R13
resistor
10 
1206
R14
resistor
10 
0402
R15
resistor
10 
0402
R16
resistor
10 
0402
R17
resistor
10 
0402
R18
resistor
0
0402
R19
resistor
0
0402
R20
resistor
0
0402
R21
resistor
0
0402
R22
resistor
0
0402
R23
resistor
-
0402
R24
resistor
0
0402
R25
resistor
0
0402
R26
resistor
-
0402
S1
DIP-switch
-
CTS-219-05
S2
DIP-switch
-
CTS-219-05
S3
DIP-switch
-
CTS-219-02
TR1
1:3 transformer
-
Mini Circuits ADT3-1T+
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
not mounted
not mounted
© NXP B.V. 2011. All rights reserved.
25 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
Table 12. List of components
See Figure 35, Figure 36 and Figure 37.
Component
Description
Conditions
Value
Size
Remarks
TR2
1:4 transformer
-
Mini Circuits ADT4-1T+
TR3
1:3 transformer
-
Mini Circuits ADT4-1T+
TR4
1:4 transformer
-
Mini Circuits ADT3-1T+
X1
-
-
not mounted
X2
SMA-connector
-
BOUT_P
X3
SMA-connector
-
BIN_P
X4
SMA-connector
-
AIN_P
X5
SMA-connector
-
AOUT_P
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
26 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
12. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A
B
D
SOT617-1
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
1/2
e b
9
y
y1 C
v M C A B
w M C
16
L
17
8
e
e2
Eh
1/2
1
terminal 1
index area
e
24
32
25
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Fig 38. Package outline SOT617-1 (HVQFN32)
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
27 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
13. Abbreviations
Table 13.
Abbreviations
Acronym
Description
ADC
Analog-to-Digital Converter
DC
Direct Current
DIP
Dual In-line Package
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
GSM
Global System for Mobile Communications
HTOL
High Temperature Operating Life
HVQFN
Heatsink Very-thin Quad Flat-pack No-leads
IF
Intermediate Frequency
LSB
Least Significant Bit
LTE
Long Term Evolution
MMIC
Monolithic Microwave Integrated Circuit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
RF
Radio Frequency
SMA
SubMiniature version A
WiMAX
Worldwide Interoperability for Microwave Access
W-CDMA
Wideband Code Division Multiple Access
14. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BGA7350 v.1
20111221
Product data sheet
-
-
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
28 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
29 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BGA7350
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 December 2011
© NXP B.V. 2011. All rights reserved.
30 of 31
BGA7350
NXP Semiconductors
50 MHz to 250 MHz high linearity Si variable gain amplifier
17. Contents
1
1.1
1.2
1.3
1.4
2
2.1
2.2
3
4
5
6
7
8
9
10
11
11.1
11.2
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5
Enable control . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Moisture sensitivity . . . . . . . . . . . . . . . . . . . . . . 9
Application information. . . . . . . . . . . . . . . . . . 10
Schematic dual VGA . . . . . . . . . . . . . . . . . . . 21
Application PCB . . . . . . . . . . . . . . . . . . . . . . . 22
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 27
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28
Legal information. . . . . . . . . . . . . . . . . . . . . . . 29
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact information. . . . . . . . . . . . . . . . . . . . . 30
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 December 2011
Document identifier: BGA7350