TI TPS68000DBTR

TPS68000
(6,4 mm x 7,8 mm)
www.ti.com
SLVS524 – OCTOBER 2005
HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
8-V to 30-V Input Voltage Range
Full Bridge Topology With Integrated Gate
Drives for 4 NMOS Switches
Synchronizable Constant Frequency
Operation
Programmabe Phase Delays of Operating
Frequency for Master-Slave Operation
Lamp Voltage and Lamp Current Regulation
Analog and Burst Dimming
Configurable Distributed Burst Dimming in
Multiple Controller Applications
Programmable Voltage Regulation Timeout
for Startup and Fault Conditions
Open-Lamp and Short-Circuit Protection
Internal Over-Temperature Protection
Undervoltage Lockout
30-pin TSSOP Package
The TPS68000 device provides a power supply
controller solution for CCFL backlight applications in a
large variety of applications. The wide input voltage
range of 8 V to 30 V makes it suitable to be powered
directly from regulated 12-V or 24-V rails, or any
other source with output voltages in this range. When
using a regulated 5-V rail, it also can be used in
notebook
computers
or
other
portable
battery-powered equipment having lower minimum
supply voltages. The controller is capable of driving
the gates of all 4 NMOS switches directly without the
need for any additional circuitry, like dedicated gate
drivers or gate-drive transformers. The wide input
voltage range also makes it easy to design CCFL
converters with higher input voltages like 120 V or
400 V coming from a power factor correction unit.
The TPS68000 also supports CCFL converter circuits
driving multi-lamp applications, either by using higher
power-rated switches and transformers, or using
several
TPS68000s
synchronized.
When
synchronized, they can be operated either at the
same frequency and phase, or phase shifted to
minimize RMS input current. Already implemented
smart dimming features, such as support of
distributed dimming, also help to optimize the
performance
of
multi-controller
applications.
(Continued on next page)
APPLICATIONS
•
•
CCFL Backlight Power Supplies for Desktop
Monitors and LCD TVs
CCFL Backlight Power Supplies for Notebook
Computers
C10
TPS68000
Supply Voltage
8V .. 30V
VCC
C1
VLOGIC
GA
SA
R2
Error Output
Synchronization
Synchronization Phase Shift
Operating Frequency
FAULT
0V
Burst Duty Cycle
(Burst Dimming Input)
C5
GC
SC
EN
STC
GB
GD
ABR
2V
0V
BBR
C6
Burst Frequency
Direct Burst Dimming Input
(Frequency + Duty Cycle)
BF
QC
3
C12
C14
C4
T1
QB
C2
V5
3.3 V
0V
QA
C
V5C
PH
SET
R1
Device Enable
Lamp current
(Analog Dimming Input)
SYNC
2.0 V
V5A
OCP
CSEN
CAO
QD
C13
R3
R4
C8
CA−
VSEN
BC
C7
VREF
GND
VAO
C9
VA−
PGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated
PRODUCT PREVIEW
•
•
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
To start the lamp, an automatic strike control is implemented. It smoothly increases the lamp voltage by
sweeping the operating frequency across the self resonance frequency of the transformer-series capacitor
resonant circuit. During this time the maximum lamp voltage is limited and regulated by a voltage control loop
until the lamp current increases to a value allowing the current control loop to take over control. The lamp current
is regulated over a wide current range. To set the lamp brightness, analog and PWM dimming circuits are
implemented. Analog and PWM dimming can be used independent of each other to control lamp brightness over
a wide range.
To protect the circuit during fault conditions, for example broken, disconnected, or shorted lamps, overvoltage
protection and overcurrent protection circuits are implemented. To protect the TPS68000 from overheating, an
internal temperature sensor is implemented that triggers controller turn-off at an excessive device temperature.
The device is packaged in a 30-pin TSSOP package measuring 6,4 mm x 7,8 mm (DBT).
ORDERING INFORMATION
PRODUCT PREVIEW
(1)
TA
PACKAGE
PART NUMBER (1)
–40°C to 85°C
30-Pin TSSOP
TPS68000DBT
The DBT package is available taped and reeled. Add R suffix to device type (e.g., TPS68000DBTR) to order quantities of 2000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
TPS68000
Input voltage range on VCC, EN, FAULT
–0.3 V to 33 V
Input voltage range on SYNC, SET, PH, STC, ABR, BBR, BF, BC, VREF, VA-, VAO, CA-, CAO
–0.3 V to 6 V
Input voltage range on VSEN, CSEN, OCP
–6 V to 6 V
Input voltage range on GD, GB, V5
–0.3 V to 6 V
maximum differential voltage between GA, V5A and SA
6V
maximum differential voltage between GC, V5C and SC
6V
maximum differential voltage between SA and PGND
35V
maximum differential voltage between SC and PGND
35V
Operating virtual junction temperature range, TJ
–40°C to 150°C
Storage temperature range Tstg
–65°C to 150°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated uner "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
THERMAL RESISTANCE
θJA
POWER RATING
TA≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
TA≤ 70°C
POWER RATING
TA≤ 85°C
DBT
63.9°C/W
1565 mW
16 mW/°C
860 mW/°C
626 mW/°C
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
VI
Supply voltage at VCC
8.0
30
V
TA
Operating free air temperature range
–40
85
°C
TJ
Operating virtual junction temperature range
–40
125
°C
2
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.5
5
5.5
V
25
mA
4.1
4.3
V
MAIN CONTROL
V5
Internal control supply
regulator
IOUT-V5< 25 mA
IOUT-V5
Control supply output
current
including internal current
consumption
VUVLO
Under voltage lockout
threshold at V5
Voltage at V5 decreasing
VOL
FAULT output low
voltage
IFAULT = 500 µA
0.2
0.4
V
Vlkg
FAULT output leakage
current
VFAULT= 5 V
0.1
1
µA
VIL
EN input low voltage
0.4
V
VIH
EN input high voltage
1.4
EN input current
VCC = 24 V
ISTC
STC source current
during strike
ISTC
STC source current
during wait
ISTC
STC source and sink
current
normal operation, VSTC = 1.25
V
V
0.05
0.1
µA
10
µA
5
µA
10
µA
Overtemperature
protection
140
°C
Overtemperature
hysteresis
20
°C
Quiescent current into
VCC
VCC = 12V, V5 = 5.5V
25
40
µA
Quiescent current into
VCC
VCC = V5 = 5V
25
40
µA
Quiescent current into
V5
VCC = V5 = 5V
1000
1500
µA
Shutdown current into
VCC
VCC = V5 = 5V, EN = 0V
1
2
µA
Shutdown current into
V5
VCC = V5 = 5V, EN = 0V
1
2
µA
Shutdown current into
VCC
VCC = 12V, EN = 0V
2.5
5
µA
VREF
Reference Voltage
IOUT-VREF < 5mA
3.3
3.33
V
IOUT-VREF
Reference output
current
3.27
5
PRODUCT PREVIEW
4.0
mA
GATE DRIVE
High side drive sink
resistance
ID = 0.05A
High side drive source
resistance
ID = 0.05A
High side drive rise
time
CG = 4.7 nF, SA = SC = 0 V,
V5A = V5C = 5 V
High side drive fall time CG = 4.7 nF
1.2
2.0
Ω
1.5
2.5
Ω
35
50
ns
15
25
ns
Time delay between
high side off and low
side on
CG = 4.7 nF
100
ns
Time delay between
low side off and high
side on
CG = 4.7 nF
100
ns
3
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low side drive sink
resistance
ID = 0.05A
1.2
2.0
Ω
Low side drive source
resistance
ID = 0.05A
1.5
2.5
Ω
Low side drive rise
time
CG = 4.7 nF, V5 = 5 V
35
50
ns
Low side drive fall time
CG = 4.7 nF
15
25
ns
30
100
kHz
0.5 x f
2xf
MAIN OSCILLATOR
PRODUCT PREVIEW
f
Oscillator frequency
programming range
fSYNC
Frequency capture
range for
synchronization
VIL
SYNC low voltage
VIH
SYNC high voltage
ISYNC
SYNC input current
VPH≤ V5 - 1.3 V
ISYNC
SYNC drive current
VSYNC≥ 1.4 V, VPH = 5 V
ISYNC
SYNC sink current
VSYNC≤ 0.4 V, VPH = 5 V
VSET
VPH
0.4
V
0.5
1.5
µA
1000
1250
1500
µA
1000
1250
1500
µA
1.4
V
Minimum pulse width
for synchronization
100
ns
SET output voltage
1.25
V
Resistor range for main
frequency
programming
280
Input voltage range for
programming phase
delay for main
oscillator clock to
synchronization
frequency
0.1
140
Phase shift of the main
VPH = 0.1 V .. 1.9 V
oscillator clock
90
IPH
PH input current
0.1
VPH
Threshold for
programming device as
main oscillator
frequency master
VPH = 2.0 V
V5– 1.3 V
80
kΩ
1.9
V
° / VPH
1
µA
V5– 0.9 V
V
VOLTAGE AND CURRENT CONTROL
RCSEN
Current sense input
impedance
VCSEN = 3.3 V
35
kΩ
RCSEN
Current sense input
impedance
VCSEN = –3.3 V
25
kΩ
RVSEN
Voltage sense input
impedance
VVSEN = 3.3 V
25
kΩ
RVSEN
Voltage sense input
impedance
VVSEN = –3.3 V
30
kΩ
ICAO, IVAO
Voltage and current
amplifier output source
current
VCAO, VVAO = 2.5 V
55
µA
ICAO, IVAO
Voltage and current
amplifier output sink
current
VCAO, VVAO = 2.5 V
4
200
µA
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
ELECTRICAL CHARACTERISTICS (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREFVREG
Virtual voltage
regulator reference
voltage
2.61
2.64
2.67
V
VREFOVP
Overvoltage
comparator threshold
3.27
3.3
3.33
V
VREFCREG
Virtual current
regulator reference
voltage
3.27
3.3
3.33
V
IOCP
Overcurrent
comparator input
current
VOCP = 3.3V
0.1
1
µA
IOCP
Overcurrent
comparator input
current
VOCP = –3.3V
50
VREFOCP
Overcurrent
comparator threshold
3.27
µA
3.3
3.33
V
0.01
0.1
µA
3.3
V
1
µA
2
V
IABR
ABR input current
VABR = 3.3 V
VABR
ABR input voltage
range for lamp current
programming
BC = V5
IBBR
BBR input current
VBBR = 2.0 V
VBBR
BBR input voltage
range for burst duty
cycle programming
0
0.1
0
Burst duty cycle
VBBR
BBR input voltage
threshold for selecting
synchronized burst
dimming
IBF
BF source current
BF capacitor range to
program internal burst
frequency
fBurst
Internal burst
frequency range
fBC
Frequency lock /
capture range for
synchronized burst
dimming
tr
Burst current pulse rise
time
IBC
BC input current
VIL
BC input low voltage
VIH
BC input high voltage
V5– 0.9 V
10
(1kHz down to 10Hz)
0.0047
0.47
µF
10
1000
Hz
0.5 x fBurst
1.5 x fBurst
VBC = 3.3V
0.1
1.4
VPH = 0 V .. 2 V, distributed
dimming selected
V
µA
400
minimum pulse width
at BC
Phase shift of the
dimming burst
compared to BC clock
%/
VBBR
50
V5– 1.3 V
PRODUCT PREVIEW
DIMMING
µs
1
µA
0.4
V
V
100
ns
180
° / VPH
5
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
PIN ASSIGNMENTS
DBT PACKAGE
(TOP VIEW)
SYNC
SET
STC
PH
BBR
BC
BF
ABR
VAO
VA−
VSEN
CA−
CAO
CSEN
OCP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VREF
GND
SA
GA
V5A
GB
VCC
V5
PGND
GD
V5C
GC
SC
EN
FAULT
PRODUCT PREVIEW
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
ABR
8
I
Analog brightness programming input. A DC voltage applied at that pin programs the lamp current
the current regulator regulates. 0 V means no current and 3.3 V means maximum current.
BBR
5
I
Burst brightness programming input. A DC voltage applied at that pin programs the duty cycle of the
burst pulses generated to dimm the brightness. 0 V means zero duty cycle and 2 V means
maximum duty cycle. Applying V5 (5 V) programs the device for synchronized burst dimming.
BC
6
I
Burst control. A PWM signal applied at that pin is directly used for burst dimming. Frequency and
duty cycle are used directly. This input has priority against the burst frequency programming with
BBR and BF
BF
7
I
Burst frequency programming. A capacitor at that pin programs the low frequency for the burst
dimming
CA-
12
I
Current amplifier negative input. This input is used to connect the compensation capacitor for
compensating the current loop.
CAO
13
O
Current amplifier output. This is the output for the current amplifier. It is used to connect the
compensation capacitor for the current loop.
CSEN
14
I
Current sense. Measuring input for the lamp current. The applied voltage (coming from a shunt
resistor) will be used for lamp current regulation. Sensed AC voltages can be applied directly. They
will be rectified internally.
EN
17
I
Enable input. Logic high enables the device.
FAULT
16
O
Error output, any detected malfunctioning of the application will be reported as error on this pin.
Error means the output is pulled low. The output is open drain to allow connecting multiple error
outputs of similar devices together.
GA
27
O
Gate drive output of switch A
GB
25
O
Gate drive output of switch B
GC
19
O
Gate drive output of switch C
GD
21
O
Gate drive output of switch D
GND
29
OCP
15
PGND
22
6
Analog ground pin. Reference ground for all control signals.
I
Over current protection. This input is used to monitor a voltage derived from a current sensor in any
part of the converter. This voltage is compared to an internal reference voltage. Exceeding the
internal reference voltage causes the device logic to turn the device off and report an error signal at
the fault pin.
Reference ground for the gate drivers and the gate drive supply.
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
PIN ASSIGNMENTS (continued)
Terminal Functions (continued)
NO.
I/O
DESCRIPTION
I
Phase delay programming input. A voltage between 0 V and 2 V applied to that pin programs the
phase delay of the operating frequency compared to the synchronizing frequency. Applying V5 (5.0
V) programs the device as a master regarding the main oscillator frequency (see SYNC). The
voltage applied to that pin is also used to determine the phase delay in a distributed dimming
configuration
PH
4
SA
28
SC
18
SET
2
I
Operating frequency programming input. A resistor connected to this pin programs the internal
operating frequency.
STC
3
I
Startup capacitor. A capacitor connected to that pin determines the the time the device waits in
voltage regulation for the lamp to strike.
SYNC
1
I/O
Synchronization input or operating frequency output. If the device is configured as master (see PH)
the pin is used to provide the synchronization frequency for the slaves. Otherwise the device works
as slave and uses the applied frequency at that pin for synchronizing the operating frequency.
V5
23
O
Input/Output of the internal 5 V regulator for Gate drive supply. A capacitor must be connected to
that pin to decouple switching noise caused by the gate drivers.
V5A
26
O
Supply input for the gate driver of the high-side switch A. A capacitor must be connected to that pin
to supply the gate driver during switching (bootstrap).
V5C
20
O
Supply input for the gate driver of the high side switch C. A capacitor must be connected to that pin
to supply the gate driver during switching (bootstrap).
VA-
10
I
Voltage amplifier negative input. This input is used to connect the compensation capacitor for
compensating the voltage loop.
VAO
9
O
Voltage amplifier output. This is the output for the voltage amplifier. It is used to connect the
compensation capacitor for the voltage loop.
VCC
24
I
Device supply voltage
VREF
30
O
Voltage reference. Output of the internal 3.3-V reference for use with all the analog control inputs.
VSEN
11
I
Voltage sense. Measuring input for the lamp voltage. This voltage is used for lamp voltage
regulation (open lamp regulation) and overvoltage protection. Sensed AC voltages can be applied
directly. They are rectified internally.
Source connection of switch A
Source connection of switch C
PRODUCT PREVIEW
TERMINAL
NAME
7
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
FUNCTIONAL BLOCK DIAGRAM (TPS68000)
V5A
GA
SA
V5
VCC
V5
Control Supply
OVP
GB
Gate
Control
Main Control
V5C
OCP
FAULT
GC
SC
V5
V5
GD
PGND
OCP
OCP
SYNC
VREF
SET
Oscillator
VREF_OCP
Phase Shift
Control
PH
CAO
PRODUCT PREVIEW
CA−
EN
Startup
and Strike
Control
SS
Rectifier
CSEN
VAO
VA−
ABR
Analog
and
Burst
Dimming
BBR
BF
Rectifier
VREF_VREG
BC
OVP
VREF
VSEN
OVP
VREF_OVP
VREF
GND
PARAMETER MEASUREMENT INFORMATION
C10
TPS68000
Supply Voltage
8V .. 30V
VCC
C1
VLOGIC
Error Output
Synchronization
Synchronization Phase Shift
Operating Frequency
FAULT
0V
Burst Duty Cycle
(Burst Dimming Input)
C5
EN
STC
GB
GD
ABR
0V
BBR
C6
BF
VREF
GND
8
C12
C14
C4
T1
QB
C2
OCP
CSEN
CAO
C8
CA−
VSEN
BC
C7
QC
3
V5
2V
Burst Frequency
Direct Burst Dimming Input
(Frequency + Duty Cycle)
GC
SC
3.3 V
0V
QA
C
V5C
PH
SET
R1
Device Enable
Lamp current
(Analog Dimming Input)
SYNC
2.0 V
V5A
GA
SA
R2
VAO
VA−
PGND
C9
QD
C13
R3
R4
TPS68000
www.ti.com
SLVS524 – OCTOBER 2005
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
PRODUCT PREVIEW
The maximum recommended junction temperature (TJ) of the TPS68000 device is 125°C. The thermal resistance
of the 30-pin TSSOP package (PW) is RθJA = 63.9°C/W. Specified regulator operation is assured to a maximum
ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 626 mW. More power can
be dissipated if the maximum ambient temperature of the application is lower.
T
T
J(MAX)
A
P
125°C 85°C 820 mW
D(MAX)
R
48.7 °CW
JA
(1)
9
MECHANICAL DATA
MPDS019D – FEBRUARY 1996 – REVISED FEBRUARY 2002
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–ā8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
20
24
28
30
38
44
50
A MAX
5,10
6,60
7,90
7,90
9,80
11,10
12,60
A MIN
4.90
6,40
7,70
7,70
9,60
10,90
12,40
DIM
4073252/E 02/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS68000DBT
PREVIEW
SM8
DBT
30
60
TBD
Call TI
Call TI
TPS68000DBTR
PREVIEW
SM8
DBT
30
2000
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
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