BGA7350 performance at IF=150 MHz

UM10608
BGA7350 performance at IF=150 MHz
Rev. 1 — 14 November 2012
User manual
Document information
Info
Content
Keywords
Dual VGA. 28 dB attenuator range IF=150 MHz NXP
Abstract
This User Manual describes the functionality and performance of the
single ended BGA7350 evaluation board, tuned for a IF of 150 MHz
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
Revision history
Rev
Date
Description
1
First publication
20121114
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
2 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
1. Introduction
The BGA7350 is a Silicon MMIC (Monolithic Microwave Integrated Circuit) processed in
NXP's mainstream Si QuBIC4+ BiCmos process. This process intrinsic inhibits high FT
figures (up to 28 GHz), while not compromising ruggedness (breakdown voltage) and
noise figures. These characteristics make this device suitable for versatile IF applications
like in Base station receive path. The BGA7350 exhibits a logic-level shutdown control to
2
reduce supply current. The BGA7350 is packed in the leadless HVQFN (5 x 5 mm ), and
in combination with the optimized die design, gives excellent thermal performance,
To ensure optimal ESD protections, all pins are ESD protected.
All above mentioned highlight makes the BGA7350 and extreme attractive device with
optimal performance/cost ratio, as compared to other devices in the market.
The single ended 150 MHz evaluation board (EVB) is designed for optimal performance
in the 150 MHz frequency ranges, with a bandwidth of 28 MHz, suitable for base station
Rx applications, as shown in Fig. 1.
Fig 1.
UM10608
User manual
Generic Base station architecture
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
3 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
2. Product Profile
2.1 General description
The BGA7350 MMIC is a dual independently digitally controlled IF Variable Gain
Amplifier (VGA) operating from 50 MHz to 250 MHz Each IF VGA amplifies with a gain
range of 24 dB and at its maximum gain setting delivers 17 dBm output power at 1 dB
gain compression and a superior linear performance.
The BGA7350 Dual IF VGA is optimized for a differential gain error of less than ±0.1 dB
for accurate gain control and has a total integrated gain error of less than ±0.3 dB.
The gain controls of each amplifier are separate digital gain-control word, which is
provided externally through two sets of 5 bits.
The BGA7350 is housed in a 32 pins 5 × 5 mm2 leadless HVQFN package.
2.2 Features and benefits

Dual independent digitally controlled 28 dB gain range VGAs, with 5-bit control
interface

50 MHz to 250 MHz frequency operating range

Gain step size: 1 dB ± 0.1 dB

18.5 dB small signal gain

Fast gain stage switching capability

17 dBm output power at 1 dB gain compression

5 V single supply operation with power-down control

Logic-level shutdown control pin reduces supply current

Excellent ESD protection at all pins

Moisture sensitivity level 2

Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)

Unconditionally stable

Excellent differential and integrated gain error
2.3 Applications
UM10608
User manual

Compatible with GSM / W-CDMA carrier/ WiMAX / LTE base-station infrastructure /
multi systems carrier

Multi channel receivers

General use for DAC driver applications
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
4 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
3. Pinning information
Transparent top view
Fig 2.
UM10608
User manual
SOT617-1 Pin configuration
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
5 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
3.1 Pin description
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
6 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
4. Functional Diagram
Fig 3.
UM10608
User manual
Functional diagram
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
7 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
5. Gain control Range
Input to all 0 to 4 gain control pins
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
> 11100
nominal power gain [dB]
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
-6
Table 3 Gain control range
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
8 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
6. EVB circuit diagram
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
9 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
7. Evaluation Board top layout
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
10 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
8. Evaluation board bottom layout
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
11 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
9. Bill of Materials (BOM)
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
12 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
Part
Value
Device
Package
Description
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
10k
10k
10k
10k
10k
10k
10k
10k
10k
10
10k
0
10
10k
10k
10k
10k
0
NM
NM
0
0
NM
0
0
NM
0
NM
0
NM
NM
0
NM
NM
0
0
NM
0
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R1206
R-EU_R0402
R-EU_R0402
R-EU_R1206
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R-EU_R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R1206
R0402
R0402
R1206
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
S1
S2
S3
DIP
DIP
DIP
219-05
219-05
219-02
CTS-219-05
CTS-219-05
CTS-219-02
Surface
Surface
Surface
TR1
TR2
TR3
TR9
ADT3-1T+
ADT4-1T+
ADT4-1T+
ADT3-1T+
transformer
transformer
transformer
transformer
Mini-Circuits
Mini-Circuits
Mini-Circuits
Mini-Circuits
X1
X2
X3
X4
X5
X10
X11
X12
X13
X14
X15
NM
BOUT_P
BIN_P
AIN_P
AOUT_P
NM
NM
NM
NM
NM
NM
con
SMA connector
SMA connector
SMA connector
SMA connector
BU-SMA-V
SMA connector
SMA connector
SMA connector
BU-SMA-V
SMA connector
SMA
SMA
SMA
SMA
FEMALE
SMA
SMA
SMA
FEMALE
SMA
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
13 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
10. Operation of the BGA7350 EVB
10.1 Applying bias
The EVB, as shown in Fig. 4, should be connected to 5V supply, according the following
connections:
1. Leave jumpers JP3 in their current position, as shown in Fig. 4
2. Apply +5V to VCC_A and/or VCC_B to the pins, as shown in Fig. 4
3. Apply ground to GND_A and/or GND_B pins
4.
VCC_A
5.
6.
GND
Pin_A
7.
8.
9.
10.
11.
Pout_A
12.
13.
14.
JP3
15.
16.
17.
Pout_B
18.
19.
20.
21.
22.
23.
24.
VCC_B
Pin_B
GND
25.
26.
Fig 4. BGA7350 EVB picture
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
14 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
10.2 Mode of operation
The EVB of the BGA7350 can either be operated in the manual mode or ‘automatic’ mode.
The BGA7350 can be enabled/disabled by switch3 (see Fig.5)
Fig 5. Enable/disable switch S3
10.2.1 Manual mode.
For manual mode operation, all jumpers, as shown in Fig. 5 must be in place. Also a 5V
pull-up voltage and ground should be applied, as indicated as 5V/GND pull-up in Fig. 6.
LSB_A
MSB_A
MSB
MSB_B
5V pull_up
GND pull_up
LSB_B
Fig. 6 jumper positions
Fig. 6 Manual gain settings by switches S1 and S2
With the positions of S1 and S2, the gain range can be adjusted according the values in Table.3.
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
15 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
10.3 Mode of operation
The EVB of the BGA7350 can either be operated in the manual mode or ‘automatic’ mode.
The BGA7350 can be enabled/disabled by switch3 (see Fig.5)
Fig 5. Enable/disable switch S3
10.3.1 Manual mode.
For manual mode operation, all jumpers, as shown in Fig. 5 must be in place. Also a 5V
pull-up voltage and ground should be applied, as indicated as 5V/GND pull-up in Fig. 6.
LSB_A
MSB_A
MSB
MSB_B
5V pull_up
GND pull_up
LSB_B
Fig. 6 jumper positions
Fig. 6 Manual gain settings by switches S1 and S2
With the positions of S1 and S2, the gain range can be adjusted according the values in Table.3.
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
16 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
10.3.2 ‘Automatic’ mode
For ‘automatic’ mode of operations the jumpers according Fig. 6 should be removed, and
2
logic levels should be applied to the rows (also I C operation is possible, but not functional
on this EVB), as indicated by the white circles (see Fig. 7). The logic levels applied to the
pins should be within the following range:
0V < ‘0’ < 0.8V
1.6V < ‘1’ < 5V
LSB_A
MSB_A
MSB_B
LSB_B
Fig. 6 removed jumpers
Fig. 7 Gain setting control by logic levels, according table 3
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
17 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11. Measurements
On the BGA7350, the following measurements have been performed:
1. S-parameters. From the S-parameter measurements the following data can be deducted:
a. S-parameters
(Spar)
b. Power gain
(Gp)
c.
(Δgadj)
Gain adjustment range
d. Gain step
(Gstep)
e. Gain Flatness
(Gflat)
f.
Differential gain error
(Egdiff)
g. Integrated gain error
(Egitg)
h. Isolation
(ISL)
i.
(P1dB)
Output power at 1dB compression
2. Harmonic Measurements. From the Harmonic measurements the following data can be
deducted:
a. Output third order intercept point
(IP3O)
b. Second harmonic
(H2)
3. Noise Measurements. From the Noise measurements the following data can be deducted:
a. Noise Figure (NF)
4. Timing measurement. From the Timing measurements the following data can be deducted:
a. Gain step settling time (min/max) (ts(step)G)
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
18 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.1 Measurement definitions
11.1.1 Differential input and output impedance
|Zi| = |((1+S11(F)) / (1-S11(F)))| * 50Ohm,
with F = 70MHz … 220MHz
|Zo| = |((1+S22(F)) / (1-S22(F)))| * 50Ohm, with F = 70MHz … 220MHz
11.1.2 Absolute gain accuracy
Absolute gain accuracy (150Mhz) = 20log(|S21(150MHz)|) – 22dB (=typical max gain)
11.1.3 Gain flatness
Gain flatness (F) = Max (Gain(F + ½ Fd … F – ½ Fd)) – Min (Gain(F + ½ Fd … F – ½ Fd))
with Gain(F) = 20*log(|S21(F)|)
11.1.4 Differential gain errors
Differential gain error = max | Gain( x ) – Gain ( x-1 ) –1dB |, with
Gain(x) = 20log(|S21(x)|) measured at 150 MHz and x = gain setting (1…24)
Differential gain error (upper 12dB) = | Gain( 0 ) – Gain ( 12 ) –12dB |, with
Gain(x) = 20log(|S21(x)|) measured at 150 MHz and x = gain setting
Differential gain error (full range) = | Gain( 0 ) – Gain ( 24 ) –24dB |, with
Gain(x) = 20log(|S21(x)|) measured at 150 MHz and x = gain setting
11.1.5 Differential phase errors
Differential phase error (consecutive gain steps) = arg(S21(x)) – arg(S21(x-1))
with x = gain setting (0…24), measured 150 MHz
Differential phase error (any two steps upper 12dB) = max(arg(S21(x;x-12))) –
min(arg(S21(x;x-12)))
with x = gain setting, measured at 150 MHz
Differential phase error (any two steps) = max(arg(S21(x))) – min(arg(S21(x)))
with x = gain setting (0…24), measured at 150 MHz
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
19 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.1.6 OPI3
OIP3low = Po(F1)+ ½ (Po(F1)-Po(F1-2MHz)), with F1=150 MHz F2 = F1+2MHz
OIP3high = Po(F2)+ ½ (Po(F2)-Po(F2-2MHz)), with F1=150 MHz F2 = F1+2MHz
OIP3 = Min (OIP3low, OIP3high)
11.1.7 H2
nd
2 order harm (F) = 20log(|S21(2*F)|) – 20log((|S21(F)|)
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
20 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.2 S-parameter measurements
The S-parameters (and the above mentioned derivative measurements) are measured with
a full two-port calibrated network analyzer; over the frequency range 70 – 220 MHz. Also
the output power compression point (P1dB) has been measured with the network analyzer. In
the latter case, a calibrated power sweep has been performed, in order to obtain the P1dB.
All gain and phase measurements have been performed with a constant output power of +5
dBm, meaning that for every 1 dB increase of attenuation, the input power also have to
increase by +1 dBm.
The non-used port's of the dual VGA (channel A or B) has been terminated with a 50-Ohm
load.
The isolation measurement (ISL) have been performed by injecting the signal to the input of
channel A, and measuring the response at the output of channel B (and vice versa), with the
remaining input and output terminated with 50 Ohm.
11.3 Harmonic measurements.
The harmonic measurements (OIP2, OIP3 and H2) have been measured with a set-up, as
described in Fig. 8.
POWER SUPPLY
SIGNAL GENERATOR
Low Pass Filter (LPF)
ISOLATOR
POWER COMBINER
SPECTRUM ANALYZER
DUT
SIGNAL GENERATOR
Low Pass Filter (LPF)
ISOLATOR
Dual VGA (Ch. A or B)
Fig. 8 Harmonic measurement set-up
A low-pass filter at the output of the signal generators guaranties suppression of the H2
generated by the generator itself.
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
21 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.4 Noise Figure measurements
The Noise Figure (NF) has been measured with a noise source (Excess Noise Ratio
ENR=15.3 dB), in combination with a spectrum analyzer with a noise measurement option.
(See Fig.9)
POWER SUPPLY
SPECTRUM ANALYZER
including NOISE OPTION
NOISE SOURCE
DUT
ENR
Dual VGA (Ch. A or B)
Fig. 9 Noise Figure Measurements
11.5 Timing Measurement.
In order to determine the gain step settling time, the set-up as shown in Fig. 10 has been
used. A pulse generator (preferably a pulse generator that can supply the proper logic
levels) is connected to the disable/enable pin of the EVB. The input (Pin_A or Pin_B) is
connected to a signal generator (or network analyzer ) to supply the RF input signal. The
response (Pout_A or Pout_B) is measured with a digital sampling scope, triggered by the
pulse generator. The 50-Ohm input of the sampling scope is used, in order to terminate the
output of the dual VGA properly.
With the pulse generator, the gain settings are switch from minimum (00000) to maximum
(11000) attenuation.
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
22 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
Pulse generator
POWER SUPPLY
Digital Sampling Oscilloscope
Signal Generator
trigger
DUT
50 Ohm input
Dual VGA (Ch. A or B)
Fig. 10 Timing measurements
11.6 Measurement results
The section following below shows performance measurements of the BGA7350 EVB in singleended operations.
The EVB has been measured under the following conditions:
• Measurement data corrected for input-and output transformer losses
− Input transformer; losses 0.55 dB, transformer ratio 1:3
− Output transformer; losses 0.6 dB, transformer ratio 1:4
• EVB optimized for 150 MHz operation (other frequency ranges can be easily optimized by
changing L1 .. L4, see also circuit diagram.
• 5V supply
• 25 deg. Ambient temperature
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
23 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.1 Gain as function of frequency and attenuator range
Note: every gain step measured @Pout= 5dBm
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
24 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.2 Phase of S21 as function of frequency and attenuator range
Note: every gain step measured @Pout= 5dBm
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
25 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.3 S-parameters; S12
Note: every gain step measured @Pout= 5dBm
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
26 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.4 S-parameters; S11
Note: every gain step measured @Pout= 5dBm
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
27 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.5 S-parameters; S22
Note: every gain step measured @Pout= 5dBm
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
28 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.6 P1dB over first 5 gain steps
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
29 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.7 Gain Flatness @maximum gain
∆Gp=0.04 dB
∆Gp=0.04 dB over operating frequency band
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
30 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.8 Noise Figure versus gain settings
Fmin=6.2 dB (@minimum attenuation, noise step = 0.8dB/dB
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
31 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.9 Harmonic Distortion (HD2) versus gain steps
Note: Pout=+5 dBm for every gain step
Freq_in=75 MHz
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
32 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.10 OIP3 over first 5 gain steps
Note: Pout per tone =+2 dBm
Freq1=150 MHz ; Freq2= 152 MHz
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
33 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
11.6.11 Summary of the gain errors
Measurement
Temperature
Power supply voltage
Power supply current
Standby current
Absolute gain
Differential gain error per 1dB consecutive steps
Integrated gain error upper 12dB
Integrated gain error full range
Gain flatness over 30MHz bandwidth at maximum gain
Gain flatness over 30MHz bandwidth at minimum gain
Maximum gain flatness over 30MHz
Minimum gain flatness over 30MHz
Unit
C
V
mA
mA
dB
|dB|
dB
dB
dB
dB
dB
dB
Value
25 deg
5
122.3
2.61
18.61
0.10
0.05
-0.18
0.04
0.08
0.03
0.16
Conditions
Definition
Maximum supply current for all gain steps
Maximum standby current (for all gain steps)
Gain measured at F=140MHz, imcluding transformer losses
Measured at F=150MHz
Measured at F=150MHz
Measured at F=150MHz
pk-pk over 30MHz bandwidth at gain=0
pk-pk over 30MHz bandwidth at gain=24
Maximum flatness over 30MHz for all gain steps
Minimum flatness over 30MHz for all gain steps
11.6.12 Isolation (between channel A and channel B)
Gain settings @170 MHz
min
max
isolation [dB]
-59.8
-60
Measured @Pout=5dBm for both min and max gain
11.6.13 Impedance summary
Measurement
Maximum input impedance (BW=30 all gainsteps)
Minimum input impedance (BW=30 all gainsteps)
Maximum output impedance (BW=30 all gainsteps)
Minimum output impedance (BW=30 all gainsteps)
Maximum input impedance (BW=30 all gainsteps)
Minimum input impedance (BW=30 all gainsteps)
Maximum output impedance (BW=30 all gainsteps)
Minimum output impedance (BW=30 all gainsteps)
UM10608
User manual
Unit
|Ohm|
|Ohm|
|Ohm|
|Ohm|
Ohm
Ohm
Ohm
Ohm
Value
54.5
45.4
53.6
45.5
54.3
45.3
49.5
44.5
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
Conditions
Maximum absolute value measured over 30MHz bandwidth, for all gain steps
Minimum absolute value measured over 30MHz bandwidth, for all gain steps
Maximum absolute value measured over 30MHz bandwidth, for all gain steps
Minimum absolute value measured over 30MHz bandwidth, for all gain steps
Maximum real value measured over 30MHz bandwidth, for all gain steps
Minimum real value measured over 30MHz bandwidth, for all gain steps
Maximum real value measured over 30MHz bandwidth, for all gain steps
Minimum real value measured over 30MHz bandwidth, for all gain steps
© NXP B.V. 2012. All rights reserved.
34 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
12. Balun Characterization
In order to determine the BGA7350 performance only, the input-and output balun characteristics (losses) must be determined for
correction. This has been done by measuring the baluns (both input and output) back-to-back, and assuming that both
transformers are identical, the measured losses can be divided by two, to determine the losses per balun.
The measurements have been performed on the (calibration) boards, as described below)
12.1 Calibration EVB schematics
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
35 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
12.2 Calibration EVB layout
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
36 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
12.3 Calibration EVB picture
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
37 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
12.4 Calibration measurement results
Input Balun, back-to-back
Output Balun, back-to back
The losses of the input balun is about 0.55 dB
The losses of the output balun is about 0.6 dB
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
38 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
13. Legal information
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
13.2 Disclaimers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
13.1 Definitions
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express,
implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire
risk as to the quality, or arising out of the use or performance, of this product
remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be
liable to customer for any special, indirect, consequential, punitive or
incidental damages (including without limitation damages for loss of
business, business interruption, loss of use, loss of data or information, and
the like) arising out the use of or inability to use the product, whether or not
based on tort (including negligence), strict liability, breach of contract, breach
of warranty or any other theory, even if advised of the possibility of such
damages.
Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by
customer for the product or five dollars (US$5.00). The foregoing limitations,
exclusions and disclaimers shall apply to the maximum extent permitted by
applicable law, even if any remedy fails of its essential purpose.
13.3 Licenses
Purchase of NXP <xxx> components
<License statement text>
13.4 Patents
Notice is herewith given that the subject device uses one or more of the
following patents and that each of these patents may have corresponding
patents in other jurisdictions.
<Patent ID> — owned by <Company name>
13.5 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are property of their respective owners.
<Name> — is a trademark of NXP B.V.
UM10608
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 14 November 2012
© NXP B.V. 2012. All rights reserved.
39 of 40
UM10608
NXP Semiconductors
BGA7350 performance at IF=150 MHz
14. Contents
1.
2.
2.1
2.2
2.3
3.
3.1
4.
5.
6.
7.
8.
9.
10.
10.1
10.2
10.2.1
10.3
10.3.1
10.3.2
11.
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
11.1.7
11.2
11.3
11.4
11.5
11.6
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
Introduction ......................................................... 3
Product Profile..................................................... 4
General description ............................................ 4
Features and benefits ........................................ 4
Applications ........................................................ 4
Pinning information ............................................ 5
Pin description.................................................... 6
Functional Diagram ............................................. 7
Gain control Range ............................................. 8
EVB circuit diagram ............................................ 9
Evaluation Board top layout ............................. 10
Evaluation board bottom layout....................... 11
Bill of Materials (BOM) ...................................... 12
Operation of the BGA7350 EVB ....................... 14
Applying bias .................................................... 14
Mode of operation ............................................ 15
Manual mode. .................................................. 15
Mode of operation ............................................ 16
Manual mode. .................................................. 16
‘Automatic’ mode.............................................. 17
Measurements ................................................... 18
Measurement definitions .................................. 19
Differential input and output impedance ........... 19
Absolute gain accuracy .................................... 19
Gain flatness .................................................... 19
Differential gain errors ...................................... 19
Differential phase errors ................................... 19
OPI3 ................................................................. 20
H2 .................................................................... 20
S-parameter measurements............................. 21
Harmonic measurements. ................................ 21
Noise Figure measurements ............................ 22
Timing Measurement. ...................................... 22
Measurement results ........................................ 23
Gain as function of frequency and attenuator
range ................................................................ 24
Phase of S21 as function of frequency and
attenuator range ............................................... 25
S-parameters; S12 ........................................... 26
S-parameters; S11 ........................................... 27
S-parameters; S22 ........................................... 28
P1dB over first 5 gain steps ............................. 29
Gain Flatness @maximum gain ....................... 30
Noise Figure versus gain settings .................... 31
11.6.9
Harmonic Distortion (HD2) versus gain steps...32
11.6.10 OIP3 over first 5 gain steps ..............................33
11.6.11 Summary of the gain errors ..............................34
11.6.12 Isolation (between channel A and channel B) ..34
11.6.13 Impedance summary ........................................34
12.
Balun Characterization......................................35
12.1
Calibration EVB schematics .............................35
12.2
Calibration EVB layout......................................36
12.3
Calibration EVB picture ....................................37
12.4
Calibration measurement results ......................38
13.
Legal information ..............................................39
13.1
Definitions.........................................................39
13.2
Disclaimers .......................................................39
13.3
Licenses ...........................................................39
13.4
Patents .............................................................39
13.5
Trademarks ......................................................39
14.
Contents .............................................................40
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in the section 'Legal information'.
© NXP B.V. 2012.
All rights reserved.
For more information, visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 November 2012
Document identifier: UM10608