SC2688 Datasheet

SC2688
Programmable Synchronous DC/DC
Converter, Dual LDO Controller
POWER MANAGEMENT
Description
Features
The SC2688 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of the circuitry necessary to implement three
DC/DC converters for powering advanced microprocessors
such as Pentium® III.
‹
‹
‹
‹
·Synchronous design, enables no heatsink solution
95% efficiency (switching section)
Designed for embedded Pentium® III requirements
1.5V, 2.5V short circuit protected linear controllers
Applications
The SC2688 switching section features latched drive output for enhanced noise immunity, pulse by pulse current
limiting and logic compatible shutdown. The SC2688
switching section operates at a fixed frequency of 140kHz,
providing an optimum compromise between size, efficiency
and cost in the intended application areas.
‹ Embedded Pentium® III microprocessor supplies.
The SC2688 linear sections are low dropout regulators
with short circuit protection, supplying 1.5V for GTL bus
and 2.5V for non-GTL I/O.
Typical Application Circuit
12V
+
5V
47uF
0.1uF
+
1500uF
10
x4
11
4
5
0.1uF
EN
12
16
14
15
3
BST
CS+
VCC
CS-
LDOEN
DH
EN
DL
AGND
FB
LDOV
PGND
GATE2
GATE1
LDOS2
LDOS1
7
0.1uF
6
0.1uF
2R2
8
2R2
10
13
1.00k
2.32k
VCC_CORE
1.9uH
5mOhm
9
1
+
2
0.1uF
SC2688S
3.3V
1500uF
x6
1k
+
1.5V
2.5V
330uF
+
330uF
Revision: March 25, 2004
+
330uF
1
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SC2688
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
VIN
-0.3 to +7
V
±1
V
-0.3 to +15
V
-1 to +15
V
VCC to AGND
PGND to AGND
BST to PGND
DH to PGND, DL to PGND (Note2)
Operating Temperature Range
TA
0 to +70
°C
Junction Temperature Range
TJ
0 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 Sec.
TLEAD
300
°C
Thermal Resistance Junction to Ambient
θJ A
80
°C/W
Thermal Impedance Junction to Case
θJ C
25
°C/W
Electrical Characteristics
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
1.238
1.250
1.263
V
7
V
15
mA
Switching Section
Output Voltage
IO = 2A in Application Circuit
Supply Voltage
VCC
Supply Current
VCC = 5.0V
8
Load Regulation
IO = 0.8A to 15A
1
%
±0.5
%
4.5
Line Regulation
Current Limit Voltage
60
70
85
mV
Oscillator Frequency
120
140
160
kHz
Oscillator Max Duty Cycle
90
95
%
Peak DH Sink/Source Current
BSTH - DH = 4.5V, DH- PGNDH = 3.3V
DH- PGNDH = 1.5V
1
100
A
mA
Peak DL Sink/Source Current
BSTL - DL = 4.5V, DL - PGNDL= 3.3V
DL- PGNDH = 1.5V
1
100
A
mA
Gain (AOL)
VOSENSE to VO
FB Input current
VFB = 1.25V
35
1
Dead Time
 2004 Semtech Corp.
40
2
100
dB
2
uA
ns
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SC2688
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = BST = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
5
mA
Linear Sections
Quiescent Current
LDOV = 12V
Output Voltage LDO1
2.493
2.525
2.556
V
Output Voltage LDO2
1.496
1.515
1.534
V
1.246
1.265
1.284
V
Reference Voltage
Gain (AOL)
Load Regulation
Iref < 100uA
LDOS (1,2) to GATE (1,2)
90
IO = 0 to 8A
0.3
%
0.3
%
1
1.5
kΩ
8.0
10
V
1.9
V
0.01
-200
1.0
-300
µA
µA
20
40
60
%
1
5
60
ms
0.5
4
30
ms
80
300
750
kΩ
Line Regulation
Output Impedance
VGATE = 6.5V
LDOV Undervoltage Lockout
6.5
LDOEN Threshold
1.3
LDOEN Sink Current
Overcurrent Trip Voltage
LDOEN = 3.3V
LDOEN = 0V
% of Vo set point
Power-up Output Short Circuit Immunity
Output Short Circuit Glitch Immunity
Gate Pulldown Impedance
GATE (1,2) -AGND;
VCC+BST=0V
VOSENSE Impedance
dB
10
kΩ
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) See Gate Resistor Selection recomendations.
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SC2688
POWER MANAGEMENT
Pin Configuration
Ordering Information
Device
TOP VIEW
GATE1
1
16
AGND
LDOS1
2
15
GATE2
LDOS2
3
14
LDOV
VCC
4
13
FB
LDOEN
5
12
EN
CS-
6
11
BST
CS+
7
10
DL
DH
8
9
(1)
SC2688STR
P ackag e
Linear
Voltage
Temp
Range (TJ)
SO-16
1.5V/2.5V
0° to 125°C
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
PGND
(16 Pin SOIC)
Pin Descriptions
Pin #
Pin Name
1
GATE1
Gate Drive Output LDO1
Pin Function
2
LDOS1
Sense Input for LDO1
3
LDOS2
Sense Input for LDO2
4
VCC
5
LDOEN
6
CS-
Current Sense Input (negative)
7
CS+
Current Sense Input (positive)
8
DH
9
PGND
Input Voltage
LDO Supply Monitor.
High Side Driver Output
Power Ground
10
DL
11
BST
Low Side Driver Output
Supply for Drivers
12
EN (1)
Logic low shuts down the converter, High or open for normal operation
13
FB
14
LDOV
+12V for LDO section
15
GATE2
Gate Drive Output LDO2
16
AGND
Small Signal Analog and Digital Ground
Switcher section feedback input
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
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SC2688
POWER MANAGEMENT
Block Diagram
CS-
VCC
CS+
EN
CURRENT
LIMIT
BST
+
70mV
REF
LEVEL SHIFT AND
HIGH SIDE DRIVE
+
FB
DH
-
-
ERROR
AMP
+
OSCILLATOR
AGND
R
Q
SHOOT-THRU
CONTROL
S
1.265V
REF
LDOEN
LDOS1
GATE1
2.5V FET
CONTROLLER
1.5V FET
CONTROLLER
SYNCHRONOUS
MOSFET DRIVE
DL
PGND
LDOV
 2004 Semtech Corp.
GATE2
5
LDOS2
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SC2688
POWER MANAGEMENT
Layout Guidelines
Careful attention to layout requirements are necessary for
successful implementation of the SC2688 PWM controller. High currents switching at 140kHz are present in the
application and their effect on ground plane voltage differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transitions in this connection and length is not so important,
however adding unnecessary impedance will reduce efficiency.
5V
12V IN
10
1
2
3
4
5
0.1uF
6
7
0.1uF
8
GATE1 AGND
LDOS1 GATE2
LDOS2
LDOV
VCC
FB
LDOEN
EN
CS-
BST
CS+
DL
DH
PGND
16
15
2.32k
Q1
Cin
14
1.00k
L
13
12
+
5mOhm
Vout
Q2
11
Cout
10
9
SC2688
Vo Lin1
3.3V
Heavy lines indicate
high current paths.
Q3
Cout Lin1
Cin Lin
Layout Diagram
SC2688
Vo Lin2
Q4
Cout Lin2
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SC2688
POWER MANAGEMENT
Layout Guidelines (Cont.)
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents
are supplied by Cout only, and connections between Cout
and the load must be short, wide copper areas to minimize inductance and resistance.
5) The SC2688 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. PGND should be returned to the ground plane
close to the package. The AGND pin should be connected
to the ground side of (one of) the output capacitor(s). If
this is not possible, the AGND pin may be connected to
the ground path between the Output Capacitor(s) and the
Cin, Q1, Q2 loop. Under no circumstances should AGND
be returned to a ground inside the Cin, Q1, Q2 loop.
6) Vcc for the SC2688 should be supplied from the 5V
supply through a 10Ω resistor, the Vcc pin should be
decoupled directly to AGND by a 0.1µF ceramic capacitor,
trace lengths should be as short as possible.
7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces running back to CS+ and CS- on the SC2688 should run parallel and close to each other. The 0.1µF capacitor should
be mounted as close to the CS+ and CS- pins as possible.
8) Ideally, the grounds for the two LDO sections should be
returned to the ground side of (one of) the output
capacitor(s).
5V
Currents in Power Section
+
Vout
+
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SC2688
POWER MANAGEMENT
Component Selection
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
R ESR ≤
and 0% duty cycle capability, so some allowance must be
made. Choosing an inductor value of 50 to 75% of the
calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped
across the ESR at a faster rate than the capacitor sags,
hence ensuring a good recovery from transient with no
additional excursions.
We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
Vt
It
Where
Vt = Maximum transient voltage excursion
It = Transient current step
ILRIPPLE =
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
Each Cap.
Technology
C
(µF)
ESR
(mΩ)
Qty.
Rqd. C
(µF)
POWER FETS - The FETs are chosen based on several
criteria, with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses.
ESR
(mΩ)
330
60
6
2000
10
OS-CON
330
25
3
990
8.3
1500
44
5
7500
8.3
Low ESR Aluminum
Ripple current allowance will define the minimum permitted inductor value.
Total
Low ESR Tantalum
a) Conduction losses are simply calculated as:
PCOND = IO2 ⋅ RDS(on) ⋅ δ
where
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
δ = duty cycle ≈
PSW = IO ⋅ VIN ⋅ 10 −2
or more generally,
PSW =
IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC
4
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
R ESR C
⋅ VA
It
where VA is the lesser of VO or (VIN − VO )
PRR = QRR ⋅ VIN ⋅ fOSC
The calculated maximum inductor value assumes 100%
 2004 Semtech Corp.
VO
VIN
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
The maximum inductor value may be calculated from:
L≤
VIN
4 ⋅ L ⋅ fOSC
To a first order approximation, it is convenient to only con-
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SC2688
POWER MANAGEMENT
Component Selection (Cont.)
sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp RDS(ON) to allow for temperature rise.
FET type
RDS(on) (mΩ)
PD (W)
Package
IRL34025
15
1.69
D2Pak
IRL2203
10.5
1.19
D2Pak
Si4410
20
2.26
S0-8
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra
output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size.
GATE RESISTOR SELECTION - The gate resistors for the
top and bottom switching FETs limit the peak gate current
and hence control the transition time. It is important to
control the off time transition of the top FET, it should be
fast to limit switching losses, but not so fast as to cause
excessive phase node oscillation below ground as this can
lead to current injection in the IC substrate and erratic
behaviour or latchup. The actual value should be determined in the application, with the final layout and FETs.
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined
by:
PCOND = IO2 ⋅ RDS( on) ⋅ (1 − δ)
For the example above:
FET type
RDS(on) (mΩ)
PD (W)
Package
IRL34025
15
1.33
D2Pak
IRL2203
10.5
0.93
D2Pak
Si4410
20
1.77
S0-8
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on the linear controllers is implemented by using the Rds(on) of the FETs. As output current increases, the regulation loop maintains the output
voltage by turning the FET on more and more. Eventually,
as the Rds(on) limit is reached, the FET will be unably to
turn on more fully, and output voltage will start to fall.
When the output voltage falls to approximately 40% of
nominal, the LDO controller is latched off, setting output
voltage to 0. Power must be cycled to reset the latch.
To prevent false latching due to capacitor inrush currents
or low supply rails, the current limit latch is initially disabled. It is enabled at a preset time (nominally 2ms) after
both the LDOV and LDOEN pins rise above their lockout
points.
To be most effective, the linear FET Rds(on) should not be
selected artificially low, the FET should be chosen so that,
at maximum required current, it is almost fully turned on.
If, for example, a linear supply of 1.5V at 4A is required
from a 3.3V ± 5% rail, max allowable Rds(on) would be.
Rds(on)max = (0.95*3.3-1.5)/4 » 400mΩ
To allow for temperature effects 200mΩ would be a suitable room temperature maximum, allowing a peak short
circuit current of approximately 15A for a short time before shutdown.
Each of the package types has a characteristic thermal
impedance. For the surface mount packages on double
sided FR4, 2 oz printed circuit board material, thermal
impedances of 40oC/W for the D2PAK and 80oC/W for the
SO-8 are readily achievable. The corresponding temperature rise is detailed below:
Temperature Rise (OC)
FET type
Top FET
Bottom FET
IRL34025
67.6
53.2
IRL2203
47.6
37.2
Si4410
180.8
141.6
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
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SC2688
POWER MANAGEMENT
Theory of Operation (Linear OCP)
The Linear controllers in the SC2688 have built in
Overcurrent Protection (OCP). An overcurrent is assumed
to have occured when the external FET is turned fully on
and the output currrent is RDS(ON) limited, this is detected
by the gate voltage going very high while the output voltage is below approximately 40% of it’s setpoint. To allow
for capacitor charging and very short overcurrent durations, the gate voltage is ramped very slowly upwards whenever the output voltage is below the OCP threshold. To
guarantee that the LDO output voltage is capable of reaching it’s setpoint, the gate drive is disabled until both LDOV
Undervoltage Lockout (UVLO) and LDOEN Threshold values are exceeded, ensuring that there is sufficient gate
drive capability and sufficient LDO input voltage capability. A block diagram of one LDO controller is shown below.
12V
3.3V
LDOV
LDOEN
Gate
1.4V/us
Vout
1V/ms
Vout/2
Time
Startup with no short circuit
If at some later time, a short circuit is applied to the output, the GATEx voltage will ramp up quickly as Vout falls to
try and maintain regulation. Once Vout has fallen to the
OCP threshold, switch S1 will open and the gate will continue ramping at the 1V/ms rate. If the short is not removed before the GATEx output reaches approximately
LDOV - 0.7V, the GATEx pin will be latched low, disabling
the LDO
+
-
10pF
C RAMP
Short
applied
LDOV
-
gm
LDOV-0.7V
1V/ms
GATEx
+
Gate
+
VREF
1.3V
R2
LDOSx
Vout
1.26V
SWITCH CLOSED
ON LOW
R
-
S1
Vout
+
Vout/2
+
10nA
R
R1
Time
14uA
AGND
Short circuit after startup
RESET BY
LDOV LOW
S
Q
+
-
R
LDOV-0.7V
If the LDO tries to start into a short, the gate ramps at the
1V/ms rate to LDOV - 0.7V, where the GATEx pin will be
latched low.
During a normal start-up, once LDOV and LDOEN have
reached their thresholds, the GATEx pin is released and
CRAMP is charged by 10nA causing the GATEx voltage to
ramp at 10nA/10pF = 1V/ms. Once the GATEx output has
ramped to the external FET threshold, Vout starts to ramp
up, following GATEx. When Vout reaches the OCP threshold, approximately 40% of setpoint, switch S1 is closed
and GATEx ramps up at a much faster rate, followed by
Vout, until Vout reaches setpoint and the loop settles into
steady state regulation.
 2004 Semtech Corp.
LDOV-0.7V
Gate
1V/ms
Time
Startup into short circuit
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SC2688
POWER MANAGEMENT
Typical Characteristics
Typical Ripple, Vo=2.0V, Io=10A
Typical Efficiency (Switching section)
96%
PIN Descriptions
Efficiency (%)
92%
88%
84%
Vo=2.8V
Vo=2.0V
Vo=2.5V
80%
76%
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
Io (Amps)
Transient Response Vo=2.4V, Io=300mA to 15A
 2004 Semtech Corp.
2.5V Linear Short circuit output response
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SC2688
POWER MANAGEMENT
Outline Drawing - SO-16
Land Pattern - SO-16
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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