SEMTECH SC1185ACSW.TR

SC1185 & SC1185A
Programmable Synchronous DC/DC
Converter, Dual LDO Controller
POWER MANAGEMENT
Description
Features
The SC1185 combines a synchronous voltage mode controller with two low-dropout linear regulators providing
most of the circuitry necessary to implement three DC/
DC converters for powering advanced microprocessors
such as Pentium® II .
Synchronous design, enables no heatsink solution
95% efficiency (switching section)
5 bit DAC for output programmability
On chip power good function
Designed for Intel Pentium® ll requirements
1.5V, 2.5V @ 1.25% for linear section
1.265V ± 1.5% Reference available
24-lead SO package. Lead free option available.
Lead free product is fully WEEE and RoHS
compliant.
The SC1185 switching section features an integrated 5
bit D/A converter, pulse by pulse current limiting, integrated power good signaling, and logic compatible shutdown. The SC1185 switching section operates at a fixed
frequency of 140kHz, providing an optimum compromise
between size, efficiency and cost in the intended application areas. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in
100mV increments and 1.30V to 2.05V in 50mV increments with no external components.
Applications
Pentium® ll microprocessor supplies
Flexible motherboards
1.3V to 3.5V microprocessor supplies
Programmable triple power supplies
The SC1185 linear sections are low dropout regulators
supplying 1.5V for GTL bus and 2.5V for non-GTL I/O.
The Reference voltage is made available for external linear regulators.
Typical Application Circuit
12V
5V
+
10
+
4.7uF
0.1uF
1500uF
x4
0.1uF
5
PWRGOOD
7
VID0
22
VID1
21
VID2
20
VID3
19
VID4
18
EN
16
1
23
24
4
VCC
CS+
PWRGOOD
CS-
VID0
9
8
0.1uF
17
VOSENSE
VID1
BSTH
VID2
DH
VID3
BSTL
VID4
DL
EN
PGNDH
AGND
PGNDL
LDOV
REF
GATE2
GATE1
LDOS2
LDOS1
IRLR3103N
1.00k
15
5mOhm
2R2
11
14
2.32k
IRLR3103N
VCC_CORE
1.9uH
13
+
2R2
10
12
1k
6
12V
3.3V
x6
3
3.3V
3
2
8
+
-
1
IRLR024N
LM358
VLIN3
+
1.5V
1500uF
2
SC1185CS
330uF
0.1uF
4
2.5V
IRLR024N
IRLR024N
+
330uF
+
330uF
Revision: July 28, 2005
+
330uF
1
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SC1185 & SC1185A
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum
Units
VIN
-0.3 to +7
V
+1
V
-0.3 to +15
V
VCC to GND
PGND to GND
BST to GND
Operating Temperature Range
TA
0 to +70
°C
Junction Temperature Range
TJ
0 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 Sec.
TL
300
°C
Thermal Impedance Junction to Ambient
θJA
80
°C/W
Thermal Impedance Junction to Case
θJC
25
°C/W
Electrical Characteristics
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
Switching Section
Output Voltage
IO = 2A in Application Circuit
See Output Voltage Table
Supply Voltage
VCC
Supply Current
VCC = 5.0V
8
Load Regulation
IO = 0.8A to 15A
1
%
+0.15
%
4.5
Line Regulation
7
V
15
mA
Current Limit Voltage
60
70
85
mV
Oscillator Frequency
125
140
160
kHz
Oscillator Max Duty Cycle
90
95
%
Peak DH Sink/Source Current
BSTH - DH = 4.5V,
DH - PGNDH = 3.1V
DH - PGNDH = 1.5v
1
100
A
mA
Peak DL Sink/Source Current
BSTL - DL = 4.5V,
DL - PGNDL = 3.1V
DL - PGNDL = 1.5V
1
100
A
mA
Gain (AOL)
VOSENSE to VO
VID Source Current
VIDx < 2.4V
VID Leakage
VIDx < 2.4V
1
35
dB
10
µA
Power good threshold voltage
88
100
Dead time
40
100
 2005 Semtech Corp.
2
10
µA
112
%
ns
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SC1185 & SC1185A
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
Parameter
Conditions
Min
Typ
Max
Units
5
mA
Linear Sections
Quiescent current
LDOV = 12V
Output Voltage LDO1
2.469
2.500
2.531
V
Output Voltage LDO2
1.481
1.500
1.519
V
1.246
1.265
1.284
V
Reference Voltage
Iref < 100µA
Gain (AOL)
LDOS (1, 2) to GATE (1, 2)
Load Regulation
IO = 0 to 8A
90
0.3
%
0.3
%
1
1.5
Ω
300
750
kΩ
Line Regulation
Output Impedance
VGATE = 6.5V
Gate Pulldown Impedance
GATE (1,2)-AGND; VCC=LDOV=OV
VOSENSE Impedance
80
dB
10
kΩ
NOTE:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
 2005 Semtech Corp.
3
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SC1185 & SC1185A
POWER MANAGEMENT
Pin Configuration
Ordering Information
TOP VIEW
Part Number
AGND
1
24
GATE2
GATE1
2
23
LDOV
LDOS1
3
22
VID0
LDOS2
4
21
VID1
VCC
5
20
VID2
REF
6
19
VID3
PWRGOOD
7
18
VID4
CS-
8
17
VOSENSE
CS+
9
16
EN
PGNDH
10
15
BSTH
DH
11
14
BSTL
PGNDL
12
13
DL
Linear
Voltage
Temp
Range (TJ)
SO-24
1.5V2.5V
0° to 125°C
SO-24
1.5V2.5V
0° to 125°C
(1)
SC1185CSW.TR
SC1185CSW.TRT(3)
SC1185ACSW.TR
SC1185ACSW.TRT(3)
Notes:
(1) Only available in tape and reel packaging. A reel contains
1000 devices.
(2) SC1185A provides improved output tolerance. See Output
Voltage Table.
(3). Lead free product. This product is fully WEEE and RoHS
compliant.
(24 Pin SOIC)
Pin Descriptions
Pin #
Pin Name
1
AGND
Small Signal Analog and Digital Ground
2
GATE1
Gate Drive Output LDO1
3
LDOS1
Sense Input for LDO1
4
LSOS2
5
VCC
6
REF
7
P ackag e
Pin Function
Sense Input for LDO2
Input Voltage
Buffered Reference Voltge output
PWRGOOD
(1)
Open collector logic output, high if VO within 10% of setpoint
8
CS-
Current Sense Input (negative)
9
CS+
Current Sense Input (positive)
10
PGNDH
11
DH
12
PGNDL
Power Ground for High Side Switch
High Side Driver Output
Power Ground for Low Side Swtch
13
DL
14
BSTL
Low side Driver Output
Supply for Low Side Driver
15
BSTH
Supply for High Side Driver
16
EN
Logic low shuts down the converter. High or open for normal operation.
(1)
17
VOSENSE
18
VID4 (1)
Programming Input (MSB)
Top end of internal feedback chain
19
VID3 (1)
Programming Input
20
VID2
(1)
Programming Input
21
VID1
(1)
Programming Input
(1)
Programming Input (LSB)
22
VID0
23
LDOV
+12V for LDO section
24
GATE2
Gate Drive Output LDO2
Note:
(1) All logic level inputs and outputs are open collector TTL compatible.
 2005 Semtech Corp.
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SC1185 & SC1185A
POWER MANAGEMENT
Block Diagram
CS-
CS+
VCC
EN
CURRENT LIMIT
REF
BSTH
-
70mV
+
VID4
VID3
VID2
LEVEL SHIFT
AND HIGH SIDE
MOSFET DRIVE
D/A
R
VID1
PGNDH
Q
OSCILLATOR
VID0
S
SHOOT-THRU
CONTROL
VOSENSE
-
OPEN
COLLECTORS
PWRGOOD
DH
BSTL
+
+
+
-
-
ERROR
AMP
SYNCHRONOUS
MOSFET DRIVE
+
DL
-
AGND
LDOS1
GATE1
2.5V FET
CONTROLLER
PGNDL
1.5V FET
CONTROLLER
1.265V
REF
AGND
LDOV
 2005 Semtech Corp.
REF
5
GATE2 LDOS2 AGND
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SC1185 & SC1185A
POWER MANAGEMENT
Output Voltage Table
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV; = 0°C < Tj < 85°C
Parameter
Standard
Vid
43210
Output Voltage
 2005 Semtech Corp.
Min
Typ
"A" Version
Max
Min
Typ
Max
Units
V
01111
1.277
1.300
1.323
1.287
1.300
1.313
01110
1.326
1.350
1.374
1.337
1.350
1.364
01101
1.375
1.400
1.425
1.386
1.400
1.414
01100
1.424
1.450
1.476
1.436
1.450
1.465
01011
1.478
1.500
1.523
1.485
1.500
1.515
01010
1.527
1.550
1.573
1.535
1.550
1.566
01001
1.576
1.600
1.624
1.584
1.600
1.616
01000
1.625
1.650
1.675
1.634
1.650
1.667
00111
1.675
1.700
1.726
1.683
1.700
1.717
00110
1.724
1.750
1.818
1.733
1.750
1.768
00101
1.782
1.800
1.869
1.782
1.800
1.818
00100
1.832
1.850
1.919
1.832
1.850
1.869
00011
1.881
1.900
1.970
1.881
1.900
1.919
00010
1.931
1.950
2.020
1.931
1.950
1.970
00001
1.980
2.000
2.020
1.980
2.000
2.020
00000
2.030
2.050
2.071
2.030
2.050
2.071
11111
1.970
2.000
2.030
1.970
2.000
2.030
11110
2.069
2.100
2.132
2.069
2.100
2.132
11101
2.167
2.200
2.233
2.167
2.200
2.233
11100
2.266
2.300
2.335
2.266
2.300
2.335
11011
2.364
2.400
2.436
2.364
2.400
2.436
11010
2.463
2.500
2.538
2.463
2.500
2.538
11001
2.561
2.600
2.639
2.561
2.600
2.639
11000
2.660
2.700
2.741
2.660
2.700
2.741
10111
2.758
2.800
2.842
2.758
2.800
2.842
10110
2.842
2.900
58
2.842
2.900
2.958
10101
2.940
3.000
3.060
2.940
3.000
3.060
10100
3.038
3.100
3.162
3.038
3.100
3.162
10011
3.136
3.200
3.264
3.136
3.200
3.264
10010
3.234
3.300
3.366
3.234
3.300
3.366
10001
3.332
3.400
3.468
3.332
3.400
3.468
10000
3.430
3.500
3.570
3.430
3.500
3.570
6
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
Careful attention to layout requirements are necessary for
successful implementation of the SC1185 PWM controller. High currents switching at 140kHz are present in the
application and their effect on ground plane voltage differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bottom FET ground.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transitions in this connection and length is not so important,
however adding unnecessary impedance will reduce efficiency.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
12V IN
5V
10
1
2
3
4
0.1uF
5
6
0.1uF
7
8
9
10
11
12
AGND
GATE2
GATE1
LDOV
LDOS1
VID0
LDOS2
VID1
VCC
VID2
REF
VID3
PWRGOOD
VID4
CS-
VOSENSE
CS+
EN
PGNDH
BSTH
DH
BSTL
PGNDL
24
23
2.32k
22
21
Q1
Cin
+
1.00k
20
5mOhm
Vout
19
L
18
+
Q2
Cout
17
16
15
14
13
DL
SC1185
Heavy lines indicate
3.3V
Vo Lin1
Q3
Cout Lin1
Cin Lin
high current paths.
+
+
Layout Diagram
SC1185(A)
Vo Lin2
Q4
+
Cout Lin2
 2005 Semtech Corp.
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents are supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
supply through a 10Ω resistor, the Vcc pin should be
decoupled directly to AGND by a 0.1µF ceramic capacitor,
trace lengths should be as short as possible.
7) The Current Sense resistor and the divider across it
should form as small a loop as possible, the traces running back to CS+ and CS- on the SC1185 should run
parallel and close to each other. The 0.1µF capacitor should
be mounted as close to the CS+ and CS- pins as possible.
5) The SC1185 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. PGNDH and PGNDL should be returned to
the ground plane close to the package. The AGND pin
should be connected to the ground side of (one of) the
output capacitor(s). If this is not possible, the AGND pin
may be connected to the ground path between the Output
Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should AGND be returned to a ground inside the
Cin, Q1, Q2 loop.
8) Ideally, the grounds for the two LDO sections should be
returned to the ground side of (one of) the output
capacitor(s).
6) Vcc for the SC1185 should be supplied from the 5V
5V
+
Vout
+
Currents in various parts of the power section
 2005 Semtech Corp.
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
COMPONENT SELECTION
S WIT
CHING SECTION
WITCHING
OUTPUT CAP
ACIT
ORS - Selection begins with the most
CAPA
CITORS
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
R ESR ≤
The calculated maximum inductor value assumes 100%
and 0% duty cycle, so some allowance must be made.
Choosing an inductor value of 50 to 75% of the calculated
maximum will guarantee that the inductor current will ramp
fast enough to reduce the voltage dropped across the ESR
at a faster rate than the capacitor sags, hence ensuring a
good recovery from transient with no additional excursions.
We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced by
the inductor ripple current flowing in the output capacitor
ESR. Ripple current can be calculated from:
Vt
It
Where
Vt = Maximum transient voltage excursion
VIN
4 ⋅ L ⋅ fOSC
It = Transient current step
ILRIPPLE =
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three
available capacitor technologies.
Ripple current allowance will define the minimum permitted inductor value.
Each Cap.
Technology
C
(µF)
ESR
(mΩ)
Qty.
Rqd. C
(µF)
Total
ESR
(mΩ)
PO
WER FETS - The FETs are chosen based on several
POWER
criteria with probably the most important being power dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom
FET body diode recovery losses.
Low ESR Tantalum
330
60
6
2000
10
OS-CON
330
25
3
990
8.3
a) Conduction losses are simply calculated as:
1500
44
5
7500
8.3
PCOND = IO2 ⋅ RDS(on) ⋅ δ
Low ESR Aluminum
where
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
δ = duty cycle ≈
b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then:
INDUCT
OR - Having decided on a suitable type and value
INDUCTOR
of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
PSW = IO ⋅ VIN ⋅ 10 −2
or more generally,
PSW =
R ESR C
⋅ VA
It
PRR = QRR ⋅ VIN ⋅ fOSC
where VA is the lesser of VO or (VIN − VO )
 2005 Semtech Corp.
IO ⋅ VIN ⋅ ( t r + t f ) ⋅ fOSC
4
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
The maximum inductor value may be calculated from:
L≤
VO
VIN
To a first order approximation, it is convenient to only con9
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SC1185 & SC1185A
POWER MANAGEMENT
Layout Guidelines
sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be: Using 1.5X Room temp RDS(ON) to allow for
temperature rise.
FET type
RDS(on) (mΩ)
PD (W)
P a cka g e
IRL34025
15
1.69
D 2P a k
IRL2203
10.5
1.19
D 2P a k
S i 4410
20
2.26
S0-8
BO
TT
OM FET - Bottom FET losses are almost entirely due
BOTT
TTOM
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
position, power dissipation will be approximately halved
and temperature rise reduced by a factor of 4.
INPUT CAP
ACIT
ORS - since the RMS ripple current in the
CAPA
CITORS
input capacitors may be as high as 50% of the output
current, suitable capacitors must be chosen accordingly.
Also, during fast load transients, there may be restrictions
on input di/dt. These restrictions require useable energy
storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize
ripple rating for a given size.
PCOND = IO2 ⋅ RDS( on) ⋅ (1 − δ)
For the example above:
FET type
RDS(on) (mΩ)
PD (W)
Package
IRL34025
15
1.33
D2Pak
IRL2203
10.5
0.93
D2Pak
Si4410
20
1.77
S0-8
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W for
the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below:
Temperature rise (oC)
FET type
Top FET
Bottom FET
IRL34025
67.6
53.2
IRL2203
47.6
37.2
S i 4410
180.8
141.6
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each
 2005 Semtech Corp.
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SC1185 & SC1185A
POWER MANAGEMENT
Typical Characteristics
Typical Efficiency at Vo=3.5V
Typical Efficiency at Vo=2.8V
95%
95%
90%
85%
Efficiency
Efficiency
90%
80%
3.5V Std
3.5V Sync
3.5V Sync Lo Rds
75%
2
4
80%
2.8V Std
2.8V Sync
2.8V Sync Lo Rds
75%
70%
0
85%
6
8
10
12
14
70%
16
0
Io (Am ps)
Typical Efficiency at Vo=2.5V
6
8
10
12
14
16
Typical Efficiency at Vo=2.0V
95%
90%
90%
85%
85%
Efficiency
Efficiency
4
Io (Am ps)
95%
80%
2.5V Std
2.5V Sync
2.5V Sync Lo Rds
75%
2
80%
2.0V Std
2.0V Sync
2.0V Sync Lo Rds
75%
70%
70%
0
2
4
6
8
10
12
14
0
16
Typical Ripple, Vo=2.8V, Io=10A
 2005 Semtech Corp.
2
4
6
8
10
12
14
16
Io (Am ps)
Io (Amps)
Transient Response Vo=2.8V, Io=300mA to 10A
11
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 2005 Semtech Corp.
CON4
1
2
3
4
J16
12
3.3V
J22
+
+
6 5 4 3 2 1
EN
VID4
VID3
VID2
C11
330uF
J12
C12
330uF
C14
330uF
Q5
IRLR024N
+
C4
0.1uF
7
5
+
4
24
23
1
16
18
19
20
21
EMPTY
R3
10
VID1
S1
+
22
C3
1500uF
R1
VID0
C2
1500uF
+
12V
5V
J21
J1
+
DL
J24
2.5V
3
2
6
12
10
13
14
11
15
17
8
9
C16
330uF
LDOS1
GATE1
REF
PGNDL
PGNDH
1.5V
J23
DH
BSTL
J14
C15
330uF
CS-
CS+
BSTH
J13
SC1185CS
LDOS2
GATE2
LDOV
AGND
EN
VID4
VID3
VID2
VID1
VID0
+
VOSENSE
C19
1500uF
PWRGOOD
VCC
U3
C18
1500uF
C5
+
C17
330uF
Q6
+
J25
IRLR024N
C13
0.1uF
Q3
IRLR3103N
R9 2R2
Q1
IRLR3103
R6 2R2
0.1uF
J15
2
3
C26
4.7uF
R18
See Table
Q4
IRLR3103N
R10 2R2
Q2
IRLR3103N
R7 2R2
C1
0.1uF
+
4
-
8
+
12V
L1
1
See Table
R17
LM358
U2A
1.9uH
DROOP
mV/A
0
1
2
5
1
2
5
1
2
5
C24
330uF
R16
0
+
3.3V
+
C25
330uF
J20
VLIN3
J19
C8
R11
See Table 2
Q7
IRLR024N
R12
1k
R15
See Table 2
R15
(Ohm)
EMPTY
10
5
2
25
12.5
5
50
25
10
R5 2.32k
R11
(Ohm)
0
2.5
3.3
EMPTY
6.3
8.3
EMPTY
12.5
16.7
EMPTY
R8 5mOhm
R4 1.00k
OFFSET
mV/V
0
2
2
2
5
5
5
10
10
10
TABLE VALID FOR 1x5mOhm SENSE
RESISTOR
+
C9
+
C7
+
VLIN3
1.5V
1.8V
2.5V
R17
18.7
42.2
97.6
R18
100
100
100
1500uF 1500uF
1500uF 1500uF
C23 +
C21 +
C10
0.1uF
C20 +
C22 +
NO CPU
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
VOUT
VCC_CORE
VOUT VID
43210
1.30
11111
1.35
11110
1.40
11101
1.45
11100
1.50
11011
1.55
11010
1.60
11001
1.65
11000
1.70
10111
1.75
10110
1.80
10101
1.85
10100
1.90
10011
1.95
10010
2.00
10001
2.05
10000
1500uF 1500uF
1500uF 1500uF
+
C6
VID
43210
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
J18
SCOPE TP
CON4
1
2
3
4
J17
SC1185 & SC1185A
POWER MANAGEMENT
Typical Application Circuit
www.semtech.com
SC1185 & SC1185A
POWER MANAGEMENT
Materials List
Item
Qty.
Reference
Value
1
5
C1, C4, C5, C10, C13
0.1uF Ceramic
2
12
C2, C3, C6, C7, C8, C9, C18, C19, C20,
C21, C22, C23
1500uF
3
8
C11, C12, C14, C15, C16, C17, C24, C25
330uF
4
1
C26
4.7uF
5
1
L1
1.9uH
6
4
Q1, Q2, Q3, Q4
IRLR3103N
7
3
Q5, Q6, Q7
IRLR024N
8
1
R1
10
9
1
R3
EMPTY
10
1
R4
1.00k
11
1
R5
2.32k
12
4
R6, R7, R9, R10
2R2
13
1
R8
5mOhm
14
2
R15, R11
See Table
15
1
R12
1k
16
1
R16
0
17
2
R17, R18
See Table
18
1
U2
LM358
19
1
U3
SC1185CS
 2005 Semtech Corp.
13
Notes
Sanyo MV-GX or equiv. Low ESR
6 Turns 16AWG on MICROMETALS
T50-52D core
IRC OAR-1 Series
SEMTECH
www.semtech.com
SC1185 & SC1185A
POWER MANAGEMENT
Outline Drawing - SO - 24
A
D
e
N
DIM
A
A1
A2
b
c
D
E1
E
e
h
J
L
L1
N
R
01
aaa
bbb
ccc
2X E/2
E1
E
R
ccc C
1
2
2X N/2 TIPS
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
3
e/2
B
D
2.65
.104 2.35
.093
0.30
.012 0.10
.004
2.55
.100 2.05
.081
.012
.020 0.31
0.51
0.33
.013 0.20
.008
.602 .606 .610 15.30 15.40 15.50
.291 .295 .299 7.40 7.50 7.60
.406 BSC
10.30 BSC
.050 BSC
1.27 BSC
.010
.030 0.25
0.75
.020
.030 0.50
0.75
1.04
.041 0.40
.016
(1.04)
(.041)
24
24
.024
.035 0.60
0.90
8°
0°
8°
0°
0.10
.004
0.25
.010
0.33
.013
h
aaa C
A2 A
SEATING
PLANE
h
H
bxN
bbb
C
A1
C A-B D
c
GAGE
PLANE
J
0.25
SIDE VIEW
NOTES:
1.
SEE DETAIL
A
L
(L1)
DETAIL
01
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MS-013, VARIATION AD.
Land Pattern - SO - 24
X
DIM
(C)
G
Z
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.362)
.276
.050
.024
.087
.449
(9.20)
7.00
1.27
0.60
2.20
11.40
Y
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2. REFERENCE IPC-SM-782A, RLP NO. 307A.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012-8790
Phone: (805)498-2111 FAX (805)498-3804
 2005 Semtech Corp.
14
www.semtech.com