PIC16C76/77 → PIC16F76/77 Migration DEVICE MIGRATIONS This document is intended to describe the differences that are present when migrating from one device to the next. Table 1 and Table 2 list the data memory organization differences and the additional Special Function Registers, Table 3 lists the differences in functionality, and Table 4 through Table 11 list the differences in the electrical and timing specifications. Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. 2: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required. XT Oscillator Differences Please refer to the PIC16F73/74/76/77 Rev. B1 Silicon Errata for more information. Please refer to the difference in parameter D042A in Table 5. MCLR Functionality Differences The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 1, is suggested. FIGURE 1: RECOMMENDED MCLR CIRCUIT VDD PIC16F7X R1 1 kΩ (or greater) MCLR C1 0.1 µF (optional, not critical) TABLE 1: No. PIC16C76/77 → PIC16F76/77 DATA MEMORY DIFFERENCES SFR Differences from PIC16C76/77 Comment 1 PMADRH:PMADRL Implemented Address register pair 2 PMDATH:PMDATL Implemented Data register pair 3 PMCON1 Implemented Control register for memory access 4 INTCON Bit 2 (TMR0IF) and Bit 5 (TMR0IE) T0IF and T0IE in PIC16C76/77 2002 Microchip Technology Inc. DS33002A-page 1 TABLE 2: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(3) Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h(1 PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 103h(1) STATUS 0001 1xxx 000q quuu 104h(1) FSR xxxx xxxx uuuu uuuu 105h — 106h PORTB IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read — — xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — ---0 0000 ---0 0000 10Ah(1,2) PCLATH — — — GIE PEIE TMR0IE(5) Write Buffer for the upper 5 bits of the Program Counter 10Bh(1) INTCON 0000 000x 0000 000u 10Ch(5) PMDATL Data Register Low Byte xxxx xxxx uuuu uuuu 10Dh(5) PMADRL Address Register Low Byte xxxx xxxx uuuu uuuu 10Eh(5) PMDATH — — xxxx xxxx uuuu uuuu 10Fh(5) PMADRH — — xxxx xxxx uuuu uuuu INTE RBIE TMR0IF(5) INTF RBIF Data Register High Byte — Address Register High Byte Bank 3 180h(1) INDF 181h OPTION 182h(1) PCL 183h(1) STATUS 184h(1) FSR 185h — 186h TRISB 187h — 188h — 189h — Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address Pointer 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu Unimplemented — — 1111 1111 1111 1111 Unimplemented — — Unimplemented — — Unimplemented — — ---0 0000 ---0 0000 PORTB Data Direction Register Write Buffer for the upper 5 bits of the Program Counter 18Ah(1,2) PCLATH — — — 18Bh(1) INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u 18Ch(5) PMCON1 — — — — — — RD 1--- ---0 1--- ---0 — (4) 18Dh — Unimplemented 18Eh — — 18Fh — — Reserved, maintain clear 0000 0000 0000 0000 Reserved, maintain clear 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: These registers can be addressed from any bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 4: This bit always reads as a ‘1’. 5: Difference from PIC16C76/77. DS33002A-page 2 2002 Microchip Technology Inc. FIGURE 2: PIC16F76/77 BANK 2 & 3 REGISTER FILE MAP File Address File Address Indirect addr.(*) 100h Indirect addr.(*) 180h TMR0 101h OPTION 181h PCL 102h PCL 182h STATUS 103h STATUS 183h FSR 104h FSR 184h 105h PORTB 106h 185h TRISB 186h 107h 187h 108h 188h 109h 189h PCLATH 10Ah PCLATH 18Ah INTCON 10Bh INTCON 18Bh PMDATL(1) PMADRL(1) 10Ch PMCON1(1) 18Ch 10Dh 18Dh PMDATH(1) PMADRH(1) 10Eh 18Eh Bank 2 10Fh 18Fh Bank 3 Unimplemented data memory locations, read as ‘0’. * Not a physical register. Note 1: New registers implemented in PIC16F77. TABLE 3: PIC16C76/77 → PIC16F76/77 FUNCTIONAL DIFFERENCES No. Module Differences from PIC16C76/77 H/W S/W Prog 1 Program Memory Read The FLASH Program Memory is readable during normal operation — Yes — Legend: H/W S/W Prog. - Issues may exist with regard to the application circuit. Issues may exist with regard to the user program. Issues may exist with regard to programming. 2002 Microchip Technology Inc. DS33002A-page 3 READING PROGRAM MEMORY The FLASH Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP. There are five SFRs used to read the program and memory: • • • • • PMCON1 PMDATL PMDATH PMADRL PMADRH PMADR The address registers can address up to a maximum of 8K words of program FLASH. When selecting a program address value, the MSByte of the address is written to the PMADRH register and the LSByte is written to the PMADRL register. The upper MSbits of PMADRH must always be clear. The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration tables. REGISTER 1: When interfacing to the program memory block, the PMDATH:PMDATL registers form a two-byte word that holds 14-bit data for reads. The PMADRH:PMADRL registers form a two-byte word that holds the 13-bit address of the FLASH location being accessed. This device can have up to 8K words of program FLASH, with an address range from 0h to 1FFFh. The unused upper bits in both the PMDATH and PMADRH registers are not implemented and read as zeroes. PMCON1 Register PMCON1 is the control register for memory access. The control bit, RD, initiates read operations. This bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the read operation. PMCON1: PROGRAM MEMORY CONTROL REGISTER (ADDRESS 18Ch) R-1 U-0 U-0 U-0 U-x U-0 U-0 R/S-0 reserved — — — — — — RD bit 7 bit 0 bit 7 Reserved: Read as ‘1’ bit 6-1 Unimplemented: Read as ‘0’ bit 0 RD: Read Control bit 1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a FLASH read Legend: DS33002A-page 4 S = Settable bit U = Unimplemented bit, read as ‘0’ W = Writable bit R = Readable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2002 Microchip Technology Inc. CONFIGURATION WORD (ADDRESS 2007h)(1) REGISTER 2: U-1 — U-1 U-1 — — U-1 — U-1 — U-1 — U-1 — u-1 U-1 u-1 BOREN —(3) CP u-1 u-1 u-1 u-1 PWRTEN WDTEN F0SC1 F0SC0 bit13 bit0 bit 13-7 Unimplemented: Read as ‘1’ bit 6 BOREN: Brown-out Reset Enable bit(2) 1 = BOR enabled 0 = BOR disabled bit 5 Unimplemented: Read as ‘1’ bit 4 CP: FLASH Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected bit 3 PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh. 2: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. 3: Difference from PIC16C76/77. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 2002 Microchip Technology Inc. U = Unimplemented bit, read as ‘1’ u = Unchanged from programmed state DS33002A-page 5 PIC16C76/77 → PIC16F76/77 ELECTRICAL CHARACTERISTICS DIFFERENCES TABLE 4: Characteristic PIC16C7X Data Sheet PIC16F7X Data Sheet Units -0.3 to 7.5 -0.3 to 6.5 V Voltage on MCLR with respect to VSS (Note 1) 0 to 14 0 to 13.5 V Voltage on RA4 with respect to VSS 0 to 14 0 to 12 V Voltage on VDD with respect to VSS Note 1: It is not recommended to tie the MCLR pin directly to VDD (see Figure 1 in this document or Figure 12-5 in the PIC16F76/77 Data Sheet for the recommended MCLR circuit). PIC16C76/77 → PIC16F76/77 DC CHARACTERISTICS DIFFERENCES TABLE 5: Param Sym No. D001 Characteristic PIC16C7X Data Sheet Min Typ† Max Units 4.0 — 6.0 V Conditions PIC16F7X Data Sheet Conditions Min Typ† Max Units 4.0 — 5.5 V All configurations 3.65 4.0 4.35 V Same as PIC16C76/77 VDD Supply Voltage 4.5 — 5.5 V HS osc configuration D005 BVDD Brown-out Reset Voltage 3.7 4.0 4.3 V BODEN bit in configuration word enabled D010 IDD Supply Current (Notes 3, 5) — 2.7 5 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V, (Note 5) — 0.9 4 mA XT, RC osc configuration D013 — 10 20 mA HS osc configuration FOSC = 20 MHz, VDD = 5.5V — 5.2 15 mA HS osc configuration D015* ∆IBOR Brown-out Reset Current (Note 6) — 350 425 µA BOR enabled, VDD = 5.0V — 25 200 µA D001A XT, RC and LP osc configuration * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: For RC osc configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F76/77 be driven with external clock in RC mode. 2: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = External square wave, from-rail to-rail; all I/O pins tri-stated, pulled to VDD. MCLR = VDD; WDT enabled/disabled as specified. 4: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. 5: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS33002A-page 6 2002 Microchip Technology Inc. TABLE 5: Param Sym No. PIC16C76/77 → PIC16F76/77 DC CHARACTERISTICS DIFFERENCES (CONTINUED) Characteristic PIC16C7X Data Sheet Min Typ† Max Units — 10.5 42 µA D021x — 1.5 19 D021B — 2.5 D023* DIBOR Brown-out Reset Current (Note 5) — D020 IPD Power-down Reset Current (Note 4, 7) Conditions PIC16F7X Data Sheet Typ† Max Units VDD = 4.0V, WDT enabled, -40°C to +85°C — 5.0 42 µA Same as PIC16C76/77 µA VDD = 4.0V, WDT disabled, -40°C to 85°C — 0.1 19 µA VDD = 4.0V, WDT disabled, -40°C to +85°C 19 µA VDD = 4.0V, WDT disabled, -40°C to +125°C — 1.5 42 µA Same as PIC16C76/77 300 425 µA BOR Enabled, VDD = 5.0V — 25 200 µA Same as PIC16C76/77 — VDD V 1.6V — VDD V D042A VIH OSC1 (in XT and 0.7VDD LP mode) D130 EP Program FLASH Memory Endurance N/A N/A N/A N/A 100 1000 — D131 VPR Program FLASH Memory VDD for Read N/A N/A N/A N/A 4.0 — 5.5 V — — 14 V — — 12 V D150* VOD Open Drain High Voltage Conditions Min RA4 pin E/W 25°C at 5V RA4 pin * These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: For RC osc configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F76/77 be driven with external clock in RC mode. 2: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = External square wave, from-rail to-rail; all I/O pins tri-stated, pulled to VDD. MCLR = VDD; WDT enabled/disabled as specified. 4: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. 5: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 2002 Microchip Technology Inc. DS33002A-page 7 TABLE 6: Param No. D001 Sym VDD PIC16LC76/77 → PIC16LF76/77 DC CHARACTERISTICS DIFFERENCES Characteristic Supply Voltage PIC16C7X Data Sheet Min Typ† Max Units 2.5 — 6.0 V Conditions LP, XT, RC osc configuration (DC - 4 MHz) Conditions Min Typ† Max Units 2.5 — 5.5 V A/D in use, -40°C - +85°C 2.0 — 5.5 V A/D not used, -40°C - +85°C 3.65 4.0 4.35 V Same as PIC16LC76/77 D005 BVDD Brown-out Reset Voltage 3.7 4.0 4.3 V D010 IDD Supply Current (Note 3, 4) — 2.0 3.8 mA XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V, (Note 5) — 0.4 2.0 mA Same as PIC16LC76/77 — 22.5 48 mA LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled — 25 48 µA Same as PIC16LC76/77 — 350 425 µA BOR enabled, VDD = 5.0V — 25 200 µA Same as PIC16LC76/77 — 7.5 30 µA VDD = 3.0V, WDT enabled, -40°C to +85°C — 2.0 30 µA Same as PIC16LC76/77 — 0.9 5 µA VDD = 3.0V, WDT disabled, -40°C to +85°C — 0.1 5 µA VDD = 3.0V, WDT disabled, -40°C to +85°C — 350 425 µA BOR enabled, VDD = 5.0V — 25 200 µA Same as PIC16LC76/77 D010A D015* ∆IBOR Brown-out Reset Current (Note 6) D020 IPD Power-down Current (Note 4, 7) D021A D023* ∆IBOR Brown-out Reset Current (Note 6) BODEN bit in configuration word enabled PIC16F7X Data Sheet Program FLASH Memory D130 EP Endurance N/A N/A N/A N/A 100 1000 — E/W D131 VPR VDD for Read N/A N/A N/A N/A 2.0 — 5.5 V D150 VOD Open Drain High Voltage — — 14 V — — 12 V * † Note 1: 2: 3: 4: 5: 6: 7: RA4 pin 25°C at 5V RA4 pin These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. For RC osc configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F76/77 be driven with external clock in RC mode. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = External square wave, from-rail to-rail; all I/O pins tri-stated, pulled to VDD. MCLR = VDD; WDT enabled/disabled as specified. Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. DS33002A-page 8 2002 Microchip Technology Inc. TABLE 7: Param No. Sym FOSC 1 TCY PIC16C76/77 → PIC16F76/77 EXTERNAL CLOCK TIMING REQUIREMENTS DIFFERENCES Characteristic External CLKI Frequency External CLKI Period PIC16C7X Data Sheet Min Typ† Max Units DC — 4 DC — 250 — Conditions PIC16F7X Data Sheet Conditions Min Typ† Max MHz XT and RC Osc mode DC — 1 MHz XT Osc mode 200 kHz DC — 32 kHz LP Osc mode — ns 1000 — — ns XT Osc mode LP osc mode XT and RC Osc mode Units † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. TABLE 8: Param No. Sym PIC16C76/77 → PIC16F76/77 CLKO AND I/O TIMING REQUIREMENTS DIFFERENCES Characteristic PIC16C7X Data Sheet Min Typ† Max Units Conditions PIC16F7X Data Sheet Min Typ† Max Units — 100 255 ns Conditions 17* TOSH2ioV OSC1↑ (Q1 cycle) to Port Out Valid — 50 150 ns 20* TioR Port Output Rise Time — — 80 ns PIC16LC7X — — 145 ns PIC16LF7X 21* TioF Port Output Fall Time — — 80 ns PIC16LC7X — — 145 ns PIC16LF7X * † These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 9: Param No. Sym 53* TCCR * † PIC16C76/77 → PIC16F76/77 CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) DIFFERENCES Characteristic CCP1 and CCP2 Output Rise Time PIC16C7X Data Sheet Min Typ† Max — 25 45 Units ns Conditions PIC16LC7X PIC16F7X Data Sheet Min Typ† Max Units — 25 50 ns Conditions PIC16LF7X These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. 2002 Microchip Technology Inc. DS33002A-page 9 TABLE 10: Param No. 78* 79* 80* PIC16C76/77 → PIC16F76/77 SPI MODE REQUIREMENTS DIFFERENCES Sym TscR TdoR PIC16C7X Data Sheet Characteristic Min Typ† Max Units SCK Output Rise Time (Master mode) PIC16LC7X — SDO Data Output Rise Time PIC16LC7X TscH2doV, SDO Data Output Valid TscL2doV after SCK Edge PIC16LC7X * † 10 25 Conditions PIC16F7X Data Sheet Min Typ† Max Units ns — 10 25 ns — — 50 ns PIC16LF7X — 25 50 ns PIC16LF7X — 25 50 ns PIC16LF7X — — 145 ns These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 11: PIC16C76/77 → PIC16F76/77 A/D CONVERTER CHARACTERISTICS DIFFERENCES PIC16C7X Data Sheet Param Sym Characteristic No. Min Typ† Max Units Conditions PIC16F7X Data Sheet Min Typ† Max Units Conditions 131 TCNV Conversion Time (not including S/H time) (Note 1) — 9.5 — TAD 9 — 9 TAD A20 VREF Reference Voltage 3.0 — VDD + 0.3 V 2.5 — VDD + 0.3 V 2.2 — VDD + 0.3 V 0°C to +125°C A50 IREF VREF Input Current (Note 1) 10 — 1000 µA During VAIN N/A acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see device data sheet. — ±5 µA During VAIN acquisition. — — 10 µA During A/D Conversion cycle. — 500 µA During A/D Conversion cycle. — -40°C to +125°C * † These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. DS33002A-page 10 2002 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. 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Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 China - Shenzhen Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-82350361 Fax: 86-755-82366086 China - Hong Kong SAR Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 10/18/02 DS33002A-page 12 2002 Microchip Technology Inc.