PIC16F73/74/76/77 PIC16F73/74/76/77 Rev. B1 Silicon/Data Sheet Errata The PIC16F73/74/76/77 Rev. B1 parts you have received conform functionally to the Device Data Sheet (DS30325B), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC16F73/74/76/77 silicon. 1. Module: Timer1 When Timer1 is running in Asynchronous mode and then disabled, data in the Timer1 register (TMR1) may become corrupted. Corruption occurs when the timer enable is turned off at the same instant that a ripple carry occurs in the timer module. 2. Module: CCP (Compare Mode) The output of the CCP module in Compare mode may become inverted when the mode of the module is changed from Compare/Clear on Match (CCPxM<3:0> = 1001) to Compare/Set on Match (CCPxM<3:0> = 1000). This may occur as a result of any operation that selectively clears bit CCPxM0, such as a BCF instruction. When this condition occurs, the output becomes inverted when the instruction is executed. It will remain inverted for all following compare operations until the module is reset. Revision C silicon will correct this issue. Work around Revision C silicon will correct this issue. Do not selectively clear bit CCPxM0 to select the Compare/Set on Match mode. Instead, clear the entire CCPxCON register, which resets the module. Follow this with an instruction to set CCPxM3 (CCPxCON<3>), which selects the Set on Match mode. Work around Date Codes that pertain to this issue: This issue only occurs in asynchronous operation. In synchronous operation, the relevant signals are latched with the CPU clock and the problem condition does not arise. When Timer1 is configured to operate as an asynchronous counter, care must be taken that there is no incoming pulse while the module is being turned off. If an incoming pulse arrives while Timer1 is being turned off, the value of register TMR1 may become corrupted. PIC16F73/74 0219 and earlier PIC16F76/77 0303 and earlier If an application requires that Timer1 be turned off, and if it is possible that Timer1 may receive an incoming pulse while being turned off, synchronize the external clock first by clearing the T1SYNC bit of register T1CON (T1CON<2>). Please note, however, that this may cause Timer1 to miss up to one count. Date Codes that pertain to this issue: PIC16F73/74 0219 and earlier PIC16F76/77 0303 and earlier 2003 Microchip Technology Inc. DS80099G-page 1 PIC16F73/74/76/77 3. Module: Oscillator (HS mode) When resonators above 2 MHz are used, the HS mode oscillator is required to ensure reliable operation. HS mode oscillator drive at frequencies from 2 MHz to 4 MHz is often excessive, resulting in the amplitude of the oscillator waveform exceeding VDD and VSS. In such cases, the waveform may experience distortion as ESD protection devices begin to operate on the OSC1 and OSC2 pins. This distortion appears as a non-sinusoidal waveform or clipping, and can generate substantial harmonics that may create excessive noise in the application. FIGURE 1: C1 The gain of the oscillator should be reduced by inserting a series resistance between the OSC2 pin and the resonator/capacitor as shown in the data sheet (see Figure 1). The value of the series resistance is dependant on VDD, resonator frequency, and temperature; however, 330 ohms has been used as a good starting point for evaluation. OSC1 OSC2 Rs To Internal Logic RF XTAL Revision C silicon will correct this issue. Work around CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) SLEEP PIC16F7X C2 Date Codes that pertain to this issue: PIC16F73/74 0219 and earlier PIC16F76/77 0303 and earlier This change will not affect operation of future revisions of silicon as long as HS mode is selected. Note: This issue applies only to resonators above 2 MHz in Revision B silicon. No issues are known to exist with crystals at any frequency using XT Oscillator mode. DS80099G-page 2 2003 Microchip Technology Inc. PIC16F73/74/76/77 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS30325B), the following clarifications and corrections should be noted. 1. Module: Core The typical and maximum supply currents (parameter D010A) specified for extended voltage devices have been changed. The IDD specifications differ from the Device Data Sheet only for devices operating at a VDD of 3.0V and a FOSC of 32 kHz with the WDT disabled. The changes in the specification are shown in bold in Table 1. Work around None. Date Codes that pertain to this issue: All. TABLE 1: Param Sym. No. D010A IDD DC SPECIFICATION CHANGES FROM DATA SHEET Characteristic/ Device Supply Current PIC16LF73/74/76/77 2003 Microchip Technology Inc. New Specification Data Sheet Specification Min Typ Max Min Typ Max — 25 48 — 20 48 Units Notes µA LP osc configuration, FOSC = 32 kHz, VDD = 3.0V, WDT disabled DS80099G-page 3 PIC16F73/74/76/77 2. Module: Pinout Correction The MLF (now known as QFN) package pinout locations for pins RA4 and RA5 were incorrectly stated in Table 1-2 of the Device Data Sheet. The correct pinout locations are indicated in bold in Table 2. TABLE 2: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION DIP SSOP SOIC Pin# MLF Pin# RA4/T0CKI RA4 T0CKI 6 3 RA5/SS/AN4 RA5 SS AN4 7 Pin Name I/O/P Type Buffer Type Description . . . ST I/O I Digital I/O – Open drain when configured as output. Timer0 external clock input. TTL 4 I/O I I Digital I/O. SPI slave select input. Analog input 4. . . . Legend: I = input — = Not used DS80099G-page 4 O = output TTL = TTL input I/O = input/output ST = Schmitt Trigger input P = power 2003 Microchip Technology Inc. PIC16F73/74/76/77 3. Module: Pinout Correction The PIC16F73/74/76/77 device family does not offer low-voltage programming. The Device Data Sheet incorrectly lists RB3 as providing the PGM function required for low-voltage programming. References to the PGM function in Tables 1-2 and Table 1-3 of the Device Data Sheet have been removed. Table 3 and Table 4 show the corrections for the PIC16F73/76 and PIC16F74/77 devices respectively, The text shown in bold has been removed. TABLE 3: Pin Name . . . RB3/PGM RB3 PGM . . . TABLE 4: Pin Name . . . RB3/PGM RB3 PGM . . . References to the PGM function in the Pin Diagrams on pages 2 and 3, and Figures 1-1 and 1-2 (pages 6 and 7) in the Data Sheet have also been removed. A reference to the PGM function listed in the Data Sheet Index has also been removed. PIC16F73 AND PIC16F76 PINOUT DESCRIPTION DIP SSOP SOIC Pin# MLF Pin# 24 21 I/O/P Type Buffer Type Description TTL I/O I/O Digital I/O. Low voltage ICSP programming enable pin. PIC16F74 AND PIC16F77 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFP Pin# 36 39 11 2003 Microchip Technology Inc. I/O/P Type Buffer Type Description TTL I/O I/O Digital I/O. Low voltage ICSP programming enable pin. DS80099G-page 5 PIC16F73/74/76/77 4. Module: Packaging (Pinout and Product Identification) 3. Section 17.1 (“Package Marking Information”) is amended to include a marking template and example for 44-pin QFN devices. These are shown in Figure 3. 4. Section 17.2 (“Package Details”) is amended to include the mechanical drawing of the 44-pin QFN package, following the existing drawings. This is shown in Figure 4. 5. In the “PIC16F7X Product Identification System” (page 171), the “ML” line item in the “Package” options section should now read (change in bold): PIC16F74 and PIC16F77 devices are now offered in a 44-pin, micro lead frame package (commonly known as “QFN”). This provides near chip scale package size. This option is in addition to the 28-pin QFN packages already available for the PIC16F73 and PIC16F76 devices. The 44-pin QFN package has been added to the product line since the original publication of the Device Data Sheet. The addition of this option requires the following additions to the Device Data Sheet (DS30325B). Referenced figures and tables follow this text. ML = For the sake of completeness, it is also noted that the package designation “MLF” is now replaced by “QFN” in all occurrences throughout the Device Data Sheet. “MLF” should be considered an obsoleted term. 1. The “Pin Diagrams” on pages 2-3 of the Data Sheet are amended with the addition of the 44-pin QFN pinout shown in Figure 2. 2. Table 1.3 of Section 1.0 (“Device Overview”) is replaced with an updated version which adds a column for QFN pin assignments. All new information is indicated in bold. FIGURE 2: QFN PINOUT DIAGRAM FOR PIC16F74/77, 44-PIN QFN PACKAGE 1 2 3 4 5 6 7 8 9 10 11 PIC16F74 PIC16F77 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD VDD RB0/INT0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 RC0/T1CKI 44-Pin QFN OSC2/CLKO OSC1/CLKI VSS VSS VDD VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 NC RB3 DS80099G-page 6 2003 Microchip Technology Inc. PIC16F73/74/76/77 FIGURE 3: PACKAGE MARKING TEMPLATE FOR PIC16F74/77, 44-PIN QFN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 2003 Microchip Technology Inc. Example PIC16F77 -I/ML 0310017 DS80099G-page 7 PIC16F73/74/76/77 TABLE 1-3: PIC16F74/77 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFN Pin# QFP Pin# I/O/P Type 13 14 32 30 I 14 15 33 31 O — Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. 1 2 18 18 I/P ST Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. RA0/AN0 RA0 AN0 2 3 19 19 RA1/AN1 RA1 AN1 3 RA2/AN2/VREFRA2 AN2 VREF- 4 RA3/AN3/VREF+ RA3 AN3 VREF+ 5 RA4/T0CKI RA4 T0CKI 6 RA5/SS/AN4 RA5 SS AN4 7 Pin Name OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 Buffer Type ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). CLKO MCLR/VPP MCLR Description VPP PORTA is a bidirectional I/O port. Legend: Note 1: 2: 3: 4: TTL I/O I 4 20 20 Digital I/O. Analog input 0. TTL I/O I 5 21 Digital I/O. Analog input 1. TTL 21 I/O I I 6 22 22 Digital I/O. Analog input 2. A/D reference voltage (Low) input. TTL I/O I I 7 23 23 Digital I/O. Analog input 3. A/D reference voltage (High) input. ST I/O I 8 24 Digital I/O – Open drain when configured as output. Timer0 external clock input. TTL 24 I/O I I Digital I/O. SPI slave select input. Analog input 4. I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS80099G-page 8 2003 Microchip Technology Inc. PIC16F73/74/76/77 TABLE 1-3: PIC16F74/77 PINOUT DESCRIPTION (CONTINUED) Pin Name DIP Pin# PLCC Pin# QFN Pin# QFP Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. 36 9 TTL/ST(1) RB0/INT RB0 INT 33 8 RB1 34 37 10 9 I/O TTL Digital I/O. RB2 35 38 11 10 I/O TTL Digital I/O. I/O I Digital I/O. External interrupt. RB3 36 39 12 11 I/O TTL Digital I/O. RB4 37 41 14 14 I/O TTL Digital I/O. RB5 38 42 15 15 I/O TTL Digital I/O. RB6/PGC RB6 PGC 39 43 16 16 RB7/PGD RB7 PGD 40 RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK SCL 18 RC4/SDI/SDA RC4 SDI SDA 23 RC5/SDO RC5 SDO 24 RC6/TX/CK RC6 TX CK 25 RC7/RX/DT RC7 RX DT 26 TTL/ST(2) I/O I/O 44 17 Digital I/O. In-circuit debugger and ICSP™ programming clock. TTL/ST(2) 17 I/O I/O Digital I/O. In-circuit debugger and ICSP™ programming data. PORTC is a bidirectional I/O port. Legend: Note 1: 2: 3: 4: 16 34 32 ST I/O O I 18 35 35 Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST I/O I I/O 19 36 36 Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST I/O I/O 20 37 37 Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST I/O I/O I/O 25 42 42 Digital I/O. Synchronous serial clock input/output for SPI™ mode. Synchronous serial clock input/output for I2C™ mode. ST I/O I I/O 26 43 43 Digital I/O. SPI data in. I2C data I/O. ST I/O O 27 44 44 Digital I/O. SPI data out. ST I/O O I/O 29 1 1 Digital I/O. USART asynchronous transmit. USART 1 synchronous clock. ST I/O I I/O Digital I/O. USART asynchronous receive. USART synchronous data. I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 2003 Microchip Technology Inc. DS80099G-page 9 PIC16F73/74/76/77 TABLE 1-3: Pin Name PIC16F74/77 PINOUT DESCRIPTION (CONTINUED) DIP Pin# PLCC Pin# QFN Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bidirectional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 RD0 PSP0 19 RD1/PSP1 RD1 PSP1 20 RD2/PSP2 RD2 PSP2 21 RD3/PSP3 RD3 PSP3 22 RD4/PSP4 RD4 PSP4 27 RD5/PSP5 RD5 PSP5 28 RD6/PSP6 RD6 PSP6 29 RD7/PSP7 RD7 PSP7 30 21 38 ST/TTL(3) 38 Digital I/O. Parallel Slave Port data. I/O I/O 22 39 ST/TTL(3) 39 Digital I/O. Parallel Slave Port data. I/O I/O 23 40 ST/TTL(3) 40 Digital I/O. Parallel Slave Port data. I/O I/O 24 41 ST/TTL(3) 41 Digital I/O. Parallel Slave Port data. I/O I/O 30 2 ST/TTL(3) 2 Digital I/O. Parallel Slave Port data. I/O I/O 31 3 ST/TTL(3) 3 Digital I/O. Parallel Slave Port data. I/O I/O 32 4 ST/TTL(3) 4 Digital I/O. Parallel Slave Port data. I/O I/O 33 5 ST/TTL(3) 5 Digital I/O. Parallel Slave Port data. I/O I/O PORTE is a bidirectional I/O port. RE0/RD/AN5 RE0 RD AN5 8 RE1/WR/AN6 RE1 WR AN6 9 RE2/CS/AN7 RE2 CS AN7 10 9 25 ST/TTL(3) 25 I/O I I 10 26 Digital I/O. Read control for parallel slave port. Analog input 5. ST/TTL(3) 26 Digital I/O. Write control for parallel slave port. Analog input 6. I/O I I 11 27 ST/TTL(3) 27 Digital I/O. Chip select control for parallel slave port. Analog input 7. I/O I I VSS 12,31 13,34 6, 30, 31 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7, 8, 28, 29 7,28 P — Positive supply for logic and I/O pins. NC — 1,17, 28,40 13 12,13, 33,34 — — These pins are not internally connected. These pins should be left unconnected. Legend: Note 1: 2: 3: 4: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS80099G-page 10 2003 Microchip Technology Inc. PIC16F73/74/76/77 FIGURE 4: 44-PIN QFN PACKAGE (DRAWING 1, PACKAGING) 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) EXPOSED METAL PAD E p D D2 2 1 B n PIN 1 INDEX ON EXPOSED PAD OPTIONAL PIN 1 INDEX ON TOP MARKING E2 L TOP VIEW BOTTOM VIEW A A1 A3 Number of Pins Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length Units Dimension Limits n p A A1 A3 E E2 D D2 B L MIN .031 .000 .262 .262 .012 .014 INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 BSC .268 .315 BSC .268 .013 .016 MAX .039 .002 .274 .274 .013 .018 MILLIMETERS* NOM 44 0.65 BSC 0.90 0.80 0.02 0 0.25 REF 8.00 BSC 6.65 6.80 8.00 BSC 6.65 6.80 0.30 0.33 0.35 0.40 MIN MAX 1.00 0.05 6.95 6.95 0.35 0.45 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-103 2003 Microchip Technology Inc. DS80099G-page 11 PIC16F73/74/76/77 REVISION HISTORY Rev A Document (2/01) Original errata document for PIC16F77 (DS80099A). Issue 1 (Timer1), page 1. Rev B Document (4/01) Addition of other members of 16F7X family for issue 1. Added issue 2 (Core), page 1 and issue 3 (A/D), page 2. Rev C Document (7/01) Added issue 4 (CCP), page 2 and issue 5 (Core), page 3. Rev D Document (8/01) Under Clarifications/Corrections to the Data Sheet, added issue 1 (Reset), page 4. Rev E Document (9/02) Removed previous Clarifications/Corrections to the Data Sheet (DS30325A), added Issue 6 (Oscillator), page 4. Rev F Document (1/03) Removed previous silicon issue 2 (Core) and silicon issue 3 (A/D), updated silicon issue 1 (Timer1), silicon issue 2 (formerly issue 4, Compare Mode) and silicon issue 3 (formerly issue 6, HS Mode) with new date code information. Moved previous silicon issue 5 (Core) to Clarifications/Corrections to the Data Sheet (DS30325B) and added issue 2 (Pinout Correction). Rev G Document (8/03) Added Data Sheet Clarification issues 3 (Pinout Correction) and 4 (Packaging). DS80099G-page 12 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. DS80099G-page 13 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Korea Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 Toronto India 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 DS80099G-page 14 Singapore 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Austria Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910 France Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc.