LT3955 60VIN LED Converter with Internal PWM Generator Features Description 3000:1 True Color PWM™ Dimming for LEDs nn Wide V Range: 4.5V to 60V IN nn Rail-to-Rail Current Sense Range: 0V to 80V nn Internal 80V/3.5A Switch nn Programmable PWM Dimming Signal Generator nn Constant Current (±3%) and Constant-Voltage (±2%) Regulation nn Accurate Analog Dimming nn Drives LEDs in Boost, SEPIC, CUK, Buck Mode, Buck-Boost Mode, or Flyback Configuration nn Output Short-Circuit Protected Boost nn Open LED Protection and Reporting nn Adjustable Switching Frequency: 100kHz to 1MHz nn Programmable V UVLO with Hysteresis IN nn C/10 Indication for Battery Chargers nn Low Shutdown Current: <1µA nn Thermally Enhanced 5mm × 6mm QFN Package The LT®3955 is a DC/DC converter designed to operate as a constant-current source and constant-voltage regulator. It features an internal low side N-channel MOSFET rated for 80V/3.5A. The LT3955 is ideally suited for driving high current LEDs, but also has features to make it suitable for charging batteries and supercapacitors. The fixed frequency, current mode architecture results in stable operation over a wide range of supply and output voltages. A voltage feedback pin serves as the input for several LED protection features, and also makes it possible for the converter to operate as a constant-voltage source. A frequency adjust pin allows the user to program the frequency from 100kHz to 1MHz to optimize efficiency, performance or external component size. nn Applications High Power LEDs Output Short-Circuit Protected Boost nn Battery and SuperCap Chargers nn Accurate Current Limited Voltage Regulators nn nn The LT3955 senses output current at the high side or at the low side of the load. The PWM input can be configured to self-oscillate at fixed frequency with duty ratio programmable from 4% to 96%. When driven by an external signal, the PWM input provides LED dimming ratios of up to 3000:1. The CTRL input provides additional analog dimming capability. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and True Color PWM is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7199560, 7321203. Typical Application 94% Efficiency 20W Boost LED Driver with Internal PWM Dimming 22µH VIN 5V TO 60V 4.7µF ×2 499k VIN EN/UVLO 147k INTVCC 100k 124k 10nF VDIM = 8V DCPWM = 97.2% LT3955 165k DIM PGND ISP VREF 1M 28.7k 350kHz 5.1k 47nF 300Hz 4.7nF CTRL PWM Dimming Waveforms at Various DIM Voltage Settings 2.2µF ×5 SW 0.82Ω 300mA VDIM = 3.87V DCPWM = 50% ILED 0.3A/DIV ISN VDIM = 1.47V DCPWM = 10% 1M FB VMODE DIM/SS SYNC PWM RT PWMOUT VC GND GNDK INTVCC 16.9k 20W LED STRING (CURRENT DERATED FOR VIN < 9V) VIN = 24V VLED = 65V 0.5ms/DIV 3955 TA01b VDIM = 0V DCPWM = 2.8% INTVCC 1µF 3955 TA01a NOTE: GND, GNDK AND SIGNAL LEVEL COMPONENTS MUST BE CONNECTED EXTERNALLY AS SHOWN. AN INTERNAL CONNECTION BETWEEN GNDK AND PGND PINS PROVIDES GROUNDING TO THE SUPPLY. 3955fb For more information www.linear.com/LT3955 1 LT3955 Absolute Maximum Ratings Pin Configuration (Note 1) VC CTRL VREF PWM VMODE DIM/SS TOP VIEW RT VIN, EN/UVLO.............................................................60V ISP, ISN, SW..............................................................80V INTVCC....................................................VIN + 0.3V, 9.6V PWMOUT............................................................ (Note 2) CTRL, VMODE............................................................15V FB, PWM, SYNC........................................................9.6V VC, VREF.......................................................................3V RT, DIM/SS...............................................................1.5V PGND, GNDK to GND..............................................±0.5V Operating Ambient Temperature Range (Notes 3, 4)............................................. –40°C to 125°C Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 150°C 36 35 34 33 32 31 30 28 ISP SYNC 1 27 ISN EN/UVLO 2 INTVCC 3 37 GND GND 4 25 FB 24 GND VIN 6 23 PWMOUT 38 SW SW 8 SW 9 21 SW 20 SW NC 10 PGND PGND PGND PGND PGND GNDK 12 13 14 15 16 17 UHE PACKAGE 36-LEAD (5mm × 6mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W, θJC = 3°C/W EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO GND PLANE EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3955EUHE#PBF LT3955EUHE#TRPBF 3955 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LT3955IUHE#PBF LT3955IUHE#TRPBF 3955 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 3955fb For more information www.linear.com/LT3955 LT3955 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted. PARAMETER CONDITIONS VIN Minimum Operating Voltage VIN Tied to INTVCC VIN Shutdown IQ EN/UVLO = 0V, PWM = 0V EN/UVLO = 1.15V, PWM = 0V VIN Operating IQ (Not Switching) PWM = 0V VREF Voltage –100µA ≤ IVREF ≤ 0µA VREF Line Regulation 4.5V ≤ VIN ≤ 60V VREF Pull-Up Current VREF = 0V SW Pin Current Limit SW Pin Leakage MIN SW Pin Voltage Drop ISW = 2A Current Out of Pin, DIM/SS = 0V DIM/SS Voltage Clamp IDIM/SS = 0µA MAX UNITS 4.5 V 1 6 µA µA 1.7 2.2 mA 2.02 2.06 V l 0.1 l 1.965 l 150 185 210 l 3.5 4.2 4.9 A 5 10 µA 0.001 SW = 48V DIM/SS Pull-Up Current TYP %/V 200 l 10 12 µA mV 14 1.2 µA V Error Amplifier Full-Scale ISP/ISN Current Sense Threshold (VISP–ISN) CTRL ≥ 1.2V, ISP = 48V, 0V ≤ FB ≤ 1.18V l CTRL ≥ 1.2V, ISN = 0V, 0V ≤ FB ≤ 1.18V l 242 243 250 257 258 268 mV mV 1/10th Scale ISP/ISN Current Sense Threshold (VISP–ISN) CTRL = 0.2V, ISP = 48V, 0V ≤ FB ≤ 1.18V l CTRL = 0.2V, ISN = 0V, 0V ≤ FB ≤ 1.18V l 21 20 25 28 30 36 mV mV Mid-Scale ISP/ISN Current Sense Threshold (VISP–ISN) CTRL = 0.5V, ISP = 48V, 0V ≤ FB ≤ 1.18V l CTRL = 0.5V, ISN = 0V, 0V ≤ FB ≤ 1.18V l 96 94 100 105 104 115 mV mV ISP/ISN Overcurrent Threshold 600 0 ISP/ISN Current Sense Amplifier Input Common Mode Range (VISN) mV 80 V ISP/ISN Input Bias Current High Side Sensing (Combined) PWM = 5V (Active), ISP = ISN = 48V PWM = 0V (Standby), ISP = ISN = 48V 100 0.1 µA µA ISP/ISN Input Bias Current Low Side Sensing (Combined) PWM = 5V, ISP = ISN = 0V –230 µA ISP/ISN Current Sense Amplifier gm (High Side Sensing) VISP–ISN = 250mV, ISP = 48V 120 µS ISP/ISN Current Sense Amplifier gm (Low Side Sensing) VISP–ISN = 250mV, ISN = 0V CTRL Pin Range for Linear Current Sense Threshold Adjustment 70 l CTRL Input Bias Current Current Out of Pin VC Output Impedance 0.9V ≤ VC ≤ 1.5V VC Standby Input Bias Current PWM = 0V FB Regulation Voltage (VFB) ISP = ISN = 48V, 0V FB Amplifier gm FB = VFB, ISP = ISN = 48V FB Pin Input Bias Current Current Out of Pin, FB = VFB FB Open LED Threshold VMODE Falling, ISP Tied to ISN C/10 Inhibit for VMODE Assertion (VISP–ISN) FB = VFB, ISN = 48V, 0V FB Overvoltage Threshold PWMOUT Falling 0 50 µS 1.0 V 100 nA 15 –20 l 1.225 MΩ 20 1.255 1.275 500 40 25 V µS 100 l VFB – 65mV VFB – 50mV VFB – 40mV 14 nA 39 VFB + 50mV VFB + 60mV VFB + 70mV nA V mV V Oscillator Switching Frequency RT = 95.3kΩ RT = 8.87kΩ l 85 925 100 1000 115 1050 kHz kHz SW Minimum Off-Time 160 ns SW Minimum On-Time 180 ns SYNC Input Low 0.4 V 3955fb For more information www.linear.com/LT3955 3 LT3955 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, CTRL = 2V, PWM = 5V, unless otherwise noted. PARAMETER CONDITIONS MIN SYNC Input High TYP MAX 1.5 UNITS V Linear Regulator INTVCC Regulation Voltage 10V ≤ VIN ≤ 60V l INTVCC Maximum Operating Voltage 7.60 7.85 4.5 IINTVCC = –10mA, VIN = 7V INTVCC Undervoltage Lockout 390 l INTVCC Current Limit 8V ≤ VIN ≤ 60V, INTVCC = 6V INTVCC Current in Shutdown EN/UVLO = 0V, INTVCC = 8V V V INTVCC Minimum Operating Voltage Dropout (VIN – INTVCC) 8.05 8.1 3.9 4.1 30 V mV 4.4 V 36 42 mA 8 13 µA 1.220 1.260 V Logic Inputs/Outputs EN/UVLO Threshold Voltage Falling l 1.180 EN/UVLO Rising Hysteresis 40 EN/UVLO Input Low Voltage IVIN Drops Below 1µA EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V EN/UVLO Pin Bias Current High EN/UVLO = 1.33V 1.7 VMODE Output Low IVMODE = 1mA VMODE Pin Leakage FB = 0V, VMODE = 12V mV 0.4 V 2.2 2.7 µA 10 100 nA 200 mV 0.1 5 µA PWM Pin Signal Generator PWM Falling Threshold PWM Threshold Hysteresis (VPWMHYS) l IDIM/SS = 0µA 0.78 0.83 0.88 V 0.35 0.47 0.6 V PWM Pull-Up Current (IPWMUP) PWM = 0.7V, IDIM/SS = 0µA 6 7.5 9 µA PWM Pull-Down Current (IPWMDN) PWM = 1.5V, IDIM/SS = 0µA 68 88 110 µA PWM Fault-Mode Pull-Down Current INTVCC = 3.6V PWMOUT Duty Ratio for PWM Signal Generator (Note 5) IDIM/SS = –6.5µA IDIM/SS = 0µA IDIM/SS = 21.5µA IDIM/SS = 52µA 3.1 6.2 40 95 4.1 7.9 48 96.5 5.2 9.2 56 98 % % % % PWMOUT Signal Generator Frequency PWM = 47nF to GND, IDIM/SS = 0µA 170 300 390 Hz 1.5 mA PWMOUT Driver PWMOUT Driver Output Rise Time (tr) CL = 560pF 35 PWMOUT Driver Output Fall Time (tf) CL = 560pF 35 PWMOUT Output Low (VOL) PWM = 0V 4 ns 0.05 PWMOUT Output High (VOH) INTVCC – 0.05 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage or current source to PWMOUT pin, otherwise permanent damage may occur. Note 3: The LT3955E is guaranteed to meet performance specifications from the 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3955I is guaranteed over the full –40°C to 125°C operating junction temperature range. ns V V Note 4: The LT3955 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum junction temperature may impair device reliability. Note 5: PWMOUT Duty Ratio is calculated: Duty = IPWMUP/(IPWMUP + IPWMDN) 3955fb For more information www.linear.com/LT3955 LT3955 Typical Performance Characteristics V(ISP–ISN) Threshold vs CTRL Voltage TA = 25°C, unless otherwise noted. V(ISP–ISN) Threshold vs ISP Voltage 260 300 V(ISP–ISN) Threshold vs Temperature 265 CTRL = 2V 200 150 100 50 V(ISP – ISN) THRESHOLD (mV) V(ISP – ISN) THRESHOLD (mV) V(ISP – ISN) THRESHOLD (mV) 250 255 250 245 0 0.5 0 240 2 1 1.5 CTRL VOLTAGE (V) 3955 G01 FB Regulation Voltage (VFB) vs Temperature 40 60 ISP VOLTAGE (V) ISN = 0V 255 250 245 3955 G02 1.250 1.245 0 25 50 75 TEMPERATURE (°C) 100 125 3955 G03 VREF Source Current vs Temperature CTRL = 2V VREF SOURCE CURRENT (µA) V(ISP– ISN) THRESHOLD (mV) 1.255 –25 200 230 1.260 ISP = 48V 240 –50 80 260 1.265 VFB (V) 20 260 V(ISP–ISN) Threshold vs FB Voltage 1.270 200 170 140 110 80 CTRL = 0.5V 190 180 170 160 50 1.240 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 20 1.22 1.225 125 3955 G04 VREF Voltage vs Temperature 2.03 2.02 2.01 2.00 0 25 50 75 TEMPERATURE (°C) 100 125 3955 G07 0 25 50 75 TEMPERATURE (°C) 100 125 3955 G06 Switching Frequency vs Temperature 420 900 415 800 700 600 500 400 300 100 –25 3955 G05 RT = 25.5k 410 405 400 395 390 385 200 –25 150 –50 1.25 1.245 1000 SWITCHING FREQUENCY (kHz) 2.04 1.99 –50 1.23 1.235 1.24 FB VOLTAGE (V) Switching Frequency vs RT 2.05 VREF (V) 0 SWITCHING FREQUENCY (kHz) –50 CTRL = 2V 100 10 RT (kΩ) 3955 G08 380 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 3955 G09 3955fb For more information www.linear.com/LT3955 5 LT3955 Typical Performance Characteristics SW Pin Current Limit vs Temperature SW Pin Current Limit vs Duty Cycle EN/UVLO Threshold vs Temperature 6 4.60 1.27 CURRENT LIMIT (A) 4.20 4.00 3.80 EN/UVLO THRESHOLD (V) 5 4.40 CURRENT LIMIT (A) TA = 25°C, unless otherwise noted. 4 3 2 0 –25 0 25 50 75 TEMPERATURE (°C) 100 125 0 20 40 60 DUTY CYCLE (%) 80 1.23 FALLING 1.21 1.19 –50 100 INTVCC Current Limit vs vs Temperature INTVCC Dropout Voltage vs Current, Temperature 40 ON-RESISTANCE (mΩ) LDO DROPOUT (V) –0.6 TA = 25°C –0.8 –1.0 TA = 130°C –1.2 –1.4 32 0 25 50 75 TEMPERATURE (°C) 100 –1.8 125 0 5 10 15 20 LDO CURRENT (mA) 25 30 3955 G13 3955 G14 PWM Signal Generator Duty Ratio vs DIM/SS Current PWM Signal Generator Frequency vs Duty Ratio 100 340 RWM FREQUENCY (Hz) 80 60 40 20 160 140 120 100 80 40 –50 –25 0 25 50 75 TEMPERATURE (°C) 0 10 20 30 DIM/SS CURRENT (µA) 40 50 3955 G16 6 100 125 3955 G15 PWMOUT Waveform CPWMOUT = 2.2nF CPWM = 47nF 320 PWM INPUT 300 PWMOUT 5V/DIV 280 200ns/DIV 0 –10 3955 G12 60 –1.6 –25 125 180 TA = –45°C –0.4 30 –50 100 200 –0.2 38 34 0 25 50 75 TEMPERATURE (°C) Switch On-Resistance vs Temperature 0 36 –25 3955 G11 3955 G10 INTVCC CURRENT LIMIT (mA) RISING 1 3.60 –50 DUTY RATIO (%) 1.25 260 0 20 40 60 DUTY RATIO (%) 80 3955 G18 100 3955 G17 3955fb For more information www.linear.com/LT3955 LT3955 Typical Performance Characteristics DIM/SS Voltage vs Current, Temperature ISP/ISN Input Bias Current vs CTRL Voltage, ISP = 48V ISP/ISN Input Bias Current vs CTRL Voltage, ISN = 0V 0 120 ISP INPUT BIAS CURRENT (µA) 100 1.25 T = –45°C, 25°C 1.20 T = 130°C 1.15 –30 INPUT BIAS CURRENT (µA) 1.30 80 60 40 ISN 10 20 30 DIM/SS CURRENT (µA) 40 0 50 0 3955 G19 0.5 1 1.5 CTRL VOLTAGE (V) PWMOUT Duty Ratio vs Temperature, IDIM/SS = 0µA 9.5 ISN –90 –120 ISP –180 2 0 0.5 1 1.5 CTRL VOLTAGE (V) 3955 G20 2 3955 G21 PWMOUT Duty Ratio vs Temperature, IDIM/SS = 21.5µA 55 CPWM = 47nF 9.0 CPWM = 47nF 53 DUTY RATIO (%) 8.5 8.0 7.5 51 49 47 7.0 6.5 –50 –25 0 45 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 VISP-ISN Overcurrent Threshold vs Temperature EN/UVLO Hysteresis Current vs Temperature 800 2.8 700 2.6 600 ISP = 24V 500 ISN = 0V 400 300 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3955 G24 25 50 75 100 125 150 TEMPERATURE (°C) 3955 G23 3955 G22 EN/UVLO CURRENT (µA) 0 DUTY RATIO (%) 1.10 –10 –60 –150 20 VISP-ISN (mV) DIM/SS VOLTAGE (V) TA = 25°C, unless otherwise noted. 2.4 2.2 2.0 1.8 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3955 G25 3955fb For more information www.linear.com/LT3955 7 LT3955 Pin Functions SYNC (Pin 1): Frequency Synchronization Pin. Used to synchronize the internal oscillator to an outside clock. If this feature is used, an RT resistor should be chosen to program a switching frequency 20% slower than SYNC pulse frequency. Tie the SYNC pin to PWMOUT if this feature is not used. EN/UVLO (Pin 2): Enable and Undervoltage Detect Pin. An accurate 1.22V falling threshold with externally programmable hysteresis causes the switching regulator to shut down when power is insufficient to maintain output regulation. Above the 1.24V (typical) rising enable threshold (but below 2.5V), EN/UVLO input bias current is sub-μA. Below the 1.22V (typical) falling threshold, an accurate 2.2μA (typical) pull-down current is enabled so the user can define the rising hysteresis with the external resistor selection. An undervoltage condition causes the switch to turn off and the PWMOUT pin to transition low and resets soft-start. Tie to 0.4V, or less, to disable the device and reduce VIN quiescent current below 1μA. Can be tied to VIN through a 100k resistor. INTVCC (Pin 3): Current limited, low dropout linear regulator regulates to 7.85V (typical) from VIN. Supplies internal loads, SW and PWMOUT drivers. Must be bypassed with a 1µF ceramic capacitor placed close to the pin and to the exposed pad GND of the IC. VIN (Pin 6): Power Supply for Internal Loads and INTVCC Regulator. Must be locally bypassed with a 0.22µF (or larger) low ESR capacitor placed close to the pin. GNDK (Pin 12): Kelvin Connection Pin between PGND and GND. Kelvin connect this pin to the GND plane close to the IC. See the Board Layout section. PGND (Pins 13 to 17): Source Terminal Switch and the GND Input to the Switch Current Comparator. PWMOUT (Pin 23): Buffered Version of PWM Signal for Driving LED Load Disconnect NMOS or Level Shift. This pin also serves in a protection function for the FB overvoltage condition—will toggle if the FB input is greater than the FB regulation voltage (VFB) plus 60mV (typical). The PWMOUT pin is driven from INTVCC. Use of a FET with gate cut-off voltage higher than 1V is recommended. 8 FB (Pin 25): Voltage Loop Feedback Pin. FB is intended for constant-voltage regulation or for LED protection and open LED detection. The internal transconductance amplifier with output VC will regulate FB to 1.25V (nominal) through the DC/DC converter. If the FB input exceeds the regulation voltage, VFB, minus 50mV and the voltage between ISP and ISN has dropped below the C/10 threshold of 25mV (typical), the VMODE pull-down is asserted. This action may signal an open LED fault. If FB is driven above the FB overvoltage threshold, the PWMOUT pin will be driven low and the internal power switch is turned off, to protect the LEDs from an overcurrent event. Do not leave the FB pin open. If not used, connect to GND. ISN (Pin 27): Connection Point for the Negative Terminal of the Current Feedback Resistor. The constant output current regulation can be programmed by ILED = 250mV/ RLED when CTRL > 1.2V or ILED = (CTRL – 100mV)/(4 • RLED). If ISN is greater than INTVCC, input bias current is typically 20μA flowing into the pin. Below INTVCC, ISN bias current decreases until it flows out of the pin. ISP (Pin 28): Connection Point for the Positive Terminal of the Current Feedback Resistor. Input bias current depends upon CTRL pin voltage. When it is greater than INTVCC it flows into the pin. Below INTVCC, ISP bias current decreases until it flows out of the pin. If the difference between ISP and ISN exceeds 600mV (typical), then an overcurrent event is detected. In response to this event, the switch is turned off and the PWMOUT pin is driven low to protect the switching regulator, a 1.5mA pull-down on PWM and a 9mA pull-down on the DIM/SS pin are activated for 4µs. VC (Pin 30): Transconductance Error Amplifier Output Pin Used to Stabilize the Switching Regulator Control Loop with an RC Network. The VC pin is high impedance when PWM is low. This feature allows the VC pin to store the demand current state variable for the next PWM high transition. Connect a capacitor between this pin and GND; a resistor in series with the capacitor is recommended for fast transient response. CTRL (Pin 31): Current Sense Threshold Adjustment Pin. Constant current regulation point VISP-ISN is one-fourth VCTRL plus an offset for 0V ≤ CTRL ≤ 1V. For CTRL > 3955fb For more information www.linear.com/LT3955 LT3955 Pin Functions 1.2V the VISP-ISN current regulation point is constant at the full-scale value of 250mV. For 1V ≤ CTRL ≤ 1.2V, the dependence of VISP-ISN upon CTRL voltage transitions from a linear function to a constant value, reaching 98% of fullscale value by CTRL = 1.1V. Do not leave this pin open. VREF (Pin 32): Voltage Reference Output Pin, Typically 2V. This pin drives a resistor divider for the CTRL pin, either for analog dimming or for temperature limit/compensation of LED load. It can be bypassed with 10nF or greater, or less than 50pF. Can supply up to 185µA (typical). PWM (Pin 33): A signal low turns off switcher, idles the oscillator and disconnects the VC pin from all internal loads. PWMOUT pin follows the PWM pin, except in fault conditions. The PWM pin can be driven with a digital signal to cause pulse width modulation (PWM) dimming of an LED load. The digital signal should be capable of sourcing or sinking 200μA at the high and low thresholds. During start-up when DIM/SS is below 1V, the first rising edge of PWM enables switching which continues until VISP-ISN ≥ 25mV or DIM/SS ≥ 1V. Connecting a capacitor from PWM pin to GND invokes a self-driving oscillator where internal pull-up and pull-down currents set a duty ratio for the PWMOUT pin for dimming LEDs. The capacitor must be placed close to the IC. The magnitudes of the pull-up/ down currents are set by the current in the DIM/SS pin. The capacitor on PWM sets the frequency of the dimming signal. For hiccup mode response to output short-circuit faults, connect this pin as shown in the application titled Boost LED Driver with Output Short-Circuit Protection. If not used, connect the PWM pin to INTVCC. VMODE (Pin 34): An open-drain pull-down on this pin asserts if the FB input is greater than the FB regulation voltage (VFB) minus 50mV (typical) AND the difference between current sense inputs ISP and ISN is less than 25mV. To function, the pin requires an external pull-up resistor, usually to INTVCC. When the PWM input is low and the DC/DC converter is idle, the VMODE condition is latched to the last valid state when the PWM input was high. When PWM input goes high again, the VMODE pin will be updated. This pin may be used to report transition from constant current regulation to constant voltage regulation modes, for instance in a charger or current limited voltage supply. DIM/SS (Pin 35): Soft-Start and PWM Dimming Signal Generator Programming Pin. This pin modulates switching regulator frequency and compensation pin voltage (VC) clamp when it is below 1V. The soft-start interval is set with an external capacitor and the DIM/SS pin charging current. The pin has an internal 12μA (typical) pull-up current source. The soft-start pin is reset to GND by an undervoltage condition (detected at the EN/UVLO pin), INTVCC undervoltage, overcurrent event sensed at ISP/ ISN, or thermal limit. After initial start-up with EN/UVLO, DIM/SS is forced low until the first PWM rising edge. When DIM/SS reaches the steady-state voltage (~1.17V), the charging current (sum of internal and external currents) is sensed and used to set the PWM pin charging and discharge currents and threshold hysteresis. In this manner, the SS charging current sets the duty cycle of the PWM signal generator associated with the PWM pin. This pin should always have a capacitor to GND, minimum 560pF value, when used with the PWM signal generator function. See typical performance curves for details on the variation of PWM pin parameters with SS charging current. Place the capacitor close to the IC. RT (Pin 36): Switching Frequency Adjustment Pin. Set the frequency using a resistor to GND (for resistor values, see the Typical Performance curve or Table 2). Do not leave the RT pin open. Place the resistor close to the IC. GND (Exposed Pad Pin 37, Pins 4, 24): Ground. Solder the exposed pads directly to the ground plane. SW (Exposed Pad Pin 38, Pins 8, 9, 20, 21): Drain of Internal Power N-channel MOSFET. 3955fb For more information www.linear.com/LT3955 9 LT3955 Block Diagram 180µA VREF 1.3V – +A7 2V F1(IDIM/SS) PWM + – CTRL 100mV 1V CLAMP – + 0.8V FAULT CTRL BUFFER – LDO +A8 1.25V OVFB COMPARATOR S R PWMINT Q SW + A2 – 1.5mA 10µA R + – A1 – gm + ISN 10µA AT A1+ = A1– CURRENT MODE COMPARATOR 1.25V FB A5 + gm – ISENSE IDIM/SS DETECT A6 + + – SHDN GND PWMINT ISP FAULT LOGIC 1.2V DIM/SS OPENLED LOGIC 25mV ISN + – BANDGAP REFERENCE GNDK FREQ PROG 12µA ISP > ISN + 0.6V T > 165°C PGND VMODE FAULT 2.2µA RSENSE 100kHz TO 1MHz OSCILLATOR 1V 1.22V 48mV RAMP GENERATOR 10µA AT FB = 1.25V VC – + + – A4 CV EAMP M1 DRIVER CC EAMP + – ISP EN/UVLO Q S ×1/4 A3 INTVCC 7.85V – + 0.8V + F3(IDIM/SS) F2(IDIM/SS) VIN PWMOUT – + FB RT SYNC FB + – – + 3955 BD 10 3955fb For more information www.linear.com/LT3955 LT3955 Operation The LT3955 is a constant-frequency, current mode converter with a low side N-channel MOSFET switch. The switch and PWMOUT pin drivers, and other chip loads, are powered from INTVCC, which is an internally regulated supply. In the discussion that follows it will be helpful to refer to the Block Diagram of the IC. In normal operation with the PWM pin low, the switch is turned off and the PWMOUT pin is driven to GND, the VC pin is high impedance to store the previous switching state on the external compensation capacitor, and the ISP and ISN pin bias currents are reduced to leakage levels. When the PWM pin transitions high, the PWMOUT pin transitions high after a short delay. At the same time, the internal oscillator wakes up and generates a pulse to set the PWM latch, turning on the internal power MOSFET switch. A voltage input proportional to the switch current, sensed by an internal current sense resistor is added to a stabilizing slope compensation ramp and the resulting switch current sense signal is fed into the negative terminal of the PWM comparator. The current in the external inductor increases steadily during the time the switch is on. When the switch current sense voltage exceeds the output of the error amplifier, labeled VC, the latch is reset and the switch is turned off. During the switch-off phase, the inductor current decreases. At the completion of each oscillator cycle, internal signals such as slope compensation return to their starting points and a new cycle begins with the set pulse from the oscillator. Through this repetitive action, the PWM control algorithm establishes a switch duty cycle to regulate a current or voltage in the load. The VC signal is integrated over many switching cycles and is an amplified version of the difference between the LED current sense voltage, measured between ISP and ISN, and the target difference voltage set by the CTRL pin. In this manner, the error amplifier sets the correct peak switch current level to keep the LED current in regulation. If the error amplifier output increases, more current is demanded in the switch; if it decreases, less current is demanded. The switch current is monitored during the on-phase and is not allowed to exceed the current limit threshold of 4.2A (typical). If the SW pin exceeds the current limit threshold, the SR latch is reset regardless of the output state of the PWM comparator. The difference between ISP and ISN is monitored to determine if the output is in a short-circuit condition. If the difference between ISP and ISN is greater than 600mV (typical), the SR latch will be reset regardless of the PWM comparator. The DIM/SS pin will be pulled down and the PWMOUT pin forced low and the SW pin turned off for at least 4µs. These functions are intended to protect the power switch as well as various external components in the power path of the DC/DC converter. In voltage feedback mode, the operation is similar to that described above, except the voltage at the VC pin is set by the amplified difference of the internal reference of 1.25V and the FB pin. If FB is lower than the reference voltage, the switch current will increase; if FB is higher than the reference voltage, the switch demand current will decrease. The LED current sense feedback interacts with the FB voltage feedback so that FB will not exceed the internal reference and the voltage between ISP and ISN will not exceed the threshold set by the CTRL pin. For accurate current or voltage regulation, it is necessary to be sure that under normal operating conditions the appropriate loop is dominant. To deactivate the voltage loop entirely, FB can be connected to GND. To deactivate the LED current loop entirely, the ISP and ISN should be tied together and the CTRL input tied to VREF. Two LED specific functions featured on the LT3955 are controlled by the voltage feedback pin. First, when the FB pin exceeds a voltage 50mV lower (–4%) than the FB regulation voltage, and the difference voltage between ISP and ISN is below 25mV (typical), the pull-down driver on the VMODE pin is activated. This function provides a status indicator that the load may be disconnected and the constant-voltage feedback loop is taking control of the switching regulator. The VMODE pin de-asserts only when PWM is high and FB drops below the voltage threshold. FB overvoltage is the second protective function. When the FB pin exceeds the FB regulation voltage by 60mV (plus 5% typical), the PWMOUT pin is driven low, ignoring the state of the PWM input. In the case where the PWMOUT pin drives a disconnect NFET, this action isolates the LED load from GND, preventing excessive current from damaging the LEDs. 3955fb For more information www.linear.com/LT3955 11 LT3955 Applications Information INTVCC Regulator Bypassing and Operation The INTVCC pin requires a capacitor for stable operation and to store the charge for the large internal MOSFET gate switching currents. Choose a 10V rated low ESR, X7R ceramic capacitor for best performance. A 1μF capacitor will be adequate for many applications. Place the capacitor close to the IC to minimize the trace length to the INTVCC pin and also to the IC ground. An internal current limit on the INTVCC output protects the LT3955 from excessive on-chip power dissipation. The INTVCC pin has its own undervoltage disable set to 4.1V (typical) to protect the internal MOSFET from excessive power dissipation caused by not being fully enhanced. If the INTVCC pin drops below the UVLO threshold, the PWMOUT pin will be forced to 0V, the power switch will be turned off and the soft-start pin will be reset. If the input voltage, VIN, will not exceed 8.1V, then the INTVCC pin could be connected to the input supply. Be aware that a small current (less than 13μA) will load the INTVCC in shutdown. This action allows the LT3955 to operate from VIN as low as 4.5V. If VIN is normally above, but occasionally drops below the INTVCC regulation voltage, then the minimum operating VIN will be close to 5V. This value is determined by the dropout voltage of the linear regulator and the INTVCC undervoltage lockout threshold mentioned above. Programming the Turn-On and Turn-Off Thresholds with the EN/UVLO Pin The power supply undervoltage lockout (UVLO) value can be accurately set by the resistor divider to the EN/UVLO pin. A small 2.2μA pull-down current is active when EN/ UVLO is below the threshold. The purpose of this current is to allow the user to program the rising hysteresis. The following equations should be used to determine the value of the resistors: R1+R2 VIN,FALLING = 1.22 • R2 VIN,RISING = 2.2µA •R1+ VIN,FALLING 12 VIN R1 LT3955 EN/UVLO R2 3955 F01 Figure 1. Resistor Connection to Set VIN Undervoltage Shutdown Threshold LED Current Programming The LED current is programmed by placing an appropriate value current sense resistor, RLED, in series with the LED string. The voltage drop across RLED is (Kelvin) sensed by the ISP and ISN pins. A half watt resistor is usually a good choice. To give the best accuracy, sensing of the current should be done at the top of the LED string. If this option is not available then the current may be sensed at the bottom of the string, or in the source of the PWM disconnect NFET driven by the PWMOUT signal. Input bias currents for the ISP and ISN inputs are shown in the typical performance characteristics and should be considered when placing a resistor in series with the ISP or ISN pins. The CTRL pin should be tied to a voltage higher than 1.2V to get the full-scale 250mV (typical) threshold across the sense resistor. The CTRL pin can also be used to dim the LED current to zero, although relative accuracy decreases with the decreasing voltage sense threshold. When the CTRL pin voltage is less than 1V, the LED current is: ILED = VCTRL – 100mV RLED • 4 When the CTRL pin voltage is between 1V and 1.2V the LED current varies with CTRL, but departs from the previous equation by an increasing amount as the CTRL voltage increases. Ultimately, the LED current no longer varies for CTRL ≥ 1.2V. At CTRL = 1.1V, the value of ILED is ~98% of the equation’s estimate. Some values are listed in Table 1. Table 1. (ISP-ISN) Threshold vs CTRL VCRTL (V) (ISP-ISN) Threshold (mV) 1.0 225 1.05 236 1.1 244.5 1.15 248.5 1.2 250 3955fb For more information www.linear.com/LT3955 LT3955 Applications Information When CTRL is higher than 1.2V, the LED current is regulated to: ILED = 250mV RLED The CTRL pin should not be left open (tie to VREF if not used). The CTRL pin can also be used in conjunction with a thermistor to provide overtemperature protection for the LED load, or with a resistor divider to VIN to reduce output power and switching current when VIN is low. The presence of a time varying differential voltage signal (ripple) across ISP and ISN at the switching frequency is expected. The amplitude of this signal is increased by high LED load current, low switching frequency and/or a smaller value output filter capacitor. Some level of ripple signal is acceptable: the compensation capacitor on the VC pin filters the signal so the average difference between ISP and ISN is regulated to the user-programmed value. Ripple voltage amplitude (peak-to-peak) in excess of 50mV should not cause mis-operation, but may lead to noticeable offset between the current regulation and the user-programmed value. These equations assume the inductor value and switching frequency have been selected so that inductor ripple current is ~600mA. Ripple current higher than this value will reduce available output current. Be aware that current limited operation at high duty cycle can greatly increase inductor ripple current, so additional margin may be required at high duty cycle. If some level of analog dimming is acceptable at minimum supply levels, then the CTRL pin can be used with a resistor divider to VIN (as shown on page 1) to provide a higher output current at nominal VIN levels. Programming Output Voltage (Constant Voltage Regulation) or Open LED/Overvoltage Threshold For a boost or SEPIC application, the output voltage can be set by selecting the values of R3 and R4 (see Figure 2) according to the following equation: VOUT = 1.25 • VOUT Output Current Capability FB R4 3955 F02 Figure 2. Feedback Resistor Connection for Boost or SEPIC LED Driver For a boost type LED driver, set the resistor from the output to the FB pin such that the expected voltage level during normal operation will not exceed 1.17V. For an LED driver of buck mode or a buck-boost mode configuration, the output voltage is typically level-shifted to a signal with respect to GND as illustrated in Figure 3. The output can be expressed as: For boost converters: VIN(MIN) VOUT(MAX) For buck mode converters: IOUT(MAX) ≤ 2.5A For SEPIC and buck-boost mode converters: IOUT(MAX) ≤ 2.5A R3 LT3955 An important consideration when using a switch with a fixed current limit is whether the regulator will be able to supply the load at the extremes of input and output voltage range. Several equations are provided to help determine this capability. Some margin to data sheet limits is included. IOUT(MAX) ≤ 2.5A R3 +R4 R4 VIN(MIN) (VOUT(MAX) + VIN(MIN) ) VOUT = VBE + 1.25 • R3 R4 3955fb For more information www.linear.com/LT3955 13 LT3955 Applications Information + RSEN(EXT) VOUT – LT3955 100k LED ARRAY COUT 3955 F03 FB R4 Figure 3. Feedback Resistor Connection for Buck Mode or Buck-Boost Mode LED Driver ISP/ISN Short-Circuit Protection Feature The ISP/ISN pins have a protection feature independent of their LED current sense feature. The purpose of this feature is to prevent the development of excessive currents that could damage the power components or the load. The action threshold (VISP-ISN > 600mV, typical) is above the default LED current sense threshold, so that no interference will occur with current regulation. Exceeding the threshold activates pull-downs on the DIM/SS and PWM pins and causes the power switch to be turned off, and the PWMOUT pin to be driven low for at least 4µs. If an overcurrent condition is sensed at ISP/ISN and the PWM pin is configured either to make an internal dimming signal, or for always-on operation as shown in the application titled Boost LED Driver with Output Short-Circuit Protection, then the LT3955 will enter a hiccup mode of operation. In this mode, after the initial response to the fault, the PWMOUT pin re-enables the output switch at an interval set by the capacitor on the PWM pin. If the fault is still present, the PWMOUT pin will go low after a short delay (typically 7µs) and turn off the output switch. This fault-retry sequence continues until the fault is no longer present in the output. PWM Dimming Control There are two methods to control the current source for dimming using the LT3955. One method uses the CTRL pin to adjust the current regulated in the LEDs. A second method uses the PWM pin to modulate the current source between zero and full current to achieve a precisely programmed average current. To make PWM dimming more accurate, the switch demand current is stored on the VC node during the quiescent phase when PWM is low. This 14 feature minimizes recovery time when the PWM signal goes high. To further improve the recovery time, a disconnect switch may be used in the LED current path to prevent the ISP node from discharging during the PWM signal low phase. The minimum PWM on or off time is affected by choice of operating frequency and external component selection. The best overall combination of PWM and analog dimming capability is available if the minimum PWM pulse is at least six switching cycles. A low duty cycle PWM signal can cause excessive start-up times if it were allowed to interrupt the soft-start sequence. Therefore, once start-up is initiated by PWM > 1.3V, it will ignore a logical disable by the external PWM input signal. The device will continue to soft-start with switching and PWMOUT enabled until either the voltage at SS reaches the 1V level, or the output current reaches one-tenth of the full-scale current. At this point the device will begin following the dimming control as designated by PWM. PWM Dimming Signal Generator The LT3955 features a PWM dimming signal generator with programmable duty cycle. The frequency of the square wave signal at PWMOUT is set by a capacitor CPWM from the PWM pin to GND according to the equation: fPWM = 14kHz • nF/CPWM The duty cycle of the signal at PWMOUT is set by a µA scale current into the DIM/SS pin (see Figure 4). 100 PWMOUT DUTY RATIO (%) R3 CPWM = 47nF 80 60 40 20 0 0 2 4 6 DIM VOLTAGE (V) 8 3955 F04 Figure 4. PWMOUT Duty Ratio vs DIM Voltage for RDIM = 124k 3955fb For more information www.linear.com/LT3955 LT3955 Applications Information Internally generated pull-up and pull-down currents on the PWM pin are used to charge and discharge its capacitor between the high and low thresholds to generate the duty cycle signal. These current signals on the PWM pin are small enough so they can be easily overdriven by a digital signal from a microcontroller to obtain very high dimming performance. The practical minimum duty cycle using the internal signal generator is about 4% if the DIM/ SS pin is used to adjust the dimming ratio. Consult the factory for techniques for and limitations of generating a duty ratio less than 4% using the internal generator. For always on operation, the PWM pin should be connected as shown in the application Boost LED Driver with Output Short-Circuit Protection. Internal PWM Oscillator Operation The PWM oscillator operation is similar to a 555 timer (bistable multi-vibrator). However, the currents that charge and discharge the capacitor are not directly proportional to the controlling current. IPULL-UP = F1(IDIM/SS) = 7.2μA•exp(0.056•IDIM/SS) IPULL-DOWN = F2(IDIM/SS) = 84μA•exp(–0.056•IDIM/SS) The negative sign in the exponential makes IPULL-DOWN decrease when IDIM/SS increases. Voltage on the external cap ramps up at dV/dt = IPULL-UP /CPWM. When the PWM pin reaches the high threshold (0.8V + F3(IDIM/SS)), the flip flop SETs and IPULL-UP goes to zero and current IPULL-DOWN goes to F2(IDIM/SS). T1 T1+ T2 dV T1= ⎛ IPULL−DOWN ⎞ ⎜ ⎟ ⎝ CPWM ⎠ dV T2 = ⎛ IPULL−UP ⎞ ⎜ ⎟ CPWM ⎠ ⎝ Duty Cycle = 0.8V + F3 (IDIM/SS) F1 (IDIM/SS) PWM CPWM 0.8V F2 (IDIM/SS) FAULT – + – + R S Q PWMINT 1.5mA VTH1 = 0.8 + F3 (IDIM/SS) VPWM dV = F3 (IDIM/SS) VTH2 = 0.8V t1 t2 dV/dt = IPULL-UP/CPWM dV/dt = IPULL-DOWN /CPWM VPWMINT 3955 F05 Figure 5. Internal PWM Oscillator Logic and Waveform 3955fb For more information www.linear.com/LT3955 15 LT3955 Applications Information After simplification, one can obtain the formula for duty cycle of PWMOUT as a function of IDIM/SS: Duty Cycle = 1 1+ 11.6 • exp(−0.112 •IDIM/SS ) To calculate the duty cycle of the internal PWM generator given a voltage of the DIM signal, determine first the current into the DIM/SS pin by the equation (referring to Figure 6): IDIM/SS = VDIM − 1.17V in µA RDIM + 2.5kΩ Knowing the IDIM/SS in μA , the duty cycle of the PWMOUT pin can be calculated for the range –10μA < IDIM/SS < 55μA: Duty (in%) = 100% 1+ 11.6 • exp(−0.112 •IDIM/SS ) cycle that is lower than range attainable using DIM/SS current. A resistor, RPD, and switch driven by PWMOUT can be added as shown in Figure 7. The addition of this resistor increases the pull-down current on PWM, thus decreasing the duration of the onphase of the switching regulator. Since PWM frequency at low duty cycle is primarily determined by the pull-up current, the additional pull-down current from RPD has little effect on the PWM period, so frequency calculation remains the same. An example solving for RPD given a 1% duty cycle is provided below. For this example, the IDIM/SS current flowing in RDIM is assumed zero, which normally provides an ~8% duty cycle. The average voltage on the PWM pin is approximately 1.05V at this IDIM/SS setting. Duty = These equations can be worked in reverse starting with a desired duty cycle using 20%, for example, and solving for a resistor value, RDIM, placed between VREF and DIM/SS: ⎛ Duty ⎞ ⎟ IDIM/SS = 8.93 • ln ⎜⎜11.6 • (1−Duty ) ⎟⎠ ⎝ ⎛ 0.2 ⎞ = 8.93 • ln ⎜11.6 • ⎟ = 9.51µA ⎝ 0.8 ⎠ VREF − 1.17 RDIM = −2.5kΩ + IDIM/SS = −2.5kΩ + 2.015 − 1.17 = 86.4kΩ 0.00951 For some applications, a duty cycle lower than 3% is desired. It is possible to achieve a discrete value of duty = IPULL−UP IPULL−UP +IPULL−DOWN +IRPD 7.2 = 0.01 7.2+ 84+IRPD IRPD = 629µA = 1.05V RPD Therefore, RPD ~ 1.65kΩ Programming the Switching Frequency The RT frequency adjust pin allows the user to program the switching frequency (fSW) from 100kHz to 1MHz to optimize efficiency/performance or external component size. Higher frequency operation yields smaller component size but increases switching losses and gate driving current, and may not allow sufficiently high or low duty LT3955 LT3955 DIM RDIM PWMOUT DIM/SS DIM PWM RDIM PWMOUT DIM/SS 10nF PWM GND GND 47nF 300Hz 10nF RPD 47nF 300Hz 3955 F06 3955 F07 Figure 6. Configuration of Dimming Resistor, RDIM 16 Figure 7. Configuration for Sub 4% PWM Dimming 3955fb For more information www.linear.com/LT3955 LT3955 Applications Information Table 2. Switching Frequency (fSW) vs RT Value 200 150 SW MINIMUM OFF-TIME 100 100 95.3 200 48.7 300 33.2 400 25.5 500 20.5 600 16.9 700 14.3 800 12.1 Thermal Considerations 900 10.7 1000 8.87 The LT3955 is rated to a maximum input voltage of 60V. Careful attention must be paid to the internal power dissipation of the IC at higher input voltages to ensure that a junction temperature of 125°C is not exceeded. This junction limit is especially important when operating at high ambient temperatures. If LT3955 junction temperature reaches 165°C, the power switch will be turned off and the PWMOUT pin will be driven to GND and the soft-start (DIM/SS) pin will be discharged to GND. Switching will be enabled after device temperature is reduced 10°C. This function is intended to protect the device during momentary thermal overload conditions. Min Duty Cycle = 220ns • fSW Max Duty Cycle = 1 – 170ns • fSW Besides the limitation by the minimum off-time, it is also recommended to choose the maximum duty cycle below 95%. SW MINIMUM ON-TIME RT (kΩ) Switching duty cycle is a key variable defining converter operation, therefore, its limits must be considered when programming the switching frequency for a particular application. The minimum duty cycle of the switch is limited by the fixed minimum on-time and the switching frequency (fSW). The maximum duty cycle of the switch is limited by the fixed minimum off-time and fSW. The following equations express the minimum/maximum duty cycle: 250 fSW (kHz) Duty Cycle Considerations 300 TIME (ns) cycle operation. Lower frequency operation gives better performance at the cost of larger external component size. For an appropriate RT resistor value see Table 2. An external resistor from the RT pin to GND is required—do not leave this pin open. DBOOST = VLED - VIN VLED DBUCK_MODE = DSEPIC , DCUK = VLED VIN VLED VLED + VIN 50 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3955 F08 Figure 8. Typical Switch Minimum On and Off Pulse Width vs Temperature The major contributors to internal power dissipation are the current in the linear regulator to drive the switch, and the ohmic losses in the switch. The linear regulator power is proportional to VIN and switching frequency, so at high VIN the switching frequency should be chosen carefully to ensure that the IC does not exceed a safe junction temperature. The internal junction temperature of the IC can be estimated by: TJ = TA + [VIN • (IQ + fSW • 7nC) + ISW2 • 0.14Ω • DSW] • θJA where TA is the ambient temperature, IQ is the quiescent current of the part (maximum 2.2mA) and θJA is the package thermal impedance (34°C/W for the 5mm × 6mm QFN package). For example, an application with TA(MAX) = 85°C, VIN(MAX) = 60V, fSW = 400kHz, and having an 3955fb For more information www.linear.com/LT3955 17 LT3955 Applications Information average switching current of 2.5A at 70% duty cycle, the maximum IC junction temperature will be approximately: TJ = 85°C + [(2.5A)2 • 0.14Ω • 0.7 + 60V • (2.2mA + 400kHz • 7nC)] • 34°C/W= 116°C The exposed pad on the bottom of the package must be soldered to a ground plane. This ground should then be connected to an internal copper ground plane with thermal vias placed directly under the package to spread out the heat dissipated by the IC. Open LED Reporting – Constant Voltage Regulation Status Pin The LT3955 provides an open-drain status pin, VMODE, that pulls low when the FB pin is within 50mV of its 1.25V regulated voltage AND output current sensed by VISP-ISN has reduced to 25mV, or 10% of the full-scale value. The 10% output current qualification (C/10) is unique for an LED driver but fully compatible with open LED indication – the qualification is always satisfied since for an open load zero current flows in the load. The C/10 feature is particularly useful in the case where VMODE is used to indicate the end of a battery charging cycle and terminate charging or transition to a float charge mode. For monitoring the LED string voltage, if the open LED clamp voltage is programmed correctly using the FB resistor divider then the FB pin should not exceed 1.18V when LEDs are connected. If the VMODE pull-down is asserted when the PWM pin transitions low, the pull-down will continue to be asserted until the next rising edge of PWM even if FB falls below the VMODE threshold. Figure 9 shows the VMODE logic block diagram. Input Capacitor Selection The input capacitor supplies the transient input current for the power inductor of the converter and must be placed and sized according to the transient current requirements. The switching frequency, output current and tolerable input voltage ripple are key inputs to estimating the capacitor value. An X7R type ceramic capacitor is usually the best choice since it has the least variation with temperature and DC bias. Typically, boost and SEPIC converters require a lower value capacitor than a buck mode converter. Assuming that a 100mV input voltage ripple is acceptable, the required capacitor value for a boost converter can be estimated as follows: ILED ISP RLED VMODE 25mV + – ISN – C/10 COMPARATOR + S Q 1mA R 1.2V FB OPEN LED COMPARATOR Therefore, a 10μF capacitor is an appropriate selection for a 400kHz boost regulator with 12V input, 48V output and 1A load. With the same VIN voltage ripple of 100mV, the input capacitor for a buck converter can be estimated as follows: A 10μF input capacitor is an appropriate selection for a 400kHz buck mode converter with a 1A load. PWM 1. VMODE ASSERTS WHEN VISP-ISN < 25mV AND FB > 1.2V, AND IS LATCHED 2. VMODE DE-ASSERTS WHEN FB < 1.19V, AND PWM = LOGIC “1” 3. ANY FAULT CONDITION RESETS THE LATCH, SO LT3955 STARTS UP WITH VMODE DE-ASSERTED Figure 9. VMODE (CV Mode) Logic Block Diagram 18 ⎛ µF ⎞ VOUT • t SW (µs) • ⎜ ⎟ VIN ⎝ A • µs ⎠ ⎛ µF ⎞ CIN (µF) = ILED (A) • t SW (µs) • 4.7 • ⎜ ⎟ ⎝ A • µs ⎠ – + CIN (µF) = ILED (A) • 3955 F09 In the buck mode configuration, the input capacitor has large pulsed currents due to the current returned through the Schottky diode when the switch is off. In this buck converter case it is important to place the capacitor as close as possible to the Schottky diode and to the GND return of the switch (i.e., the sense resistor). It is also important to consider the ripple current rating of the capacitor. For 3955fb For more information www.linear.com/LT3955 LT3955 Applications Information best reliability, this capacitor should have low ESR and ESL and have an adequate ripple current rating. Table 3. Recommended Ceramic Capacitor Manufacturers MANUFACTURER WEB TDK www.tdk.com Kemet www.kemet.com Murata www.murata.com Taiyo Yuden www.t-yuden.com Output Capacitor Selection The selection of the output capacitor depends on the load and converter configuration, i.e., step-up or step-down and the operating frequency. For LED applications, the equivalent resistance of the LED is typically low and the output filter capacitor should be sized to attenuate the current ripple. Use of X7R type ceramic capacitors is recommended. To achieve the same LED ripple current, the required filter capacitor is larger in the boost and buck-boost mode applications than that in the buck mode applications. Lower operating frequencies will require proportionately higher capacitor values. Soft-Start Capacitor Selection For many applications, it is important to minimize the inrush current at start-up. The built-in soft-start circuit significantly reduces the start-up current spike and output voltage overshoot. Connect a capacitor from the DIM/SS pin to GND to use this feature. The soft-start interval is set by the soft-start capacitor selection according to the equation: The soft-start capacitor discharges if one of the following events occurs: the EN/UVLO falls below its threshold; output overcurrent is detected at the ISP/ISN pins; IC overtemperature; or INTVCC undervoltage. During startup with EN/UVLO, charging of the soft-start capacitor is enabled after the first PWM high period. In the start-up sequence, after switching is enabled by PWM the switching continues until VISP-ISN > 25mV or DIM/SS > 1V. PWM pin negative edges during this start-up interval are not processed until one of these two conditions are met so that the regulator can reach steady state operation shortly after PWM dimming commences. Schottky Rectifier Selection The power Schottky diode conducts current during the interval when the switch is turned off. Select a diode rated for the maximum SW voltage of the application and the RMS diode current. If using the PWM feature for dimming, it may be important to consider diode leakage, which increases with the temperature, from the output during the PWM low interval. Therefore, choose the Schottky diode with sufficiently low leakage current. Table 4 has some recommended component vendors. The diode current and VF should be considered when selecting the diode to be sure that power dissipation does not exceed the rating of the diode. The power dissipated by the diode in a converter is: PD = ID • VF • (1-DMAX) It is prudent to measure the diode temperature in steady state to ensure that its absolute maximum ratings are not exceeded. Table 4. Schottky Rectifier Manufacturers 1.2V 100µs TSS = CSS • = CSS • 12µA nF MANUFACTURER WEB On Semiconductor www.onsemi.com Central Semiconductor www.centralsemi.com provided there is no additional current supplied to the DIM/SS pin for programming the duty cycle of the PWM dimming signal generator. A typical value for the soft-start capacitor is 10nF which gives a 1ms start-up interval. The soft-start pin reduces the oscillator frequency and the maximum current in the switch. Diodes, Inc. www.diodes.com Inductor Selection The inductor used with the LT3955 should have a saturation current rating appropriate to the maximum switch current of 4.9A. Choose an inductor value based on operating 3955fb For more information www.linear.com/LT3955 19 LT3955 Applications Information frequency, input and output voltage to provide a current mode signal of approximately 0.6A magnitude. The following equations are useful to estimate the inductor value for continuous conduction mode operation (use the minimum value for VIN and maximum value for VLED): LBUCK = VLED ( VIN – VLED ) VIN • 0.6A • fOSC LBUCK-BOOST = LBOOST = VLED • VIN ( VLED + VIN ) • 0.6A • fOSC VIN ( VLED – VIN) VLED • 0.6A • fOSC Use the equation for Buck-Boost when choosing an inductor value for SEPIC – if the SEPIC inductor is coupled, then the equation’s result can be used as is. If the SEPIC uses two uncoupled inductors, then each should have a inductance double the result of the equation. Table 5 provides some recommended inductor vendors. Table 5. Recommended Inductor Manufacturers MANUFACTURER WEB Coilcraft www.coilcraft.com Cooper-Coiltronics www.cooperet.com Würth-Midcom www.we-online.com Vishay www.vishay.com Loop Compensation The LT3955 uses an internal transconductance error amplifier whose VC output compensates the control loop. The external inductor, output capacitor and the compensation resistor and capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size and cost. The compensation resistor and capacitor at VC are selected to optimize control loop response and stability. For typical LED applications, a 4.7nF compensation capacitor at VC is adequate, and a series 20 resistor should always be used to increase the slew rate on the VC pin to maintain tighter regulation of LED current during fast transients on the input supply to the converter. Disconnect Switch Selection An NMOS in series with the LED string at the cathode is recommended in most LT3955 applications to improve the PWM dimming. The NMOS BVDSS rating should be as high as the open LED regulation voltage set by the FB pin, which is typically the same rating as the power switch of the converter. The maximum continuous drain current ID(MAX) rating should be higher than the maximum LED current. A PMOS high side disconnect is needed for buck mode, buck-boost mode or an output short circuit protected boost. A level shift to drive the PMOS switch is shown in the application schematic Boost LED Driver with Output Short Circuit Protection. In the case of a high side disconnect follow the same guidelines as for the NMOS regarding voltage and current ratings. It is important to include a bypass diode to GND at the drain of the PMOS switch to ensure that the voltage rating of this switch is not exceeded during transient fault events. The DC-Coupling Capacitor Selection for SEPIC LED Driver The DC voltage rating of the DC-coupling capacitor CDC connected between the primary and secondary inductors of a SEPIC should be larger than the maximum input voltage: VCDC > VIN(MAX) CDC has nearly a rectangular current waveform. During the switch off-time, the current through CDC is IVIN, while approximately –ILED flows during the on-time. The CDC voltage ripple causes current distortions on the primary and secondary inductors. The CDC should be sized to limit its voltage ripple. The power loss on the CDC ESR reduces the LED driver efficiency. Therefore, the sufficient low ESR ceramic capacitors should be selected. The X5R or X7R ceramic capacitor is recommended for CDC. 3955fb For more information www.linear.com/LT3955 LT3955 Applications Information Short-Circuit Protection for a Boosted Output The LT3955 has two features that provide protection from a shorted circuit load on a boost. The first of these is the ISP/ISN based overcurrent response. The second is the FB overvoltage response. The primary mode of action for both features is to drive the PWMOUT pin low, which turns off the switch connecting the output to the load. The ISP/ISN shortcircuit protection also drives the PWM and DIM/SS pins low for a brief period of time. For best protection, a PMOS disconnect switch M1 is placed as shown in Figure 10. During an overcurrent event caused by a short across the LED string, the current in Rs increases until PNP Q1 turns on and pulls up the gate of M1, throttling back the current. In approximately 1µs, the ISP/ISN overcurrent response will cause the PWMOUT pin to drive low, which will turn off M1 altogether. If an external PWM signal is used, then the circuit including Q3, the 1N4148 diode and two resistors must be used to ensure the switch remains off while the output is in a faulted state. This sub-circuit drives the FB pin into the overvoltage state. If the PWM pin is configured (with a capacitor load) as shown in the application titled Boost LED Driver with Output Short Protection, then the small circuit driving FB may be omitted. In this case, the boost converter will demonstrate a hiccup mode response, turning on M1 at an interval determined by the PWM capacitor, then turning off after ~1µs due to excessive current, until the fault clears. RS 0.5Ω D1 COUT PGND LT3955 1k Q1 2k ISP M1 ISN 0.15nF 1M PWMOUT 20k Q2 FB Q3 24.9k GND INTVCC INTVCC 1µF 2.2k 27k 1N4148 1k D2 3955 F10 Figure 10. Protection Circuit for Fault to Ground on LED Load. Includes Fast Level Shift for PWM Switch M1 3955fb For more information www.linear.com/LT3955 21 LT3955 Applications Information CSS CTRL VMODE The high speed operation of the LT3955 demands careful attention to board layout and component placement. The exposed pads of the package are important for thermal management of the IC. It is crucial to achieve a good electrical and thermal contact between the GND exposed pad and the ground plane of the board. To reduce electromagnetic interference (EMI), it is important to minimize the area of the high dV/dt switching node between the inductor, SW pin and anode of the Schottky rectifier. Use a ground plane under the switching node to eliminate interplane coupling to sensitive signals. The lengths of the high dI/dt traces from the switch node through the Schottky rectifier and filter capacitor to PGND, should be minimized. The output capacitors should terminate as close as possible to the PGND pins. The PGND and GND planes on the PCB should not be connected together. Instead, a single pin named GNDK (Pin 12) should be connected to the GND plane and pins through vias. This pin is internally attached to the PGND pins, but provides a proper connection between the GND and PGND pins when the IC is placed on the PCB, as shown in the suggested layout (Figure 11). Likewise, the ground terminal of the bypass capacitor for the INTVCC regulator should be placed near the GND of the IC. The ground for the compensation network and other DC control signals should be star connected to the GND Exposed Pad of the IC. Do not extensively route high impedance signals such as FB and VC, as they may pick up switching noise. Since there is a small variable DC input bias current to the ISN and ISP inputs, resistance in series with these pins should be minimized to avoid creating an offset in the current sense threshold. PWM Board Layout RT 1 28 LT3955 2 CVCC 27 VIA FROM LED+ LED– 3 3 4 R1 R2 25 VIN R4 R3 M1 24 GND VIAS TO SW PLANE VIA FROM VOUT 36 35 34 33 32 31 30 VIA FROM PWMOUT VIAS TO GND PLANE CC RC 6 1 23 2 PWMOUT VIA 8 VIAS FROM PGND 21 9 20 SW 10 12 13 14 15 16 17 PGND VIAS L1 D1 COUT COUT RS CVIN VIN PGND VOUT LED+ VIA VIA LED+ 3955 F07 Figure 11. Boost Converter Suggested Layout 22 3955fb For more information www.linear.com/LT3955 LT3955 Typical Applications 94% Efficiency 20W Boost LED Driver with Internal PWM Dimming L1 22µH VIN 5V TO 60V CVIN 4.7µF ×2 100V R1 499k VIN INTVCC 100k 124k 10nF RS 0.82Ω LT3955 165k DIM PGND ISP VREF 1M COUT 2.2µF ×5 100V SW EN/UVLO R2 147k D1 RT 28.7k 350kHz CTRL 300mA ISN R3 1M FB VMODE DIM/SS SYNC PWM RT PWMOUT VC GND GNDK INTVCC RC 5.1k 47nF CC 300Hz 4.7nF 20W LED STRING (CURRENT DERATED FOR VIN < 9V) R4 16.9k INTVCC CVCC 1µF M1 3955 TA02a M1: VISHAY Si2328DS L1: TDK SLF12575-220M4R0 D1: DIODES PDS3100 Boost Efficiency, Output Current vs VIN 0.9 98 0.6 92 89 0.3 86 OUTPUT CURRENT (A) EFFICIENCY (%) 95 83 80 4 12 20 28 36 VIN (V) 44 52 0 60 3955 TA02b 3955fb For more information www.linear.com/LT3955 23 LT3955 Typical Applications Boost LED Driver with Output Short-Circuit Protection with Internally Generated PWM VIN 6V TO 40V L1 22µH 2.2µF 50V ×2 499k VIN PGND 2.4k ISP VREF 1M 2.2µF 100V ×2 SW EN/UVLO 107k D1 LT3955 121k 0.5Ω CTRL INTVCC ISN 1M 100k OPTION FOR INTERNAL PWM DIMMING 47nF 10nF M1 24.9k SYNC PWMOUT INTVCC DIM/SS VC GND GNDK RT 124k 1k Q2 FB VMODE PWM DIM 500mA 20k LED+ D2 INTVCC 28.7k 350kHz 5.1k Q1 20W LED STRING 1k 1µF 4.7nF 3955 TA03a 1N4148 28k M1: VISHAY Si7113DN L1: COILTRONICS DR125-220-R D1: DIODES PDS3100 D2: VISHAY 10BQ100 Q1: ZETEX FMMT493 Q2: ZETEX FMMT 593 OPTIONAL CIRCUIT FOR ALWAYS-ON OPERATION PWM Dimming Waveform Waveform for LED Shorted to GND VIN = 24V, DIM = 0V PWMOUT 5V/DIV DIM = 8V PWMOUT 10V/DIV ILED 0.5A/DIV VLED+ 20V/DIV ILED 0.2A/DIV 1ms/DIV 24 3955 TA03b 20µs/DIV 3955 TA03c 3955fb For more information www.linear.com/LT3955 LT3955 Typical Applications 60W Buck Mode LED Driver VIN 48V TO 60V 787k VIN 237k ISP EN/UVLO 750Ω INTVCC LT3955 VMODE 0.1µF 200k Q1 4.7µF 50V X7R ×4 M1 VREF SYNC CTRL PWMOUT 60W LED STRING Q2 PWM DIM/SS 28.7k 350kHz 1.4A ISN FB 100k 20k 0.176Ω 200k 1k L1 33µH SW RT PGND VC GND GNDK INTVCC 15k D1 2.2µF 100V X7R ×4 INTVCC 1µF 4.7nF 14k VIN 3955 TA04a M1: VISHAY SILICONIX Si7461DP L1: WÜRTH ELEKTRONIK 744066330 D1: VISHAY 10MQ100N Q1: ZETEX FMMT593 Q2: ZETEX FMMT493 Efficiency vs VIN 100 EFFICIENCY (%) 98 96 94 92 90 48 50 52 54 VIN (V) 56 58 60 3955 TA04b 3955fb For more information www.linear.com/LT3955 25 LT3955 Typical Applications Boost LED Driver with Output Short-Circuit Protection with Externally Driven PWM VIN 8V TO 40V D1 L1, 10µH 2.2µF 50V ×2 499k VIN SW PGND EN/UVLO 90.9k 0.5Ω 2.2µF 100V ×4 VREF 1M CTRL LT3955 INTVCC 100k ISP Q1 M1 ISN 150pF 1M SYNC PWMOUT VMODE 1k 2.4k 20k 140k Q2 FB PWM DIM/SS Q3 24.9k INTVCC GND GNDK RT VC 10nF 500mA 5.1k 4.7nF INTVCC 2.2k 1µF 27k 1k 1N4148 28.7k 350kHz D2 SHORT-CIRCUIT DETECTOR 20W LED STRING 3955 TA07a M1: VISHAY SILICONIX Si7309DN L1: COILTRONICS DR127-100 D1: DIODES PDS3100 D2: VISHAY 10BQ100 Q1, Q3: ZETEX FMMT 593 Q2: ZETEX FMMT 493 Waveform for LED Shorted to GND VPWM 5V/DIV PWM Dimming Waveform PWM 2.5V/DIV VSW 20V/DIV LED STRING SHORTED ID(M1) 0.5A/DIV VIN = 24V 26 100µs/DIV ILED 0.2A/DIV 3955 TA07b 20µs/DIV 3955 TA07c 3955fb For more information www.linear.com/LT3955 LT3955 Typical Applications 10W SEPIC LED Driver 3 2.2µF 50V 1 D1 • VIN 6V TO 40V L1, 22µH 1:1 2.2µF 50V ×2 499k VIN •2 SW 10µF 25V 4 ×2 EN/UVLO VREF 1M 107k INTVCC CTRL LT3955 1M PGND 500mA 47.5k 121k 100k 0.5Ω FB VMODE PWM DIM/SS VC 10nF 10k ISP ISN 10W LED STRING PWMOUT SYNC INTVCC GND GNDK RT INTVCC 1µF 28.7k 350kHz 4.7nF M1 3955 TA05a M1: VISHAY Si2306BD L1: COILTRONICS DRQ127-220-R D1: DIODES PDS3100 3000:1 PWM Dimming at 120Hz 95 0.8 90 0.7 85 0.6 80 0.5 75 0.4 70 5 10 15 20 25 VIN (V) 30 35 40 PWM 5V/DIV OUTPUT CURRENT (A) EFFICIENCY (%) Efficiency vs VIN ILED 0.2A/DIV VIN = 24V 1µs/DIV 3955 TA05c 0.3 3955 TA05b 3955fb For more information www.linear.com/LT3955 27 LT3955 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHE Package Variation: UHE36(28)MA 36(28)-Lead Plastic QFN (5mm × 6mm) (Reference LTC DWG # 05-08-1836 Rev D) 28 27 25 24 23 21 20 0.70 ±0.05 30 1.88 ± 0.05 31 5.50 ± 0.05 4.10 ± 0.05 1.50 REF 3.00 ± 0.05 32 33 16 3.00 ± 0.05 0.12 ± 0.05 34 17 1.53 ± 0.05 15 14 PACKAGE OUTLINE 13 0.48 ± 0.05 12 35 36 1 2 3 4 6 0.50 BSC 8 9 0.25 ±0.05 10 2.00 REF 5.10 ± 0.05 6.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 0.75 ± 0.05 R = 0.10 TYP PIN 1 TOP MARK (NOTE 6) 30 31 32 1.50 REF 33 34 35 28 1 27 1.88 ± 0.10 3.00 ± 0.10 0.12 ± 0.10 2.00 REF 25 24 6.00 ± 0.10 36 PIN 1 NOTCH R = 0.30 OR 0.35 × 45° CHAMFER 2 3 4 6 23 1.53 ± 0.10 21 0.48 ± 0.10 3.00 ± 0.10 20 8 R = 0.125 TYP 9 10 0.40 ± 0.10 17 16 15 0.25 ± 0.05 0.50 BSC 0.200 REF 0.00 – 0.05 14 13 12 (UHE36(28)MA) QFN 0112 REV D BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 28 3955fb For more information www.linear.com/LT3955 LT3955 Revision History REV DATE DESCRIPTION A 11/14 Clarified the ISP/ISN Input Bias Current graph PAGE NUMBER Clarified the Pin Functions description 9 Added Internal PWM Oscillator section 15 Added Short-Circuit Protection in the Boosted Output section 21 Clarified Typical Applications B 6/15 7 23-27 Clarified Electrical Characteristics 4 Clarified V(ISP-ISN) Threshold vs FB Voltage Graph 5 Clarified Graphs 7 Moved Pin Functions 8 3955fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LT3955 29 LT3955 Typical Application Solar Panel SEPIC Battery Charger WÜRTH SOLAR PANEL VOC = 37.5V VMPP = 28V 23W VIN 2.2µF 50V L1A, 33µH 1:1 D1 OUT VCHARGE = 14.3V VFLOAT = 13.3V AT 25°C BAT 250mΩ + • 300k 475k VIN SW EN/UVLO LT3955 INTVCC 10µF 25V 30.1k PGND ISP ISN 93.1k VREF 158k 113k M1 VMODE PWM DIM/SS 0.1µF VC OUT BAT INTVCC GND GNDK RT 499k 49.9k 1µF 1.0 0.8 0.6 0.4 0 28.7k 350kHz 10nF NOTE: GND, GNDK AND SIGNAL LEVEL COMPONENTS MUST BE CONNECTED EXTERNALLY AS SHOWN. AN INTERNAL CONNECTION BETWEEN GNDK AND PGND PINS PROVIDES GROUNDING TO THE SUPPLY. 20 24 28 32 VIN (V) 36 40 3955 TA06c Battery Charger Waveforms 3955 TA06a M1: ZETEX ZXM61N03F L1: COILTRONICS DRQ127-330-R D1: ON SEMI MBRS260T3G Q1: ZETEX FMMT593 IBAT vs VIN 1.2 0.2 10.5k INTVCC BAT 10k NTC FB CTRL 100k L1B PWMOUT SYNC 24.9k Q1 • CHARGING CURRENT (A) 4.7µF 50V VBAT 10V/DIV CURRENT HITS C/10 BATTERY IS HELD AT FLOAT VOLTAGE THE PART IS IBAT TURNED ON 0.33A/DIV VMODE 10V/DIV 10ms/DIV 3955 TA06b NOTE: WAVEFORMS SHOWN AS TESTED WITH 5Ω IN SERIES WITH 2mF CAPACITIVE LOAD. Related Parts PART NUMBER LT3954 LT3956 DESCRIPTION High Side 40V, 5A, 1MHz LED Driver with 3,000:1 PWM Dimming and Internal PWM Generator High Side 80V, 3.5A, 1MHz LED Driver with 3,000:1 PWM Dimming LT3761 High Side 100V, 1MHz LED Controller with 3,000:1 PWM Dimming and Internal PWM Generator LT3791/LT3791-1 60V, Synchronous Buck-Boost 1MHz LED Controller High Side 60V, 1MHz LED Controller with True Color 3,000:1 PWM Dimming High Side 100V, 1MHz LED Controller with 3,000:1 PWM Dimming, Input/Output Current Limit Synchronous Step-Down 20A LED Driver with Three-State LED Current Control LT3796/LT3796-1 High Side 100V, 1MHz LED Controller with True Color 3,000:1 PWM Dimming LT3755/LT3755-1 LT3755-2 LT3756/LT3756-1 LT3756-2 LT3743 30 Linear Technology Corporation COMMENTS VIN: 4.5V to 40V, VOUT(MAX) = 40V, 3000:1 True Color PWM, Analog, ISD < 1µA, 5mm × 6mm QFN-36 VIN: 6V to 80V, VOUT(MAX) = 80V, 3000:1 True Color PWM, Analog, ISD < 1µA, 5mm × 6mm QFN-36 VIN: 4.5V to 60V, VOUT(MAX) = 80V, 3000:1 True Color PWM, Analog, ISD < 1µA, MSOP-16E VIN: 4.7V to 60V, VOUT: 0V to 60V, 100:1 True Color PWM, Analog, ISD < 1µA, TSSOP-38E VIN: 4.5V to 40V, VOUT: 5V to 60V, 3,000:1 True Color PWM, Analog, ISD < 1µA, 3mm × 3mm QFN-16, MSOP-16E VIN: 6V to 100V, VOUT: 5V to 100V, 3,000:1 True Color PWM, Analog, ISD < 1µA, 3mm × 3mm QFN-16, MSOP-16E VIN: 5.5V to 36V, VOUT: 5.5V to 35V, 3,000:1 True Color PWM, Analog, ISD < 1µA, 4mm × 5mm QFN-28, TSSOP-28E VIN: 6V to 100V, VOUT(MAX) = 100V, 3000:1 True Color PWM, Analog, ISD < 1µA, TSSOP-28E 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT3955 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3955 3955fb LT 0615 REV B • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014