MCP48FEBXX
8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile
Digital-to-Analog Converters with SPI Interface
Features
• Operating Voltage Range:
- 2.7V to 5.5V - full specifications
- 1.8V to 2.7V - reduced device specifications
• Output Voltage Resolutions:
- 8-bit: MCP48FEB0X (256 Steps)
- 10-bit: MCP48FEB1X (1024 Steps)
- 12-bit: MCP48FEB2X (4096 Steps)
• Rail-to-Rail Output
• Fast Settling Time of 7.8 µs (typical)
• DAC Voltage Reference Source Options:
- Device VDD
- External VREF pin (buffered or unbuffered)
- Internal Band Gap (1.22V typical)
• Output Gain Options:
- Unity (1x)
- 2x
• Nonvolatile Memory (EEPROM):
- User-programmed Power-on Reset
(POR)/Brown-out Reset (BOR) output
setting, recall and device configuration bits
- Auto Recall of Saved DAC register setting
- Auto Recall of Saved Device Configuration
(Voltage Reference, Gain, Power-Down)
• Power-on/Brown-out Reset Protection
• Power-Down Modes:
- Disconnects output buffer (High Impedance)
- Selection of VOUT pull-down resistors
(100 k or 1 k)
• Low Power Consumption:
- Normal operation: <180 µA (Single),
380 µA (Dual)
- Power-down operation: 650 nA typical
- EEPROM write cycle (1.9 mA maximum)
• SPI Interface:
- Supports ‘00’ and ‘11’ modes
- Up to 20 MHz writes and 10 MHz reads
- Input buffers support interfacing to
low-voltage digital devices
• Package Types: 10-lead MSOP
• Extended Temperature Range: -40°C to +125°C
2015 Microchip Technology Inc.
Package Types
MCP48FEBx1
MSOP
Single
VDD
1
2
VREF0 3
VOUT0 4
NC 5
CS
10 SDI
9 SCK
8 SDO
7 VSS
6 LAT0/HVC
MCP48FEBx2
MSOP
Dual
VDD
CS
VREF(1)
VOUT0
VOUT1
1
2
3
4
5
10 SDI
9 SCK
8 SDO
7 VSS
6 LAT0/HVC (1)
Note 1: Associated with both DAC0 and DAC1
General Description
The MCP48FEBXX are Single- and Dual-channel 8-bit,
10-bit, and 12-bit buffered voltage output
Digital-to-Analog Converters (DAC) with nonvolatile
memory and an SPI serial interface.
The VREF pin, the device VDD or the internal band gap
voltage can be selected as the DAC’s reference
voltage. When VDD is selected, VDD is connected
internally to the DAC reference circuit. When the VREF
pin is used, the user can select the output buffer’s gain
to be 1 or 2. When the gain is 2, the VREF pin voltage
should be limited to a maximum of VDD/2.
These devices have an SPI-compatible serial interface.
Write commands are supported up to 20 MHz while
read commands are supported up to 10 MHz.
Applications
•
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Low-Power Portable Instrumentation
PC Peripherals
Data Acquisition Systems
Motor Control
DS20005429B-page 1
MCP48FEBXX
MCP48FEBX1 Device Block Diagram (Single-Channel Output)
Power-up/
Brown-out Control
Memory (32x16)
SDI
SDO
SCK
CS
SPI Serial Interface Module
and
Control Logic
(WiperLock™ Technology)
VREF1:VREF0
and PD1:PD0
Band Gap
(1.22V)
DAC0 (Vol and NV)
VREF (Vol and NV)
Power-down (Vol and NV)
Gain (Vol and NV)
Status (Vol)
VDD
VREF0
+ (1)
-
PD1:PD0
VSS
VREF1:VREF0
Resistor
Ladder
VDD
LAT0/HVC
Gain
PD1:PD0 and
VREF1:VREF0
VBG
Op
Amp
VOUT0
PD1:PD0
100 k
VSS
1 k
VDD
Note 1: If Internal Band Gap is selected, this buffer has a 2x gain. If the G bit = ‘1’, this is a total gain of 4.
DS20005429B-page 2
2015 Microchip Technology Inc.
MCP48FEBXX
MCP48FEBX2 Device Block Diagram (Dual-Channel Output)
SDI
SDO
SCK
CS
Power-up/
Brown-out Control
VREF1:VREF0
and PD1:PD0
VREF
Memory (32x16)
DAC0 and 1 (Vol & NV)
VREF (Vol and NV)
Power-down (Vol and NV)
Gain (Vol and NV)
Status (Vol)
SPI Serial Interface Module
and
Control Logic
(WiperLock™ Technology)
Band Gap
(1.22V)
VDD
Gain
PD1:PD0 and
VREF1:VREF0
VBG
Op
Amp
VOUT0
PD1:PD0
+ (1)
-
VSS
VREF1:VREF0
LAT/HVC
Resistor
Ladder
VDD
PD1:PD0
VREF1:VREF0
and PD1:PD0 V
100 k
VSS
1 k
VDD
Gain
DD
+ (1)
-
PD1:PD0
VSS
VREF1:VREF0
Resistor
Ladder
VDD
VOUT1
PD1:PD0
100 k
intVR1
Op
Amp
1 k
PD1:PD0 and
VREF1:VREF0
Band Gap
(1.22V)
Note 1: If Internal Band Gap is selected, this buffer has a 2x gain, if the G bit = ‘1’, this is a total gain of 4.
2015 Microchip Technology Inc.
DS20005429B-page 3
MCP48FEBXX
Control
Interface
DAC Output
POR/BOR
Setting (1)
MCP48FEB01
Resolution
(bits)
Device
# of
Channels
Device Features
# of
VREF
Inputs
1
8
SPI
7Fh
1
Internal # of
band
LAT
gap ? Inputs
Memory
Specified
Operating Range
(VDD) (2)
Yes
1
EEPROM
1.8V to 5.5V
MCP48FEB11
1
10
SPI
1FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP48FEB21
1
12
SPI
7FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP48FEB02
2
8
SPI
7Fh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP48FEB12
2
10
SPI
1FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP48FEB22
2
12
SPI
7FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FVB01
1
8
I2C™
7Fh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FVB11
1
10
I2C
1FFh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FVB21
1
12
I2C
7FFh
1
Yes
1
RAM
1.8V to 5.5V
2
MCP47FVB02
2
8
I C
7Fh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FVB12
2
10
I2C
1FFh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FVB22
2
12
I2C
7FFh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FEB01
1
8
I2C
7Fh
1
Yes
1
EEPROM
1.8V to 5.5V
1FFh
1
Yes
1
EEPROM
1.8V to 5.5V
7FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FEB11
1
10
I2C
MCP47FEB21
1
12
I2C
MCP47FEB02
2
8
I2C
7Fh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FEB12
2
10
I2C
1FFh
1
Yes
1
EEPROM
1.8V to 5.5V
12
I2C
7FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FEB22
Note 1:
2:
2
Factory Default value. The DAC output POR/BOR value can be modified via the nonvolatile DAC output
register(s) (available only on nonvolatile devices (MCP4XFEBXX)).
Analog output performance specified from 2.7V to 5.5V.
DS20005429B-page 4
2015 Microchip Technology Inc.
MCP48FEBXX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Voltage on VDD with respect to VSS ......................................................................................................... -0.6V to +6.5V
Voltage on all pins with respect to VSS ............................................................................................... -0.6V to VDD+0.3V
Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP on HV pins) .......................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum current out of VSS pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum current into VDD pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum current sourced by the VOUT pin ............................................................................................................20 mA
Maximum current sunk by the VOUT pin..................................................................................................................20 mA
Maximum current sunk by the VREF pin .................................................................................................................125 µA
Maximum input current source/sunk by SDI, SCK, and CS pins .............................................................................2 mA
Maximum output current sunk by SDO Output pin .................................................................................................25 mA
Total power dissipation (1) ....................................................................................................................................400 mW
Package power dissipation (TA = +50°C, TJ = +150°C)
MSOP-10 ..................................................................................................................................................490 mW
ESD protection on all pins ±4 kV (HBM)
±400V (MM)
±1.5 kV (CDM)
Latch-Up (per JEDEC JESD78A) @ +125°C ..................................................................................................... ±100 mA
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ...............................................................................................-55°C to +125°C
Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C
Maximum Junction Temperature (TJ) .................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
2015 Microchip Technology Inc.
DS20005429B-page 5
MCP48FEBXX
DC CHARACTERISTICS
DC Characteristics
Parameters
Supply Voltage
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to VSS, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym.
Min.
Typ.
Max.
Units
Conditions
VDD
2.7
—
5.5
V
1.8
—
2.7
V
DAC operation (reduced analog
specifications) and Serial Interface
—
—
1.7
V
RAM retention voltage (VRAM) < VPOR
VDD voltages greater than VPOR/BOR
limit Ensure that device is out of reset.
VDD Voltage
(rising) to ensure device
Power-on Reset
VPOR/BOR
VDD Rise Rate to ensure
Power-on Reset
VDDRR
High-Voltage Commands
Voltage Range (HVC pin)
VHV
VSS
—
12.5
V
The HVC pin will be at one of three input
levels (VIL, VIH or VIHH) (1)
High-Voltage
Input Entry Voltage
VIHHEN
9.0
—
—
V
Threshold for Entry into
WiperLock Technology
High-Voltage
Input Exit Voltage
VIHHEX
—
—
VDD + 0.8V
V
(Note 2)
Power-on Reset to Output-Driven Delay
TPORD
—
25
50
µs
VDD rising, VDD > VPOR
(Note 3)
V/ms
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 3
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
DS20005429B-page 6
2015 Microchip Technology Inc.
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Parameters
Supply Current
Power-Down
Current
Sym.
IDD
IDDP
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to VSS, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Min.
—
Typ.
—
Max.
320
Units
µA
Conditions
Single
1MHz
(2)
—
—
910
µA
10MHz
—
—
1.7
mA
20MHz
—
—
510
µA
—
—
1.1
mA
—
—
1.85
mA
—
—
250
µA
Dual
(2)
1MHz (2)
10MHz (2)
Serial Interface Active
(Not High-Voltage Command)
VRxB:VRxA = ‘01’ (6)
VOUT is unloaded, VDD = 5.5V
Volatile DAC Register = 000h
20MHz
Single
1MHz (2)
—
—
840
µA
—
—
1.65
mA
—
—
380
µA
—
—
970
µA
Serial Interface Active
(Not
High-Voltage Command)
10MHz
VRxB:VRxA = ‘10’ (4)
(2)
20MHz
VOUT is unloaded.
1MHz (2) VREF = VDD = 5.5V
10MHz (2) Volatile DAC Register = 000h
—
—
1.75
mA
20MHz (2)
—
—
180
µA
Single
—
—
380
µA
Dual
—
—
180
µA
Single
—
—
380
µA
Dual
—
—
1.9
mA
EE Write Current
VREF = VDD = 5.5V
(After write, Serial Interface is Inactive.)
Write all 0’s to non-volatile DAC 0 (address 10h).
VOUT pins are unloaded.
—
145
180
µA
Single
—
260
400
µA
Dual
—
0.65
3.8
µA
PDxB:PDxA = ‘01’ (5),
VOUT not connected
(2)
Dual
Serial Interface Inactive (2)
(Not High-Voltage Command)
VRxB:VRxA = ‘00’
SCK = SDI = VSS
VOUT is unloaded.
Volatile DAC Register = 000h
Serial Interface Inactive (2)
(Not High-Voltage Command)
VRxB:VRxA = ‘11’, VREF = VDD
SCK = SDI = VSS
VOUT is unloaded.
Volatile DAC Register = 000h
HVC = 12.5V (High-Voltage Command)
Serial Interface Inactive
VREF = VDD = 5.5V, LAT/HVC = VIHH
DAC registers = 000h
VOUT pins are unloaded.
Note 2
This parameter is ensured by characterization.
Note 4
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
Note 5
The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
Note 6
By design, this is the worst-case current mode.
2015 Microchip Technology Inc.
DS20005429B-page 7
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Parameters
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to VSS, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym.
Resistor Ladder
RL
Resistance
Resolution
N
(# of Resistors
and # of Taps) (see
B.1 “Resolution”)
Nominal VOUT Match (11) |VOUT - VOUTMEAN|
/VOUTMEAN
Min.
Typ.
Max.
Units
100
140
180
k
256
1024
4096
—
—
—
0.5
—
15
Taps
Taps
Taps
1.0
1.2
—
Conditions
1.8V VDD 5.5V
VREF 1.0V (7)
8-bit No Missing Codes
10-bit No Missing Codes
12-bit No Missing Codes
%
2.7V VDD 5.5V (2)
%
1.8V (2)
ppm/°C Code = Mid-scale
(7Fh, 1FFh or 7FFh)
VOUT Tempco (see
VOUT/T
B.19 “VOUT
Temperature
Coefficient”)
VREF pin Input Voltage
VREF
VSS
—
VDD
V
1.8V VDD 5.5V (1)
Range
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 7
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP48FEBX2), this is the effective resistance of the each resistor ladder. The
resistance measurement is of the two resistor ladders measured in parallel.
Note 11
Variation of one output voltage to mean output voltage.
DS20005429B-page 8
2015 Microchip Technology Inc.
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC
Characteristics
Parameters
Zero-Scale Error
(see B.5
“Zero-Scale
Error (EZS)”)
(Code = 000h)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to VSS, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym.
Min.
Typ.
Max.
Units
EZS
—
—
0.75
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
—
—
3
LSb
2015 Microchip Technology Inc.
8-bit
LSb
LSb
LSb
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
—
—
12
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
-15
±1.5
+15
LSb
Offset Error
EOS
(see B.7 “Offset
Error (EOS)”)
Offset Voltage
VOSTC
—
±10
—
Temperature
Coefficient
Note 2 This parameter is ensured by characterization.
Conditions
LSb
LSb
LSb
LSb
LSb
LSb
LSb
mV
VRxB:VRxA = ‘11’, Gx = ‘0’
VREF = VDD, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’
VDD = 5.5V, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘10’, Gx = ‘0’, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘11’, Gx = ‘0’, No Load
VRxB:VRxA = ‘01’, Gx = ‘0’, No Load
10-bit
VRxB:VRxA = ‘11’, Gx = ‘0’
VREF = VDD, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’
VDD = 5.5V, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘10’, Gx = ‘0’, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘11’, Gx = ‘0’, No Load
VRxB:VRxA = ‘01’, Gx = ‘0’
No Load
12-bit VRxB:VRxA = ‘11’, Gx = ‘0’
VREF = VDD, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’
VDD = 5.5V, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘10’, Gx = ‘0’, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘11’, Gx = ‘0’, No Load
VRxB:VRxA = ‘01’, Gx = ‘0’
No Load
VRxB:VRxA = ‘00’
Gx = ‘0’
No Load
µV/°C
DS20005429B-page 9
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Full-Scale Error
(see B.4
“Full-Scale
Error (EFS)”)
EFS
—
—
4.5
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
—
—
18
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
—
—
70
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
This parameter is ensured by characterization.
LSb
Note 2
DS20005429B-page 10
Conditions
8-bit
LSb
LSb
LSb
10-bit
LSb
LSb
LSb
LSb
LSb
12-bit
Code = FFh, VRxB:VRxA = ‘11’
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFh, VRxB:VRxA = ‘10’
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFh, VRxB:VRxA = ‘01’
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFh, VRxB:VRxA = ‘00’
No Load
Code = 3FFh, VRxB:VRxA = ‘11’
Gx = ‘0’, VREF = 2.048V, No Load
Code = 3FFh, VRxB:VRxA = ‘10’
Gx = ‘0’, VREF = 2.048V, No Load
Code = 3FFh, VRxB:VRxA = ‘01’
Gx = ‘0’, VREF = 2.048V, No Load
Code = 3FFh, VRxB:VRxA = ‘00’
No Load
Code = FFFh, VRxB:VRxA = ‘11’
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFFh, VRxB:VRxA = ‘10’
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFFh, VRxB:VRxA = ‘01’
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFFh, VRxB:VRxA = ‘00’
No Load
2015 Microchip Technology Inc.
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Parameters
Gain Error
(see B.9 “Gain Error
(EG)”)(8)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym.
Min.
Typ.
Max.
Units
EG
-1.0
±0.1
+1.0
% of
FSR
8-bit
% of
FSR
10-bit
% of
FSR
12-bit
-1.0
-1.0
±0.1
±0.1
G/°C
—
-3
Gain-Error Drift (see B.10
“Gain-Error Drift (EGD)”)
Note 2
This parameter is ensured by characterization.
Note 8
This gain error does not include offset error.
2015 Microchip Technology Inc.
+1.0
+1.0
—
Conditions
Code = 250, No Load
VRxB:VRxA = ‘00’
Gx = ‘0’
Code = 1000, No Load
VRxB:VRxA = ‘00’
Gx = ‘0’
Code = 4000, No Load
VRxB:VRxA = ‘00’
Gx = ‘0’
ppm/°C
DS20005429B-page 11
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Sym.
Min.
Typ.
Max.
Units
Integral
Nonlinearity
(see B.11 “Integral
Nonlinearity
(INL)”) (10)
INL
-0.5
±0.1
+0.5
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
-1.5
±0.4
+1.5
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
-6
±1.5
+6
Note 2
Note 10
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
Conditions
8-bit
VRxB:VRxA = ‘10’
(codes: 6 to 250)
VDD = VREF = 5.5V
VRxB:VRxA = ‘00’, ‘01’, ‘11’
VRxB:VRxA = ‘01’
VDD = 5.5V, Gx = ‘1’
VRxB:VRxA = ‘10’, ‘11’
VREF = 1.0V, Gx = ‘1’
VDD = 1.8V
VREF = 1.0V
10-bit VRxB:VRxA = ‘10’
(codes: 25 to 1000)
VDD = VREF = 5.5V
VRxB:VRxA = ‘00’, ‘01’, ‘11’
VRxB:VRxA = ‘01’
VDD = 5.5V, Gx = ‘1’
VRxB:VRxA = ‘10’, ‘11’
VREF = 1.0V, Gx = ‘1’
VDD = 1.8V
VREF = 1.0V
12-bit VRxB:VRxA = ‘10’
(codes: 100 to 4000)
VDD = VREF = 5.5V.
VRxB:VRxA = ‘00’, ‘01’, ‘11’
See Section 2.0 “Typical
LSb
Performance Curves”(2)
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘01’
Performance Curves”(2)
VDD = 5.5V, Gx = ‘1’
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘10’, ‘11’
Performance Curves”(2)
VREF = 1.0V, Gx = ‘1’
See Section 2.0 “Typical
LSb
VDD = 1.8V
Performance Curves”(2)
VREF = 1.0V
This parameter is ensured by characterization.
Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000.
DS20005429B-page 12
2015 Microchip Technology Inc.
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Differential
Nonlinearity
(see B.12
“Differential
Nonlinearity
(DNL)”)(10)
Note 2
Note 10
Sym.
Min.
Typ.
Max.
Units
DNL
-0.25
±0.0125
+0.25
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
-0.5
±0.05
+0.5
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
-1.0
±0.2
+1.0
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
Conditions
8-bit
VRxB:VRxA = ‘10’
(codes: 6 to 250)
VDD = VREF = 5.5V
Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’
Char: VRxB:VRxA = ‘01’
VDD = 5.5V, Gx = ‘1’
Char: VRxB:VRxA = ‘10’, ‘11’
VREF = 1.0V, Gx = ‘1’
VDD = 1.8V
10-bit VRxB:VRxA = ‘10’
(codes: 25 to 1000)
VDD = VREF = 5.5V
Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’
Char: VRxB:VRxA = ‘01’
VDD = 5.5V, Gx = ‘1’
Char: VRxB:VRxA = ‘10’, ‘11’
VREF = 1.0V, Gx = ‘1’
VDD = 1.8V
12-bit VRxB:VRxA = ‘10’
(codes: 100 to 4000)
VDD = VREF = 5.5V
Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’
See Section 2.0 “Typical
LSb
Performance Curves”(2)
See Section 2.0 “Typical
LSb
Char: VRxB:VRxA = ‘01’
Performance Curves”(2)
VDD = 5.5V, Gx = ‘1’
See Section 2.0 “Typical
LSb
Char: VRxB:VRxA = ‘10’, ‘11’
Performance Curves”(2)
VREF = 1.0V, Gx = ‘1’
See Section 2.0 “Typical
LSb
VDD = 1.8V
Performance Curves”(2)
This parameter is ensured by characterization.
Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to
4000.
2015 Microchip Technology Inc.
DS20005429B-page 13
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
-3 dB Bandwidth
(see B.16 “-3 dB
Bandwidth”)
BW
—
200
—
kHz
—
100
—
kHz
VOUT(MIN)
—
0.01
—
VOUT(MAX)
—
—
PM
—
VDD –
0.04
66
—
SR
ISC
—
3
0.44
9
—
14
VBG
VBGTC
1.18
—
1.22
15
1.26
—
V
ppm/°C
2.0
2.2
—
—
5.5
5.5
V
V
VREF pin voltage stable
VOUT output linear
VSS
VSS
—
—
—
—
1
-64
VDD – 0.04
VDD
—
—
V
V
pF
dB
VRxB:VRxA = ‘11’ (Buffered mode)
VRxB:VRxA = ‘10’ (Unbuffered mode)
VRxB:VRxA = ‘10’ (Unbuffered mode)
VREF = 2.048V ± 0.1V
VRxB:VRxA = ‘10’, Gx = ‘0’
Frequency = 1 kHz
Output Amplifier
Minimum Output
Voltage
Maximum Output
Voltage
Phase Margin
Slew Rate (9)
Short-Circuit Current
Internal Band Gap
Band Gap Voltage
Band Gap Voltage
Temperature
Coefficient
Operating Range
(VDD)
External Reference (VREF)
Input Range (1)
VREF
Input Capacitance
Total Harmonic
Distortion (1)
CREF
THD
Conditions
VREF = 2.048V ± 0.1V
VRxB:VRxA = ‘10’, Gx = ‘0’
VREF = 2.048V ± 0.1V
VRxB:VRxA = ‘10’, Gx = ‘1’
1.8V VDD 5.5V
Output Amplifier’s minimum drive
V
1.8V VDD 5.5V
Output Amplifier’s maximum drive
Degree CL = 400 pF
RL =
(°)
V/µs
RL = 5 k
mA
DAC code = Full Scale
V
Dynamic Performance
Major Code
—
45
—
nV-s
1 LSb change around major carry
Transition Glitch (see
(7FFh to 800h)
B.14 “Major-Code
Transition Glitch”)
Digital Feedthrough
—
<10
—
nV-s
(see B.15 “Digital
Feed-through”)
Note 1
This parameter is ensured by design.
Note 9
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit
device).
DS20005429B-page 14
2015 Microchip Technology Inc.
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Parameters
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym.
Min.
Typ.
Max.
Digital Inputs/Outputs (CS, SCK, SDI, SDO, LAT0/HVC)
Schmitt Trigger
VIH
0.45 VDD
—
—
High-Input Threshold
0.5 VDD
—
—
—
—
0.2 VDD
Schmitt Trigger
VIL
Low-Input Threshold
—
0.1 VDD
—
Hysteresis of Schmitt
VHYS
Trigger Inputs
VSS
—
0.3 VDD
Output Low Voltage
VOL
VSS
—
0.3 VDD
Output High Voltage
VOH
0.7VDD
—
VDD
0.7VDD
—
VDD
Input Leakage Current
IIL
-1
—
1
Pin Capacitance
CIN, COUT
—
10
—
2015 Microchip Technology Inc.
Units
V
V
V
Conditions
2.7V VDD 5.5V
1.8V VDD 2.7V
V
V
V
V
V
µA
pF
IOL = 5 mA, VDD = 5.5V
IOL = 1 mA, VDD = 1.8V
IOH = -2.5 mA, VDD = 5.5V
IOH = -1 mA, VDD = 1.8V
VIN = VDD and VIN = VSS
fC = 20 MHz
DS20005429B-page 15
MCP48FEBXX
DC CHARACTERISTICS (CONTINUED)
DC Characteristics
Parameters
RAM Value
Value Range
DAC Register
POR/BOR Value
PDCON Initial
Factory Setting
EEPROM
Endurance
Data Retention
EEPROM Range
Initial Factory Setting
EEPROM Programming
Write Cycle Time
Power Requirements
Power Supply Sensitivity
(B.17 “Power-Supply
Sensitivity (PSS)”)
Note 1
Note 2
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym.
Min.
N
0h
0h
0h
N
ENEE
DREE
N
N
tWC
Max.
—
FFh
—
3FFh
—
FFFh
See Table 4-2
See Table 4-2
See Table 4-2
See Table 4-2
—
—
0h
0h
0h
1M
—
200
—
—
FFh
—
3FFh
—
FFFh
See Table 4-2
—
11
16
—
0.002
0.005
—
0.002
0.005
—
0.002
0.005
This parameter is ensured by design.
This parameter is ensured by characterization.
DS20005429B-page 16
PSS
Typ.
Units
hex
hex
hex
hex
hex
hex
hex
Cycles
Years
hex
hex
hex
ms
%/%
%/%
%/%
Conditions
8-bit
10-bit
12-bit
8-bit
10-bit
12-bit
Note 1, Note 2
At +25°C (1), ( 2)
8-bit
DACx Register(s)
10-bit DACx Register(s)
12-bit DACx Register(s)
VDD = +1.8V to 5.5V
8-bit
10-bit
12-bit
Code = 7Fh
Code = 1FFh
Code = 7FFh
2015 Microchip Technology Inc.
MCP48FEBXX
DC Notes:
1.
2.
3.
4.
5.
6.
7.
This parameter is ensured by design.
This parameter is ensured by characterization.
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
By design, this is the worst-case current mode.
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP48FEBX2), this is the effective resistance of the each resistor ladder. The resistance
measurement is of the two resistor ladders measured in parallel.
8. This gain error does not include offset error.
9. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).
10. Code range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000.
11. Variation of one output voltage to mean output voltage.
2015 Microchip Technology Inc.
DS20005429B-page 17
MCP48FEBXX
1.1
Reset, Power-Down, and SPI Mode Timing Waveforms and Requirements
VPOR (VBOR)
VDD
tPORD
tBORD
VOUT at High Z
VOUT
SPI Interface is operational
FIGURE 1-1:
Power-on and Brown-out Reset Waveforms.
24th bit
1st bit
(Write
(Next
command) command)
24th bit
(Write
command)
SCK
tPDE
tPDD
VOUT
FIGURE 1-2:
TABLE 1-1:
SPI Power-Down Command Waveforms.
RESET AND POWER-DOWN TIMING
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +1.8V to 5.5V, VSS = 0V
RL = 5 k from VOUT to VSS, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Timing Characteristics
Parameters
Power-on Reset Delay
Sym. Min. Typ. Max. Units
Conditions
tPORD
—
60
—
µs
Brown-out Reset Delay tBORD
—
45
—
µs
VDD transitions from VDD(MIN) > VPOR
VOUT driven to VOUT disabled
Power-Down Output
Disable Time Delay
TPDD
—
10.5
—
µs
PDxB:PDxA = ‘11’, ‘10’, or ‘01’ “00” started from
falling edge of the SCK at the end of the 24th clock cycle.
Volatile DAC Register = FFh, VOUT = 10 mV.
VOUT not connected.
Power-Down Output
Enable Time Delay
TPDE
—
1
—
µs
PDxB:PDxA = “00” ‘11’, ‘10’, or ‘01’ started from
falling edge of the SCK at the end of the 24th clock cycle.
VOUT = VOUT - 10 mV. VOUT not connected.
DS20005429B-page 18
2015 Microchip Technology Inc.
MCP48FEBXX
± 0.5 LSb
VOUT
New Value
Old Value
FIGURE 1-3:
TABLE 1-2:
VOUT Settling Time Waveform.
VOUT SETTLING TIMING
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Unless otherwise noted, all parameters apply across these specified operating ranges:
VDD = +1.8V to 5.5V, VSS = 0V
RL = 5 k from VOUT to VSS, CL = 100 pF
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Timing Characteristics
Parameters
Sym.
Min.
Typ.
Max.
Units
VOUT Settling Time
(±0.5LSb error band,
CL = 100 pF)
(see B.13 “Settling
Time”)
tS
—
7.8
—
µs
8-bit
Code = 40h C0h; C0h 40h (3)
—
7.8
—
µs
10-bit
Code = 100h 300h; 300h 100h (3)
—
7.8
—
µs
12-bit
Code = 400h C00h; C00h 400h (3)
Note 3
Conditions
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit
device).
2015 Microchip Technology Inc.
DS20005429B-page 19
MCP48FEBXX
HVC
VIHH
VIH
VIH
VIH
98
97
CS
VIL
84
96
“1”
LAT
VIH
“1”
“0”
“0”
70
94
72
96
SCK
83
71
80
MSb
SDO
73
SDI
HVC
74
77
MSb IN
FIGURE 1-4:
BIT6 - - - -1
LSb IN
SPI Timing (Mode = 11) Waveforms.
VIHH
VIH
VIH
LSb
BIT6 - - - - - -1
VIH
82
CS
VIL
84
“1”
LAT
VIH
98
97
96
“0”
“0”
SCK
94
70
MSb
SDO
73
FIGURE 1-5:
DS20005429B-page 20
96
83
71
SDI
“1”
80
72
BIT6 - - - - - -1
LSb
74
MSb IN
77
BIT6 - - - -1
LSb IN
SPI Timing (Mode = 00) Waveforms.
2015 Microchip Technology Inc.
MCP48FEBXX
TABLE 1-3:
SPI REQUIREMENTS (MODE = 11)
SPI AC Characteristics
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40C TA +125C (Extended)
Operating Voltage range is described in DC Characteristics.
Param.
No.
Characteristic
Symbol
FSCK
70
71
SCK input frequency
TcsA2scH CS Active (VIL) to command’s 1st SCK input
TscH
SCK input high time
72
TscL
73
74
77
80
TdiV2scH
TscH2diL
TcsH2DOZ
TscL2doV
83
TscH2csL CS Inactive (VIH) after SCK edge
84
94
96
97
98
Note 1
Note 4
SCK input low time
Setup time of SDI input to SCK edge
Hold time of SDI input from SCK edge
CS Inactive (VIH) to SDO output hi-impedance
SDO data output valid after SCK edge
TcsH
TLATSU
TLAT
Min.
Max. Units
—
10
—
20
—
60
20
400
20
400
10
20
—
—
—
100
1
50
20
20
0
1
—
—
—
—
—
—
—
50
45
170
—
Conditions
MHz VDD = 2.7V to 5.5V
(Read Command)
MHz VDD = 2.7V to 5.5V
(All Other Commands)
MHz VDD = 1.8V to 2.7V
ns
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns
ns
ns Note 1
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
µs VDD = 1.8V to 2.7V
ns
ns Write Data transferred (4)
ns
ns High-Voltage Commands(1)
CS high time (VIH)
—
LAT to SCK↑ (write data 24th bit) setup time
—
LAT high or low time
—
THVCSU
HVC to SCK (1st data bit)
—
(HVC setup time)
THVCHD
SCK ↑ (last bit of command (8th or 24th bit))
25
—
ns High-Voltage Commands(1)
to HVC (HVC hold time)
This parameter is ensured by design.
The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94) or
the current register data value may not be transferred to the output latch (VOUT) before the register is
overwritten with the new value.
2015 Microchip Technology Inc.
DS20005429B-page 21
MCP48FEBXX
TABLE 1-4:
SPI REQUIREMENTS (MODE = 00)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40C TA +125C (Extended)
Operating Voltage range is described in DC Characteristics.
SPI AC Characteristics
Param.
No.
Sym.
FSCK
70
71
Characteristic
SCK input frequency
TcsA2scH CS Active (VIL) to SCK input
TscH
SCK input high time
72
TscL
73
74
77
80
TDIV2scH
TscH2DIL
TcsH2DOZ
TscL2DOV
82
TssL2doV SDO data output valid after
CS Active (VIL)
TscH2csL CS Inactive (VIH) after SCK edge
83
84
94
96
97
98
Note 1
Note 4
TcsH
TLATSU
TLAT
THVCSU
SCK input low time
Setup time of SDI input to SCK edge
Hold time of SDI input from SCK edge
CS Inactive (VIH) to SDO output hi-impedance
SDO data output valid after SCK edge
Min. Max. Units
—
10
—
20
—
60
20
400
20
400
10
20
—
—
—
—
1
—
—
—
—
—
—
—
50
45
170
70
100
1
50
10
50
0
—
Conditions
MHz VDD = 2.7V to 5.5V
(Read Command)
MHz VDD = 2.7V to 5.5V
(All Other Commands)
MHz VDD = 1.8V to 2.7V
ns
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns
ns
ns Note 1
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns
ns
µs
ns
ns
ns
ns
VDD = 2.7V to 5.5V
VDD = 1.8V to 2.7V
CS high time (VIH)
—
LAT to SCK↑ (write data 24th bit) setup time
—
Write Data transferred (4)
LAT high or low time
—
HVC to SCK (1st data bit)
—
High-Voltage
(HVC setup time)
Commands (1)
THVCHD SCK (last bit of command (8th or 24th bit)) to
25
—
ns High-Voltage
HVC (HVC hold time)
Commands (1)
This parameter is ensured by design.
The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94) or
the current register data value may not be transferred to the output latch (VOUT) before the register is
overwritten with the new value.
DS20005429B-page 22
2015 Microchip Technology Inc.
MCP48FEBXX
Timing Table Notes:
1.
2.
3.
4.
This parameter is ensured by design.
This parameter ensured by characterization.
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).
The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94) or the
current register data value may not be transferred to the output latch (VOUT) before the register is overwritten with
the new value.
2015 Microchip Technology Inc.
DS20005429B-page 23
MCP48FEBXX
Temperature Specifications
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
202
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Thermal Resistance, 10LD-MSOP
Note 1:
The MCP48FEBXX devices operate over this extended temperature range, but with reduced performance.
Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C.
DS20005429B-page 24
2015 Microchip Technology Inc.
MCP48FEBXX
2.0
Note:
TYPICAL PERFORMANCE CURVES
The device Performance Curves are available in a separate document. This is done to keep the file size of
this PDF document less than the 10 MB file attachment limit of many mail servers.
The MCP48FXBXX Performance Curves document is literature number DS20005440, and can be found
on the Microchip website. Look on the MCP48FEBXX product page under “Documentation and Software”,
in the Data Sheets category.
2015 Microchip Technology Inc.
DS20005429B-page 25
MCP48FEBXX
NOTES:
DS20005429B-page 26
2015 Microchip Technology Inc.
MCP48FEBXX
3.0
PIN DESCRIPTIONS
Overviews of the pin functions are provided in
Sections 3.1 “Positive Power Supply Input (VDD)”
through Section 3.10 “SPI - Serial Clock Pin (SCK)”.
The descriptions of the pins for the single-DAC output
device are listed in Table 3-1, and descriptions for the
dual-DAC output device are listed in Table 3-2.
TABLE 3-1:
MCP48FEBX1 (Single-DAC) Pinout Description
Pin
MSOP-10LD
Symbol
I/O
Buffer
Type
1
VDD
—
P
Standard Function
Supply Voltage Pin
2
CS
I
ST
3
VREF0
A
Analog
Voltage Reference Input Pin
4
VOUT0
A
Analog
Buffered Analog Voltage Output Pin
5
NC
—
—
6
LAT0/HVC
I
HV ST
7
VSS
—
P
Ground Reference Pin for all circuitries on the device
8
SDO
O
—
SPI Serial Data Output Pin
9
SCK
I
ST
SPI Serial Clock Pin
10
SDI
I
ST
SPI Serial Data Input Pin
Legend:
TABLE 3-2:
A = Analog
I = Input
SPI Chip Select Pin
Not Internally Connected
DAC Register Latch/High-Voltage Command Pin.
Latch Pin allows the value in the Serial Shift Register to transfer to the
volatile DAC register. High-Voltage command allows User
Configuration Bits to be written.
ST = Schmitt Trigger HV = High Voltage
O = Output
I/O = Input/Output
P = Power
MCP48FEBX2 (Dual-DAC) Pinout Description
Pin
MSOP-10LD
Symbol
I/O
Buffer
Type
1
VDD
—
P
Supply Voltage Pin
2
CS
I
ST
SPI Chip Select Pin
Standard Function
3
VREF
A
Analog
Voltage Reference Input Pin (for DAC0 and DAC1)
4
VOUT0
A
Analog
Buffered Analog Voltage Output 0 Pin
5
VOUT1
A
Analog
Buffered Analog Voltage Output 1 Pin
6
LAT0/HVC
I
HV ST
DAC Register Latch/High-Voltage Command Pin. Latch Pin allows the
value in the Serial Shift Register to transfer to the volatile DAC register
(for DAC0 and DAC1). High-Voltage command allows User
Configuration Bits to be written.
7
VSS
—
P
Ground Reference Pin for all circuitries on the device
8
SDO
O
—
SPI Serial Data Output Pin
9
SCK
I
ST
SPI Serial Clock Pin
SDI
I
ST
SPI Serial Data Input Pin
10
Legend:
A = Analog
I = Input
2015 Microchip Technology Inc.
ST = Schmitt Trigger HV = High Voltage
O = Output
I/O = Input/Output
P = Power
DS20005429B-page 27
MCP48FEBXX
3.1
Positive Power Supply Input (VDD)
3.4
No Connect (NC)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS.
The NC pin is not connected to the device.
The power supply at the VDD pin should be as clean as
possible for a good DAC performance. It is
recommended to use an appropriate bypass capacitor
of about 0.1 µF (ceramic) to ground. An additional
10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate noise present in
application boards.
3.5
3.2
Voltage Reference Pin (VREF)
The VREF pin is either an input or an output. When the
DAC’s voltage reference is configured as the VREF pin,
the pin is an input. When the DAC’s voltage reference is
configured as the internal band gap, the pin is an output.
When the DAC’s voltage reference is configured as the
VREF pin, there are two options for this voltage input:
• VREF pin voltage buffered
• VREF pin voltage unbuffered
The buffered option is offered in cases where the
external reference voltage does not have sufficient
current capability to not drop its voltage when
connected to the internal resistor ladder circuit.
When the DAC’s voltage reference is configured as the
device VDD, the VREF pin is disconnected from the
internal circuit.
When the DAC’s voltage reference is configured as the
internal band gap, the VREF pin’s drive capability is
minimal, so the output signal should be buffered.
See Section 5.2 “Voltage Reference Selection” and
Register 4-2 for more details on the configuration bits.
The VSS pin is the device ground reference.
The user must connect the VSS pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application PCB (printed
circuit board), it is highly recommended that the VSS pin
be tied to the analog ground path or isolated within an
analog ground plane of the circuit board.
3.6
Analog Output Voltage Pin (VOUT)
VOUT is the DAC analog voltage output pin. The DAC
output has an output amplifier. The DAC output range is
dependent on the selection of the voltage reference
source (and potential Output Gain selection). These are:
• Device VDD - The full-scale range of the DAC
output is from VSS to approximately VDD.
• VREF pin - The full-scale range of the DAC output
is from VSS to G VRL, where G is the gain
selection option (1x or 2x).
• Internal Band Gap - The full-scale range of the
DAC output is from VSS to G (2 VBG), where G
is the gain selection option (1x or 2x).
In Normal mode, the DC impedance of the output pin is
about 1. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1 k, 100 k, or open. The Power-Down Selection bits
settings are shown in Register 4-3 and Table 5-5.
Latch Pin (LAT)/High-Voltage
Command (HVC)
The LAT pin is used to force the transfer of the DAC
register’s shift register to the DAC output register. This
allows DAC outputs to be updated at the same time.
The update of the VRxB:VRxA, PDxB:PDxA and Gx
bits are also controlled by the LAT pin state.
The HVC pin allows the device’s nonvolatile user configuration bits to be programmed when the HVC pin is
greater than the VIHH entry voltage.
3.7
SPI - Chip Select Pin (CS)
The CS pin enables/disables the serial interface. The
serial interface must be enabled for the SPI commands
to be received by the device.
Refer to Section 6.2 “SPI Serial Interface” for more
details of SPI Serial Interface communication.
The NC pin is not connected to the device.
3.8
3.3
Ground (VSS)
SPI - Serial Data In Pin (SDI)
The SDI pin is the serial data input pin of the SPI
interface. The SDI pin is used to read the DAC registers
and configuration bits.
Refer to Section 6.2 “SPI Serial Interface” for more
details of SPI Serial Interface communication.
3.9
SPI - Serial Data Out Pin (SDO)
The SDO pin is the serial data output pin of the SPI
interface. The SDO pin is used to write the DAC
registers and configuration bits.
Refer to Section 6.2 “SPI Serial Interface” for more
details of SPI Serial Interface communication.
3.10
SPI - Serial Clock Pin (SCK)
The SCK pin is the serial clock pin of the SPI interface.
The MCP48FEBXX SPI Interface only accepts external
serial clocks.
Refer to Section 6.2, SPI Serial Interface for more
details of SPI Serial Interface communication.
DS20005429B-page 28
2015 Microchip Technology Inc.
MCP48FEBXX
4.0
GENERAL DESCRIPTION
The MCP48FEBX1 (MCP48FEB01, MCP48FEB11,
and MCP48FEB21) devices are single-channel voltage
output devices. The MCP48FEBX2 (MCP48FEB02,
MCP48FEB12, and MCP48FEB22) devices are
dual-channel voltage output devices.
These devices are offered with 8-bit (MCP48FEB0X),
10-bit (MCP48FEB1X) and 12-bit (MCP48FEB2X)
resolution and include nonvolatile memory (EEPROM),
an SPI serial interface and a write latch (LAT) pin to
control the update of the written DAC value to the DAC
output pin.
The devices use a resistor ladder architecture. The
resistor
ladder
DAC
is
driven
from
a
software-selectable voltage reference source. The
source can be either the device’s internal VDD, an
external VREF pin voltage (buffered or unbuffered) or
an internal band gap voltage source.
The DAC output is buffered with a low power and
precision output amplifier (op amp). This output
amplifier provides a rail-to-rail output with low offset
voltage and low noise. The gain (1x or 2x) of the
output buffer is software configurable.
4.1
Power-on Reset/Brown-out Reset
(POR/BOR)
The internal Power-on Reset (POR)/Brown-out Reset
(BOR) circuit monitors the power supply voltage (VDD)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR).
The maximum VPOR/VBOR voltage is less than 1.8V.
POR occurs as the voltage is rising (typically from 0V),
while BOR occurs as the voltage is falling (typically
from VDD(MIN) or higher).
The POR and BOR trip points are at the same voltage,
and the condition is determined by whether the VDD
voltage is rising or falling (see Figure 4-1). What occurs
is different depending on whether the reset is a POR or
BOR.
the
electrical
When
VPOR/VBOR < VDD < 2.7V,
performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its EEPROM and reading and
writing to its volatile memory if the proper serial
command is executed.
This device also has user-programmable nonvolatile
memory (EEPROM), which allows the user to save the
desired POR/BOR value of the DAC register and
device configuration bits. High-voltage lock bits can be
used to ensure that the devices output settings are not
accidentally modified.
The devices operate from a single supply voltage. This
voltage is specified from 2.7V to 5.5V for full specified
operation, and from 1.8V to 5.5V for digital operation.
The devices operate between 1.8V and 2.7V, but
some device parameters are not specified.
The main functional blocks are:
•
•
•
•
•
•
Power-on Reset/Brown-out Reset (POR/BOR)
Device Memory
Resistor Ladder
Output Buffer/VOUT Operation
Internal Band Gap (Voltage Reference)
SPI Serial Interface Module
2015 Microchip Technology Inc.
DS20005429B-page 29
MCP48FEBXX
4.1.1
POWER-ON RESET
4.1.2
The Power-on Reset is the case where the device VDD
is having power applied to it from the VSS voltage level.
As the device powers up, the VOUT pin will float to an
unknown value. When the device’s VDD is above the
transistor threshold voltage of the device, the output
will start being pulled low. After the VDD is above the
POR/BOR trip point (VBOR/VPOR), the resistor
network’s wiper will be loaded with the POR value
(mid-scale). The volatile memory determines the
analog output (VOUT) pin voltage. After the device is
powered-up, the user can update the device memory.
When the rising VDD voltage crosses the VPOR trip
point, the following occurs:
• Nonvolatile DAC register value is latched into
volatile DAC register
• Nonvolatile configuration bit values are latched
into volatile configuration bits
• POR Status bit is set (‘1’)
• The Reset Delay Timer (tPORD) starts; when the
reset delay timer (tPORD) times out, the SPI serial
interface is operational. During this delay time, the
SPI interface will not accept commands.
• The Device Memory Address pointer is forced to
00h.
BROWN-OUT RESET
The Brown-out Reset occurs when a device had
power applied to it and that power (voltage) drops
below the specified range.
When the falling VDD voltage crosses the VPOR trip
point (BOR event), the following occurs:
• Serial Interface is disabled
• EEPROM Writes are disabled
• Device is forced into a Power-Down state
(PDxB:PDxA = ‘11’). Analog circuitry is turned off.
• Volatile DAC Register is forced to 000h
• Volatile configuration bits VRxB:VRxA and Gx are
forced to ‘0’
If the VDD voltage decreases below the VRAM voltage,
all volatile memory may become corrupted.
As the voltage recovers above the VPOR/VBOR voltage,
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
condition may cause the memory location (volatile and
nonvolatile) to become corrupted.
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
The analog output (VOUT) state will be determined by
the state of the volatile configuration bits and the DAC
register. This is called a Power-on Reset (event).
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
Volatile memory
POR starts Reset Delay Timer.
retains data value When timer times out, SPI interface
can operate (if VDD VDD(MIN))
Volatile memory
becomes corrupted
VDD(MIN)
TPORD (50 µs max.)
VPOR
VBOR
VRAM
Normal Operation
Device in
unknown
state
Device in
POR state
POR reset forced active
FIGURE 4-1:
DS20005429B-page 30
EEPROM data latched into volatile
configuration bits and DAC register.
POR status bit is set (‘1’)
Below
minimum
operating
voltage
Device Device in
in power unknown
-down state
state
BOR reset,
volatile DAC Register = 000h
volatile VRxB:VRxA = 00
volatile Gx = 0
volatile PDxB:PDxA = 11
Power-on Reset Operation.
2015 Microchip Technology Inc.
MCP48FEBXX
4.2
4.2.2
Device Memory
User memory includes three types of memory:
This memory can be grouped into two uses of
nonvolatile memory. These are the DAC Output Value
and Configuration registers:
• Volatile Register Memory (RAM)
• Nonvolatile Register Memory
• Device Configuration Memory
Each memory address is 16 bits wide. There are five
nonvolatile user-control bits that do not reside in
memory mapped register space (see Section 4.2.3
“Device Configuration Memory”).
4.2.1
VOLATILE REGISTER MEMORY
(RAM)
DAC0 and DAC1 Output Value Registers
VREF Select Register
Power-Down Configuration Register
Gain and Status Register
WiperLock Technology Status Register
The device starts writing the EEPROM memory
location at the completion of the serial interface
command. For the SPI interface, this is when the CS
pin goes inactive (VIH).
The volatile memory starts functioning when the
device VDD is at (or above) the RAM retention voltage
(VRAM). The volatile memory will be loaded with the
default device values when the VDD rises across the
VPOR/VBOR voltage trip point.
Note:
When the nonvolatile memory is written,
the corresponding volatile memory is not
modified.
The nonvolatile DAC registers enable stand-alone
operation of the device (without Microcontroller control)
after being programmed to the desired value.
MEMORY MAP (x16)
Address
CL0
10h
Nonvolatile DAC0 Register
DL0
CL1
11h
Nonvolatile DAC1 Register
DL1
—
12h
Reserved
—
Reserved
—
13h
Reserved
—
Reserved
—
14h
Reserved
—
05h
Reserved
—
15h
Reserved
—
06h
Reserved
—
16h
Reserved
—
07h
Reserved
—
17h
Reserved
—
08h
VREF Register
—
18h
Nonvolatile VREF Register
—
Function
00h
Volatile DAC0 Register
01h
Volatile DAC1 Register
02h
Reserved
03h
04h
Config
Bit (1)
Config
Bit (1)
Address
TABLE 4-1:
• Nonvolatile DAC0 and DAC1 Output Value
Registers
• Nonvolatile VREF Select Register
• Nonvolatile Power-Down Configuration Register
• Nonvolatile Gain Register
The nonvolatile memory starts functioning below the
device’s VPOR/VBOR trip point, and is loaded into the
corresponding volatile registers whenever the device
rises above the POR/BOR voltage trip point.
There are up to six volatile memory locations:
•
•
•
•
•
NONVOLATILE REGISTER
MEMORY
Function
09h
Power-Down Register
—
19h
Nonvolatile Power-Down Register
—
0Ah
Gain and Status Register
—
1Ah
NV Gain Register
—
0Bh
WiperLock™ Technology Status Register
—
1Bh
Reserved
—
0Ch
Reserved
—
1Ch
Reserved
—
0Dh
Reserved
—
1Dh
Reserved
—
0Eh
Reserved
—
1Eh
Reserved
—
0Fh
Reserved
—
1Fh
Reserved
—
Volatile Memory address range
Nonvolatile Memory address range
Note 1: Device Configuration Memory bits require a High-Voltage enable or disable command (LAT/LAT0 = VIHH,
or CS = VIHH) to modify the bit value.
2015 Microchip Technology Inc.
DS20005429B-page 31
MCP48FEBXX
4.2.3
DEVICE CONFIGURATION
MEMORY
4.2.5
UNIMPLEMENTED (RESERVED)
LOCATIONS
There are up to five nonvolatile user bits that are not
directly mapped into the address space. These
nonvolatile device configuration bits control the
following functions:
Normal (voltage) commands (read or write) to any
unimplemented memory address (reserved) will result
in a command error condition (CMDERR). Read
commands of a reserved location will read bits as ‘1’.
• DAC Register
• Configuration WiperLock Technology (2 bits per
DAC)
High-Voltage commands (enable or disable) to any
unimplemented configuration bits will result in a
command error condition (CMDERR).
The Status register shows the states of the device
WiperLock Technology configuration bits. The Status
register is described in Register 4-6.
4.2.5.1
The operation of WiperLock Technology is discussed
in Section 4.2.6 “WiperLock Technology”.
4.2.4
Table 4-2 shows the default factory POR initialization
of the device memory map for the 8-, 10- and 12-bit
devices.
UNIMPLEMENTED REGISTER BITS
Note:
Read commands of a valid location will read
unimplemented bits as ‘0’.
POR/BOR Value
Address
The volatile memory locations will be
determined by the nonvolatile memory
states (registers and device configuration
bits).
FACTORY DEFAULT POR / BOR VALUES
10-bit
12-bit
8-bit
10-bit
12-bit
Function
8-bit
Function
POR/BOR Value
Address
TABLE 4-2:
Default Factory POR Memory State
of Nonvolatile Memory (EEPROM)
00h Volatile DAC0 Register
7Fh
1FFh
7FFh
10h Nonvolatile DAC0 Register
7Fh
1FFh
7FFh
01h Volatile DAC1 Register
7Fh
1FFh
7FFh
11h Nonvolatile DAC1 Register
7Fh
1FFh
7FFh
12h Reserved
(1)
FFh
3FFh
FFFh
13h Reserved
(1)
FFh
3FFh
FFFh
(1)
02h Reserved
(1)
03h Reserved
(1)
04h Reserved
(1)
FFh
3FFh
FFFh
14h Reserved
FFh
3FFh
FFFh
05h Reserved (1)
FFh
3FFh
FFFh
15h Reserved (1)
FFh
3FFh
FFFh
FFFh
16h Reserved
(1)
FFh
3FFh
FFFh
17h Reserved
(1)
FFh
3FFh
FFFh
06h Reserved
(1)
07h Reserved
(1)
FFh
FFh
FFh
FFh
3FFh
3FFh
3FFh
3FFh
FFFh
FFFh
FFFh
08h VREF Register
0000h 0000h 0000h
18h Nonvolatile VREF
Register
0000h 0000h 0000h
09h Power-Down Register
0000h 0000h 0000h
19h Nonvolatile Power-Down
Register
0000h 0000h 0000h
0Ah Gain and Status Register
0080h 0080h 0080h
1Ah NV Gain
0000h 0000h 0000h
0Bh WiperLock™ Technology
Status Register
0Ch Reserved (1)
(1)
FFh
3FFh
FFFh
FFFh
1Ch Reserved (1)
FFh
3FFh
FFFh
FFFh
1Dh Reserved
(1)
FFh
3FFh
FFFh
FFh
3FFh
FFFh
FFh
3FFh
FFFh
0000h 0000h 0000h
FFh
3FFh
1Bh Reserved
0Dh Reserved
(1)
0Eh Reserved
(1)
FFh
3FFh
FFFh
1Eh Reserved
(1)
0Fh Reserved
(1)
FFh
3FFh
FFFh
1Fh Reserved
(1)
FFh
Volatile Memory address range
Note 1:
3FFh
Nonvolatile Memory address range
Reading a reserved memory location will result in the SPI command Command Error condition. The SDO pin will
output all ‘0’s. Forcing the CS pin to the VIH state will reset the SPI interface.
DS20005429B-page 32
2015 Microchip Technology Inc.
MCP48FEBXX
4.2.6
WIPERLOCK TECHNOLOGY
The MCP48FEBXX device’s WiperLock technology
allows application-specific device settings (DAC
register and configuration) to be secured without
requiring the use of an additional write-protect pin.
There are two configuration bits (DLx:CLx) for each
DAC (DAC0 and DAC1).
Dependent on the state of the DLx:CLx configuration
bits, WiperLock technology prevents the serial
commands from the following actions on the DACx
registers and bits:
• Writing to the specified volatile DACx Register
memory location
• Writing to the specified nonvolatile DACx Register
memory location
• Writing to the specified volatile DACx
configuration bits
• Writing to the specified nonvolatile DACx
configuration bits
Note:
Please refer to Section 7.4 “Enable Configuration
Bit” and Section 7.5 “Disable Configuration Bit”
commands for operation.
Note:
4.2.6.1
Each pair of these configuration bits control one of four
modes. These modes are shown in Table 4-3. The
addresses for the configuration bits are shown in
Table 4-1.
To modify the CL0 bit, the enable or
disable command specifies address 00h,
while to modify the DL0 bit, the enable or
disable command specifies address 10h.
During device communication, if the
Device Address/Command combination is
invalid or an unimplemented Address is
specified, then the MCP48FEBXX will
Command Error that Command byte. To
reset the serial interface state machine,
the CS pin must be driven to the inactive
state (VIH) before returning to the active
state (VIL or VIHH).
POR/BOR Operation with
WiperLock Technology Enabled
The WiperLock Technology state is not affected by a
POR/BOR event. A POR/BOR event will load the
Volatile DAC0 (DAC1) register values with the
Nonvolatile DAC0 (DAC1) register values.
To modify the configuration bits, the HVC pin must be
forced to the VIHH state and then receive an enable or
disable command on the desired pair of DAC Register
addresses.
WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS - FUNCTIONAL DESCRIPTION
DLx:CLx (1)
TABLE 4-3:
Volatile
11
Locked
Locked
Locked
Locked
All DACx registers are locked.
10
Locked
Locked
Unlocked
Locked
All DACx registers are locked except volatile DACx
Configuration registers.
This allows operation of power-down modes.
01
Unlocked
Locked
Unlocked
Locked
Volatile DACx registers unlocked, nonvolatile DACx
registers locked.
Unlocked
Unlocked
Unlocked
Unlocked
00
Note 1:
2:
Register / Bits
DACx
Nonvolatile
DACx Configuration (2)
Volatile
Nonvolatile
Comments
All DACx registers are unlocked.
The state of these configuration bits (DLx:CLx) are reflected in WLxB:WLxA bits as shown in Register 4-6.
DAC configuration bits include Voltage Reference Control bits (VRxB:VRxA), Power-Down Control bits
(PDxB:PDxA), and Output Gain bits (Gx).
2015 Microchip Technology Inc.
DS20005429B-page 33
MCP48FEBXX
4.2.7
DEVICE REGISTERS
Register 4-1 shows the format of the DAC Output Value
registers for both the volatile memory locations and the
nonvolatile memory locations. These registers will be
either 8 bits, 10 bits, or 12 bits wide. The values are
right justified.
REGISTER 4-1:
12-bit
DAC0 AND DAC1 REGISTERS (VOLATILE AND NONVOLATILE)
U-0
U-0
U-0
U-0
—
—
—
—
D11
D10
(1)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
10-bit
—
—
—
—
—
—
8-bit
—
—
—
—
—(1)
—(1)
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
—(1)
—(1)
D07
D06
D05
D04
D03
D02
D01
D00
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= 12-bit device
12-bit
10-bit
W = Writable bit
‘1’ = Bit is set
= 10-bit device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= 8-bit device
8-bit
bit 15-12 bit 15-10 bit 15-8
Unimplemented: Read as ‘0’
bit 11-0
—
—
D11-D00: DAC Output value - 12-bit devices
FFFh = Full-Scale output value
7FFh = Mid-Scale output value
000h = Zero-Scale output value
—
bit 9-0
—
D09-D00: DAC Output value - 10-bit devices
3FFh = Full-Scale output value
1FFh = Mid-Scale output value
000h = Zero-Scale output value
—
—
bit 7-0
D07-D00: DAC Output value - 8-bit devices
FFh = Full-Scale output value
7Fh = Mid-Scale output value
000h = Zero-Scale output value
Note 1:
Unimplemented bit, read as ‘0’.
DS20005429B-page 34
x = Bit is unknown
2015 Microchip Technology Inc.
MCP48FEBXX
Register 4-2 shows the format of the Voltage
Reference Control Register. Each DAC has two bits to
control the source of the voltage reference of the DAC.
This register is for both the volatile memory locations
and the nonvolatile memory locations.
REGISTER 4-2:
VOLTAGE REFERENCE (VREF) CONTROL REGISTER (VOLATILE
AND NONVOLATILE) (ADDRESSES 08h AND 18h)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
Dual
—
—
—
—
—
—
—
—
—
—
—
—
R/W-0 R/W-0 R/W-0 R/W-0
—(1)
—(1)
VR0B VR0A
VR1B VR1A VR0B VR0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= Dual-channel device
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
VRxB-VRxA: DAC Voltage Reference Control bits
11 = VREF pin (Buffered); VREF buffer enabled
10 = VREF pin (Unbuffered); VREF buffer disabled
01 = Internal Band Gap (1.22V typical); VREF buffer enabled
VREF voltage driven when powered-down
00 = VDD (Unbuffered); VREF buffer disabled.
Use this state with Power-Down bits for lowest current.
Note 1:
Unimplemented bit, read as ‘0’.
2015 Microchip Technology Inc.
x = Bit is unknown
DS20005429B-page 35
MCP48FEBXX
Register 4-3 shows the format of the Power-Down
Control Register. Each DAC has two bits to control the
Power-Down state of the DAC. This register is for both
the volatile memory locations and the nonvolatile
memory locations.
REGISTER 4-3:
POWER-DOWN CONTROL REGISTER (VOLATILE AND NONVOLATILE)
(ADDRESSES 09h, 19h)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
Dual
—
—
—
—
—
—
—
—
—
—
—
—
R/W-0 R/W-0 R/W-0 R/W-0
—(1)
—(1)
PD0B PD0A
PD1B PD1A PD0B PD0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
Single
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= Dual-channel device
x = Bit is unknown
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
PDxB-PDxA: DAC Power-Down Control bits(2)
11 = Powered Down - VOUT is open circuit.
10 = Powered Down - VOUT is loaded with a 100 k resistor to ground.
01 = Powered Down - VOUT is loaded with a 1 k resistor to ground.
00 = Normal Operation (Not powered-down)
Note 1:
2:
Unimplemented bit, read as ‘0’.
See Table 5-5 and Figure 5-10 for more details.
DS20005429B-page 36
2015 Microchip Technology Inc.
MCP48FEBXX
Register 4-4 shows the format of the volatile Gain
Control and System Status Register. Each DAC has one
bit to control the gain of the DAC and three Status bits.
REGISTER 4-4:
Single
Dual
GAIN CONTROL AND SYSTEM STATUS REGISTER (VOLATILE) (ADDRESS 0Ah)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—(1)
G0
—
—
—
—
—
—
G1
G0
U-0
U-0
U-0
U-0
U-0
U-0
POR EEWA
—
—
—
—
—
—
POR EEWA
—
—
—
—
—
R/W-0 R/W-0 R/C-1
R-0
bit 15
—
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
C = Clear-able bit
‘0’ = Bit is cleared
= Dual-channel device
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
Single
Dual
bit 15-9
bit 15-10 Unimplemented: Read as ‘0’
—
bit 9
G1: DAC1 Output Driver Gain control bits (Dual-Channel Device only)
1 = 2x Gain
0 = 1x Gain
bit 8
bit 8
G0: DAC0 Output Driver Gain control bits
1 = 2x Gain
0 = 1x Gain
bit 7
bit 7
POR: Power-on Reset (Brown-out Reset) Status bit
This bit indicates if a Power-on Reset (POR) or Brown-out Reset (BOR) event has
occurred since the last read command of this register. Reading this register clears the
state of the POR Status bit.
1 = A POR (BOR) event occurred since the last read of this register. Reading this register clears
this bit.
0 = A POR (BOR) event has not occurred since the last read of this register.
bit 6
bit 6
EEWA: EEPROM Write Active Status bit
This bit indicates if the EEPROM Write Cycle is occurring.
1 = An EEPROM Write Cycle is currently occurring. Only serial commands to the volatile
memory are allowed.
0 = An EEPROM Write Cycle is NOT currently occurring.
bit 5-0
bit 5-0
Unimplemented: Read as ‘0’
Note 1:
Unimplemented bit, read as ‘0’.
2015 Microchip Technology Inc.
DS20005429B-page 37
MCP48FEBXX
Register 4-5 shows the format of the Nonvolatile Gain
Control Register. Each DAC has one bit to control the
gain of the DAC.
REGISTER 4-5:
Single
Dual
GAIN CONTROL REGISTER (NONVOLATILE) (ADDRESS 1Ah)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—(1)
G0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
G1
G0
—
—
—
—
—
—
—
R/W-0 R/W-0
bit 15
—
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= Dual-channel device
x = Bit is unknown
Single
Dual
bit 15-9
bit 15-10 Unimplemented: Read as ‘0’
—
bit 9
G1: DAC1 Output Driver Gain control bits (Dual-Channel Device only)
1 = 2x Gain
0 = 1x Gain
bit 8
bit 8
G0: DAC0 Output Driver Gain control bits
1 = 2x Gain
0 = 1x Gain
bit 7-0
bit 6-0
Unimplemented: Read as ‘0’
Note 1:
Unimplemented bit, read as ‘0’.
DS20005429B-page 38
2015 Microchip Technology Inc.
MCP48FEBXX
Register 4-6 shows the format of the DAC WiperLock
Technology Status Register.
REGISTER 4-6:
DAC WIPERLOCK TECHNOLOGY STATUS REGISTER (VOLATILE) (ADDRESS 0BH)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0(1)
R-0(1)
R-0(1)
R-0(1)
Single
—
—
—
—
—
—
—
—
—
—
—
—
—(2)
—(2)
WL0B WL0A
Dual
—
—
—
—
—
—
—
—
—
—
—
—
WL1B WL1A WL0B WL0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= Dual-channel device
x = Bit is unknown
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
WLxB-WLxA: WiperLock Technology Status bits: These bits reflect the state of the DLx:CLx
nonvolatile configuration bits.
11 = DAC wiper and DAC Configuration (volatile and nonvolatile registers) are locked.
(DLx = CLx = Enabled)
10 = DAC wiper (volatile and nonvolatile) and DAC Configuration (nonvolatile registers) are
locked (DLx = Enabled; CLx = Disabled).
01 = DAC wiper (nonvolatile) and DAC Configuration (nonvolatile registers) are locked.
(DLx = Disabled; CLx = Enabled)
00 = DAC wiper and DAC Configuration are unlocked (DLx = CLx = Disabled).
Note 1:
POR Value dependent on the programmed values of the DLx:CLx configuration bits. The devices are
shipped with a default DLx:CLx configuration bit state of ‘0’.
Unimplemented bit, read as ‘0’.
2:
2015 Microchip Technology Inc.
DS20005429B-page 39
MCP48FEBXX
NOTES:
DS20005429B-page 40
2015 Microchip Technology Inc.
MCP48FEBXX
5.0
The functional blocks of the DAC include:
DAC CIRCUITRY
•
•
•
•
•
•
The Digital-to-Analog Converter circuitry converts a
digital value into its analog representation. The
description details the functional operation of the device.
The DAC Circuit uses a resistor ladder implementation.
Devices have up to two DACs.
Figure 5-1 shows the functional block diagram for the
MCP48FEBXX DAC circuitry.
VDD
Voltage
Reference
Selection
Resistor Ladder
Voltage Reference Selection
Output Buffer/VOUT Operation
Internal Band Gap (as a voltage reference)
Latch Pin (LAT)
Power-Down Operation
Power-Down
Operation
PD1:PD0 and
VREF1:VREF0
VREF
+
-
VDD
VDD
VREF1:VREF0
PD1:PD0 and BGEN
Band Gap
(1.22V typical)
VREF1:VREF0
PD1:PD0
VDD
A (RL)
RS(2n)
DAC
Output
Selection
Power-Down
Operation
PD1:PD0
VW
VOUT
+
RS(2n - 1)
-
Output Buffer/VOUT
Operation
RRL RS(2n - 3)
100 k
PD1:PD0
Gain
(1x or 2x)
RS(2n - 2)
1 k
VRL
Internal Band Gap
Power-Down
Operation
(~140 k)
DAC Register Value
VW = ---------------------------------------------------------------------- V RL
# Resistor in Resistor Ladder
RS(2)
Where:
# Resistors in Resistor Ladder = 256 (MCP48FEB0X)
Resistor
Ladder
1024 (MCP48FEB1X)
RS(1)
4096 (MCP48FEB2X)
B
FIGURE 5-1:
MCP48FEBXX DAC Module Block Diagram.
2015 Microchip Technology Inc.
DS20005429B-page 41
MCP48FEBXX
5.1
Resistor Ladder
PD1:PD0
The Resistor Ladder is a digital potentiometer with the
B terminal internally grounded and the A terminal
connected to the selected reference voltage (see
Figure 5-2). The volatile DAC register controls the
wiper position. The wiper voltage (VW) is proportional to
the DAC register value divided by the number of
resistor elements (RS) in the ladder (256, 1024 or 4096)
related to the VRL voltage.
The output of the resistor network will drive the input of
an output buffer.
VRL
DAC
Register
RS(2n)
2n - 1
RS(2n - 1)
RRL
RS(2n - 2)
RW (1)
2n - 2
RW (1)
The Resistor Network is made up of these three parts:
VW
• Resistor Ladder (string of RS elements)
• Wiper switches
• DAC Register decode
The resistor ladder (RRL) has a typical impedance of
approximately 140 k. This resistor ladder resistance
(RRL) may vary from device to device by up to ±20%.
Since this is a voltage divider configuration, the actual
RRL resistance does not affect the output given a fixed
voltage at VRL.
Equation 5-1 shows the calculation for the step
resistance:
EQUATION 5-1:
RS CALCULATION
R RL
R S = ------------ 256
Note:
1
RS(1)
RW
(1)
0
(1)
RW
Analog Mux
DAC Register Value
V W = ---------------------------------------------------------------------- V RL
# Resistor in Resistor Ladder
Where:
# Resistors in R-Ladder = 256 (MCP48FEB0X)
8-bit Device
1024 (MCP48FEB1X)
4096 (MCP48FEB2X)
R RL
RS = --------------- 1024
10-bit Device
R RL
RS = --------------- 4096
12-bit Device
Note 1: The analog switch resistance (RW)
does not affect performance due to the
voltage divider configuration.
FIGURE 5-2:
Block Diagram.
Resistor Ladder Model
The maximum wiper position is 2n – 1,
while the number of resistors in the
resistor ladder is 2n. This means that
when the DAC register is at full-scale,
there is one resistor element (RS)
between the wiper and the VRL voltage.
If the unbuffered VREF pin is used as the VRL voltage
source, this voltage source should have a low output
impedance.
When the DAC is powered-down, the resistor ladder is
disconnected from the selected reference voltage.
DS20005429B-page 42
2015 Microchip Technology Inc.
MCP48FEBXX
Voltage Reference Selection
The resistor ladder has up to four sources for the
reference
voltage.
Two
user
control
bits
(VREF1:VREF0) are used to control the selection, with
the selection connected to the VRL node (see
Figures 5-3 and 5-4). The four voltage source options
for the Resistor Ladder are:
1.
2.
3.
4.
VDD pin voltage
Internal Voltage Reference (VBG)
VREF pin voltage unbuffered
VREF pin voltage internally buffered
VREF1:VREF0
VREF
VDD
Band Gap
Reference
Selection
5.2
VRL
Buffer
FIGURE 5-3:
Resistor Ladder Reference
Voltage Selection Block Diagram.
The selection of the voltage is specified with the volatile
VREF1:VREF0 configuration bits (see Register 4-2).
There are nonvolatile and volatile VREF1:VREF0
configuration bits. On a POR/BOR event, the state of the
nonvolatile VREF1:VREF0 configuration bits is latched
into the volatile VREF1:VREF0 configuration bits.
VDD
PD1:PD0 and
VREF1:VREF0
VREF
+
VRL
When the user selects the VDD as reference, the VREF
pin voltage is not connected to the resistor ladder.
-
If the VREF pin is selected, then a selection has to be
made between the Buffered or Unbuffered mode.
5.2.1
UNBUFFERED MODE
VDD
The VREF pin voltage may be from VSS to VDD.
VDD
Note 1: The voltage source should have a low
output impedance. If the voltage source
has a high output impedance, then the
voltage on the VREF’s pin would be lower
than expected. The resistor ladder has a
typical impedance of 140 k and a
typical capacitance of 29 pF.
2: If the VREF pin is tied to the VDD voltage,
VDD mode (VREF1:VREF0 = ‘00’) is
recommended.
5.2.2
BUFFERED MODE
The VREF pin voltage may be from 0.01V to
VDD - 0.04V. The input buffer (amplifier) provides low
offset voltage, low noise, and a very high input
impedance, with only minor limitations on the input
range and frequency response.
Note 1: Any variation or noises on the reference
source can directly affect the DAC output.
The reference voltage needs to be as
clean as possible for accurate DAC
performance.
2: If the VREF pin is tied to the VDD voltage,
VDD mode (VREF1:VREF0 = ‘00’) is
recommended.
2015 Microchip Technology Inc.
VREF1:VREF0
VREF1:VREF0
PD1:PD0
and BGEN
Band Gap (1)
(1.22V typical)
Note 1: The Band Gap voltage (VBG) is 1.22V
typical. The band gap output goes through
the buffer with a 2x gain to create the VRL
voltage. See Section 5.4 “Internal Band
Gap” for additional information on the
band gap circuit.
FIGURE 5-4:
Reference Voltage Selection
Implementation Block Diagram.
5.2.3
BAND GAP MODE
If the Internal Band Gap is selected, then the external
VREF pin should not be driven and only use
high-impedance loads. Decoupling capacitors are
recommended for optimal operation.
The band gap output is buffered, but the internal
switches limit the current that the output should source
to the VREF pin. The resistor ladder buffer is used to
drive the Band Gap voltage for the cases of multiple
DAC outputs. This ensures that the resistor ladders are
always properly sourced when the band gap is selected.
DS20005429B-page 43
MCP48FEBXX
Output Buffer/VOUT Operation
VDD
The Output Driver buffers the wiper voltage (VW) of the
Resistor Ladder.
Note:
The load resistance must keep higher than
5 k for the stable and expected analog
output (to meet electrical specifications).
PD1:PD0
VW
VOUT
+
PD1:PD0
Gain(1)
1 k
The DAC output is buffered with a low power and
precision output amplifier (op amp). This amplifier
provides a rail-to-rail output with low offset voltage and
low noise. The amplifier’s output can drive the resistive
and high-capacitive loads without oscillation. The
amplifier provides a maximum load current which is
enough for most programmable voltage reference
applications. Refer to Section 1.0 “Electrical
Characteristics” for the specifications of the output
amplifier.
100 k
5.3
Note 1: Gain options are 1x and 2x.
FIGURE 5-5:
Output Driver Block Diagram.
Figure 5-5 shows the block diagram of the output driver
circuit.
5.3.1
The user can select the output gain of the output
amplifier. The gain options are:
The amplifier’s gain is controlled by the Gain (G)
configuration bit (see Register 4-5) and the VRL
reference selection.
a)
b)
Gain of 1, with either the VDD or VREF pin used
as reference voltage.
Gain of 2.
Power-down logic also controls the output buffer
operation
(see
Section 5.6
“Power-Down
Operation”
for
additional
information
on
Power-Down). In any of the three power-down modes,
the op amp is powered-down and its output becomes a
high impedance to the VOUT pin.
PROGRAMMABLE GAIN
The volatile G bit value can be modified by:
• POR events
• BOR events
• SPI write commands
Table 5-1 shows the gain bit operation.
TABLE 5-1:
OUTPUT DRIVER GAIN
Gain Bit
Gain
0
1
1
2
Comment
Limits VREF pin voltages
relative to device VDD voltage.
DS20005429B-page 44
2015 Microchip Technology Inc.
MCP48FEBXX
5.3.2
OUTPUT VOLTAGE
The volatile DAC Register values, along with the
device’s configuration bits, control the analog VOUT
voltage. The volatile DAC Register’s value is unsigned
binary. The formula for the output voltage is given in
Equation 5-2. Table 5-3 shows examples of volatile
DAC register values and the corresponding theoretical
VOUT voltage for the MCP48FEBXX devices.
EQUATION 5-2:
CALCULATING OUTPUT
VOLTAGE (VOUT)
V RL DAC Register Value
VOUT = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
5.3.3
STEP VOLTAGE (VS)
The Step Voltage is dependent on the device resolution
and the calculated output voltage range. One LSb is
defined as the ideal voltage difference between two
successive codes. The step voltage can easily be
calculated by using Equation 5-3 (DAC Register Value
is equal to 1). Theoretical step voltages are shown in
Table 5-2 for several VREF voltages.
EQUATION 5-3:
VS CALCULATION
V RL
VS = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
Where:
Where:
# Resistors in R-Ladder = 4096 (MCP48FEB2X)
# Resistors in R-Ladder = 4096 (12-bit)
1024 (10-bit)
1024 (MCP48FEB1X)
256 (8-bit)
256 (MCP48FEB0X)
Note:
When Gain = 2 (VRL = VREF) and
if VREF > VDD / 2, the VOUT voltage will be
limited to VDD. So if VREF = VDD, then the
VOUT voltage will not change for volatile
DAC Register values mid-scale and greater,
since the op amp is at full-scale output.
The following events update the DAC register value
and therefore the analog voltage output (VOUT):
• Power-on Reset
• Brown-out Reset
• Write command
TABLE 5-2:
THEORETICAL STEP
VOLTAGE (VS) (1)
VREF
5.0
2.7
1.8
1.5
1.22 mV
659 uV
439 uV
366 uV
1.0
244 uV 12-bit
VS 4.88 mV 2.64 mV 1.76 mV 1.46 mV 977 uV 10-bit
19.5 mV 10.5 mV 7.03 mV 5.86 mV 3.91 mV 8-bit
Note 1: When Gain = 1x, VFS = VRL, and VZS = 0V.
The VOUT voltage will start driving to the new value
after the event has occurred.
2015 Microchip Technology Inc.
DS20005429B-page 45
MCP48FEBXX
5.3.4
OUTPUT SLEW RATE
Figure 5-6 shows an example of the slew rate of the
VOUT pin. The slew rate can be affected by the
characteristics of the circuit connected to the VOUT pin.
VOUT(B)
DACx = A
DACx= B
Time
V OUT B – V OUT A
Slew Rate = -------------------------------------------------T
FIGURE 5-6:
5.3.4.1
VOUT pin Slew Rate.
Small Capacitive Load
With a small capacitive load, the output buffer’s current
is not affected by the capacitive load (CL). But still, the
VOUT pin’s voltage is not a step transition from one
output value (DAC register value) to the next output
value. The change of the VOUT voltage is limited by the
output buffer’s characteristics, so the VOUT pin voltage
will have a slope from the old voltage to the new
voltage. This slope is fixed for the output buffer, and is
referred to as the buffer slew rate (SRBUF).
5.3.4.2
DRIVING RESISTIVE AND
CAPACITIVE LOADS
The VOUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications). A VOUT vs. Resistive Load
characterization graph is provided in the Typical
Performance Curves for this device (DS20005440).
VOUT drops slowly as the load resistance decreases
after about 3.5 k. It is recommended to use a load
with RL greater than 5 k.
VOUT
VOUT(A)
5.3.5
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the VOUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
VOUT pin.
When driving large capacitive loads with the output
buffer, a small series resistor (RISO) at the output (see
Figure 5-7) improves the output buffer’s stability
(feedback loop’s phase margin) by making the output
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
Large Capacitive Load
With a larger capacitive load, the slew rate is
determined by two factors:
• The output buffer’s short-circuit current (ISC)
• The VOUT pin’s external load
IOUT cannot exceed the output buffer’s short-circuit
current (ISC), which fixes the output buffer slew rate
(SRBUF). The voltage on the capacitive load (CL), VCL,
changes at a rate proportional to IOUT, which fixes a
capacitive load slew rate (SRCL).
The VCL voltage slew rate is limited to the slower of the
output buffer’s internally set slew rate (SRBUF) and the
capacitive load slew rate (SRCL).
VW
Op
Amp
VOUT
VCL
RISO
RL
CL
FIGURE 5-7:
Circuit to Stabilize Output
Buffer for Large Capacitive Loads (CL).
The RISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this RISO resistor
value should be verified on the bench. Modify the
RISO’s resistance value until the output characteristics
meet your requirements.
A method to evaluate the system’s performance is to
inject a step voltage on the VREF pin and observe the
VOUT pin’s characteristics.
Note:
DS20005429B-page 46
Additional insight into circuit design for
driving capacitive loads can be found in
AN884 – “Driving Capacitive Loads With
Op Amps” (DS00884).
2015 Microchip Technology Inc.
MCP48FEBXX
TABLE 5-3:
Device
DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (VOUT) (VDD = 5.0V)
LSb
Equation
µV
5.0V
5.0V/4096
1,220.7
1x
VRL (4095/4096) 1
2.5V
2.5V/4096
610.4
1x
VRL (4095/4096) 1
2.499390
VRL (4095/4096) 2)
4.998779
1x
VRL (2047/4096) 1)
2.498779
VRL(1)
1111 1111 1111
(2)
MCP48FEB2X (12-bit)
2x
0111 1111 1111
0011 1111 1111
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
MCP48FEB1X (10-bit)
01 1111 1111
00 1111 1111
00 0000 0000
MCP48FEB0X (8-bit)
1111 1111
0111 1111
0011 1111
1.249390
VRL (2047/4096) 2)
2.498779
1.248779
5.0V
5.0V/4096
1,220.7
1x
VRL (1023/4096) 1)
2.5V
2.5V/4096
610.4
1x
VRL (1023/4096) 1)
0.624390
VRL (1023/4096) 2)
1.248779
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
1x
VRL (0/4096) * 1)
1x
VRL (0/4096) * 1)
0
2x(2)
VRL (0/4096) * 2)
0
3:
0
5.0V
5.0V/1024
4,882.8
1x
VRL (1023/1024) 1
4.995117
2.5V
2.5V/1024
2,441.4
1x
VRL (1023/1024) 1
2.497559
2x(2)
VRL (1023/1024) 2
4.995117
1x
VRL (511/1024) 1
2.495117
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
1x
VRL (511/1024) 1
1.247559
2x(2)
VRL (511/1024) 2
2.495117
5.0V
5.0V/1024
4,882.8
1x
VRL (255/1024) 1
1.245117
2.5V
2.5V/1024
2,441.4
1x
VRL (255/1024) 1
0.622559
2x(2)
VRL (255/1024) 2
1.245117
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
1x
VRL (0/1024) 1
0
1x
VRL (0/1024) 1
0
2x(2)
VRL (0/1024) 1
0
5.0V
5.0V/256
19,531.3
1x
VRL (255/256) 1
4.980469
2.5V
2.5V/256
9,765.6
1x
VRL (255/256) 1
2.490234
2x(2)
VRL (255/256) 2
4.980469
1x
VRL (127/256) 1
2.480469
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
1x
VRL (127/256) 1
1.240234
2x(2)
VRL (127/256) 2
2.480469
5.0V
5.0V/256
19,531.3
1x
VRL (63/256) 1
1.230469
2.5V
2.5V/256
9,765.6
1x
VRL (63/256) 1
0.615234
VRL (63/256) 2
1.230469
1x
VRL (0/256) 1
0
1x
VRL (0/256) 1
0
2x(2)
VRL (0/256) 2
0
2x
Note 1:
2:
4.998779
VRL (2047/4096) 1)
(2)
0000 0000
V
1x
2x
11 1111 1111
Equation
2x(2)
(2)
0000 0000 0000
VOUT(3)
Gain
Selection (2)
Volatile DAC
Register Value
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
VRL is the resistor ladder’s reference voltage. It is independent of VREF1:VREF0 selection.
Gain selection of 2x (Gx = ‘1‘) requires voltage reference source to come from VREF pin
(VREF1:VREF0 = ‘10‘ or ‘11’) and requires VREF pin voltage (or VRL) ≤ VDD/2, or from the internal band
gap (VREF1:VREF0 = ‘01’).
These theoretical calculations do not take into account the Offset, Gain and Nonlinearity errors.
2015 Microchip Technology Inc.
DS20005429B-page 47
MCP48FEBXX
5.4
Internal Band Gap
The internal band gap is designed to drive the Resistor
Ladder Buffer.
The resistance of a resistor ladder (RRL) is targeted to
be 140 k (40 k), which means a minimum
resistance of 100 k.
The band gap selection can be used across the VDD
voltages while maximizing the VOUT voltage ranges.
For VDD voltages below the 2 Gain VBG voltage, the
output for the upper codes will be clipped to the VDD
voltage. Table 5-4 shows the maximum DAC register
code given device VDD and Gain bit setting.
5.5
2.7
2.0
3)
(
DAC Gain
VDD
TABLE 5-4:
VOUT USING BAND GAP
Max DAC Code (1)
12-bit 10-bit 8-bit
Comment
1
FFFh
3FFh
FFh VOUT(max) = 2.44V (2)
2
FFFh
3FFh
FFh VOUT(max) = 4.88V (2)
1
FFFh
3FFh
FFh VOUT(max) = 2.44V (2)
2
8DAh
236h
8Dh ~ 0 to 55% range
1
D1Dh
347h
D1h ~ 0 to 82% range
68Eh
1A3h
68h
2
(4)
~ 0 to 41% range
Note 1:
2:
3:
Without the VOUT pin voltage being clipped.
When VBG = 1.22V typical.
Band gap performance achieves full
performance starting from a VDD of 2.0V.
4:
It is recommended to use Gain = 1 setting
instead.
DS20005429B-page 48
2015 Microchip Technology Inc.
MCP48FEBXX
5.5
Latch Pin (LAT)
The Latch pin controls when the volatile DAC Register
value is transferred to the DAC wiper. This is useful for
applications that need to synchronize the wiper(s)
updates to an external event, such as zero crossing or
updates to the other wipers on the device. The LAT pin
is asynchronous to the serial interface operation.
Serial Shift Reg
Register Address
Write Command
16 Clocks
Vol. DAC Register x
LAT
Transfer
SYNC
Data
(internal signal)
DAC wiper x
When the LAT pin is high, transfers from the volatile DAC
register to the DAC wiper are inhibited. The volatile DAC
register value(s) can be continued to be updated.
When the LAT pin is low, the volatile DAC register value
is transferred to the DAC wiper.
Note:
This allows both the volatile DAC0 and
DAC1 Registers to be updated while the
LAT pin is high, and to have outputs
synchronously updated as the LAT pin is
driven low.
Figure 5-8 shows the interaction of the LAT pin and the
loading of the DAC wiper x (from the volatile DAC
Register x). The transfers are level driven. If the
LAT pin is held low, the corresponding DAC wiper is
updated as soon as the volatile DAC Register value is
updated.
LAT SYNC
Transfer
Data
Comment
1
1
0
No Transfer
1
0
0
No Transfer
0
1
1
Vol. DAC Register x DAC wiper x
0
0
0
No Transfer
FIGURE 5-8:
LAT and DAC Interaction.
The LAT pin allows the DAC wiper to be updated to an
external event as well as have multiple DAC
channels/devices update at a common event.
Since the DAC wiper x is updated from the Volatile
DAC Register x, all DACs that are associated with a
given LAT pin can be updated synchronously.
If the application does not require synchronization, then
this signal should be tied low.
Figure 5-9 shows two cases of using the LAT pin to
control when the wiper register is updated relative to
the value of a sine wave signal.
Case 1: Zero Crossing of Sine Wave to update volatile DAC0 register (using LAT pin)
Case 2: Fixed Point Crossing of Sine Wave to update volatile DAC0 register (using LAT pin)
Indicates where LAT pin pulses active (volatile DAC0 register updated).
FIGURE 5-9:
Example use of LAT pin operation.
2015 Microchip Technology Inc.
DS20005429B-page 49
MCP48FEBXX
Power-Down Operation
• Turn off most the DAC module’s internal circuits
(output op amp, resistor ladder, et al.)
• Op amp output becomes high-impedance to the
VOUT pin
• Disconnects resistor ladder from reference
voltage (VRL)
• Retains the value of the volatile DAC register and
configuration bits and the nonvolatile (EEPROM)
DAC register and configuration bits
Depending on the selected power-down mode, the
following will occur:
• VOUT pin is switched to one of two resistive
pull-downs (See Table 5-5):
- 100 k (typical)
- 1 k (typical)
• Op amp is powered-down and the VOUT pin
becomes high-impedance.
There is a delay (TPDE) between the PD1:PD0 bits
changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ with the
op amp no longer driving the VOUT output and the
pull-down resistors sinking current.
In any of the power-down modes where the VOUT pin is
not externally connected (sinking or sourcing current),
the power-down current will typically be ~650 nA for a
single-DAC device. As the number of DACs increases,
the device’s power-down current will also increase.
The Power-Down bits are modified by using a write
command to the volatile Power-Down register, or a POR
event which transfers the nonvolatile Power-Down
register to the volatile Power-Down register.
Section 7.0 “SPI Commands” describes the SPI
commands. The Write Command can be used to update
the volatile PD1:PD0 bits.
Note:
The SPI serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
host controller device.
DS20005429B-page 50
VDD
PD1:PD0
VW
VOUT
+
PD1:PD0
Gain(1)
100 k
To allow the application to conserve power when the
DAC operation is not required, three power-down
modes are available. The Power-Down configuration
bits (PD1:PD0) control the power-down operation
(Figure 5-10 and Table 5-5). On devices with multiple
DACs, each DACs power-down mode is individually
controllable. All power-down modes do the following:
1 k
5.6
Note 1: Gain options are 1x and 2x.
FIGURE 5-10:
Diagram.
VOUT Power-Down Block
TABLE 5-5:
PD1
PD0
0
0
POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
Function
Normal operation
0
1
1 k resistor to ground
1
0
100 k resistor to ground
1
1
Open Circuit
Table 5-6 shows the current sources for the DAC based
on the selected source of the DAC’s reference voltage
and if the device is in normal operating mode or one of
the power-down modes.
TABLE 5-6:
DAC CURRENT SOURCES
PD1:0 = ‘00’,
PD1:0 ‘00’,
Device VDD
VREF1:0
=
VREF1:0 =
Current
Source
00 01 10 11 00 01 10 11
Output
Op Amp
Y
Y
Y
Y
N
N
N
N
Resistor
Ladder
Y
Y
N (1)
Y
N
N
N (1)
N
RL Op Amp
N
Y
N
Y
N
N
N
N
Band Gap
N
Y
N
N
N
Y
N
N
Note 1:
Current is sourced from the VREF pin, not
the device VDD.
2015 Microchip Technology Inc.
MCP48FEBXX
5.6.1
EXITING POWER-DOWN
When the device exits Power-Down mode, the
following occurs:
• Disabled circuits (op amp, resistor ladder, et al.)
are turned on
• The resistor ladder is connected to selected
reference voltage (VRL)
• The selected pull-down resistor is disconnected
• The VOUT output will be driven to the voltage
represented by the volatile DAC Register’s value
and configuration bits
The VOUT output signal will require time as these
circuits are powered-up and the output voltage is driven
to the specified value as determined by the volatile
DAC register and configuration bits.
Note:
Since the op amp and resistor ladder were
powered-off (0V), the op amp’s input
voltage (VW) can be considered 0V. There
is a delay (TPDD) between the PD1:PD0
bits updating to ‘00’ and the op amp
driving the VOUT output. The op amp’s
settling time (from 0V) needs to be taken
into account to ensure the VOUT voltage
reflects the selected value.
A write command forcing the PD1:PD0 bits to ‘00’, will
cause the device to exit the power-down mode.
5.7
DAC Registers, Configuration
Bits, and Status Bits
The MCP48FEBXX devices have both volatile and
nonvolatile (EEPROM) memory. Table 4-2 shows the
volatile and non-volatile memory and their interaction
due to a POR event.
There are five configuration bits in both the volatile and
nonvolatile memory, the DAC registers in both the
volatile and nonvolatile memory, and two volatile status
bits. The DAC registers (volatile and nonvolatile) will be
either 12 bits (MCP48FEB2X), 10 bits (MCP48FEB1X),
or 8 bits (MCP48FEB0X) wide.
When the device is first powered-up, it automatically
uploads the EEPROM memory values to the volatile
memory. The volatile memory determines the analog
output (VOUT) pin voltage. After the device is
powered-up, the user can update the device memory.
The SPI interface is how this memory is read and
written. Refer to Section 6.0 “SPI Serial Interface
Module” and Section 7.0 “SPI Commands” for more
details on reading and writing the device’s memory.
When the nonvolatile memory is written, the device
starts writing the EEPROM cell at the rising edge of the
CS pin.
Register 4-4 shows the operation of the device status
bits, Table 4-1 and Table 4-3 show the operation of the
device configuration bits, and Table 4-2 shows the
factory default value of a POR/BOR event for the
device configuration bits.
There are two status bits. These are only in volatile
memory and give indication on the status of the device.
The POR bit indicates if the device VDD is above or
below the POR trip point. During normal operation, this
bit should be ‘1’. The EEWA bit indicates if an
EEPROM write cycle is in progress. While the EEWA
bit is low (during the EEPROM writing), all commands
are ignored, except for the Read command.
2015 Microchip Technology Inc.
DS20005429B-page 51
MCP48FEBXX
NOTES:
DS20005429B-page 52
2015 Microchip Technology Inc.
MCP48FEBXX
6.0
SPI SERIAL INTERFACE
MODULE
6.2
The MCP48FEBXX’s SPI Serial Interface Module
supports the SPI serial protocol specification.
Figure 6-1 shows a typical SPI interface connection.
SPI SERIAL INTERFACE
The MCP48FEBXX devices support the SPI serial
protocol. This SPI operates in slave mode (does not
generate the serial clock).
The SPI interface uses up to four pins. These are:
The command format and waveforms for the
MCP48FEBXX is defined in Section 7.0 “SPI
Commands”.
•
•
•
•
6.1
An additional HVC pin is available for High Voltage
command support. High Voltage commands allow the
device to enable and disable nonvolatile configuration
bits. Without high voltage present, those bits are
inhibited from being modified.
Overview
This sections discusses some of the specific
characteristics of the MCP48FEBXX’s Serial Interface
Module.
The following sections discuss some of these
device-specific characteristics:
•
•
•
•
Communication Data Rates
Communication Data Rates
POR/BOR
Interface Pins (CS, SCK, SDI, SDO, and
LAT/HVC)
CS - Chip Select
SCK - Serial Clock
SDI - Serial Data In
SDO - Serial Data Out
Typical SPI Interfaces are shown in Figure 6-1. In the
SPI interface, the Master’s Output pin is connected to
the Slave’s Input pin, and the Master’s Input pin is
connected to the Slave’s Output pin.
The MCP48FEBXX SPI’s module supports two (of the
four) standard SPI modes. These are Mode 0,0 and
1,1. The SPI mode is determined by the state of the
SCK pin (VIH or VIL) when the CS pin transitions from
inactive (VIH) to active (VIL).
The HVC pin is high-voltage tolerant. To enter a
high voltage command, the HVC pin must be greater
than the VIHH voltage.
6.3
Communication Data Rates
The MCP48FEBXX supports clock rates (bit rate) of up
to 20 MHz for write commands and 10 MHz for read
commands.
For most applications, the write time will be considered
more important, since that is how the device operation
is controlled.
6.4
POR/BOR
On a POR/BOR event, the SPI Serial Interface Module
state machine is reset, which includes that the
Device’s Memory Address pointer is forced to 00h.
Typical SPI Interface Connections
Host
Controller
MCP48FEBXX
SDO
(Master Out - Slave In (MOSI))
SDI
SDI
(Master In - Slave Out (MISO))
SDO
SCK
SCK
I/O
CS
I/O (1)
HVC (2)
Note 1: If High Voltage commands are desired, some type of external circuitry needs to be implemented.
2: Requires the VIHH voltage to enable the High Voltage commands.
FIGURE 6-1:
Typical SPI Interface Block Diagram.
2015 Microchip Technology Inc.
DS20005429B-page 53
MCP48FEBXX
6.5
Interface Pins (CS, SCK, SDI, SDO,
and LAT/HVC)
The operation of the five interface pins and the
High Voltage command (HVC) pin are discussed in
this section. These pins are:
•
•
•
•
•
SDI (Serial Data In)
SDO (Serial Data Out)
SCK (Serial Clock)
CS (Chip Select)
LAT/HVC (High Voltage command)
SERIAL DATA IN (SDI)
Serial Data Out (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL or
VIHH), the SDO pin will be driven. The state of the
SDO pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
6.5.1.2
The Chip Select (CS) signal is used to select the
device and frame a command sequence. To start a
command, or sequence of commands, the CS signal
must transition from the inactive state (VIH) to an
active state (VIL or VIHH).
Note: There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the
rising edge of the SCK signal.
6.5.1.1
The CS Signal
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
The serial interface works on either 8-bit or 24-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
6.5.1
6.5.1.3
Serial Clock (SCK)
(SPI Frequency Of Operation)
The SPI interface is specified to operate up to 20 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the
VIH level.
When the CS pin returns to the inactive state (VIH), the
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
6.5.1.4
The HVC Signal
The high-voltage capability of the HVC pin allows High
Voltage commands. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
6.5.2
THE SPI MODES
The SPI module supports two (of the four) standard
SPI modes. These are Mode 0,0 and 1,1. The mode
is determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.5.2.1
Mode 0,0
In Mode 0,0:
TABLE 6-1:
SCK FREQUENCY
Command
Read
Write,
Enable,
Disable
10 MHz
20 MHz (1, 2)
Memory Type Access
Nonvolatile
Memory
Volatile
Memory
SDI, SDO
• SCK idle state = low (VIL)
• Data is clocked in on the SDI pin on the rising
edge of SCK
• Data is clocked out on the SDO pin on the falling
edge of SCK
6.5.2.2
Mode 1,1
In Mode 1,1:
SDI, SDO
10 MHz
20 MHz
(2)
Note 1: After a write command, the internal write
cycle must complete before the next SPI
command is received.
2: This is a design goal. The SDO pin
performance is believed to be the limiting
factor.
DS20005429B-page 54
• SCK idle state = high (VIH)
• Data is clocked in on the SDI pin on the rising
edge of SCK
• Data is clocked out on the SDO pin on the falling
edge of SCK
2015 Microchip Technology Inc.
MCP48FEBXX
7.0
The supported commands are shown in Table 7-1. These
commands allow for both single data or continuous data
operation. Table 7-1 also shows the required number of
bit clocks for each command’s different mode of
operation.
SPI COMMANDS
This section documents the commands that the device
supports.
The MCP48FEBXX’s SPI command format supports
32 memory address locations and four commands.
Commands may have two modes. These are:
Normal Serial commands are those where the HVC
pin is driven to either VIH or VIL. With High-Voltage
Serial commands, the HVC pin is driven to VIHH.
• Normal Serial Commands
• High-Voltage Serial Commands
The 8-bit commands (see Figure 7-1) are used to
modify the device Configuration bits (Enable
Configuration Bit and Disable Configuration Bit),
while the 24-bit commands (see Figure 7-2) are used
to read and write to the device registers (Read
Command and Write Command). These commands
contain a Command Byte and two Data Bytes.
The four commands are:
• Write command (C1:C0 = ‘00’)
• Read command (C1:C0 = ‘11’)
• Commands to Modify the Device Configuration
Bits:
(HVC = VIHH)
- Enable Configuration Bit (C1:C0 = ‘10’)
- Disable Configuration Bit (C1:C0 = ‘01’)
TABLE 7-1:
Table 7-2 shows an overview of all the SPI commands
and their interaction with other device features.
SPI COMMANDS - NUMBER OF CLOCKS
Command
Code
Operation
HV
Write Command
C1
C0
0
0
Mode(1)
No (3) Single
(3)
Continuous
0
No
1
No (3)
Single
1
1
No (3)
Continuous
Enable Configuration
Bit Command
1
0
Yes Single
1
0
Yes Continuous
Disable Configuration
Bit Command
0
1
Yes Single
0
1
Yes Continuous
0
Read Command
Note 1:
2:
3:
4:
(4)
1
# of Bit
Clocks
(2)
Data Update Rate
(8-bit/10-bit/12-bit)
(Data Words/Second)
@ 1 MHz @ 10 MHz
Comments
@ 20 MHz(3)
24
41,666
416,666
833,333
24 * n
41,666
416,666
833,333
24
41,666
416,666
833,333
24 * n
41,666
416,666
833,333
8
8*n
8
8*n
For 10 data words
For 10 data words
125,000 1,250,000 2,500,000
125,000 1,250,000 2,500,000 For 10 data words
125,000 1,250,000 2,500,000
125,000 1,250,000 2,500,000 For 10 data words
Nonvolatile registers can only use the “Single” mode.
“n” indicates the number of times the command operation is to be repeated.
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition
(CMDERR) will NOT be generated.
This command is useful to determine when an EEPROM programming cycle has completed.
2015 Microchip Technology Inc.
DS20005429B-page 55
MCP48FEBXX
7.0.1
COMMAND BYTE
TABLE 7-2:
The command byte has three fields: the address, the
command, and one data bit (see Figure 7-1). Currently
only one of the data bits is defined (D8). This is for the
Write command.
C1:C0
Bit
States
# of
Bits
Command
Normal or HV
11
Read Data
24-Bits Normal
00
Write Data
24-Bits Normal
8-Bits HV Only
01
Enable (1)
10
Disable (1)
8-Bits HV Only
Note 1: High Voltage enable and disable
commands on select nonvolatile memory
locations.
The device memory is accessed when the master
sends a proper command byte to select the desired
operation. The memory location getting accessed is
contained in the command byte’s AD4:AD0 bits. The
action desired is contained in the command byte’s
C1:C0 bits, see Table 7-2. C1:C0 determines if the
desired memory location will be read, written, enabled
or disabled.
As the command byte is being loaded into the device
(on the SDI pin), the device’s SDO pin is driving. The
SDO pin will output high bits for the first seven bits of
that command. On the 8th bit, the SDO pin will output
the CMDERR bit state (see Section 7.0.3 “Error
Condition”).
7.0.2
COMMAND BIT OVERVIEW
8-bit Command
Command Byte
A A A A A C C C
D D D D D 1 0 M
4 3 2 1 0
D
E
R
R
DATA BYTES
Data bytes are only present in the Read and the
Write commands. These commands concatenate the
two data bytes after the command byte, for a 24-bit
long command (see Figure 7-1).
Memory
Address
Command
Bits
CC
1 0
0 0 = Write Data
0 1 = Disable (1)
1 0 = Enable (1)
1 1 = Read Data
Command
Bits
Note 1: This command uses the 8-bit format.
FIGURE 7-1:
8-Bit SPI Command Format.
24-bit Command
Command Byte
Data Word (2 Bytes)
A A A A A C C C D D D D D D D D D D D D D D D D
D D D D D 1 0 M 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
4 3 2 1 0
D 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
E
R
R
Data Bits (8-, 10-, or 12-bits)
Memory
Address
Command
Bits
CC
1 0
0 0 = Write Data (1)
0 1 = Disable
1 0 = Enable
1 1 = Read Data (1)
Command
Bits
Note 1: This command uses the 24-bit format.
FIGURE 7-2:
DS20005429B-page 56
24-bit SPI Command Format.
2015 Microchip Technology Inc.
MCP48FEBXX
7.0.3
ERROR CONDITION
The Command Error (CMDERR) bit indicates if the
five address bits received (AD4:AD0) and the two
command bits received (C1:C0) are a valid
combination (see Figures 7-1 and 7-2). The CMDERR
bit is high if the combination is valid and low if the
combination is invalid.
The Command Error bit will also be low if a write to a
nonvolatile address has been specified and another
SPI command occurs before the CS pin is driven
inactive (VIH).
SPI commands that do not have a multiple of eight
clocks are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
7.0.3.1
Aborting a Transmission
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the
CS pin to be forced inactive (VIH). If the CS pin is
forced to the inactive state (VIH), the serial interface is
reset. Partial commands are not executed.
7.0.4
CONTINUOUS COMMANDS
The device supports the ability to execute commands
continuously. While the CS pin is in the active state
(VIL), any sequence of valid commands may be
received.
The following example is a valid sequence of events:
1.
2.
3.
4.
5.
CS pin driven active (VIL)
Read command
Write command (Volatile memory)
Write command (Nonvolatile memory)
CS pin driven inactive (VIH)
Note 1: It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is advisable to take the CS pin inactive
then force it back to the active state.
2: It is also recommended that long
command strings should be broken down
into shorter command strings. This
reduces the probability of noise on the
SCK pin, corrupting the desired SPI
command string.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that noise corrupts
the value of the data being clocked into the
MCP48FEBXX or the SCK pin is injected with extra
clock pulses. This may cause data to be corrupted in
the device, or a Command Error to occur, since the
address and command bits were not a valid
combination. The extra SCK pulse will also cause the
SPI data (SDI) and clock (SCK) to be out of sync.
Forcing the CS pin to the inactive state (VIH) resets the
serial interface. The SPI interface will ignore activity on
the SDI and SCK pins until the CS pin transition to the
active state is detected (VIH to VIL or VIH to VIHH).
Note 1: When data is not being received by the
MCP48FEBXX, it is recommended that the
CS pin be forced to the inactive level (VIL).
2: It is also recommended that long
continuous command strings be broken
down into single commands or shorter
continuous command strings. This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
commands.
2015 Microchip Technology Inc.
DS20005429B-page 57
MCP48FEBXX
7.1
Write Command
Write commands are used to transfer data to the
desired memory location (from the Host controller). The
Write command can be issued to both the volatile and
nonvolatile memory locations.
Write commands can be structured as either Single or
Continuous.
The format of the command is shown in Figures 7-3
(Single) and 7-4 (Continuous).
A write command to a volatile memory location
changes that location after a properly formatted write
command has been received.
A write command to a nonvolatile memory location will
start an EEPROM write cycle only after a properly
formatted write command has been received and the
CS pin transitions to the inactive state (VIH).
Note 1: Writes to certain memory locations will be
dependent on the state of the
WiperLock™ technology status bits.
2: During device communication, if the
Device Address/Command combination is
invalid or an unimplemented Device
Address
is
specified,
then
the
MCP48FEBXX will generate a Command
Error state. To reset the SPI state
machine, the CS pin must transition to the
inactive state (VIH).
7.1.1
SINGLE WRITE TO VOLATILE
MEMORY
The write operation requires that the CS pin be in the
active state (VIL). Typically, the CS pin will be in the
inactive state (VIH) and is driven to the active state
(VIL). The 24-bit Write command (Command Byte
and Data Bytes) is then clocked in on the SCK and
SDI pins. Once all 24 bits have been received, the
specified volatile address is updated. A write will not
occur if the Write command isn’t exactly 24 clock
pulses. This protects against system issues corrupting
the nonvolatile memory locations.
Figures 7-5 and 7-6 show the waveforms for a single
write (depending on SPI mode).
7.1.2
SINGLE WRITE TO NONVOLATILE
MEMORY
The sequence to write to a single nonvolatile memory
location is the same as a single write to volatile
memory with the exception that after the CS pin is
driven inactive (VIH), the EEPROM write cycle (tWC) is
started. A write cycle will not start if the Write
command isn’t exactly 24 clock pulses. This protects
against system issues corrupting the nonvolatile
memory locations.
Once a write command to a nonvolatile memory
location has been received, no other SPI commands
should be received before the CS pin transitions to the
inactive state (VIH), or the current SPI command will
have a Command Error (CMDERR) occur.
After the CS pin is driven inactive (VIH), the serial
interface may immediately be re-enabled by driving
the CS pin to the active state (VIL).
During an EEPROM write cycle, access to the volatile
memory is allowed when using the appropriate
command sequence. Commands that address
nonvolatile memory are ignored until the EEPROM
write cycle (tWC) completes. This allows the Host
Controller to operate on the volatile DAC registers.
Note:
The EEWA status bit indicates if an
EEPROM write cycle is active (see
Register 4-4).
Figures 7-5 and 7-6 show the waveforms for a single
write (depending on the SPI mode).
DS20005429B-page 58
2015 Microchip Technology Inc.
MCP48FEBXX
7.1.3
CONTINUOUS WRITES TO
VOLATILE MEMORY
7.1.4
A Continuous Write mode of operation is possible when
writing to the device’s volatile memory registers (see
Table 7-3). Figure 7-4 shows the sequence for three
continuous writes. The writes do not need to be to the
same volatile memory address.
TABLE 7-3:
Continuous writes to nonvolatile memory are not
allowed, and attempts to do so will result in a
Command Error (CMDERR) condition.
7.1.5
VOLATILE MEMORY
ADDRESSES
Single-Channel
Dual-Channel
00h
Yes
Yes
01h
No
Yes
08h
Yes
Yes
09h
Yes
Yes
0Ah
Yes
Yes
is ignored, but a Command Error condition (CMDERR)
will NOT be generated.
Command
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
0
0
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
C D
M 1
D 5
E
R
R
1 1
0 0
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
If the state of the HVC pin is VIHH, then the command
Address
Address
CONTINUOUS WRITES TO
NONVOLATILE MEMORY
Data bits (8, 10, or 12 bits)
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
0
9
D
0
8
D
0
7
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 Valid (1)
0 Invalid (2, 3)
Note 1: If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.
12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller
operation (i.e., no data manipulation before transmitting the desired value).
2: Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)
will be output as ‘1’.
3: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition
is cleared (the CS pin is forced to the inactive state).
FIGURE 7-3:
Write Command - SDI and SDO States.
2015 Microchip Technology Inc.
DS20005429B-page 59
MCP48FEBXX
Address
Command
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
0
0
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address
Data bits (8, 10, or 12 bits)
C D
M 1
D 5
E
R
R
1 1
0 0
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
0
9
D
0
8
D
0
7
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 Valid (1)
0 Invalid (2, 3)
Command
Data bits (8, 10, or 12 bits)
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
0
0
C D
M 1
D 5
E
R
R
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
0
9
D
0
8
D
0
7
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
0
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid (1)
0
0
0
0
0
0
0 (4) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid (2, 3)
Address
Command
Data bits (8, 10, or 12 bits)
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
0
0
C D
M 1
D 5
E
R
R
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
0
9
D
0
8
D
0
7
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
0
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid (1)
0
0
0
0
0
0
0 (4) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid (2, 3)
Note 1: If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.
12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller
operation (i.e., no data manipulation before transmitting the desired value).
2: Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)
will be output as ‘1’.
3: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition
is cleared (the CS pin is forced to the inactive state).
4: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR condition.
FIGURE 7-4:
DS20005429B-page 60
Continuous Write Sequence (Volatile Memory only).
2015 Microchip Technology Inc.
MCP48FEBXX
HVC (1)
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
CMDERR bit
SDO
bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15
bit1
bit0
SDI
AD4 AD3 AD2 AD1 AD0
bit23 bit22 bit21 bit20 bit19
D1
bit1
D0
bit0
0
0
D16 D15
bit16 bit15
Input
Sample
Note
1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-5:
HVC (1)
24-Bit Write Command (C1:C0 = “00”) - SPI Waveform with PIC MCU (Mode 1,1).
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
CMDERR bit
SDO
bit23
bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15
AD4 AD3 AD2 AD1 AD0
bit23 bit22 bit21 bit20 bit19
SDI
0
0
D16 D15
bit16 bit15
bit1
bit0
D1
bit1
D0
bit0
Input
Sample
Note
1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-6:
24-Bit Write Command (C1:C0 = “00”) - SPI Waveform with PIC MCU (Mode 0,0).
2015 Microchip Technology Inc.
DS20005429B-page 61
MCP48FEBXX
7.2
Read Command
Note 1: During device communication, if the
Device Address/Command combination
is invalid or an unimplemented Address is
specified, then the MCP48FEBXX will
command error that byte. To reset the
SPI state machine, the CS pin must be
driven to the VIH state.
The Read command is a 24-bit command and is used
to transfer data from the specified memory location to
the Host controller. The Read command can be issued
to both the volatile and nonvolatile memory locations.
The format of the command as well as an example SDI
and SDO data is shown in Figure 7-7.
The first 7-bits of the Read command determine the
address and the command. The 8th clock will output
the CMDERR bit on the SDO pin. By means of the
remaining 16 clocks, the device will transmit the data
bits of the specified address (AD4:AD0).
2: If the LAT pin is High (VIH), reads of the
volatile DAC Register read the output
value, not the internal register.
3: The read commands operate the same
regardless of the state of the
High-Voltage Command (HVC) signal.
During an EEPROM write cycle (write to nonvolatile
memory
location
or
Enable/Disable
Configuration
Bit command), the Read
command can only read the volatile memory locations.
By reading the Status Register (0Ah), the Host
Controller can determine when the write cycle has
completed (via the state of the EEWA bit)
7.2.1
LAT PIN INTERACTION
During a Read command of the DACx Registers, if the
LAT pin transitions from VIH to VIL, then the read data
may be corrupted. This is due to the fact that the data
being read is the output value and not the DAC register
value. The LAT pin transition causes an update of the
output value. Based on the DAC output value, the
DACx register value, and the Command bit where the
LAT pin transitions, the value being read could be
corrupted.
The Read command formats include:
• Single Read
• Continuous Reads
If LAT pin transitions occur during a read of the DACx
register, it is recommended that sequential reads be
performed until the two most recent read values match.
Then the most recent read data is good.
7.2.2
SINGLE READ
The Read command operation requires that the
CS pin be in the active state (VIL). Typically, the CS pin
will be in the inactive state (VIH) and is driven to the
active state (VIL). The 24-bit Read command
(Command Byte and Data Byte) is then clocked in on
the SCK and SDI pins. The SDO pin starts driving data
on the 8th bit (CMDERR bit), and the addressed data
comes out on the 9th through 24th clocks.
Address
Command
A
D
4
A
D
3
A
D
2
A
D
1
A
D
0
1
1
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SDI
C
M
D
E
R
R
1
0
Data bits (8-, 10, or 12-bits)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
d
0
d
0
d
0
d
0
d
0
d
0
d
0
d
0
d
0
d
0
d
0
d Valid (1)
0 Invalid (2, 3)
Note 1: If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.
12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller
operation (i.e., no data manipulation before transmitting the desired value).
2: Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)
will be output as ‘1’.
3: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition
is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
DS20005429B-page 62
Read Command - SDI and SDO States.
2015 Microchip Technology Inc.
MCP48FEBXX
7.2.3
CONTINUOUS READS
Figure 7-8 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
Continuous-reads format allows the device’s memory
to be read quickly. Continuous reads are possible to all
memory locations. If a nonvolatile memory write cycle
is occurring, then read commands may only access the
volatile memory locations.
Address
This is useful in reading the System Status register
(0Ah) to determine if an EEPROM write cycle has
completed (EEWA bit).
Command
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
1
1
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
Address
Data bits (8, 10, or 12 bits)
C
M
D
E
R
R
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 Valid (1)
0 Invalid (2, 3)
Command
Data bits (8, 10, or 12 bits)
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
1
1
C
M
D
E
R
R
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid (1)
0
0
0
0
0
0
0 (4) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid (2, 3)
Address
Command
Data bits (8, 10, or 12 bits)
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
1
1
C
M
D
E
R
R
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid (1)
0
0
0
0
0
0
0 (4) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid (2, 3)
Note 1: If a valid Address/Command occurs, then the data bits are dependent on the resolution of the device.
12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data is right justified for ease of Host Controller
operation (i.e., no data manipulation before transmitting the desired value).
2: Unimplemented data bits (D15:D12 on 12-bit device, D15:D10 on 10-bit device, D15:D08 on 8-bit device)
will be output as ‘1’.
3: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition
is cleared (the CS pin is forced to the inactive state).
4: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This
command will not be completed and requires the CS pin to return to VIH to clear the CMDERR condition.
FIGURE 7-8:
Continuous-Reads Sequence.
2015 Microchip Technology Inc.
DS20005429B-page 63
MCP48FEBXX
HVC (1)
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
CMDERR bit
SDO
bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15
bit1
bit0
SDI
AD4 AD3 AD2 AD1 AD0
bit23 bit22 bit21 bit20 bit19
D1
bit1
D0
bit0
1
1
D16 D15
bit16 bit15
Input
Sample
Note
1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-9:
24-Bit Read Command (C1:C0 = “11”) - SPI Waveform with PIC MCU (Mode 1,1).
HVC (1)
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
SDO
CMDERR bit
bit23
bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15
AD4 AD3 AD2 AD1 AD0
bit23 bit22 bit21 bit20 bit19
SDI
1
1
D16 D15
bit16 bit15
bit1
bit0
D1
bit1
D0
bit0
Input
Sample
Note
1:
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.
FIGURE 7-10:
DS20005429B-page 64
24-Bit Read Command (C1:C0 = “11”) - SPI Waveform with PIC MCU (Mode 0,0).
2015 Microchip Technology Inc.
MCP48FEBXX
7.3
Commands to Modify the Device
Configuration Bits
7.4
The MCP48FEBXX devices support two commands
which are used to program the device’s configuration
bits. These commands require a high voltage (VIHH) on
the HVC pin. These commands are:
Enable Configuration Bit
(High Voltage)
Figure 7-11 (Enable) shows the formats for a single
Enable Configuration Bit command. The
command will only start the EEPROM write cycle (tWC)
after a properly formatted command has been
received.
• Enable Configuration Bit
• Disable Configuration Bit
During an EEPROM write cycle, only serial commands
to volatile memory are accepted. All other serial
commands are ignored until the EEPROM write cycle
(tWC) completes. This allows the Host Controller to
operate on the volatile DAC, the volatile VREF,
Power-Down, Gain and Status, and WiperLock
Technology Status registers. The EEWA bit in the
Status register indicates the status of the EEPROM
write cycle.
The configuration bits are used to inhibit the DAC
values from inadvertent modification. High voltage is
required to change the state of these bits if/when the
DAC values need to be modified.
7.4.1
HIGH-VOLTAGE COMMAND (HVC)
SIGNAL
The High-Voltage Command (HVC) signal is used to
indicate that the command, or sequence of commands,
are in the High-Voltage mode. Signals higher than VIHH
(~9.0V) on the LAT/HVC pin puts the device into
High-Voltage mode. High-Voltage commands allow the
device’s WiperLock technology and write-protect
features to be enabled and disabled.
Note 1: There is a required delay after the
HVC pin is driven to the VIHH level on the
1st edge of the SCK pin.
Address
Command
A
SDI D
4
A
D
3
A
D
2
A
D
1
A
D
0
1
0
C A
M D
D 4
E
R
R
A
D
3
A
D
2
A
D
1
A
D
0
1
0
C
M
D
E
R
R
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Invalid (1, 2)
Note 1: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
2: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid.
This command will not be completed and requires the CS pin to return to VIH to clear the
CMDERR condition.
FIGURE 7-11:
Enable Command Sequence.
2015 Microchip Technology Inc.
DS20005429B-page 65
MCP48FEBXX
VIHH
VIH
VIH
HVC
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
CMDERR bit
“1” = “Valid” Command/Address
“0” = “Invalid” Command/Address
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMDERR bit
SDI
AD4
AD3
AD2
AD1
AD0
1
bit0
0
bit0
bit7
Input
Sample
FIGURE 7-12:
8-Bit Enable Command (C1:C0 = “10”) - SPI Waveform with PIC MCU (Mode 1,1).
VIHH
VIH
VIH
HVC
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
SDO
CMDERR bit
“1” = “Valid” Command/Address
“0” = “Invalid” Command/Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMDERR bit
SDI
AD4
bit7
AD3
AD2
AD1
AD0
1
0
bit0
bit0
Input
Sample
FIGURE 7-13:
DS20005429B-page 66
8-Bit Enable Command (C1:C0 = “10”) - SPI Waveform with PIC MCU (Mode 0,0).
2015 Microchip Technology Inc.
MCP48FEBXX
7.5
7.5.1
Disable Configuration Bit
(High Voltage)
The High-Voltage Command (HVC) signal is used to
indicate that the command, or sequence of commands,
are in the High-Voltage mode. Signals higher than VIHH
(~9.0V) on the HVC pin puts the MCP48FEBXX
devices into High-Voltage mode. High Voltage
commands allow the device’s WiperLock technology
and write protect features to be enabled and disabled.
Figure 7-14 (Disable) shows the formats for a single
Disable Configuration Bit command. The
command will only start an EEPROM write cycle (tWC)
after a properly formatted command has been
received.
During an EEPROM write cycle, only serial commands
to volatile memory are accepted. All other serial
commands are ignored until the EEPROM write cycle
(tWC) completes. This allows the Host Controller to
operate on the volatile DAC, the volatile VREF,
Power-Down, Gain and Status, and WiperLock
Technology Status registers. The EEWA bit in the
Status register indicates the status of an EEPROM
write cycle.
Address
HIGH-VOLTAGE COMMAND (HVC)
SIGNAL
Note 1: There is a required delay after the HVC
pin is driven to the VIHH level to the 1st
edge of the SCK pin.
Command
A
D
4
A
D
3
A
D
2
A
D
1
A
D
0
0
1
C A
M D
D 4
E
R
R
A
D
3
A
D
2
A
D
1
A
D
0
0
1
C
M
D
E
R
R
SDO 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 Valid
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
SDI
Invalid (1, 2)
Note 1: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
2: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid.
This command will not be completed and requires the CS pin to return to VIH to clear the
CMDERR condition.
FIGURE 7-14:
Disable Command Sequence.
2015 Microchip Technology Inc.
DS20005429B-page 67
MCP48FEBXX
VIHH
VIH
VIH
HVC
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
CMDERR bit
“1” = “Valid” Command/Address
“0” = “Invalid” Command/Address
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMDERR bit
SDI
AD4
AD3
AD2
AD1
AD0
0
bit0
1
bit0
bit7
Input
Sample
FIGURE 7-15:
8-Bit Disable Command (C1:C0 = “01”) - SPI Waveform with PIC MCU (Mode 1,1).
VIHH
VIH
VIH
HVC
VIH
CS
VIL
SCK
PIC Write to
SSPBUF
SDO
CMDERR bit
“1” = “Valid” Command/Address
“0” = “Invalid” Command/Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CMDERR bit
SDI
AD4
bit7
AD3
AD2
AD1
AD0
0
1
bit0
bit0
Input
Sample
FIGURE 7-16:
DS20005429B-page 68
8-Bit Disable Command (C1:C0 = “01”) - SPI Waveform with PIC MCU (Mode 0,0).
2015 Microchip Technology Inc.
MCP48FEBXX
8.0
TYPICAL APPLICATIONS
The MCP48FEBXX family of devices are general
purpose, single/dual-channel voltage output DACs for
various applications where a precision operation with low
power and nonvolatile EEPROM memory is needed.
Since the devices include a nonvolatile EEPROM
memory, the user can utilize these devices for
applications that require the output to return to the
previous setup value on subsequent power-ups.
C1
Set Point or Offset Trimming
Sensor Calibration
Portable Instrumentation (Battery-Powered)
Motor Control
8.1
C2
VREF 3
VOUT0
Analog
Output
VOUT1
C3
Applications generally suited for the devices are:
•
•
•
•
VDD 1
CS 2
VDD
C4
Any noise induced on the VDD line can affect the DAC
performance. Typical applications will require a bypass
capacitor in order to filter out high-frequency noise on the
VDD line. The noise can be induced onto the power
supply’s traces or as a result of changes on the DAC
output. The bypass capacitor helps to minimize the effect
of these noise sources on signal integrity. Figure 8-1
shows an example of using two bypass capacitors (a
10 µF tantalum capacitor and a 0.1 µF ceramic capacitor)
in parallel on the VDD line. These capacitors should be
placed as close to the VDD pin as possible (within 4 mm).
If the application circuit has separate digital and analog
power supplies, the VDD and VSS pins of the device
should reside on the analog plane.
To MCU
7 V
SS
6 LAT/HVC
MCP48FEBX2
(a) Circuit when VDD is selected as reference
(Note: VDD is connected to the reference circuit internally.)
VDD
C1
C2
VDD 1
CS 2
VREF
C5
VREF 3
VOUT0
4
VOUT1
5
C6
Optional
Analog
Output
10 SDI
9 SCK
8 SDO
To MCU
7
VSS
6 LAT/HVC
MCP48FEBX2
C3
C4
Optional
(b) Circuit when external reference is used.
C1 :
0.1 µF capacitor
Ceramic
C2 :
10 µF capacitor
Tantalum
C3 :
~ 0.1 µF
Optional to reduce noise
in VOUT pin.
C4 :
0.1 µF capacitor
Ceramic
C5 :
10 µF capacitor
Tantalum
C6 :
0.1 µF capacitor
Ceramic
FIGURE 8-1:
Circuit.
2015 Microchip Technology Inc.
5
9 SCK
8 SDO
Optional
Power Supply Considerations
The power source should be as clean as possible. The
power supply to the device is also used for the DAC
voltage reference internally if the internal VDD is
selected as the resistor ladder’s reference voltage
(VRxB:VRxA = ‘00’).
4
10 SDI
Bypass Filtering Example
DS20005429B-page 69
MCP48FEBXX
8.2
Application Examples
The MCP48FEBXX devices are rail-to-rail output DACs
designed to operate with a VDD range of 2.7V to 5.5V.
The internal output operational amplifier is robust
enough to drive common, small-signal loads directly,
thus eliminating the cost and size of external buffers for
most applications. The user can use gain of 1 or 2 of
the output operational amplifier by setting the
Configuration register bits. Also, the user can use
internal VDD as the reference or use an external
reference. Various user options and easy-to-use
features make the devices suitable for various modern
DAC applications.
Application examples include:
•
•
•
•
•
•
•
•
•
Decreasing Output Step Size
Building a “Window” DAC
Bipolar Operation
Selectable Gain and Offset Bipolar Voltage Output
Designing a Double-Precision DAC
Building Programmable Current Source
Serial Interface Communication Times
Power Supply Considerations
Layout Considerations
8.2.1
8.2.1.1
Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve small step size are:
• Using Lower Vref Pin Voltage: Using an external
voltage reference (VREF) is an option if the
external reference is available with the desired
output voltage range. However, occasionally,
when using a low-voltage reference voltage, the
noise floor causes a SNR error that is intolerable.
• Using A Voltage Divider On The DAC’s Output:
Using a voltage divider provides some
advantages when external voltage reference
needs to be very low or when the desired output
voltage is not available. In this case, a larger
value reference voltage is used while two
resistors scale the output range down to the
precise desired level.
Figure 8-2 illustrates this concept. A bypass capacitor
on the output of the voltage divider plays a critical
function in attenuating the output noise of the DAC and
the induced noise from the environment.
VDD
DC SET POINT OR CALIBRATION
A common application for the devices is a
digitally-controlled set point and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP48FEB2X provides 4096 output
steps. If voltage reference is 4.096V (where Gx = ‘0’),
the LSb size is 1 mV. If a smaller output step size is
desired, a lower external voltage reference is needed.
Optional
VREF VDD
RSENSE
VCC+
VOUT
VTRIP Comp.
+
C1
V –
R1
MCP48FEBXX
VO
R2
SPI
4-wire
CC
FIGURE 8-2:
Example Circuit Of Set Point
or Threshold Calibration.
EQUATION 8-1:
VOUT AND VTRIP
CALCULATIONS
VOUT = VREF • G •
DAC Register Value
2N
R2
V trip = V OUT --------------------
R 1 + R 2
DS20005429B-page 70
2015 Microchip Technology Inc.
MCP48FEBXX
8.2.1.2
Building a “Window” DAC
8.3
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
If the threshold is not near VREF, 2 • VREF, or VSS, then
creating a “window” around the threshold has several
advantages. One simple method to create this “window”
is to use a voltage divider network with a pull-up and
pull-down resistor. Figure 8-3 and Figure 8-5 illustrate
this concept.
Bipolar Operation
Bipolar operation is achievable by utilizing an external
operational amplifier. This configuration is desirable
due to the wide variety and availability of op amps. This
allows a general purpose DAC, with its cost and
availability advantages, to meet almost any desired
output voltage range, power and noise performance.
Figure 8-4 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC's output to a selected
offset. Note that R4 can be tied to VDD instead of VSS if
a higher offset is desired.
Optional
VREF VDD
Optional
VREF VDD
VCC+
RSENSE
VCC+
R1
MCP48FEBXX
R3
VO
VTRIP Comp.
+
C1 V –
VOUT
SPI
4-wire
R2
VCC+
R3
MCP48FEBXX
VOUT
VOA+
VO
C1
R4
VCC–
SPI
4-wire
CC
R2
VIN
R1
VCC–
FIGURE 8-3:
DAC.
Single-Supply “Window”
FIGURE 8-4:
Digitally-Controlled Bipolar
Voltage Source Example Circuit.
EQUATION 8-2:
VOUT AND VTRIP
CALCULATIONS
EQUATION 8-3:
VOUT = VREF • G •
DAC Register Value
VOUT = VREF • G •
2N
V OUT R23 + V 23 R1
V TRIP = --------------------------------------------R 1 + R23
Thevenin
Equivalent
VOUT, VOA+, AND VO
CALCULATIONS
VOA+ =
R2R3
R23 = ------------------R2 + R3
VOUT
2N
VOUT • R4
R3 + R4
VO = VOA+ • (1 +
VCC+ R2 + V CC- R 3
V23 = -----------------------------------------------------R 2 + R3
DAC Register Value
R2
R1
) - VDD • (
R2
R1
)
R1
VTRIP
R23
V23
2015 Microchip Technology Inc.
DS20005429B-page 71
MCP48FEBXX
8.4
Selectable Gain and Offset Bipolar
Voltage Output
In some applications, precision digital control of the
output range is desirable. Figure 8-5 illustrates how to
use DAC devices to achieve this in a bipolar or
single-supply application.
This circuit is typically used for linearizing a sensor
whose slope and offset varies.
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
Bipolar DAC Example
Optional
VCC+
Optional
VREF VDD
R5
VCC+
R3
MCP48FEBXX
VO
SPI
4-wire
VOA+
C1
R4
R2
VIN
R1
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V.
C1 = 0.1 µF
Step 2: Calculate the resolution needed:
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is desired.
Step 3: The amplifier gain (R2/R1), multiplied by
full-scale VOUT (4.096V), must be equal to
the desired minimum output to achieve
bipolar operation. Since any gain can be
realized by choosing resistor values
(R1 + R2), the VREF value must be selected
first. If a VREF of 4.096V is used, solve for
the amplifier’s gain by setting the DAC to 0,
knowing that the output needs to be -2.05V.
FIGURE 8-5:
Bipolar Voltage Source with
Selectable Gain and Offset.
EQUATION 8-6:
VOUT, VOA+, AND VO
CALCULATIONS
VOUT = VREF • G •
VOA+ =
DAC Register Value
R3 + R4
VO = VOA+ • ( 1 +
EQUATION 8-4:
Step 4: Next, solve for R3 and R4 by setting the
DAC to 4096, knowing that the output
needs to be +2.05V.
EQUATION 8-5:
R4
2
2.05V + 0.5 4.096V
------------------------ = ------------------------------------------------------- = -- R3 + R 4
1.5 4.096V
3
If R4 = 20 k, then R3 = 10 k
R2
R1
) - VIN • (
Offset Adjust
R2
1
------ = --R1
2
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
2N
VOUT • R4 + VCC- • R5
The equation can be simplified to:
– R2
– 2.05
--------- = ----------------R1
4.096V
VCC–
VCC–
An output step size of 1 mV with an output range of
±2.05V is desired for a particular application.
VOUT
EQUATION 8-7:
Thevenin
Equivalent
R2
R1
)
Gain Adjust
BIPOLAR “WINDOW” DAC
USING R4 AND R5
V CC+ R 4 + VCC- R5
V 45 = --------------------------------------------R 4 + R5
VOUT R 45 + V 45 R 3
VIN+ = --------------------------------------------R3 + R 45
R4R5
R45 = ------------------R4 + R5
R2
R2
V O = V IN+ 1 + ------ – V A ------
R1
R1
Offset Adjust Gain Adjust
DS20005429B-page 72
2015 Microchip Technology Inc.
MCP48FEBXX
8.5
Designing a Double-Precision
DAC
8.6
Building Programmable Current
Source
Figure 8-6 shows an example design of a single-supply
voltage output capable of up to 24-bit resolution. This
requires two 12-bit DACs. This design is simply a
voltage divider with a buffered output.
Figure 8-7 shows an example of building a
programmable current source using a voltage follower.
The current sensor resistor is used to convert the DAC
voltage output into a digitally-selectable current source.
Double-Precision DAC Example
The smaller RSENSE is, the less power dissipated
across it. However, this also reduces the resolution that
the current can be controlled.
If a similar application to the one developed in Bipolar
DAC Example required a resolution of 1 µV instead of
1 mV and a range of 0V to 4.1V, then 12-bit resolution
would not be adequate.
Step 1: Calculate the resolution needed:
4.1V/1 µV = 4.1 x 106.
Since 222 = 4.2 x 106, 22-bit resolution is
desired. Since DNL = ±1.0 LSb, this design
can be attempted with the 12-bit DAC.
Step 2: Since DAC1’s VOUT1 has a resolution of
1 mV, its output only needs to be “pulled”
1/1000 to meet the 1 µV target. Dividing
VOUT0 by 1000 would allow the application
to compensate for DAC1’s DNL error.
Step 3: If R2 is 100, then R1 needs to be 100 k.
Step 4: The resulting transfer function is shown in
the equation of Example 8-8.
VREF
VDD
VOUT
Load
VCC+
IL
MCP48FEBXX
Ib
VCC–
SPI
4-wire
IL
Ib = ----
RSENSE
VOUT
I L = ------------------ ------------R SENSE + 1
where Common-Emitter Current Gain
Optional
VREF
VDD
(or VREF)
Optional
VDD
MCP48FEBX2
FIGURE 8-7:
Source.
Digitally-Controlled Current
VOUT0
(DAC0)
R1
SPI
4-wire
VCC+
VOUT
Optional
VREF
VDD
0.1 µF
R2
VCC–
MCP48FEBX2
VOUT1
(DAC1)
SPI
4-wire
FIGURE 8-6:
Simple Double-Precision
DAC using MCP48FEBX2.
EQUATION 8-8:
VOUT =
VOUT CALCULATION
VOUT0 • R2 + VOUT1 • R1
R1 + R2
Where:
VOUT0 = (VREF • G • DAC0 Register Value)/4096
VOUT1 = (VREF • G • DAC1 Register Value)/4096
Gx = Selected Op Amp Gain
2015 Microchip Technology Inc.
DS20005429B-page 73
MCP48FEBXX
8.7
Serial Interface Communication
Times
Table 8-1 shows time/frequency of the supported
operations of the SPI serial interface for the different
serial interface operational frequencies. This, along
with the VOUT output performance (such as slew rate),
would be used to determine your application’s volatile
DAC register update rate.
TABLE 8-1:
SERIAL INTERFACE TIMES / FREQUENCIES
Command
Code
Operation
Write Command
Read Command
Mode (1)
C
1
C
0
0
0 No(4) Single
0
(5)
HV
0
No(4)
Continuous
No(4)
Single
# of Bit
Clocks
Data Update Rate
(8-bit/10-bit/12-bit)
(Data Words/Second)
Comments
(2)
1 MHz
10 MHz
20 MHz (3)
24
41,666
416,666
833,333
24n
41,666
416,666
833,333
1
1
1
1 No(4) Continuous
Enable Configuration
Bit Command
1
0
Yes Single
8
125,000 1,250,000
2,500,000
1
0
Yes Continuous
8n
125,000 1,250,000
2,500,000 For 10 data words
Disable Configuration
Bit Command
0
1
Yes Single
8
125,000 1,250,000
2,500,000
0
1
Yes Continuous
8n
125,000 1,250,000
2,500,000 For 10 data words
Note 1:
2:
3:
4:
5:
24
41,666
416,666
N.A.
24n
41,666
416,666
N.A.
For 10 data words
For 10 data words
Nonvolatile registers can only use the “Single” mode.
“n” indicates the number of times the command operation is to be repeated.
Write command only.
If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition
(CMDERR) will NOT be generated
This command is useful to determine when an EEPROM programming cycle has completed.
DS20005429B-page 74
2015 Microchip Technology Inc.
MCP48FEBXX
8.8
8.8.2
Design Considerations
In the design of a system with the MCP48FEBXX
devices, the following considerations should be taken
into account:
• Power Supply Considerations
• Layout Considerations
8.8.1
LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
• Noise
• PCB Area Requirements
8.8.2.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-8 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as close
(within 4 mm) to the device power pin (VDD) as possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP48FEBXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors should be terminated to the
analog ground plane.
Note:
Breadboards and wire-wrapped boards
are not recommended.
8.8.2.2
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the typical package
dimensions and area for the different package options.
0.1 µF
VDD
PACKAGE FOOTPRINT(1)
TABLE 8-2:
Package
VOUT
VSS
FIGURE 8-8:
Connections.
SCK
CS
Pins
SDI
SDO
PIC® Microcontroller
VREF
MCP48FEBXX
0.1 µF
Type
Package Footprint
Code
Dimensions
(mm)
Area (mm2)
Length Width
10 MSOP
Note 1:
UN
3.00
4.90
14.70
Does not include recommended land
pattern dimensions. Dimensions are
typical values.
VSS
Typical Microcontroller
2015 Microchip Technology Inc.
DS20005429B-page 75
MCP48FEBXX
NOTES:
DS20005429B-page 76
2015 Microchip Technology Inc.
MCP48FEBXX
9.0
DEVELOPMENT SUPPORT
Development support can be classified into two groups.
These are:
• Development Tools
• Technical Documentation
9.1
Development Tools
The MCP48FEBXX devices currently do not have any
development tools or bond-out boards. Please visit the
Device's web product page (Development Tools tab) for
the development tools availability after the release of
this data sheet.
9.2
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-1 shows
some of these documents.
TABLE 9-1:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1326
Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications
DS01326
—
Signal Chain Design Guide
DS21825
—
Analog Solutions for Automotive Applications Design Guide
DS01005
2015 Microchip Technology Inc.
DS20005429B-page 77
MCP48FEBXX
NOTES:
DS20005429B-page 78
2015 Microchip Technology Inc.
MCP48FEBXX
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
10-Lead MSOP
Example
48FE01
528256
Device Number
Device Number
Code
MCP48FEB01-E/UN
48FE01
MCP48FEB02-E/UN
48FE02
MCP48FEB01T-E/UN
48FE01
MCP48FEB02T-E/UN
48FE02
MCP48FEB11-E/UN
48FE11
MCP48FEB12-E/UN
48FE12
MCP48FEB11T-E/UN
48FE11
MCP48FEB12T-E/UN
48FE12
MCP48FEB21-E/UN
48FE21
MCP48FEB22-E/UN
48FE22
MCP48FEB21T-E/UN
48FE21
MCP48FEB22T-E/UN
48FE22
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015 Microchip Technology Inc.
DS20005429B-page 79
MCP48FEBXX
UN
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005429B-page 80
2015 Microchip Technology Inc.
MCP48FEBXX
UN
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015 Microchip Technology Inc.
DS20005429B-page 81
MCP48FEBXX
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005429B-page 82
2015 Microchip Technology Inc.
MCP48FEBXX
APPENDIX A:
REVISION HISTORY
Revision B (September 2015)
• Fixed a header/part number typographical error.
Revision A (September 2015)
• Original release of this document.
2015 Microchip Technology Inc.
DS20005429B-page 83
MCP48FEBXX
B.1
TERMINOLOGY
Resolution
Resolution is the number of DAC output states that
divide the full-scale range. For the 12-bit DAC, the
resolution is 212, meaning the DAC code ranges from
0 to 4095.
Note:
B.2
When there are 2N resistors in the resistor
ladder and 2N tap points, the full-scale
DAC register code is the resistor element
(1 LSb) from the source reference voltage
(VDD or VREF).
Least Significant Bit (LSb)
This is the voltage difference between two successive
codes. For a given output voltage range, it is divided by
the resolution of the device (Equation B-1). The range
may be VDD (or VREF) to VSS (ideal), the DAC register
codes across the linear range of the output driver
(Measured 1), or full-scale to zero-scale (Measured 2).
EQUATION B-1:
LSb VOLTAGE
CALCULATION
B.3
Monotonic Operation
Monotonic operation means that the device’s output
voltage (VOUT) increases with every 1 code step (LSb)
increment (from VSS to the DAC’s reference voltage
(VDD or VREF)).
VS64
40h
VS63
3Fh
Wiper Code
APPENDIX B:
3Eh
VS3
03h
VS1
02h
01h
VS0
00h
VW (@ tap)
n=?
VW = VSn + VZS(@ Tap 0)
n=0
Voltage (VW ~= VOUT)
FIGURE B-1:
VW (VOUT).
Ideal
V
VREF
VLSb(IDEAL) = DD
or
2N
2N
Measured 1
V
- VOUT(@100)
VLSb(Measured) = OUT(@4000)
(4000 - 100)
Measured 2
V
-V
VLSb = OUT(@FS)N OUT(@ZS)
2 -1
2N = 4096 (MCP48FEB2X)
= 1024 (MCP48FEB1X)
= 256
(MCP48FEB0X)
DS20005429B-page 84
2015 Microchip Technology Inc.
MCP48FEBXX
B.4
Full-Scale Error (EFS)
The Full-Scale Error (see Figure B-3) is the error on
the VOUT pin relative to the expected VOUT voltage
(theoretical) for the maximum device DAC register
code (code FFFh for 12-bit, code 3FFh for 10-bit, and
code FFh for 8-bit) (see Equation B-2). The error is
dependent on the resistive load on the VOUT pin (and
where that load is tied to, such as VSS or VDD). For
loads (to VSS) greater than specified, the full-scale
error will be greater.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION B-2:
EFS =
Total Unadjusted Error (ET)
The Total Unadjusted Error (ET) is the difference
between the ideal and measured VOUT voltage.
Typically, calibration of the output voltage is
implemented to improve system performance.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
Equation B-4 shows the Total Unadjusted Error
calculation.
EQUATION B-4:
FULL-SCALE ERROR
VOUT(@FS) - VIDEAL(@FS)
VLSb(IDEAL)
Where:
EFS is expressed in LSb.
VOUT(@FS) = The VOUT voltage when the DAC
register code is at full-scale.
VIDEAL(@FS) = The ideal output voltage when the
DAC register code is at full-scale.
VLSb(IDEAL) = The theoretical voltage step size.
B.5
B.6
Zero-Scale Error (EZS)
ET =
TOTAL UNADJUSTED
ERROR CALCULATION
( VOUT_Actual(@code) - VOUT_Ideal(@Code) )
VLSb(Ideal)
Where:
ET is expressed in LSb.
VOUT_Actual(@code) = The measured DAC output
voltage at the specified code.
VOUT_Ideal(@code) = The calculated DAC output
voltage at the specified code.
( code * VLSb(Ideal) )
VLSb(Ideal) = VREF/# Steps
12-bit = VREF/4096
10-bit = VREF/1024
8-bit = VREF/256
The Zero-Scale Error (see Figure B-2) is the difference
between the ideal and measured VOUT voltage with the
DAC register code equal to 000h (Equation B-3).
The error is dependent on the resistive load on the
VOUT pin (and where that load is tied to, such as VSS or
VDD). For loads (to VDD) greater than specified, the
zero-scale error will be greater.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION B-3:
EZS =
ZERO-SCALE ERROR
VOUT(@ZS)
VLSb(IDEAL)
Where:
EZS is expressed in LSb.
VOUT(@ZS) = The VOUT voltage when the DAC
register code is at Zero-scale.
VLSb(IDEAL) = The theoretical voltage step size.
2015 Microchip Technology Inc.
DS20005429B-page 85
MCP48FEBXX
B.7
Offset Error (EOS)
The offset error is the delta voltage of the VOUT voltage
from the ideal output voltage at the specified code.
This code is specified where the output amplifier is in
the linear operating range; for the MCP48FEBXX we
specify code 100 (decimal). Offset error does not
include gain error. Figure B-2 illustrates this.
This error is expressed in mV. Offset error can be negative or positive. The offset error can be calibrated by
software in application circuits.
B.9
Gain Error (EG)
Gain error is a calculation based on the ideal slope
using the voltage boundaries for the linear range of the
output driver (ex code 100 and code 4000) (see
Figure B-3). The gain error calculation nullifies the
device’s offset error.
Gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. Gain error is usually expressed as percent of
full-scale range (% of FSR) or in LSb. FSR is the ideal
full-scale voltage of the DAC (see Equation B-5).
Gain Error (EG)
(@ code = 4000)
VREF
Actual
Transfer
Function
VOUT
VOUT
Actual
Transfer
Function
Zero-Scale
Error (EZS)
Ideal Transfer
Function
0
100
Offset
Error (EOS)
FIGURE B-2:
Error.
B.8
Full-Scale
Error (EFS)
Ideal Transfer
Function
4000
DAC Input Code
Offset Error and Zero-Scale
Offset Error Drift (EOSD)
Offset error drift is the variation in offset error due to a
change in ambient temperature. Offset error drift is
typically expressed in ppm/oC or µV/oC.
0
100
Ideal Transfer
Function shifted by
Offset Error
(crosses at start of
defined linear range)
4000
DAC Input Code
4095
FIGURE B-3:
Error Example.
Gain Error and Full-Scale
EQUATION B-5:
EXAMPLE GAIN ERROR
EG =
( VOUT(@4000) - VOS - VOUT_Ideal(@4000) )
VFull-Scale Range
• 100
Where:
EG is expressed in % of full-scale range (FSR).
VOUT(@4000) = The measured DAC output
voltage at the specified code.
VOUT_Ideal(@4000) = The calculated DAC output
voltage at the specified code.
( 4000 * VLSb(Ideal) )
VOS = Measured offset voltage.
VFull Scale Range = Expected full-scale output
value (such as the VREF
voltage).
B.10
Gain-Error Drift (EGD)
Gain-error drift is the variation in gain error due to a
change in ambient temperature. Gain error drift is
typically expressed in ppm/oC (of full-scale range).
DS20005429B-page 86
2015 Microchip Technology Inc.
MCP48FEBXX
B.11
Integral Nonlinearity (INL)
The Integral Nonlinearity (INL) error is the maximum
deviation of an actual transfer function from an ideal
transfer function (straight line) passing through the
defined end points of the DAC transfer function (after
offset and gain errors have been removed).
In the MCP48FEBXX, INL is calculated using the
defined end points, DAC code 100 and code 4000.
INL can be expressed as a percentage of
full-scale range (FSR) or in LSb. INL is also called
Relative Accuracy. Equation B-6 shows how to
calculate the INL error in LSb and Figure B-4 shows an
example of INL accuracy.
Positive INL means higher VOUT voltage than ideal.
Negative INL means lower VOUT voltage than ideal.
EQUATION B-6:
INL ERROR
- VCalc_Ideal )
(V
EINL = OUT
VLSb(Measured)
Where:
INL is expressed in LSb.
VCalc_Ideal = Code * VLSb(Measured) + VOS
VOUT(Code = n) = The measured DAC output
voltage with a given DAC
register code
VLSb(Measured) = For Measured:
(VOUT(4000) - VOUT(100))/3900
VOS = Measured offset voltage.
B.12
Differential Nonlinearity (DNL)
The Differential Nonlinearity (DNL) error (see
Figure B-5) is the measure of step size between codes
in actual transfer function. The ideal step size between
codes is 1 LSb. A DNL error of zero would imply that
every code is exactly 1 LSb wide. If the DNL error is less
than 1 LSb, the DAC guarantees monotonic output and
no missing codes. Equation B-7 shows how to calculate
the DNL error between any two adjacent codes in LSb.
EQUATION B-7:
DNL ERROR
( VOUT(code = n+1) - VOUT(code = n) )
EDNL =
VLSb(Measured)
-1
Where:
DNL is expressed in LSb.
VOUT(Code = n) = The measured DAC output voltage
with a given DAC register code.
VLSb(Measured) = For Measured:
(VOUT(4000) - VOUT(100))/3900
7
DNL = 0.5 LSb
6
5
DNL = 2 LSb
Analog 4
Output
(LSb) 3
2
7
INL = < -1 LSb
6
INL = - 1 LSb
5
Analog 4
Output
(LSb) 3
1
0
000 001 010
011 100 101 110 111
DAC Input Code
Ideal Transfer Function
INL = 0.5 LSb
Actual Transfer Function
2
FIGURE B-5:
DNL Accuracy.
1
0
000 001 010
011 100 101 110 111
DAC Input Code
Ideal Transfer Function
Actual Transfer Function
FIGURE B-4:
INL Accuracy.
2015 Microchip Technology Inc.
DS20005429B-page 87
MCP48FEBXX
B.13
Settling Time
Settling time is the time delay required for the VOUT
voltage to settle into its new output value. This time is
measured from the start of code transition to when the
VOUT voltage is within the specified accuracy.
In the MCP48FEBXX, the settling time is a measure of
the time delay until the VOUT voltage reaches within
0.5 LSb of its final value, when the volatile DAC
Register changes from 1/4 to 3/4 of the full-scale range
(12-bit device: 400h to C00h).
B.14
Major-Code Transition Glitch
Major-Code transition glitch is the impulse energy
injected into the DAC analog output when the code in
the DAC register changes state. It is normally specified
as the area of the glitch in nV-Sec, and is measured
when the digital code is changed by 1 LSb at the major
carry transition.
Example: 011...111 to 100...000
or 100...000 to 011...111
B.15
Digital Feed-through
Digital feed-through is the glitch that appears at the
analog output, caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec, and is measured with a full-scale change on
the digital input pins.
B.17
Power-Supply Sensitivity (PSS)
PSS indicates how the output of the DAC is affected by
changes in the supply voltage. PSS is the ratio of the
change in VOUT to a change in VDD for mid-scale output
of the DAC. The VOUT is measured while the VDD is
varied from 5.5V to 2.7V as a step (VREF voltage held
constant), and expressed in %/%, which is the
% change of the DAC output voltage with respect to the
% change of the VDD voltage.
EQUATION B-8:
PSS CALCULATION
V OUT @5.5V – VOUT @2.7V
----------------------------------------------------------------------------------V OUT @5.5V
PSS = ---------------------------------------------------------------------------------- 5.5V – 2.7V
--------------------------------5.5V
Where:
PSS is expressed in %/%.
VOUT(@5.5V) = The measured DAC output
voltage with VDD = 5.5V.
VOUT(@2.7V) = The measured DAC output
voltage with VDD = 2.7V.
B.18
Power-Supply Rejection Ratio
(PSRR)
The digital feed-through is measured when the DAC is
not being written to the output register.
PSRR indicates how the output of the DAC is affected
by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full-scale
output of the DAC. The VOUT is measured while the
VDD is varied ± 10% (VREF voltage held constant), and
expressed in dB or µV/V.
B.16
B.19
Example: all 0s to all 1s and vice versa.
-3 dB Bandwidth
This is the frequency of the signal at the VREF pin that
causes the voltage at the VOUT pin to fall -3 dB value
from a static value on the VREF pin. The output
decreases due to the RC characteristics of the resistor
ladder and the characteristics of the output buffer.
VOUT Temperature Coefficient
The VOUT Temperature Coefficient quantifies the error
in the resistor ladder’s resistance ratio (DAC Register
code value) and Output Buffer due to temperature drift.
B.20
Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end output voltage (Nominal output
voltage VOUT) due to temperature drift. For a DAC this
error is typically not an issue due to the ratiometric
aspect of the output.
B.21
Noise Spectral Density
Noise spectral density is a measurement of the
device’s internally-generated random noise, and is
characterized as a spectral density (voltage per √Hz).
It is measured by loading the DAC to the
mid-scale value and measuring the noise at the
VOUT pin. It is measured in nV/√Hz.
DS20005429B-page 88
2015 Microchip Technology Inc.
MCP48FEBXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X(1)
PART NO.
Device
X
Tape and Temperature
Reel
Range
/XX
Examples:
a) MCP48FEB01-E/UN:
Package
b) MCP48FEB01T-E/UN:
Device:
MCP48FEB01: Single-Channel 8-Bit NV DAC
with External + Internal References
MCP48FEB02: Dual-Channel 8-Bit NV DAC
with External + Internal References
a) MCP48FEB11-E/UN:
MCP48FEB11: Single-Channel 10-Bit NV DAC
with External + Internal References
MCP48FEB12: Dual-Channel 10-Bit NV DAC
with External + Internal References
b) MCP48FEB11T-E/UN:
MCP48FEB21: Single-Channel 12-Bit NV DAC
with External + Internal References
MCP48FEB22: Dual-Channel 12-Bit NV DAC
with External + Internal References
Tape and
Reel:
T
Blank
Temperature
Range:
E
Package:
UN =
=
=
=
Tape and Reel(1)
Tube
a) MCP48FEB21-E/UN:
b) MCP48FEB21T-E/UN:
-40°C to +125°C (Extended)
a) MCP48FEB22-E/UN:
Plastic Micro Small Outline (MSOP),
10-Lead
b) MCP48FEB22T-E/UN:
Note
2015 Microchip Technology Inc.
1:
8-bit VOUT resolution, Single
Channel,
Tube,
Extended
Temperature., 10-Lead MSOP
Package
8-bit VOUT resolution, Single
Channel, Tape and Reel,
Extended Temperature,
10-Lead MSOP Package
10-bit VOUT resolution, Single
Channel,
Tube,
Extended
Temperature, 10-Lead MSOP
Package
10-bit VOUT resolution, Single
Channel, Tape and Reel,
Extended Temperature,
10-Lead MSOP Package
12-bit VOUT resolution, Single
Channel,
Tube,
Extended
Temperature, 10-Lead MSOP
Package
12-bit VOUT resolution, Single
Channel, Tape and Reel,
Extended Temperature,
10-Lead MSOP Package
12-bit VOUT resolution, Dual
Channel,
Tube,
Extended
Temperature, 10-Lead MSOP
Package
12-bit VOUT resolution, Dual
Channel, Tape and Reel,
Extended Temperature,
10-Lead MSOP Package
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip sales office for package
availability for the Tape and Reel option.
DS20005429B-page 89
MCP48FEBXX
NOTES:
DS20005429B-page 90
2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-828-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005429B-page 91
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS20005429B-page 92
2015 Microchip Technology Inc.