MCP47FVBXX
8- /10- /12-Bit Single/Dual Voltage Output Volatile
Digital-to-Analog Converters with I²C™ Interface
Features
• Operating Voltage Range:
- 2.7V to 5.5V – Full Specifications
- 1.8V to 2.7V – Reduced Device Specifications
• Output Voltage Resolutions:
- 8-bit: MCP47FVB0X (256 Steps)
- 10-bit: MCP47FVB1X (1024 Steps)
- 12-bit: MCP47FVB2X (4096 Steps)
• Rail-to-Rail Output
• Fast Settling Time of 6 µs (typical)
• DAC Voltage Reference Source Options:
- Device VDD
- External VREF pin (buffered or unbuffered)
- Internal Band Gap (1.22V typical)
• Output Gain Options:
- (1x) Unity
- 2x (when not using internal VDD as voltage
source)
• Power-on/Brown-out Reset Protection
• Power-Down Modes:
- Disconnects output buffer (High Impedance)
- Selection of VOUT pull-down resistors
(100 k or 1 k)
• Low Power Consumption:
- Normal operation: <180 µA (Single), 380 µA
(Dual)
- Power-down operation: 650 nA typical
• I2C™ Interface:
- Slave address options: four predefined
addresses
- Standard (100 kbps), Fast (400 kbps), and
High-Speed (up to 3.4 Mbps) modes
- High Voltage Command Support
(MCP47FEBXX compatibility)
• Package Types: 8-lead TSSOP
• Extended Temperature Range: -40°C to +125°C
Package Types
MCP47FVBX1
TSSOP
Single
8 SDA
VREF0 2
7 SCL
VOUT0 3
6 LAT0/HVC
NC 4
5 VSS
MCP47FVBX2
TSSOP
Dual
VDD 1
8 SDA
(1)
7 SCL
VREF
Note 1:
2
VOUT0 3
6 LAT(1)/HVC
VOUT1 4
5 VSS
This pin’s signal can be connected to DAC0
and/or DAC1.
General Description
The MCP47FVBXX are Single- and Dual-channel 8-bit,
10-bit, and 12-bit buffered voltage output Digital-toAnalog Converters (DAC) with volatile memory and an
I2C serial interface.
The VREF pin, the device VDD or the internal band gap
voltage can be selected as the DAC’s reference
voltage. When VDD is selected, VDD is connected
internally to the DAC reference circuit. When the VREF
pin is used, the user can select the output buffer’s gain
to be 1 or 2. When the gain is 2, the VREF pin voltage
should be limited to a maximum of VDD/2.
These devices have a two-wire I2C-compatible serial
interface for Standard (100 kHz), Fast (400 kHz) or
High-Speed (1.7 MHz and 3.4 MHz) modes.
Applications
•
•
•
•
•
•
2015 Microchip Technology Inc.
VDD 1
Set Point or Offset Trimming
Sensor Calibration
Low-Power Portable Instrumentation
PC Peripherals
Data Acquisition Systems
Motor Control
DS20005405A-page 1
MCP47FVBXX
MCP47FVBX1 Device Block Diagram (Single-Channel Output)
SDA
SCL
Memory (32x16)
I2C™ Serial
Interface
Module and
Control Logic
DAC0 (Vol)
VREF (Vol)
Power-down (Vol)
Gain (Vol)
Status (Vol)
VREF1:VREF0
and PD1:PD0
Band Gap
(1.22V)
VDD
VREF0
+
-(1)
PD1:PD0
VSS
VREF1:VREF0
Resistor
Ladder
VDD
LAT0/HVC
Gain
PD1:PD0 and
VREF1:VREF0
VBG
Op
Amp
VOUT0
PD1:PD0
100 k
VSS
Power-up/
Brown-out
Control
1 k
VDD
Note 1: If Internal Band Gap is selected, this buffer has a 2x gain. If the G bit = ‘1’, this is a total gain of 4.
DS20005405A-page 2
2015 Microchip Technology Inc.
MCP47FVBXX
MCP47FVBX2 Device Block Diagram (Dual-Channel Output)
SDA
SCL
Memory (32x16)
DAC0 and 1 (Vol)
VREF (Vol)
Power-down (Vol)
Gain (Vol)
Status (Vol)
I2C™ Serial
Interface
Module and
Control Logic
VREF1:VREF0
and PD1:PD0
VREF
VDD
Gain
PD1:PD0 and
VREF1:VREF0
Band Gap VBG
(1.22V)
Op
Amp
VOUT0
PD1:PD0
+
(1)
-
VSS
VREF1:VREF0
LAT/HVC
Resistor
Ladder
VDD
PD1:PD0
VREF1:VREF0
and PD1:PD0 V
100 k
VSS
Power-up/
Brown-out
Control
1 k
VDD
Gain
DD
+(1)
-
PD1:PD0
VSS
VREF1:VREF0
Resistor
Ladder
VDD
VOUT1
PD1:PD0
100 k
intVR1
Op
Amp
1 k
PD1:PD0 and
VREF1:VREF0
Band Gap
(1.22V)
Note 1: If Internal Band Gap is selected, this buffer has a 2x gain. If the G bit = ‘1’, this is a total gain of 4.
2015 Microchip Technology Inc.
DS20005405A-page 3
MCP47FVBXX
Control
Interface
DAC Output
POR/BOR
Setting (1)
MCP47FVB01
Resolution
(bits)
Device
# of
Channels
Family Device Features
# of
VREF
Inputs
1
8
I2C™
7Fh
1
Yes
1
RAM
1.8V to 5.5V
2
Internal
band
gap
?
# of
LAT
Inputs
Memory
Specified
Operating Range
(VDD) (2)
MCP47FVB11
1
10
I C
1FFh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FVB21
1
12
I2C
7FFh
1
Yes
1
RAM
1.8V to 5.5V
2
MCP47FVB02
2
8
I C
7Fh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FVB12
2
10
I2C
1FFh
1
Yes
1
RAM
1.8V to 5.5V
I2
MCP47FVB22
2
12
7FFh
1
Yes
1
RAM
1.8V to 5.5V
MCP47FEB01
1
8
I2C™
7Fh
1
Yes
1
EEPROM
1.8V to 5.5V
2
C
MCP47FEB11
1
10
I C
1FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FEB21
1
12
I2C
7FFh
1
Yes
1
EEPROM
1.8V to 5.5V
2
MCP47FEB02
2
8
I C
7Fh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FEB12
2
10
I2C
1FFh
1
Yes
1
EEPROM
1.8V to 5.5V
12
I2C
7FFh
1
Yes
1
EEPROM
1.8V to 5.5V
MCP47FEB22
Note 1:
2:
2
The Factory Default value.
Analog performance specified from 2.7V to 5.5V.
DS20005405A-page 4
2015 Microchip Technology Inc.
MCP47FVBXX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Voltage on VDD with respect to VSS ......................................................................................................... -0.6V to +6.5V
Voltage on all pins with respect to VSS ............................................................................................... -0.6V to VDD+0.3V
Input clamp current, IIK (VI < 0, VI > VDD, VI > VPP on HV pins) .......................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA
Maximum current out of VSS pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum current into VDD pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum current sourced by the VOUT pin ............................................................................................................20 mA
Maximum current sunk by the VOUT pin..................................................................................................................20 mA
Maximum current sunk by the VREF pin .................................................................................................................125 µA
Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA
Maximum output current sunk by SDA Output pin .................................................................................................25 mA
Total power dissipation (1) ....................................................................................................................................400 mW
Package power dissipation (TA = +50°C, TJ = +150°C)
TSSOP-8...................................................................................................................................................700 mW
ESD protection on all pins ±4 kV (HBM)
±400V (MM)
±2 kV (CDM)
Latch-Up (per JEDEC JESD78A) @ +125°C ..................................................................................................... ±100 mA
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ...............................................................................................-55°C to +125°C
Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C
Maximum Junction Temperature (TJ) .................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
2015 Microchip Technology Inc.
DS20005405A-page 5
MCP47FVBXX
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Supply Voltage
Sym.
Min.
Typ.
Max.
Units
Conditions
VDD
2.7
—
5.5
V
1.8
—
2.7
V
DAC operation (reduced analog
specifications) and Serial Interface
—
—
1.7
V
RAM retention voltage (VRAM) < VPOR
VDD voltages greater than VPOR/BOR limit
ensure that device is out of reset.
VDD Voltage
(rising) to ensure device
Power-on Reset
VPOR/BOR
VDD Rise Rate to ensure
Power-on Reset
VDDRR
High-Voltage Commands
Voltage Range (HVC pin)
VHV
VSS
—
12.5
V
The HVC pin will be at one of three input
levels (VIL, VIH or VIHH) (1)
High-Voltage
Input Entry Voltage
VIHHEN
9.0
—
—
V
Threshold for Entry into WiperLock™
Technology
High-Voltage
Input Exit Voltage
VIHHEX
—
—
VDD + 0.8V
V
(Note 1)
Power-on Reset to Output-Driven Delay
TPORD
—
25
50
µs
VDD rising, VDD > VPOR
(Note 3)
V/ms
Note 1
This parameter is ensured by design.
Note 3
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
DS20005405A-page 6
2015 Microchip Technology Inc.
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Supply Current
Power-Down
Current
Sym.
IDD
IDDP
Min.
Typ.
Max.
Units
Conditions
—
—
500
µA
Single
—
—
700
µA
Dual
Serial Interface Active
(Not High-Voltage Command),
VRxB:VRxA = ‘01’ (6),
VOUT is unloaded, VDD = 5.5V
volatile DAC register = 000h
I2C™: FSCL = 3.4 MHz
—
—
400
µA
Single
—
—
550
µA
Dual
—
—
180
µA
Single
—
—
380
µA
Dual
—
—
180
µA
Single
—
—
380
µA
Dual
—
145
180
µA
Single
—
260
400
µA
Dual
—
0.65
3.8
µA
PDxB:PDxA = ‘01’ (5),
VOUT not connected
Serial Interface Active (2)
(Not High-Voltage Command),
VRxB:VRxA = ‘10’ (4),
VOUT is unloaded, VREF = VDD = 5.5V
volatile DAC register = 000h
I2C: FSCL = 3.4 MHz
Serial Interface Inactive (2)
(Not High-Voltage Command),
VRxB:VRxA = ‘00’,
SCL = SDA = VSS, VOUT is unloaded,
volatile DAC register = 000h
Serial Interface Inactive (2)
(Not High-Voltage Command),
VRxB:VRxA = ‘11’, VREF = VDD,
SCL = SDA = VSS, VOUT is unloaded,
volatile DAC register = 000h
HVC = 12.5V (High-Voltage
Command), Serial Interface Inactive
VREF = VDD = 5.5V, LAT/HVC = VIHH,
DAC registers = 000h,
VOUT pins are unloaded.
Note 2
This parameter is ensured by characterization.
Note 4
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
Note 5
The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
Note 6
By design, this is worst-case Current mode.
2015 Microchip Technology Inc.
DS20005405A-page 7
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Sym.
Min.
Typ.
Max.
Units
Resistor Ladder
Resistance
Resolution
(# of Resistors
and # of Taps) (see
C.1 “Resolution”)
Nominal VOUT
Match (12)
RL
100
140
180
k
VOUT Tempco (see
C.19 “VOUT
N
|VOUT - VOUTMEAN|
/VOUTMEAN
VOUT/T
256
1024
4096
—
—
—
0.5
—
15
Taps
Taps
Taps
1.0
1.2
—
Conditions
1.8V VDD 5.5V,
VREF 1.0V(7)
8-bit No Missing Codes
10-bit No Missing Codes
12-bit No Missing Codes
%
2.7V VDD 5.5V(2)
%
1.8V(2)
ppm/°C Code = Mid-scale
(7Fh, 1FFh or 7FFh)
Temperature
Coefficient”)
VREF Pin Input
VREF
VSS
—
VDD
V
1.8V VDD 5.5V(1)
Voltage Range
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 7
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP47FVBX2), this is the effective resistance of the each resistor ladder. The
resistance measurement is of the two resistor ladders measured in parallel.
Note 12 Variation of one output voltage to mean output voltage.
DS20005405A-page 8
2015 Microchip Technology Inc.
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Zero-Scale Error
(see C.5
“Zero-Scale
Error (EZS)”)
(Code = 000h)
Sym.
Min.
Typ.
Max.
Units
EZS
—
—
0.75
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
—
—
3
LSb
2015 Microchip Technology Inc.
8-bit
VRxB:VRxA = ‘11’, Gx = ‘0’,
VREF = VDD, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’,
VDD = 5.5V, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘10’, Gx = ‘0’. No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘11’, Gx = ‘0’. No Load
VRxB:VRxA = ‘01’, Gx = ‘0’, No Load
10-bit
VRxB:VRxA = ‘11’, Gx = ‘0’,
VREF = VDD, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’,
VDD = 5.5V, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘10’, Gx = ‘0’. No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘11’, Gx = ‘0’. No Load
VRxB:VRxA = ‘01’, Gx = ‘0’, No Load
12-bit
VRxB:VRxA = ‘11’, Gx = ‘0’,
VREF = VDD, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’,
VDD = 5.5V, No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘10’, Gx = ‘0’. No Load
VDD = 1.8V, VREF = 1.0V
VRxB:VRxA = ‘11’, Gx = ‘0’. No Load
VRxB:VRxA = ‘01’, Gx = ‘0’, No Load
LSb
LSb
LSb
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
—
—
12
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
-15
±1.5
+15
LSb
Offset Error
EOS
(see C.7 “Offset
Error (EOS)”)
Offset Voltage
VOSTC
—
±10
—
Temperature
Coefficient
Note 2 This parameter is ensured by characterization.
Conditions
LSb
LSb
LSb
LSb
LSb
LSb
LSb
mV
VRxB:VRxA = ‘00’, Gx = ‘0’, No Load
µV/°C
DS20005405A-page 9
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Full-Scale Error
(see C.4
“Full-Scale
Error (EFS)”)
EFS
—
—
4.5
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
—
—
18
LSb
Note 2
8-bit
LSb
LSb
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
—
—
70
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
This parameter is ensured by characterization.
LSb
DS20005405A-page 10
Conditions
10-bit
LSb
LSb
LSb
LSb
LSb
12-bit
Code = FFh, VRxB:VRxA = ‘11’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFh, VRxB:VRxA = ‘10’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFh, VRxB:VRxA = ‘01’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFh, VRxB:VRxA = ‘00’,
No Load
Code = 3FFh, VRxB:VRxA = ‘11’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = 3FFh, VRxB:VRxA = ‘10’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = 3FFh, VRxB:VRxA = ‘01’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = 3FFh, VRxB:VRxA = ‘00’,
No Load
Code = FFFh, VRxB:VRxA = ‘11’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFFh, VRxB:VRxA = ‘10’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFFh, VRxB:VRxA = ‘01’,
Gx = ‘0’, VREF = 2.048V, No Load
Code = FFFh, VRxB:VRxA = ‘00’,
No Load
2015 Microchip Technology Inc.
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Gain Error
(see C.9 “Gain Error
(EG)”)(9)
Sym.
Min.
Typ.
Max.
EG
-1.0
±0.1
+1.0
-1.0
±0.1
+1.0
-1.0
±0.1
+1.0
—
-3
—
-2.5
—
+0.5
Gain-Error Drift (see C.10 G/°C
“Gain-Error Drift (EGD)”)
ET
Total Unadjusted Error
(see C.6 “Total
Unadjusted Error (ET)”)(2)
See Section 2.0 “Typical
Performance Curves”
-10.0
—
+2.0
See Section 2.0 “Typical
Performance Curves”
-40.0
—
+8.0
See Section 2.0 “Typical
Performance Curves”
Note 2
Note 9
Units
Conditions
% of
8-bit
FSR
% of
10-bit
FSR
% of
12-bit
FSR
ppm/°C
LSb
8-bit
LSb
LSb
10-bit
LSb
LSb
LSb
12-bit
Code = 250, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’
Code = 1000, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’
Code = 4000, No Load
VRxB:VRxA = ‘00’, Gx = ‘0’
VRxB:VRxA = ‘00’.
No Load.
VDD = 1.8V,
VRxB:VRxA = ‘11’, Gx = ‘0’,
VREF = 1.0V, No Load.
VRxB:VRxA = ‘00’.
No Load.
VDD = 1.8V,
VRxB:VRxA = ‘11’, Gx = ‘0’,
VREF = 1.0V, No Load.
VRxB:VRxA = ‘00’.
No Load.
VDD = 1.8V,
VRxB:VRxA = ‘11’, Gx = ‘0’,
VREF = 1.0V, No Load.
This parameter is ensured by characterization.
This gain error does not include offset error.
2015 Microchip Technology Inc.
DS20005405A-page 11
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Sym.
Min.
Typ.
Max.
Units
Integral
Nonlinearity
(see C.11 “Integral
Nonlinearity
(INL)”)(8, 11)
INL
-0.5
±0.1
+0.5
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
-1.5
±0.4
+1.5
LSb
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
See Section 2.0 “Typical
Performance Curves”(2)
-6
±1.5
+6
LSb
Note 2
Note 8
Note 11
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
Conditions
8-bit
VRxB:VRxA = ‘10’
(codes: 6 to 250),
VDD = VREF = 5.5V.
VRxB:VRxA = ‘00’, ‘01’, ‘11’.
VRxB:VRxA = ‘01’,
VDD = 5.5V, Gx = ‘1’.
VRxB:VRxA = ‘10’, ‘11’,
VREF = 1.0V, Gx = ‘1’.
VDD = 1.8V, VREF = 1.0V
10-bit VRxB:VRxA = ‘10’ (codes: 25 to
1000), VDD = VREF = 5.5V.
VRxB:VRxA = ‘00’, ‘01’, ‘11’.
VRxB:VRxA = ‘01’,
VDD = 5.5V, Gx = ‘1’.
VRxB:VRxA = ‘10’, ‘11’,
VREF = 1.0V, Gx = ‘1’.
VDD = 1.8V, VREF = 1.0V.
12-bit VRxB:VRxA = ‘10’ (codes: 100 to
4000), VDD = VREF = 5.5V.
VRxB:VRxA = ‘00’, ‘01’, ‘11’.
See Section 2.0 “Typical
LSb
Performance Curves”(2)
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘01’,
Performance Curves”(2)
VDD = 5.5V, Gx = ‘1’.
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘10’, ‘11’,
Performance Curves”(2)
VREF = 1.0V, Gx = ‘1’.
See Section 2.0 “Typical
LSb
VDD = 1.8V, VREF = 1.0V.
Performance Curves”(2)
This parameter is ensured by characterization.
INL and DNL are measured at VOUT with VRL = VDD (VRxB:VRxA = ‘00’).
Code Range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.
DS20005405A-page 12
2015 Microchip Technology Inc.
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Differential
Nonlinearity
(see C.12
“Differential
Nonlinearity
(DNL)”)(8, 11)
Sym.
Min.
Typ.
Max.
Units
DNL
-0.25
±0.0125
+0.25
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
-0.5
±0.05
+0.5
LSb
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
See Section 2.0 “Typical
Performance Curves” (2)
-1.0
±0.2
+1.0
Note 2
Note 8
Note 11
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
Conditions
8-bit
VRxB:VRxA = ‘10’ (codes: 6 to 250),
VDD = VREF = 5.5V.
Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’.
Char: VRxB:VRxA = ‘01’,
VDD = 5.5V, Gx = ‘1’.
Char: VRxB:VRxA = ‘10’, ‘11’,
VREF = 1.0V, Gx = ‘1’.
VDD = 1.8V
10-bit VRxB:VRxA = ‘10’ (codes: 25 to
1000),
VDD = VREF = 5.5V.
Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’.
Char: VRxB:VRxA = ‘01’,
VDD = 5.5V, Gx = ‘1’.
Char: VRxB:VRxA = ‘10’, ‘11’,
VREF = 1.0V, Gx = ‘1’.
VDD = 1.8V
12-bit VRxB:VRxA = ‘10’ (codes: 100 to
4000), VDD = VREF = 5.5V.
Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’.
See Section 2.0 “Typical
LSb
Performance Curves” (2)
See Section 2.0 “Typical
LSb
Char: VRxB:VRxA = ‘01’,
Performance Curves” (2)
VDD = 5.5V, Gx = ‘1’.
See Section 2.0 “Typical
LSb
Char: VRxB:VRxA = ‘10’, ‘11’,
Performance Curves” (2)
VREF = 1.0V, Gx = ‘1’.
See Section 2.0 “Typical
LSb
VDD = 1.8V
Performance Curves” (2)
This parameter is ensured by characterization.
INL and DNL are measured at VOUT with VRL = VDD (VRxB:VRxA = ‘00’).
Code Range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.
2015 Microchip Technology Inc.
DS20005405A-page 13
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Sym.
Min.
Typ.
Max.
Units
-3 dB Bandwidth
(see C.16 “-3 dB
Bandwidth”)
BW
—
86.5
—
kHz
—
67.7
—
kHz
VOUT(MIN)
—
0.01
—
VOUT(MAX)
—
—
PM
—
VDD –
0.04
66
—
SR
ISC
—
3
0.44
9
—
14
VBG
VBGTC
1.18
—
1.22
15
1.26
—
V
ppm/°C
2.0
2.2
—
—
5.5
5.5
V
V
VREF pin voltage stable
VOUT output linear
VSS
VSS
—
—
—
—
1
-64
VDD – 0.04
VDD
—
—
V
V
pF
dB
VRxB:VRxA = ‘11’ (Buffered mode)
VRxB:VRxA = ‘10’ (Unbuffered mode)
VRxB:VRxA = ‘10’ (Unbuffered mode)
VREF = 2.048V ± 0.1V,
VRxB:VRxA = ‘10’, Gx = ‘0’,
Frequency = 1 kHz
Output Amplifier
Minimum Output
Voltage
Maximum Output
Voltage
Phase Margin
Slew Rate (10)
Short-Circuit Current
Internal Band Gap
Band Gap Voltage
Band Gap Voltage
Temperature
Coefficient
Operating Range
(VDD)
External Reference (VREF)
Input Range (1)
VREF
Input Capacitance
Total Harmonic
Distortion (1)
CREF
THD
Conditions
VREF = 2.048V ± 0.1V,
VRxB:VRxA = ‘10’, Gx = ‘0’
VREF = 2.048V ± 0.1V,
VRxB:VRxA = ‘10’, Gx = ‘1’
1.8V VDD 5.5V,
Output Amplifier’s minimum drive
V
1.8V VDD 5.5V,
Output Amplifier’s maximum drive
Degree CL = 400 pF, RL =
(°)
V/µs
RL = 5 k
mA
DAC code = Full Scale
V
Dynamic Performance
Major Code
—
45
—
nV-s
1 LSb change around major carry
Transition Glitch (see
(7FFh to 800h)
C.14 “Major-Code
Transition Glitch”)
Digital Feedthrough
—
<10
—
nV-s
(see C.15 “Digital
Feed-through”)
Note 1
This parameter is ensured by design.
Note 10 Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit
device).
DS20005405A-page 14
2015 Microchip Technology Inc.
MCP47FVBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V,
Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
DC Characteristics
Parameters
Sym.
Digital Inputs/Outputs (LAT0/HVC)
Schmitt Trigger HighVIH
Input Threshold
Schmitt Trigger Low-Input
VIL
Threshold
Hysteresis of Schmitt
VHYS
Trigger Inputs
Input Leakage Current
IIL
Pin Capacitance
CIN, COUT
Digital Interface (SDA, SCL)
Output Low Voltage
VOL
Min.
Typ.
Max.
Units
Conditions
0.45 VDD
—
—
V
0.5 VDD
—
—
—
—
0.2 VDD
V
V
—
0.1 VDD
—
V
-1
—
—
10
1
—
µA
pF
VIN = VDD and VIN = VSS
fC = 3.4 MHz
—
—
—
0.4
0.2 VDD
—
V
V
V
VDD 2.0V, IOL = 3 mA
VDD < 2.0V, IOL = 1 mA
1.8V VDD 5.5V
2.7V VDD 5.5V (Allows 2.7V
Digital VDD with 5V Analog VDD)
1.8V VDD 2.7V
Input High Voltage
(SDA and SCL Pins)
Input Low Voltage
(SDA and SCL Pins)
Input Leakage
VIH
—
—
0.7 VDD
VIL
—
—
0.3 VDD
V
1.8V VDD 5.5V
ILI
-1
—
1
µA
Pin Capacitance
RAM Value
Value Range
CPIN
—
10
—
pF
SCL = SDA = VSS or
SCL = SDA = VDD
fC = 3.4 MHz
N
0h
0h
0h
DAC Register POR/BOR
Value
PDCON Initial
Factory Setting
Power Requirements
Power Supply Sensitivity
(C.17 “Power-Supply
Sensitivity (PSS)”)
Note 1
Note 2
N
—
0.002
—
0.002
—
0.002
This parameter is ensured by design.
This parameter is ensured by characterization.
2015 Microchip Technology Inc.
PSS
—
FFh
—
3FFh
—
FFFh
See Table 4-2
See Table 4-2
See Table 4-2
See Table 4-2
0.005
0.005
0.005
hex
hex
hex
hex
hex
hex
hex
8-bit
10-bit
12-bit
8-bit
10-bit
12-bit
%/%
%/%
%/%
8-bit Code = 7Fh
10-bit Code = 1FFh
12-bit Code = 7FFh
DS20005405A-page 15
MCP47FVBXX
DC Notes:
1.
2.
3.
4.
5.
6.
7.
This parameter is ensured by design.
This parameter is ensured by characterization.
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
By design, this is worst-case Current mode.
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For dualchannel devices (MCP47FVBX2), this is the effective resistance of the each resistor ladder. The resistance
measurement is of the two resistor ladders measured in parallel.
8. INL and DNL are measured at VOUT with VRL = VDD (VRxB:VRxA = ‘00’).
9. This gain error does not include offset error.
10. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device).
11. Code Range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.
12. Variation of one output voltage to mean output voltage.
DS20005405A-page 16
2015 Microchip Technology Inc.
MCP47FVBXX
1.1
Timing Waveforms and Requirements
± 1 LSb
New Value
VOUT Old Value
FIGURE 1-1:
TABLE 1-1:
VOUT Settling Time Waveforms.
WIPER SETTLING TIMING
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +1.8V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
VOUT Settling Time
(±1LSb error band,
CL = 100 pF )
(see C.13 “Settling
Time”)
tS
—
6
—
µs
8-bit
Code = 3Fh BFh; BFh 3Fh(1)
—
6
—
µs
10-bit
Code = 0FFh 2FFh; 2FFh 0FFh(1)
—
6
—
µs
12-bit
Code = 3FFh BFFh; BFFh 3FFh(1)
Note 1
Conditions
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit
device).
2015 Microchip Technology Inc.
DS20005405A-page 17
MCP47FVBXX
I2C Mode Timing Waveforms and Requirements
1.2
VPOR (VBOR)
VDD
tPORD
SCL
tBORD
VIH
VIH
SDA
VOUT at High Z
VOUT
I2C™ Interface is operational
FIGURE 1-2:
Power-on and Brown-out Reset Waveforms.
Stop
ACK
Start
ACK
SDA
SCL
tPDE
tPDD
VOUT
I2C™ Power-Down Command Timing.
FIGURE 1-3:
TABLE 1-2:
RESET TIMING
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (Extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +1.8V to 5.5V, VSS = 0V, RL = 5 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Power-on Reset
Delay
tPORD
—
60
—
µs
Monitor ACK bit response to ensure device responds to
command.
Brown-out Reset
Delay
tBORD
—
45
—
µs
VDD transitions from VDD(MIN) > VPOR
VOUT driven to VOUT disabled
Power-Down Output
Disable Time Delay
TPDD
—
10.5
—
µs
PDxB:PDxA = ‘11’, ‘10’, or ‘01’ -> “00” started from falling edge of the SCL at the end of the 8th clock cycle.
Volatile DAC register = FFh, VOUT = 10 mV. VOUT not
connected.
Power-Down Output
Enable Time Delay
TPDE
—
1
—
µs
PDxB:PDxA = “00” ‘11’, ‘10’, or ‘01’ started from
falling edge of the SCL at the end of the 8th clock cycle.
VOUT = VOUT - 10 mV. VOUT not connected.
DS20005405A-page 18
Max. Units
Conditions
2015 Microchip Technology Inc.
MCP47FVBXX
SCL
91
90
93
92
SDA
Start
Condition
96
94
95
ACK/ACK
Pulse
Stop
Condition
96
LAT
I2C™ Bus Start/Stop Bits Timing Waveforms.
FIGURE 1-4:
VIH
SCL
93
91
90
92
111
SDA
VIL
Start
Condition
FIGURE 1-5:
Stop
Condition
I2C™ Bus Start/Stop Bits Timing Waveforms.
2015 Microchip Technology Inc.
DS20005405A-page 19
MCP47FVBXX
I2C BUS START/STOP BITS AND LAT REQUIREMENTS
TABLE 1-3:
I2C™ AC Characteristics
Param.
Symbol
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C TA +125C (Extended)
Operating Voltage range is described in DC Characteristics
Characteristic
90
91
92
93
Cb
TSU:STA
THD:STA
TSU:STO
THD:STO
Max.
Units
0
100
kHz
Fast Mode
0
400
kHz
Cb = 400 pF, 2.7V - 5.5V
High-Speed 1.7
0
1.7
MHz
Cb = 400 pF, 4.5V - 5.5V
Cb = 100 pF, 4.5V - 5.5V
Standard Mode
FSCL
D102
Min.
Bus Capacitive
Loading
Start Condition
Setup Time
(Only relevant for
repeated Start
condition)
Start Condition
Hold time
(After this period the
first clock pulse is
generated)
Stop Condition
Setup Time
Stop Condition
Hold Time
High-Speed 3.4
0
3.4
MHz
100 kHz mode
—
400
pF
400 kHz mode
—
400
pF
1.7 MHz mode
—
400
pF
3.4 MHz mode
—
100
pF
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1.7 MHz mode
160
—
ns
3.4 MHz mode
160
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1.7 MHz mode
160
—
ns
3.4 MHz mode
160
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1.7 MHz mode
160
—
ns
3.4 MHz mode
160
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1.7 MHz mode
160
—
ns
3.4 MHz mode
Conditions
Cb = 400 pF, 1.8V - 5.5V(2)
Note 2
Note 2
Note 2
Note 2
160
—
ns
94
TLATSU
LAT ↑ to SCL↑ (write data ACK bit)
Setup Time
10
—
ns
Write Data delayed(3)
95
TLATHD
SCL ↑ to LAT↑ (write data ACK bit)
Hold Time
250
—
ns
Write Data delayed(3)
96
TLAT
LAT High or Low Time
50
—
ns
97
THVCSU
HVC High to SCL High
(of Start condition) – Setup Time
25
—
µs
High-Voltage Commands
98
THVCHD
SCL Low (of Stop condition) to
HVC Low – Hold Time
25
—
µs
High-Voltage Commands
Note 2
Not Tested. This parameter ensured by characterization.
Note 3
The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising
edge (Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not.
DS20005405A-page 20
2015 Microchip Technology Inc.
MCP47FVBXX
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
I2C™ Bus Timing Waveforms.
FIGURE 1-6:
TABLE 1-4:
I2C BUS REQUIREMENTS (SLAVE MODE)
I2C™ AC Characteristics
Param.
No.
Sym.
100
THIGH
101
102A(2)
102B(2)
Note 2
TLOW
TRSCL
TRSDA
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C TA +125C (Extended)
Operating Voltage range is described in DC Characteristics
Characteristic
Clock high time
Clock low time
SCL rise time
SDA rise time
Min.
Max.
Units
Conditions
100 kHz mode
4000
—
ns
1.8V-5.5V(2)
400 kHz mode
600
—
ns
2.7V-5.5V
1.7 MHz mode
120
—
ns
4.5V-5.5V
3.4 MHz mode
60
—
ns
4.5V-5.5V
100 kHz mode
4700
—
ns
1.8V-5.5V(2)
400 kHz mode
1300
—
ns
2.7V-5.5V
1.7 MHz mode
320
—
ns
4.5V-5.5V
3.4 MHz mode
160
—
ns
4.5V-5.5V
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
40
ns
3.4 MHz mode
10
80
ns
After a Repeated Start
condition or an
Acknowledge bit
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
After a Repeated Start
condition or an
Acknowledge bit
Not Tested. This parameter ensured by characterization.
2015 Microchip Technology Inc.
DS20005405A-page 21
MCP47FVBXX
TABLE 1-5:
I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C™ AC Characteristics
Param.
No.
Sym.
103A(2)
TFSCL
103B
(2)
106
107
109
TFSDA
THD:DAT
TSU:DAT
TAA
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C TA +125C (Extended)
Operating Voltage range is described in DC Characteristics
Characteristic
SCL fall time
SDA fall time
Data input hold
time
Data input
setup time
Output valid
from clock
111
TBUF
TSP
Bus free time
Input filter spike
suppression
(SDA and SCL)
Max.
Units
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
80
ns
3.4 MHz mode
10
40
ns
100 kHz mode
—
300
ns
Conditions
Cb is specified to be from
10 to 400 pF
(100 pF maximum for
3.4 MHz mode)(4)
Cb is specified to be from
10 to 400 pF
(100 pF maximum for
3.4 MHz mode)(4)
400 kHz mode
20 + 0.1Cb
300
ns
1.7 MHz mode
20
160
ns
3.4 MHz mode
10
80
ns
100 kHz mode
0
—
ns
1.8V-5.5V(2, 5)
400 kHz mode
0
—
ns
2.7V-5.5V(5)
1.7 MHz mode
0
—
ns
4.5V-5.5V(5)
3.4 MHz mode
0
—
ns
4.5V-5.5V(5)
100 kHz mode
250
—
ns
Note 2, Note 6
Note 6
400 kHz mode
100
—
ns
1.7 MHz mode
10
—
ns
3.4 MHz mode
10
—
ns
100 kHz mode
—
3450
ns
400 kHz mode
—
900
ns
Note 7
1.7 MHz mode
—
150
ns
Cb = 100 pF(7, 8)
—
310
ns
Cb = 400 pF(2, 7)
—
150
ns
Cb = 100 pF(7)
Time the bus must be free
before a new transmission can start(2)
3.4 MHz mode
110
Min.
Note 2, Note 7
100 kHz mode
4700
—
ns
400 kHz mode
1300
—
ns
1.7 MHz mode
N.A.
—
ns
3.4 MHz mode
N.A.
—
ns
100 kHz mode
—
50
ns
400 kHz mode
—
50
ns
1.7 MHz mode
—
10
ns
Spike suppression
3.4 MHz mode
—
10
ns
Spike suppression
NXP Spec states N.A.(2)
Note 2
Not Tested. This parameter ensured by characterization.
Note 4
Use Cb in pF for the calculations.
Note 5
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
Note 6
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it
must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the
standard-mode I2C bus specification) before the SCL line is released.
Note 7
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
Note 8
Ensured by the TAA 3.4 MHz specification test.
DS20005405A-page 22
2015 Microchip Technology Inc.
MCP47FVBXX
Timing Table Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device).
Not Tested. This parameter ensured by characterization.
The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge
(Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not.
Use Cb in pF for the calculations.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not
unintentionally create a Start or Stop condition.
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output
the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL
line is released.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
Ensured by the TAA 3.4 MHz specification test.
2015 Microchip Technology Inc.
DS20005405A-page 23
MCP47FVBXX
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Symbol
Min.
Typical
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
139
—
°C/W
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Thermal Resistance, 8L-TSSOP
Note 1:
The MCP47FVBXX devices operate over this extended temperature range, but with reduced performance.
Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C.
DS20005405A-page 24
2015 Microchip Technology Inc.
MCP47FVBXX
2.0
Note:
TYPICAL PERFORMANCE CURVES
The device Performance Curves are available in a separate document. This is done to keep the file size of
this PDF document less than the 10 MB file attachment limit of many mail servers.
The MCP47FXBXX Performance Curves document is literature number DS20005378, and can be found
on the Microchip website. Look at the MCP47FVBXX product page under “Documentation and Software”,
in the Data Sheets category.
2015 Microchip Technology Inc.
DS20005405A-page 25
MCP47FVBXX
NOTES:
DS20005405A-page 26
2015 Microchip Technology Inc.
MCP47FVBXX
3.0
PIN DESCRIPTIONS
Overviews of the pin functions are provided in
Sections 3.1 “Positive Power Supply Input (VDD)”
through Section 3.8 “I2C - Serial Data Pin (SDA)”. The
descriptions of the pins for the single-DAC output
device are listed in Table 3-1, and descriptions for the
dual-DAC output device are listed in Table 3-2.
TABLE 3-1:
MCP47FVBX1 (SINGLE-DAC) PINOUT DESCRIPTION
Pin
Symbol
I/O
Buffer
Type
Standard Function
TSSOP-8L
1
VDD
—
P
Supply Voltage pin
2
VREF0
A
Analog
Voltage Reference Input pin
3
VOUT0
A
Analog
Buffered analog voltage output pin
4
NC
—
—
Not Internally Connected
5
VSS
—
P
Ground reference pin for all circuitries on the device
6
LAT0/HVC
I
HV ST
7
SCL
I
ST
I2C™ Serial Clock pin
8
SDA
I/O
ST
I2C Serial Data pin
Legend:
TABLE 3-2:
A = Analog
I = Input
DAC register Latch/High-Voltage Command pin. Latch pin allows the
value in the Serial Shift register to transfer to the volatile DAC register.
High-Voltage command allows User Configuration bits to be written.
ST = Schmitt Trigger
O = Output
I/O = Input/Output
P = Power
MCP47FVBX2 (DUAL-DAC) PINOUT DESCRIPTION
Pin
Symbol
I/O
Buffer
Type
Standard Function
TSSOP-8
1
VDD
—
P
Supply Voltage pin
2
VREF
A
Analog
Voltage Reference Input pin (for DAC0 or DAC0 and DAC1)
3
VOUT0
A
Analog
Buffered analog voltage output 0 pin (DAC0 output)
4
VOUT1
A
Analog
Buffered analog voltage output 1 pin (DAC1 output)
5
VSS
—
P
Ground reference pin for all circuitries on the device
6
LAT/HVC
I
HV ST
7
SCL
I
ST
I2C™ Serial Clock pin
8
SDA
I/O
ST
I2C Serial Data pin
Legend:
A = Analog
I = Input
2015 Microchip Technology Inc.
DAC register Latch/High-Voltage Command pin. Latch pin allows the
value in the Serial Shift register to transfer to the volatile DAC register(s)
(for DAC0 or DAC0 and DAC1). High-Voltage command allows User Configuration bits to be written.
ST = Schmitt Trigger
O = Output
I/O = Input/Output
P = Power
DS20005405A-page 27
MCP47FVBXX
3.1
Positive Power Supply Input (VDD)
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS.
The power supply at the VDD pin should be as clean as
possible for a good DAC performance. It is
recommended to use an appropriate bypass capacitor
of about 0.1 µF (ceramic) to ground. An additional
10 µF capacitor (tantalum) in parallel is also
recommended to further attenuate noise present in
application boards.
3.2
Voltage Reference Pin (VREF)
The VREF pin is either an input or an output. When the
DAC’s voltage reference is configured as the VREF pin,
the pin is an input. When the DAC’s voltage reference is
configured as the internal band gap, the pin is an output.
When the DAC’s voltage reference is configured as the
VREF pin, there are two options for this voltage input:
VREF pin voltage buffered or unbuffered. The buffered
option is offered in cases where the external reference
voltage does not have sufficient current capability to not
drop it’s voltage when connected to the internal resistor
ladder circuit.
3.5
Ground (VSS)
The VSS pin is the device ground reference.
The user must connect the VSS pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application PCB (printed
circuit board), it is highly recommended that the VSS pin
be tied to the analog ground path or isolated within an
analog ground plane of the circuit board.
3.6
Latch Pin (LAT)
The LAT pin is used to force the transfer of the DAC
register’s shift register to the DAC output register. This
allows DAC outputs to be updated at the same time.
The update of the VRxB:VRxA, PDxB:PDxA, Gx bits
are also controlled by the LAT pin state.
This pin supports the high voltage (VIHH) supported by
the HVC pin of the nonvolatile family device’s
(MCP47FEBXX).
3.7
I2C - Serial Clock Pin (SCL)
See Section 5.2 “Voltage Reference Selection” and
Register 4-2 for more details on the Configuration bits.
The SCL pin is the serial clock pin of the I2C interface.
The MCP47FVBXX’s I2C interface only acts as a slave
and the SCL pin accepts only external serial clocks.
The input data from the Master device is shifted into the
SDA pin on the rising edges of the SCL clock and
output from the device occurs at the falling edges of the
SCL clock. The SCL pin is an open-drain N-channel
driver. Therefore, it needs an external pull-up resistor
from the VDD line to the SCL pin. Refer to Section 6.0
“I2C Serial Interface Module” for more details of I2C Serial
Interface communication.
3.3
3.8
When the DAC’s voltage reference is configured as the
device VDD, the VREF pin is disconnected from the
internal circuit.
When the DAC’s voltage reference is configured as the
internal band gap, the VREF pin’s drive capability is
minimal, so the output signal should be buffered.
Analog Output Voltage Pin (VOUT)
VOUT is the DAC analog voltage output pin. The DAC
output has an output amplifier. The DAC output range is
dependent on the selection of the voltage reference
source (and potential Output Gain selection). These are:
• Device VDD - The full-scale range of the DAC
output is from VSS to approximately VDD.
• VREF pin - The full-scale range of the DAC output
is from VSS to G VRL, where G is the gain
selection option (1x or 2x).
• Internal Band Gap - The full-scale range of the
DAC output is from VSS to G (2 VBG), where G
is the gain selection option (1x or 2x).
I2C - Serial Data Pin (SDA)
The SDA pin is the serial data pin of the I2C interface.
The SDA pin is used to write or read the DAC registers
and Configuration bits. The SDA pin is an open-drain
N-channel driver. Therefore, it needs an external
pull-up resistor from the VDD line to the SDA pin. Except
for Start and Stop conditions, the data on the SDA pin
must be stable during the high period of the clock. The
high or low state of the SDA pin can only change when
the clock signal on the SCL pin is low. Refer to
Section 6.0 “I2C Serial Interface Module” for more details
of I2C Serial Interface communication.
In Normal mode, the DC impedance of the output pin is
about 1. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1 k, 100 k, or open. The Power-Down selection bits
settings are shown Register 4-3 (Table 5-5).
3.4
No Connect (NC)
The NC pin is not connected to the device.
DS20005405A-page 28
2015 Microchip Technology Inc.
MCP47FVBXX
4.0
GENERAL DESCRIPTION
The MCP47FVBX1 (MCP47FVB01, MCP47FVB11,
and MCP47FVB21) devices are single-channel voltage
output devices. MCP47FVBX2 (MCP47FVB02,
MCP47FVB12, and MCP47FVB22) devices are dualchannel voltage output devices.
These devices are offered with 8-bit (MCP47FVB0X),
10-bit (MCP47FVB1X) and 12-bit (MCP47FVB2X)
resolution and include an I2C serial interface and a
write latch (LAT) pin to control the update of the written
DAC value to the DAC output pin.
The devices use a resistor ladder architecture. The
resistor ladder DAC is driven from a softwareselectable voltage reference source. The source can
be either the device’s internal VDD, an external VREF
pin voltage (buffered or unbuffered) or an internal band
gap voltage source.
The DAC output is buffered with a low power and
precision output amplifier (op amp). This output
amplifier provides a rail-to-rail output with low offset
voltage and low noise. The gain (1x or 2x) of the
output buffer is software configurable.
4.1
Power-on Reset/Brown-out Reset
(POR/BOR)
The internal Power-on Reset (POR)/Brown-out Reset
(BOR) circuit monitors the power supply voltage (VDD)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR).
The maximum VPOR/VBOR voltage is less than 1.8V.
POR occurs as the voltage is rising (typically from 0V),
while BOR occurs as the voltage is falling (typically
from VDD(MIN) or higher).
The POR and BOR trip points are at the same voltage,
and the condition is determined by whether the VDD
voltage is rising or falling (see Figure 4-1). What occurs is
different depending on if the reset is a POR or BOR reset.
the
electrical
When
VPOR/VBOR < VDD < 1.8V,
performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its volatile memory if the proper
serial command is executed.
The devices operates from a single supply voltage.
This voltage is specified from 2.7V to 5.5V for full
specified operation, and from 1.8V to 5.5V for digital
operation. The device operates between 1.8V and
2.7V, but some device parameters are not specified.
The main functional blocks are:
•
•
•
•
•
•
Power-on Reset/Brown-out Reset (POR/BOR)
Device Memory
Resistor Ladder
Output Buffer/VOUT Operation
Internal Band Gap (Voltage Reference)
I2C Serial Interface Module
2015 Microchip Technology Inc.
DS20005405A-page 29
MCP47FVBXX
4.1.1
POWER-ON RESET
4.1.2
The Power-on Reset is the case where the device VDD
is having power applied to it from the VSS voltage level.
As the device powers-up, the VOUT pin will float to an
unknown value. When the device’s VDD is above the
transistor threshold voltage of the device, the output
will start being pulled low. After the VDD is above the
POR/BOR trip point (VBOR/VPOR), the resistor
network’s wiper will be loaded with the POR value
(mid-scale). The volatile memory determines the
analog output (VOUT) pin voltage. After the device is
powered-up, the user can update the device memory.
When the rising VDD voltage crosses the VPOR trip
point, the following occurs:
• The default DAC POR value latched into volatile
DAC register
• The default DAC POR Configuration bit values
latched into volatile Configuration bits
• POR Status bit is set (‘1’)
• The Reset Delay Timer (tPORD) starts; when the
reset delay timer (tPORD) times out, the I2C serial
interface is operational. During this delay time, the
I2C interface will not accept commands.
• The Device Memory Address pointer is forced to
00h.
BROWN-OUT RESET
The Brown-out Reset occurs when a device had
power applied to it, and that power (voltage) drops
below the specified range.
When the falling VDD voltage crosses the VPOR trip
point (BOR event), the following occurs:
• Serial Interface is disabled
• Device is forced into a power-down state
(PDxB:PDxA = ‘11’). Analog circuitry is turned off.
• Volatile DAC register is forced to 000h
• Volatile configuration bits VRxB:VRxA and Gx are
forced to ‘0’
If the VDD voltage decreases below the VRAM voltage,
all volatile memory may become corrupted.
As the voltage recovers above the VPOR/VBOR voltage
see Section 4.1.1 “Power-on Reset”.
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
The analog output (VOUT) state will be determined by
the state of the volatile Configuration bits and the DAC
register. This is called a Power-on Reset (event).
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
Volatile memory
POR starts Reset Delay Timer.
retains data value When timer times out, I2C™ interface
can operate (if VDD VDD(MIN))
Volatile memory
becomes corrupted
VDD(MIN)
TPORD (20 µs max.)
VPOR
VBOR
VRAM
Normal Operation
Device in
unknown
state
Device in
POR state
POR reset forced active
FIGURE 4-1:
DS20005405A-page 30
Default Device configuration latched
into volatile configuration bits and
DAC register.
POR status bit is set (‘1’)
Below
minimum
operating
voltage
Device Device in
in power unknown
down
state
state
BOR reset,
volatile DAC register = 000h
volatile VRxB:VRxA = 00
volatile Gx = 0
volatile PDxB:PDxA = 11
Power-on Reset Operation.
2015 Microchip Technology Inc.
MCP47FVBXX
4.2
Device Memory
User memory includes two types of memory:
• Volatile Register Memory (RAM)
• Device Configuration Memory
Each memory address is 16 bits wide. The memory
mapped register space is shown in Table 4-1. (see
Section 4.2.2 “Device Configuration Memory”).
4.2.1
VOLATILE REGISTER MEMORY
(RAM)
There are up to six Volatile Memory locations:
•
•
•
•
•
DAC0 and DAC1 Output Value registers
VREF Select register
Power-Down Configuration register
Gain and Status register
WiperLock Technology Status register
The volatile memory starts functioning when the
device VDD is at (or above) the RAM retention voltage
(VRAM). The volatile memory will be loaded with the
default device values when the VDD rises across the
VPOR/VBOR voltage trip point.
Function
00h
Volatile DAC0 register
01h
02h
Address
MEMORY MAP (x16)
Address
TABLE 4-1:
Function
10h
Reserved
Volatile DAC1 register
11h
Reserved
Reserved
12h
Reserved
03h
Reserved
13h
Reserved
04h
Reserved
14h
Reserved
05h
Reserved
15h
Reserved
06h
Reserved
16h
Reserved
07h
Reserved
17h
Reserved
08h
VREF register
18h
Reserved
09h
Power-Down register
19h
Reserved
0Ah
Gain and Status register
1Ah
Reserved
0Bh
WiperLock Technology Status register
1Bh
Reserved
0Ch
Reserved
1Ch
Reserved
0Dh
Reserved
1Dh
Reserved
0Eh
Reserved
1Eh
Reserved
0Fh
Reserved
1Fh
Reserved
Volatile Memory address range
Note 1:
Nonvolatile Memory address range(1)
Nonvolatile memory address range is shown to reflect memory map compatibility with the MCP47FEBXX family
of devices.
2015 Microchip Technology Inc.
DS20005405A-page 31
MCP47FVBXX
4.2.2
DEVICE CONFIGURATION
MEMORY
High-Voltage Commands (Enable or Disable) to any
unimplemented Configuration bits will result in a
Command Error condition (NACK).
The STATUS register is described in Register 4-4.
4.2.3
UNIMPLEMENTED REGISTER BITS
Read Commands of a valid location will read unimplemented bits as ‘0’.
4.2.4
4.2.4.1
Default Factory POR Memory State
Table 4-2 shows the default factory POR initialization
of the device memory map for the 8-, 10- and 12-bit
devices.
UNIMPLEMENTED (RESERVED)
LOCATIONS
Normal (Voltage) Commands (Read or Write) to any
unimplemented memory address (Reserved) will result
in a Command Error condition (NACK). Read
Commands of a reserved location will read bits as ‘1’.
FACTORY DEFAULT POR / BOR VALUES
1FFh
7FFh
7Fh
1FFh
12-bit
12-bit
7Fh
Function
10-bit
01h Volatile DAC1 register
10-bit
00h Volatile DAC0 register
8-bit
Function
POR/BOR Value
8-bit
Address
POR/BOR Value
Address
TABLE 4-2:
10h Reserved (1)
FFh
3FFh
FFFh
7FFh
11h Reserved
(1)
FFh
3FFh
FFFh
12h Reserved
(1)
FFh
3FFh
FFFh
13h Reserved
(1)
FFh
3FFh
FFFh
(1)
02h Reserved
(1)
03h Reserved
(1)
04h Reserved
(1)
FFh
3FFh
FFFh
14h Reserved
FFh
3FFh
FFFh
05h Reserved (1)
FFh
3FFh
FFFh
15h Reserved (1)
FFh
3FFh
FFFh
FFFh
16h Reserved
(1)
FFh
3FFh
FFFh
17h Reserved
(1)
FFh
3FFh
FFFh
18h Reserved
(1)
FFh
3FFh
FFFh
19h Reserved
(1)
FFh
3FFh
FFFh
1Ah Reserved
(1)
FFh
3FFh
FFFh
1Bh Reserved
(1)
FFh
3FFh
FFFh
FFFh
1Ch Reserved (1)
FFh
3FFh
FFFh
(1)
06h Reserved
(1)
07h Reserved
(1)
08h VREF register
09h Power-Down register
0Ah Gain and Status register
0Bh WiperLock Technology
Status register
0Ch Reserved (1)
FFh
FFh
FFh
FFh
3FFh
3FFh
3FFh
3FFh
FFFh
FFFh
FFFh
0000h 0000h 0000h
0000h 0000h 0000h
0080h 0080h 0080h
0000h 0000h 0000h
FFh
3FFh
(1)
FFh
3FFh
FFFh
1Dh Reserved
FFh
3FFh
FFFh
0Eh Reserved (1)
FFh
3FFh
FFFh
1Eh Reserved (1)
FFh
3FFh
FFFh
0Fh Reserved (1)
FFh
3FFh
FFFh
1Fh Reserved (1)
FFh
3FFh
FFFh
0Dh Reserved
Volatile Memory address range
Note 1:
Nonvolatile Memory address range
I2C
Reading a reserved memory location will result in the
command to Not ACK the command byte. The
device data bits will output all ‘1’s. A Start condition will reset the I2C interface.
DS20005405A-page 32
2015 Microchip Technology Inc.
MCP47FVBXX
4.2.5
DEVICE REGISTERS
Register 4-1 shows the format of the DAC Output Value
registers for the volatile memory locations. These registers will be either 8 bits, 10 bits, or 12 bits wide. The
values are right justified.
REGISTER 4-1:
12-bit
DAC0 AND DAC1 REGISTERS (VOLATILE)
U-0
U-0
U-0
U-0
—
—
—
—
D11
D10
(1)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
10-bit
—
—
—
—
—
—
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
8-bit
—
—
—
—
—(1)
—(1)
—(1)
—(1)
D07
D06
D05
D04
D03
D02
D01
D00
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
= 12-bit device
12-bit
10-bit
W = Writable bit
‘1’ = Bit is set
= 10-bit device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= 8-bit device
x = Bit is unknown
8-bit
bit 15-12 bit 15-10 bit 15-8
Unimplemented: Read as ‘0’
bit 11-0
—
—
D11-D00: DAC Output value - 12-bit devices
FFFh = Full-Scale output value
7FFh = Mid-Scale output value
000h =Zero-Scale output value
—
bit 9-0
—
D09-D00: DAC Output value - 10-bit devices
3FFh = Full-Scale output value
1FFh = Mid-Scale output value
000h =Zero-Scale output value
—
—
bit 7-0
D07-D00: DAC Output value - 8-bit devices
FFh = Full-Scale output value
7Fh = Mid-Scale output value
000h =Zero-Scale output value
Note 1:
Unimplemented bit, read as ‘0’.
2015 Microchip Technology Inc.
DS20005405A-page 33
MCP47FVBXX
Register 4-2 shows the format of the Voltage Reference Control register. Each DAC has two bits to control
the source of the voltage reference of the DAC. This
register is for the volatile memory locations. The width
of this register is 2 times the number of DACs for the
device.
REGISTER 4-2:
VOLTAGE REFERENCE (VREF) CONTROL REGISTER (ADDRESS 08h)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
Dual
—
—
—
—
—
—
—
—
—
—
—
—
R/W-0 R/W-0 R/W-0 R/W-0
—(1)
—(1)
VR0B VR0A
VR1B VR1A VR0B VR0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= Dual-channel device
x = Bit is unknown
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
VRxB-VRxA: DAC Voltage Reference Control bits
11 = VREF pin (Buffered); VREF buffer enabled.
10 = VREF pin (Unbuffered); VREF buffer disabled.
01 = Internal Band Gap (1.22V typical); VREF buffer enabled. VREF voltage driven when
powered-down.
00 = VDD (Unbuffered); VREF buffer disabled. Use this state with Power-down bits for lowest
current.
Note 1:
Unimplemented bit, read as ‘0’.
DS20005405A-page 34
2015 Microchip Technology Inc.
MCP47FVBXX
Register 4-3 shows the format of the Power-Down
Control register. Each DAC has two bits to control the
Power-Down state of the DAC. This register is for the
volatile memory locations. The width of this register is
2 times the number of DACs for the device.
REGISTER 4-3:
POWER-DOWN CONTROL REGISTER (ADDRESS 09h)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
Single
—
—
—
—
—
—
—
—
—
—
—
—
—(1)
Dual
—
—
—
—
—
—
—
—
—
—
—
—
PB1B PB1A PB0B PB0A
R/W-0 R/W-0 R/W-0 R/W-0
—(1)
PB0B PB0A
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
= Dual-channel device
x = Bit is unknown
Single
Dual
bit 15-2
bit 15-4
Unimplemented: Read as ‘0’
bit 1-0
bit 3-0
PBxB-PBxA: DAC Power-Down Control bits(2)
11 = Powered Down - VOUT is open circuit.
10 = Powered Down - VOUT is loaded with a 100 k resistor to ground.
01 = Powered Down - VOUT is loaded with a 1 k resistor to ground.
00 = Normal Operation (Not powered-down).
Note 1:
2:
Unimplemented bit, read as ‘0’.
See Table 5-5 and Figure 5-10 for more details.
2015 Microchip Technology Inc.
DS20005405A-page 35
MCP47FVBXX
Register 4-4 shows the format of the Gain Control and
System Status register. Each DAC has one bit to
control the gain of the DAC and three Status bits. This
register is for the volatile memory locations.
REGISTER 4-4:
Single
Dual
GAIN CONTROL AND SYSTEM STATUS REGISTER (ADDRESS 0Ah)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—(1)
G0
POR
—
—
—
—
—
—
—
—
—
—
—
—
—
G1
G0
POR
—
—
—
—
—
—
R/W-0 R/W-0 R/C-1
bit 15
—
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
= Single-channel device
C = Clearable bit
‘0’ = Bit is cleared
= Dual-channel device
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
Single
Dual
bit 15-9
bit 15-10 Unimplemented: Read as ‘0’
—
bit 9
G1: DAC1 Output Driver Gain control bits (Dual-Channel Device only)
1 = 2x Gain. Not applicable when VDD is used as VRL.
0 = 1x Gain.
bit 8
bit 8
G0: DAC0 Output Driver Gain control bits
1 = 2x Gain. Not applicable when VDD is used as VRL.
0 = 1x Gain.
bit 7
bit 7
POR: Power-on Reset (Brown-out Reset) Status bit
This bit indicates if a Power-on Reset (POR) or Brown-out Reset (BOR) event has
occurred since the last read command of this register. Reading this register clears the
state of the POR Status bit.
1 = A POR (BOR) event occurred since the last read of this register. Reading this register clears
this bit.
0 = A POR (BOR) event has not occurred since the last read of this register.
bit 6-0
bit 6-0
Unimplemented: Read as ‘0’
Note 1:
Unimplemented bit, read as ‘0’.
DS20005405A-page 36
2015 Microchip Technology Inc.
MCP47FVBXX
5.0
The functional blocks of the DAC include:
DAC CIRCUITRY
•
•
•
•
•
•
The Digital to Analog Converter circuitry converts a digital
value into its analog representation. The description
describes the functional operation of the device.
The DAC Circuit uses a resistor ladder implementation.
Devices have up to two DACs.
Figure 5-1 shows the functional block diagram for the
MCP47FVBXX DAC circuitry.
VDD
Voltage
Reference
Selection
Resistor Ladder
Voltage Reference Selection
Output Buffer/VOUT Operation
Internal Band Gap (as a voltage reference)
Latch Pin (LAT)
Power-Down Operation
Power-Down
Operation
PD1:PD0 and
VREF1:VREF0
VREF
+
-
VDD
VDD
VREF1:VREF0
PD1:PD0 and BGEN
Band Gap
(1.22V typical)
VREF1:VREF0
PD1:PD0
VDD
A (RL)
RS(2n)
DAC
Output
Selection
Power-Down
Operation
PD1:PD0
VW
VOUT
+
RS(2n - 1)
-
Output Buffer/VOUT
Operation
RRL RS(2n - 3)
100 k
PD1:PD0
Gain
(1x or 2x)
RS(2n - 2)
1 k
VRL
Internal Band Gap
Power-Down
Operation
(~140 k)
DAC Register Value
V W = ---------------------------------------------------------------------- V RL
# Resistor in Resistor Ladder
RS(2)
Where:
# Resistors in Resistor Ladder = 256 (MCP47FVB0X)
Resistor
Ladder
1024 (MCP47FVB1X)
RS(1)
4096 (MCP47FVB2X)
B
FIGURE 5-1:
MCP47FVBXX DAC Module Block Diagram.
2015 Microchip Technology Inc.
DS20005405A-page 37
MCP47FVBXX
5.1
Resistor Ladder
PD1:PD0
The Resistor Ladder is a digital potentiometer with the
B Terminal internally grounded and the A Terminal
connected to the selected reference voltage (see
Figure 5-2). The volatile DAC register controls the
wiper position. The wiper voltage (VW) is proportional to
the DAC register value divided by the number of resistor elements (RS) in the ladder (256, 1024 or 4096)
related to the VRL voltage.
The output of the resistor network will drive the input of
an output buffer.
VRL
DAC
register
RS(2n)
2n - 1
RW (1)
RS(2n - 1)
RRL
2n - 2
RW (1)
RS(2n - 2)
The Resistor Network is made up of these three parts:
VW
• Resistor Ladder (string of RS elements)
• Wiper switches
• DAC register decode
The resistor ladder (RRL) has a typical impedance of
approximately 140 k. This resistor ladder resistance
(RRL) may vary from device to device up to ±20%.
Since this is a voltage divider configuration, the actual
RRL resistance does not affect the output given a fixed
voltage at VRL.
Equation 5-1 shows the calculation for the step
resistance.
Note:
The maximum wiper position is 2n – 1,
while the number of resistors in the
resistor ladder is 2n. This means that
when the DAC register is at full scale,
there is one resistor element (RS)
between the wiper and the VRL voltage.
If the unbuffered VREF pin is used as the VRL voltage
source, this voltage source should have a low output
impedance.
When the DAC is powered-down, the resistor ladder is
disconnected from the selected reference voltage.
DS20005405A-page 38
1
RW
RS(1)
(1)
0
(1)
RW
Analog Mux
DAC Register Value
V W = ---------------------------------------------------------------------- V RL
# Resistor in Resistor Ladder
Where:
# Resistors in R-Ladder = 256 (MCP47FVB0X)
1024 (MCP47FVB1X)
4096 (MCP47FVB2X)
Note 1: The analog switch resistance (RW)
does not affect performance due to the
voltage divider configuration.
FIGURE 5-2:
Block Diagram.
Resistor Ladder Model
EQUATION 5-1:
RS CALCULATION
RRL
R S = ------------ 256
8-bit Device
R RL
R S = --------------- 1024
10-bit Device
R RL
R S = --------------- 4096
12-bit Device
2015 Microchip Technology Inc.
MCP47FVBXX
Voltage Reference Selection
The resistor ladder has up to four sources for the reference voltage. Two user control bits (VREF1:VREF0)
are used to control the selection, with the selection connected to the VRL node (see Figures 5-3 and 5-4). The
four voltage source options for the Resistor Ladder are:
1.
2.
3.
4.
VDD pin voltage
Internal Voltage Reference (VBG)
VREF pin voltage unbuffered
VREF pin voltage internally buffered
The selection of the voltage is specified with the volatile
VREF1:VREF0 configuration bits (see Register 4-2). On
a POR/BOR event, the default configuration state is
latched into the volatile VREF1:VREF0 configuration
bits.
VREF1:VREF0
VREF
VDD
Band Gap
FIGURE 5-3:
Resistor Ladder Reference
Voltage Selection Block Diagram.
VDD
PD1:PD0 and
VREF1:VREF0
VREF
+
VRL
If the VREF pin is selected, then select between the
buffered or unbuffered mode.
-
UNBUFFERED MODE
The VREF pin voltage may be from VSS to VDD.
VDD
Note 1: The voltage source should have a low
output impedance. If the voltage source
has a high output impedance, then the
voltage on the VREF’s pin would be lower
than expected. The resistor ladder has a
typical impedance of 140 k and a typical capacitance of 29 pF.
2: If the VREF pin is tied to the VDD voltage, VDD mode (VREF1:VREF0 = ‘00’)
is recommended.
5.2.2
VRL
Buffer
When the user selects the VDD as reference, the VREF
pin voltage is not connected to the resistor ladder.
5.2.1
Reference
Selection
5.2
BUFFERED MODE
The VREF pin voltage may be from 0.01V to VDD 0.04V. The input buffer (amplifier) provides low offset
voltage, low noise, and a very high input impedance,
with only minor limitations on the input range and frequency response.
Note 1: Any variation or noises on the reference
source can directly affect the DAC output.
The reference voltage needs to be as
clean as possible for accurate DAC
performance.
2: If the VREF pin is tied to the VDD voltage, VDD mode (VREF1:VREF0 = ‘00’)
is recommended.
2015 Microchip Technology Inc.
VDD
VREF1:VREF0
VREF1:VREF0
PD1:PD0
and BGEN
Band Gap (1)
(1.22V typical)
Note 1: The Band Gap voltage (VBG) is 1.22V
typical. The band gap output goes through
the buffer with a 2x gain to create the VRL
voltage. See Section 5.4 “Internal Band
Gap” for addition information on the band
gap circuit.
FIGURE 5-4:
Reference Voltage Selection
Implementation Block Diagram.
5.2.3
BANDGAP MODE
If the Internal Band Gap is selected, then the external
VREF pin should not be driven and only use
high-impedance loads. Decoupling capacitors are
recommended for optimal operation.
The band gap output is buffered, but the internal
switches limit the current that the output should source
to the VREF pin. The resistor ladder buffer is used to
drive the Band Gap voltage for the cases of multiple
DAC outputs. This ensures that the resistor ladders are
always properly sourced when the band gap is selected.
DS20005405A-page 39
MCP47FVBXX
5.3
Output Buffer/VOUT Operation
TABLE 5-1:
The Output Driver buffers the wiper voltage (VW) of the
Resistor Ladder.
The DAC output is buffered with a low power and
precision output amplifier (op amp). This amplifier
provides a rail-to-rail output with low offset voltage and low
noise. The amplifier’s output can drive the resistive and
high-capacitive loads without oscillation. The amplifier
provides a maximum load current which is enough for
most programmable voltage reference applications. Refer
to Section 1.0 “Electrical Characteristics” for the
specifications of the output amplifier.
The load resistance must keep higher than
5 k for the stable and expected analog
output (to meet electrical specifications).
Note:
Figure 5-5 shows a block diagram of the output driver
circuit.
OUTPUT DRIVER GAIN
Gain Bit
Gain
0
1
1
2
5.3.1
Comment
Limits VREF pin voltages
relative to device VDD voltage.
PROGRAMMABLE GAIN
The amplifier’s gain is controlled by the Gain (G)
configuration bit (see Register 4-4) and the VRL
reference selection (see Register 4-2). When the VRL
reference selection is the device’s VDD voltage, the G
bit is ignored and a gain of 1 is used.
The volatile G bit value can be modified by:
• POR event
• BOR event
• I2C Write commands
• I2C General Call Reset command
The user can select the output gain of the output
amplifier. Gain options are:
a)
b)
Gain of 1, with either VDD or VREF pin used as
reference voltage.
Gain of 2, only when VREF pin or Internal Band
Gap is used as reference voltage. The VREF pin
voltage should be limited to VDD/2.
Power-down logic also controls the output buffer operation (see Section 5.6 “Power-Down Operation” for
additional information on Power-down). In any of the
three Power-Down modes, the op amp is powereddown and its output becomes a high impedance to the
VOUT pin.
Table 5-1 shows the gain bit operation. When the
reference voltage selection (VRL) is the device’s VDD
voltage, the G bit is ignored and a gain of 1 is used.
VDD
PD1:PD0
VW
VOUT
+
-
1 k
100 k
PD1:PD0
Gain(1)
Note 1: Gain options are 1x and 2x.
FIGURE 5-5:
DS20005405A-page 40
Output Driver Block Diagram.
2015 Microchip Technology Inc.
MCP47FVBXX
5.3.2
OUTPUT VOLTAGE
The volatile DAC register values, along with the
device’s configuration bits, control the analog VOUT
voltage. The volatile DAC register’s value is unsigned
binary. The formula for the output voltage is provided in
Equation 5-2. Table 5-3 shows examples of volatile
DAC register values and the corresponding theoretical
VOUT voltage for the MCP47FVBXX devices.
EQUATION 5-2:
CALCULATING OUTPUT
VOLTAGE (VOUT)
V RL DAC Register Value
VOUT = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
5.3.3
STEP VOLTAGE (VS)
The Step Voltage is dependent on the device resolution
and the calculated output voltage range. One LSb is
defined as the ideal voltage difference between two
successive codes. The step voltage can easily be calculated by using Equation 5-3 (DAC register value is
equal to 1). Theoretical Step Voltages are shown in
Table 5-2 for several VREF voltages.
EQUATION 5-3:
VS CALCULATION
V RL
VS = ---------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
Where:
Where:
# Resistors in R-Ladder = 4096 (MCP47FVB2X)
# Resistors in R-Ladder = 4096 (12-bit)
1024 (10-bit)
1024 (MCP47FVB1X)
256 (8-bit)
256 (MCP47FVB0X)
Note:
When Gain = 2 (VRL = VREF),
if VREF > VDD / 2, the VOUT voltage will be
limited to VDD. So if VREF = VDD, then the
VOUT voltage will not change for volatile
DAC register values mid-scale and greater,
since the op amp is at full-scale output.
The following events update the DAC register value
and therefore the analog voltage output (VOUT):
• Power-on Reset
• Brown-out Reset
• I2C Write Command, Falling edge of the acknowledge pulse of the last write command byte
• I2C General Call Reset command, Output is
updated with POR data.
TABLE 5-2:
THEORETICAL STEP
VOLTAGE (VS) (1)
VREF
5.0
2.7
1.8
1.5
1.0
1.22mV
659uV
439uV
366uV
244uV
12-bit
977uV
10-bit
VS 4.88mV 2.64mV 1.76mV 1.46mV
19.5mV 10.5mV 7.03mV 5.86mV 3.91mV 8-bit
Note 1: When Gain = 1x, VFS = VRL, and VZS = 0V.
Next, the VOUT voltage will start driving to the new
value after the event has occurred.
2015 Microchip Technology Inc.
DS20005405A-page 41
MCP47FVBXX
5.3.4
OUTPUT SLEW RATE
Figure 5-6 shows an example of the slew rate of the
VOUT pin. The slew rate can be affected by the characteristics of the circuit connected to the VOUT pin.
VOUT(B)
DACx = A
DACx= B
Time
V OUT B – V OUT A
Slew Rate = -------------------------------------------------T
FIGURE 5-6:
5.3.4.1
VOUT Pin Slew Rate.
Small Capacitive Load
With a small capacitive load, the output buffer’s current
is not affected by the capacitive load (CL). But still, the
VOUT pin’s voltage is not a step transition from one output value (DAC register value) to the next output value.
The change of the VOUT voltage is limited by the output
buffer’s characteristics, so the VOUT pin voltage will
have a slope from the old voltage to the new voltage.
This slope is fixed for the output buffer, and is referred
to as the buffer slew rate (SRBUF).
5.3.4.2
DRIVING RESISTIVE AND
CAPACITIVE LOADS
The VOUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications). A VOUT vs. Resistive Load characterization graph can be seen in the Char Data for this
device (DS20005378).
VOUT drops slowly as the load resistance decreases
after about 3.5 k. It is recommended to use a load
with RL greater than 5 k.
VOUT
VOUT(A)
5.3.5
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the VOUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
VOUT pin.
So, when driving large capacitive loads with the output
buffer, a small series resistor (RISO) at the output (see
Figure 5-7) improves the output buffer’s stability
(feedback loop’s phase margin) by making the output
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
Large Capacitive Load
With a larger capacitive load, the slew rate is
determined by two factors:
VW
• The output buffer’s short-circuit current (ISC)
• The VOUT pin’s external load
IOUT cannot exceed the output buffer’s short-circuit current (ISC), which fixes the output buffer slew rate
(SRBUF). The voltage on the capacitive load (CL), VCL,
changes at a rate proportional to IOUT, which fixes a
capacitive load slew rate (SRCL).
So the VCL voltage slew rate is limited to the slower of
the output buffer’s internally set slew rate (SRBUF) and
the capacitive load slew rate (SRCL).
Op
Amp
VOUT
VCL
RISO
RL
CL
FIGURE 5-7:
Circuit to Stabilize Output
Buffer for Large Capacitive Loads (CL).
The RISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this RISO resistor
value should be verified on the bench. Modify the
RISO’s resistance value until the output characteristics
meet your requirements.
A method to evaluate the system’s performance is to
inject a step voltage on the VREF pin and observe the
VOUT pin’s characteristics.
Note:
DS20005405A-page 42
Additional insight into circuit design for
driving capacitive loads can be found in
AN884 – “Driving Capacitive Loads With
Op Amps” (DS00000884).
2015 Microchip Technology Inc.
MCP47FVBXX
TABLE 5-3:
Device
DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (VOUT) (VDD = 5.0V)
Volatile DAC
Register Value
1111 1111 1111
VRL
(1)
LSb
Gain
Selection
Equation
µV
(2)
5.0V
5.0V/4096
1,220.7
1x
VRL (4095/4096) 1
4.998779
2.5V
2.5V/4096
610.4
1x
VRL (4095/4096) 1
2.499390
MCP47FVB2X (12-bit)
0011 1111 1111
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
MCP47FVB1X (10-bit)
11 1111 1111
01 1111 1111
00 1111 1111
00 0000 0000
MCP47FVB0X (8-bit)
1111 1111
0111 1111
0011 1111
0000 0000
Note 1:
2:
3:
V
VRL (4095/4096) 2)
4.998779
VRL (2047/4096) 1)
2.498779
(2)
1x
VRL (2047/4096) 1)
1.249390
2x(2)
VRL (2047/4096) 2)
2.498779
5.0V
5.0V/4096
1,220.7
1x
VRL (1023/4096) 1)
1.248779
2.5V
2.5V/4096
610.4
1x
VRL (1023/4096) 1)
0.624390
VRL (1023/4096) 2)
1.248779
2x
0000 0000 0000
Equation
1x
2x
0111 1111 1111
VOUT(3)
5.0V
5.0V/4096
1,220.7
2.5V
2.5V/4096
610.4
(2)
1x
VRL (0/4096) * 1)
1x
VRL (0/4096) * 1)
0
2x(2)
VRL (0/4096) * 2)
0
0
5.0V
5.0V/1024
4,882.8
1x
VRL (1023/1024) 1
4.995117
2.5V
2.5V/1024
2,441.4
1x
VRL (1023/1024) 1
2.497559
2x(2)
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
VRL (1023/1024) 2
4.995117
1x
VRL (511/1024) 1
2.495117
1x
VRL (511/1024) 1
1.247559
2x(2)
VRL (511/1024) 2
2.495117
5.0V
5.0V/1024
4,882.8
1x
VRL (255/1024) 1
1.245117
2.5V
2.5V/1024
2,441.4
1x
VRL (255/1024) 1
0.622559
2x(2)
VRL (255/1024) 2
1.245117
5.0V
5.0V/1024
4,882.8
2.5V
2.5V/1024
2,441.4
1x
VRL (0/1024) 1
0
1x
VRL (0/1024) 1
0
2x(2)
VRL (0/1024) 1
0
5.0V
5.0V/256
19,531.3
1x
VRL (255/256) 1
4.980469
2.5V
2.5V/256
9,765.6
1x
VRL (255/256) 1
2.490234
2x(2)
VRL (255/256) 2
4.980469
1x
VRL (127/256) 1
2.480469
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
1x
VRL (127/256) 1
1.240234
2x(2)
VRL (127/256) 2
2.480469
5.0V
5.0V/256
19,531.3
1x
VRL (63/256) 1
1.230469
2.5V
2.5V/256
9,765.6
1x
VRL (63/256) 1
0.615234
2x(2)
VRL (63/256) 2
1.230469
1x
VRL (0/256) 1
0
1x
VRL (0/256) 1
0
2x(2)
VRL (0/256) 2
0
5.0V
5.0V/256
19,531.3
2.5V
2.5V/256
9,765.6
VRL is the resistor ladder’s reference voltage. It is independent of VREF1:VREF0 selection.
Gain selection of 2x (Gx = ‘1‘) requires voltage reference source to come from VREF pin
(VREF1:VREF0 = ‘10’ or ‘11’) and requires VREF pin voltage (or VRL) ≤ VDD/2 or from the internal band
gap (VREF1:VREF0 = ‘01’).
These theoretical calculations do not take into account the Offset, Gain and nonlinearity errors.
2015 Microchip Technology Inc.
DS20005405A-page 43
MCP47FVBXX
5.4
Internal Band Gap
The internal band gap is designed to drive the Resistor
Ladder Buffer.
The resistance of a resistor ladder (RRL) is targeted to
be 140 k (40 k), which means a minimum resistance of 100 k.
The band gap selection can be used across the VDD
voltages while maximizing the VOUT voltage ranges.
For VDD voltages below the 2 Gain VBG voltage, the
output for the upper codes will be clipped to the VDD
voltage. Table 5-4 shows the maximum DAC register
code given device VDD and Gain bit setting.
5.5
2.7
2.0(4)
VOUT USING BAND GAP
DAC Gain
VDD
TABLE 5-4:
Max DAC Code (1)
1
FFFh
3FFh
FFh VOUT(max) = 2.44V(3)
2
FFFh
3FFh
FFh VOUT(max) = 4.88V(3)
1
FFFh
3FFh
FFh VOUT(max) = 2.44V(3)
12bit
Comment
10-bit 8-bit
2
8DAh
236h
8Dh ~ 0 to 55% range
1
D1Dh
347h
D1h ~ 0 to 82% range
68Eh
1A3h
68h
2(2)
Note 1:
2:
3:
4:
~ 0 to 41% range
Without the VOUT pin voltage being clipped
Recommended to use Gain = 1 setting
When VBG = 1.22V typical
Band gap performance achieves full
performance starting from a VDD of 2.0V.
DS20005405A-page 44
2015 Microchip Technology Inc.
MCP47FVBXX
5.5
Latch Pin (LAT)
The Latch pin controls when the volatile DAC register
value is transferred to the DAC wiper. This is useful for
applications that need to synchronize the wiper(s)
updates to an external event, such as zero crossing or
updates to the other wipers on the device. The LAT pin
is asynchronous to the serial interface operation.
Serial Shift reg.
Register Address
Write Command
16 Clocks
Vol. DAC register x
LAT
Transfer
SYNC
Data
(internal signal)
DAC wiper x
When the LAT pin is high, transfers from the volatile DAC
register to the DAC wiper are inhibited. The volatile DAC
register value(s) can be continued to be updated.
When the LAT pin is low, the volatile DAC register value
is transferred to the DAC wiper.
Note:
This allows both the volatile DAC0 and
DAC1 registers to be updated while the
LAT pin is high, and to have outputs synchronously updated as the LAT pin is
driven low.
Figure 5-8 shows the interaction of the LAT pin and the
loading of the DAC wiper x (from the volatile DAC register x). The transfers are level driven. If the LAT pin is
held low, the corresponding DAC wiper is updated as
soon as the volatile DAC register value is updated.
LAT SYNC
Transfer
Data
Comment
1
1
0
No Transfer
1
0
0
No Transfer
0
1
1
Vol. DAC register x DAC wiper x
0
0
0
No Transfer
FIGURE 5-8:
LAT and DAC Interaction.
The LAT pin allows the DAC wiper to be updated to an
external event as well as have multiple DAC channels/devices update at a common event.
Since the DAC wiper x is updated from the Volatile
DAC register x, all DACs that are associated with a
given LAT pin can be updated synchronously.
If the application does not require synchronization, then
this signal should be tied low.
Figure 5-9 shows two cases of using the LAT pin to
control when the wiper register is updated relative to
the value of a sine wave signal.
Case 1: Zero Crossing of Sine Wave to update volatile DAC0 register (using LAT pin)
Case 2: Fixed point Crossing of Sine Wave to update volatile DAC0 register (using LAT pin)
Indicates where LAT pin pulses active (volatile DAC0 register updated)
FIGURE 5-9:
Example Use of LAT Pin Operation.
2015 Microchip Technology Inc.
DS20005405A-page 45
MCP47FVBXX
Power-Down Operation
To allow the application to conserve power when the
DAC operation is not required, three power-down
modes are available. The Power-Down configuration
bits (PD1:PD0) control the power-down operation
(Figure 5-10 and Table 5-5). On devices with multiple
DACs, each DAC’s power-down mode is individually
controllable. All power-down modes do the following:
V DD
PD1:PD0
VW
-
• Turn off most the DAC module’s internal circuits
(output op amp, resistor ladder,...)
• Op amp output becomes high-impedance to the
VOUT pin
• Disconnects resistor ladder from reference
voltage (VRL)
• Retains the value of the volatile DAC register and
configuration bits
Depending on the selected power-down mode, the
following will occur:
• VOUT pin is switched to one of two resistive pulldowns (See Table 5-5)
- 100 k (typical)
- 1 k (typical)
• Op amp is powered-down and the VOUT pin is
high-impedance.
There is a delay (TPDE) between the PD1:PD0 bits
changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the op
amp no longer driving the VOUT output and the pulldown resistors sinking current.
In any of the power-down modes where the VOUT pin is
not externally connected (sinking or sourcing current),
the power-down current will typically be ~650 nA for a
single-DAC device. As the number of DACs increases,
the device’s power-down current will also increase.
The power-down bits are modified by using a Write
command to the volatile Power-Down register, or a POR
event which forces the volatile Power-Down bits to the
Normal operation state.
Section 7.0 “Device Commands” describes the I2C
commands for writing the power-down bits. The
commands that can update the volatile PD1:PD0 bits are:
•
•
•
•
Write Command (Normal and High-Voltage)
Read Command (Normal and High-Voltage)
General Call Reset
General Call Wake-up
Note:
V OUT
+
PD1:PD0
(1)
1k
Gain
100 k
5.6
Note 1: Gain options are 1x and 2x.
FIGURE 5-10:
Diagram.
VOUT Power-Down Block
TABLE 5-5:
POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
PD1
PD0
Function
0
0
Normal operation
0
1
1 k resistor to ground
1
0
100 k resistor to ground
1
1
Open circuit
Table 5-6 shows the current sources for the DAC based
on the selected source of the DAC’s reference voltage
and if the device is in normal operating mode or one of
the power-down modes.
TABLE 5-6:
Device VDD
Current
Source
DAC CURRENT SOURCES
PD1:0 ‘00’,
VREF1:0 =
PD1:0 = ‘00’,
VREF1:0 =
00 01
10
11 00 01
10
11
Output
Op Amp
Y
Y
Y
Y
N
N
N
N
Resistor
Ladder
Y
Y
N (1)
Y
N
N
N (1)
N
RL Op Amp
N
Y
N
Y
N
N
N
N
Band Gap
N
Y
N
N
N
Y
N
N
Note 1:
Current is sourced from the VREF pin, not the
device VDD.
The I2C serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
I2C master device.
DS20005405A-page 46
2015 Microchip Technology Inc.
MCP47FVBXX
5.6.1
EXITING POWER-DOWN
When the device exits the power-down mode the
following occurs:
• Disabled circuits (op amp, resistor ladder, ...) are
turned on
• Resistor ladder is connected to selected
reference voltage (VRL)
• Selected pull-down resistor is disconnected
• The VOUT output will be driven to the voltage
represented by the volatile DAC register’s value
and configuration bits
The VOUT output signal will require time as these
circuits are powered-up and the output voltage is driven
to the specified value as determined by the volatile
DAC register and configuration bits.
Note:
Since the op amp and resistor ladder were
powered-off (0V), the op amp’s input
voltage (VW) can be considered 0V. There
is a delay (TPDD) between the PD1:PD0
bits updating to ‘00’ and the op amp driving the VOUT output. The op amp’s settling
time (from 0V) needs to be taken into
account to ensure the VOUT voltage
reflects the selected value.
The following events will change the PD1:PD0 bits to ‘00’
and therefore exit the Power-Down mode. These are:
5.7
DAC Registers, Configuration
Bits, and Status Bits
The MCP47FVBXX devices have volatile memory.
Table 4-2 shows the volatile and the interaction due to
a POR event.
There are five configuration bits in the volatile memory,
the DAC registers in the volatile memory and two volatile status bits. The volatile DAC registers will be either
12-bits (MCP47FVB2X), 10-bits (MCP47FVB1X), or 8bits (MCP47FVB0X) wide.
When the device is first powered-up, it automatically
forces the device default values to the volatile memory.
The volatile memory determines the analog output
(VOUT) pin voltage. After the device is powered-up, the
user can update the device memory.
The I2C interface is how this memory is read and written.
Refer to Section 6.0 “I2C Serial Interface Module” and
Section 7.0 “Device Commands” for more details on
reading and writing the device’s memory.
Register 4-4 shows the operation of the device status
bits and Table 4-2 shows the factory default value of a
POR/BOR event for the device configuration bits.
There is one status bit (the POR bit) and it indicates if
the device VDD is above or below the POR trip point.
After a POR event, this bit is a ‘1’, reading the Gain
Control and System Status register clears this bit (‘0’).
• Any I2C write command where the PD1:PD0 bits
are ‘00’
• I2C General Call Wake-up Command
• I2C General Call Reset Command.
5.6.2
RESET COMMANDS
When the MCP47FVBXX is in the valid operating voltage, the I2C General Call Reset command will force a
Reset event. This is similar to the Power-on Reset,
except that the Reset delay timer is not started.
If the I2C interface bus does not seem to be responsive, the technique shown in Section 8.9 “Software
I2C Interface Reset Sequence” can be used to force the
I2C interface to be reset.
2015 Microchip Technology Inc.
DS20005405A-page 47
MCP47FVBXX
I2C SERIAL INTERFACE
MODULE
6.0
The MCP47FVBXX’s I2C Serial Interface Module supports the I2C serial protocol specification. This I2C
interface is a two-wire interface (clock and data).
Figure 6-1 shows a typical I2C interface connection.
2
The I C specification only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. The frame content
(commands) for the MCP47FVBXX is defined in
Section 7.0 “Device Commands”.
An overview of the I2C protocol is available in
Section Appendix B: “I2C Serial Interface”.
6.3
The I2C interface specifies different communication bit
rates. These are referred to as Standard, Fast or HighSpeed modes. The MCP47FVBXX supports these three
modes. The clock rates (bit rate) of these modes are:
• Standard mode: up to 100 kHz (kbit/s)
• Fast mode: up to 400 kHz (kbit/s)
• High-Speed mode (HS mode): up to 3.4 MHz
(Mbit/s)
A description on how to enter High-Speed mode is
described in Section 6.9 “Entering High-Speed
(HS) Mode”.
6.4
Typical I2C™ Interface Connections
MCP47FVBXX
(Slave)
Host
Controller
(Master)
SCL
SDA
6.1
SDA
The memory address is the 5-bit value that specifies
the location in the device’s memory that the specified
command will operate on.
Typical I2C Interface.
Overview
The following sections discuss some of these devicespecific characteristics.
Interface Pins (SCL and SDA)
Communication Data Rates
POR/BOR
Device Memory Address
General Call Commands
Device I2C Slave Addressing
Entering High-Speed (HS) Mode
6.2
On a POR/BOR event, the I2C Serial Interface Module
state machine is reset, which includes forcing the
device’s Memory Address pointer to 00h.
6.5
This sections discusses some of the specific characteristics of the MCP47FVBXX’s I2C Serial Interface Module.
This is to assist in the development of your application.
•
•
•
•
•
•
•
POR/BOR
SCL
Other Devices
FIGURE 6-1:
Communication Data Rates
Interface Pins (SCL and SDA)
The MCP47FVBXX I2C’s module SCL pin does not
generate the serial clock since the device operates in
Slave mode. Also, the MCP47FVBXX will not stretch
the clock signal (SCL) since memory read access
occurs fast enough.
Device Memory Address
On a POR/BOR event, the device’s Memory Address
pointer is forced to 00h.
The MCP47FVBXX retains the last “Device Memory
Address” that it has received. That is, the
MCP47FVBXX does not “corrupt” the “Device Memory
Address” after Repeated Start or Stop conditions.
6.6
General Call Commands
The General Call commands utilize the I2C
specification reserved General Call command address
and command codes. The MCP47FVBXX also implements a non-standard General Call command.
The General Call commands are
• General Call Reset
• General Call Wake-up (MCP47FVBXX defined)
The General Call Wake-up command will cause all the
MCP47FVBXX devices to exit their power-down state.
6.7
Multi-Master Systems
The MCP47FVBXX is not a Master device (generate
the interface clock), but can be used in multi-master
applications.
The MCP47FVBXX I2C’s module implements slope
control on the SDA pin output driver.
DS20005405A-page 48
2015 Microchip Technology Inc.
MCP47FVBXX
Device I2C Slave Addressing
6.8
The MCP47FVBXX has a fixed 7-bit slave address.
The address byte is the first byte received following the
Start condition from the master device (see Figure 6-2).
Acknowledge bit
Start bit
TABLE 6-1:
7-bit I2C™
Address
R/W ACK
1
1
0
0
0
0
A0 Address
MCP47FVBXXA1T-E/ST
A6 A5
A4
FIGURE 6-2:
I2C Control Byte.
Note:
A3
A2 A1
A0
Slave Address Bits in the
The I2C 10-bit Addressing mode is not
supported.
Tape and Reel
Tape and Reel
MCP47FVBXXA2-E/ST
MCP47FVBXXA2T-E/ST
Tape and Reel
MCP47FVBXXA3-E/ST
‘1100011’
Note 1:
Comment
MCP47FVBXXA1-E/ST
‘1100001’
‘1100010’
0
Device Order Code(1)
MCP47FVBXXA0T-E/ST
Address Byte
Slave Address (7-bits)
I2C ADDRESS/ORDER CODE
MCP47FVBXXA0-E/ST
‘1100000’
Read/Write bit
Slave Address
Table 6-1 shows the four standard orderable I2C slave
addresses and their respective device order code.
MCP47FVBXXA3T-E/ST
Tape and Reel
‘xx’ in the order code indicates the resolution and number of output channels for the
device.
Custom I2C Slave Address Options
6.8.0.1
I2C
Custom
Slave Address options can be requested.
Customers can request the custom I2C Slave Address
via the Non-Standard Customer Authorization Request
(NSCAR) process.
Note 1: Non-Recurring
Engineering
(NRE)
charges
and
minimum
ordering
requirements for custom orders. Please
contact Microchip sales for additional
information.
2: A custom device will be assigned custom
device marking.
2015 Microchip Technology Inc.
DS20005405A-page 49
MCP47FVBXX
6.9
Entering High-Speed (HS) Mode
The I2C specification requires that a High-Speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by the master sending
a special address byte following the Start bit. This byte
is referred to as the High-Speed Master Mode Code
(HSMMC).
The device can now communicate at up to 3.4 Mbit/s
on SDA and SCL lines. The device will switch out of the
HS mode on the next Stop condition.
The master code is sent as follows:
1.
2.
3.
Start condition (S)
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the High-Speed (HS)
mode master.
No Acknowledge (A)
The MCP47FVBXX device does not acknowledge the
HS Select byte. However, upon receiving this command, the device switches to HS mode.
See Figure 6-3 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the NXP I2C specification.
6.9.1
SLOPE CONTROL
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
6.9.2
PULSE GOBBLER
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes <10 ns during HS mode.
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgments. The master device
can then either issue a Repeated Start bit to address a
different device (at High-Speed) or a Stop bit to return
to Fast/Standard bus speed. After the Stop bit, any
other master device (in a multi-master system) can
arbitrate for the I2C bus.
F/S-mode
S
HS-mode
‘0000 1XXX’b
HS Select Byte
A Sr ‘Slave Address’ R/W A
Control Byte
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
P = Stop bit (Stop condition terminates HS Mode)
FIGURE 6-3:
DS20005405A-page 50
P
“Data”
A/A
Command/Data Byte(s)
F/S-mode
HS-mode continues
Sr ‘Slave Address’ R/W A
Control Byte
HS Mode Sequence.
2015 Microchip Technology Inc.
MCP47FVBXX
7.0
7.0.1
DEVICE COMMANDS
ABORTING A TRANSMISSION
A Restart or Stop condition in an expected data bit
position will abort the current command sequence and
if the command was a write, that data word will not be
written to the MCP47FVBXX. Also the I2C state
machine will be reset.
This section documents the commands that the device
supports.
The commands can be grouped into the following
categories:
• Write Command (Normal and High-Voltage)
(C1:C0 = ‘00’)
• Read Command (Normal and High-Voltage)
(C1:C0 = ‘11’)
• General Call Commands
If the condition was a Restart (Start), then the following
byte will be expected to be the Slave Address byte.
If the condition was a Stop, the device will monitor for
the Start Condition.
The supported commands are shown in Table 7-1. These
commands allow for both a single data or continuous data
operation. Continuous data operation means that the I2C
Master does not generate a Stop bit but repeats the
required data/clocks. This allows faster updates since the
overhead of the I2C control byte is removed. Table 7-1
also shows the required number of bit clocks for each
command’s different mode of operation.
TABLE 7-1:
DEVICE COMMANDS - NUMBER OF CLOCKS
Command
# of Bit
Clocks
Code
Operation
HV
Mode
(1)
400kHz
3.4MHz (4)
38
2,632
10,526
89,474
Read Command (Normal
and High-Voltage)(5)
27n + 11
3,559
14,235
120,996
48
2,083
8,333
70,833
General Call Reset
0
(2)
Single
0
(2)
Continuous
1
1
(2)
Random
1
1
(2)
Continuous
18n + 11
4,762
19,048
161,905
Last Address
29
3,448
13,793
117,241
0
0
Comments
100kHz
C1 C0
Write Command (Normal
and High-Voltage)(5)
Data Update Rate
(8-bit/10-bit/12-bit)
(Data Words/Second)
For 10 data words
For 10 data words
1
1
(2)
—
—
(2)
Single
20
5,000
20,000
170,000
Note 3
—
—
(2)
Single
20
5,000
20,000
170,000
Note 3
Command
General Call Wake-up
Command
Note 1:
2:
3:
4:
5:
“n” indicates the number of times the command operation is to be repeated.
This command can be either normal voltage or high voltage.
Determined by General Call command byte after the I2C General Call address.
There is a minimal overhead to enter into 3.4 MHz mode.
High-Voltage commands are supported for serial interface compatibility with the MCP47FEBXX devices.
2015 Microchip Technology Inc.
DS20005405A-page 51
MCP47FVBXX
7.1
7.1.1
Write Command
(Normal and High-Voltage)
Write commands are used to transfer data to the
desired memory location (from the Host controller). The
Write command can be issued to the Volatile memory
locations.
Write commands can be structured as either Single or
Continuous. The continuous format allows the fastest
data update rate for the devices memory locations.
The format of the command is shown in Figure 7-1
(Single) and Figure 7-3 (Continuous). For example
ACK/NACK behavior see Figure 7-2.
SINGLE WRITE TO VOLATILE
MEMORY
For volatile memory locations, data is written to the
MCP47FVBXX after every data word transfer (during
the Acknowledge). If a Stop or Restart condition is
generated during a data transfer (before the A), the
data will not be written to the MCP47FVBXX. After the
A bit, the master can initiate the next sequence with a
Stop or Restart condition.
Refer to Figure 7-1 for the byte write sequence.
A Write command to a volatile memory location
changes that location after a properly formatted Write
command and the A/A clock has been received.
Note 1: During device communication, if the
Device Address/Command combination
is invalid or an unimplemented Device
Address
is
specified,
then
the
MCP47FVBXX will NACK that byte. To
reset the I2C state machine, the
I2C communication must detect a Start
bit.
ACK bit (1, 2)
Write bit
(1)
ACK bit
I2C™ Slave Address
Memory Address Command
Start bit
SA SA SA SA SA SA SA
S 6 5 4 3 2 1 0 0
Control Byte
A
AD AD AD AD AD
4 3 2 1 0 0 0
x
A
WRITE Command Reserved
(1)
ACK bit
Write “Data” bits
ACK bit (1, 2)
Stop bit (2)
D D D D D D D D
D D D D D D D D
15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A P
Write Data
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: At the falling edge of the SCL pin for the Write command ACK bit, the MCP47FVBXX device updates the
value of the specified device register.
3: This command sequence does not need to terminate (using the Stop bit), and the Write command can
be repeated (see continuous write format, Section 7.1.2 “Continuous Writes to Volatile Memory”).
FIGURE 7-1:
DS20005405A-page 52
Write Random Address Command.
2015 Microchip Technology Inc.
MCP47FVBXX
7.1.2
CONTINUOUS WRITES TO
VOLATILE MEMORY
A Continuous Write mode of operation is possible when
writing to the device’s volatile memory registers (see
Table 7-1). This Continuous Write mode allows writes
without a Stop or Restart condition or repeated transmissions of the I2C Control Byte. Figure 7-3 shows the
sequence for three continuous writes. The writes do not
need to be to the same volatile memory address. The
sequence ends with the master sending a Stop or
Restart condition.
TABLE 7-1:
7.1.3
The High Voltage Command (HVC) signal is used to
indicate that the command, or sequence of commands,
are in the High Voltage operational state. High Voltage
Command support allows I2C signal voltage compatibility with MCP47FEBXX devices.
Note:
VOLATILE MEMORY
ADDRESSES
Address
Single-Channel
Dual-Channel
00h
Yes
Yes
01h
No
Yes
08h
Yes
Yes
09h
Yes
Yes
0Ah
Yes
Yes
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
Writes to a volatile DAC register will not
transfer to the output register until the LAT
(HVC) pin is transitioned from the VIHHEN
voltage to a VIL voltage.
Data Byte
ACK
Data Byte
ACK
Command
ACK
S Slave Address
Master
R/W
ACK
Write 1 Byte Command
P
S S S S S S S S 0 1 A A A A A C C x A D D D D D D D D 1 D D D D D D D D 1 P
A A A A A A A
D D D D D 1 0
C 1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0
6 5 4 3 2 1 0
4 3 2 1 0
K 5 4 3 2 1 0 9 8
7 6 5 4 3 2 1 0
Example 1 (No Command Error)
Master
S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P
MCP47FVBXXA0
0
0
0
0
I2C™ Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 d d d d d d d d 0 d d d d d d d d 0 P
Example 2 (Command Error)
Master
S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P
MCP47FVBXXA0
I2C Bus
0
1
1
1
S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 0 d d d d d d d d 1 d d d d d d d d 1 P
Note: Once a Command Error has occurred (Example 2) the MCP47FVBXX will NACK until a Start condition occurs.
FIGURE 7-2:
I2C ACK / NACK Behavior (Write Command Example).
2015 Microchip Technology Inc.
DS20005405A-page 53
MCP47FVBXX
ACK bit (1, 2)
Write bit
(1)
ACK bit
I2C™ Slave Address
Memory Address Command
Start bit
SA SA SA SA SA SA SA
S 6 5 4 3 2 1 0 0
A
AD AD AD AD AD
4 3 2 1 0 0 0
Write Command
Control Byte
x
A
Reserved
ACK bit (1, 2)
(1)
ACK bit
Write “Data” bits
D D D D D D D D
D D D D D D D D
15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A
Write Data
Device
Memory
Address Command
AD AD AD AD AD
4 3 2 1 0 0 0
Write Command
ACK bit (1)
x
AD AD AD AD AD
4 3 2 1 0 0 0
Write Command
ACK bit (1)
x
ACK bit (1, 2)
D D D D D D D D
D D D D D D D D
A 15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A
Reserved
Device
Memory
Address Command
ACK bit (1)
Write “Data” bits
Write Data
(1)
ACK bit
Write “Data” bits
ACK bit (1, 2)
Stop bit (3)
D D D D D D D D
D D D D D D D D
A 15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A P
Reserved
Write Data
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: At the falling edge of the SCL pin for the Write command ACK bit, the MCP47FVBXX device updates
the value of the specified device register.
3: This command sequence does not need to terminate (using the Stop bit), and the Write command can
be repeated (see continuous write format, Section 7.1.2 “Continuous Writes to Volatile Memory”).
4: Only functions when writing to volatile registers (AD4:AD0 = 00h through 0Ah).
FIGURE 7-3:
DS20005405A-page 54
Continuous Write Commands.
2015 Microchip Technology Inc.
MCP47FVBXX
7.2
Read Command
(Normal and High-Voltage)
Read commands are used to transfer data from the
specified memory location (to the Host controller).
The Read command formats include:
• Single Read
- Single Memory Address
- Last Memory Address Accessed
• Continuous Reads
The MCP47FVBXX retains the last Device Memory
Address that it has received. This means the
MCP47FVBXX does not corrupt the Device Memory
Address after Repeated Start or Stop conditions.
Note 1: During device communication, if the
Device Address/Command combination
is invalid or an unimplemented Address is
specified, then the MCP47FVBXX will
NACK that byte. To reset the I2C state
machine, the I2C communication must
detect a Start bit.
2: If the LAT pin is High (VIH), reads of the
volatile DAC register read the output
value, not the internal register.
3: The Read commands operate the same
regardless of the state of the HighVoltage Command (HVC) signal.
4: High Voltage Command support allows
I2C signal voltage compatibility with
MCP47FEBXX devices.
2015 Microchip Technology Inc.
7.2.1
SINGLE READ
The Read command format writes two bytes, the Control byte and the Read command byte (desired memory
address and the Read command), and then has a
Restart condition. Then a 2nd Control byte is transmitted, but this control byte indicates a I2C read operation
(R/W bit = ‘1’).
7.2.1.1
Single Memory Address
Figure 7-4 shows the sequence for reading a specified
memory address.
7.2.1.2
Last Memory Address Accessed
Figure 7-5 shows the waveforms for a single read of
the last memory location accessed.
7.2.2
CONTINUOUS READS
Continuous reads allows the device’s memory to be
read quickly and are possible to all memory locations.
Figure 7-7 shows the sequence for three continuous
reads.
For continuous reads, instead of transmitting a Stop or
Restart condition after the data transfer, the master
continually reads the data byte. The sequence ends
with the master Not Acknowledging and then sending a
Stop or Restart.
7.2.3
IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP47FVBXX expects to receive complete, valid
I2C commands and will assume any command not
defined as a valid command is due to a bus corruption,
thus entering a passive high condition on the SDA signal. All signals will be ignored until the next valid Start
condition and Control Byte are received.
DS20005405A-page 55
MCP47FVBXX
ACK bit (1)
Write bit
(1)
Repeated Start bit
ACK bit
Memory Address Command
Start bit
I2C™ Slave Address
SA SA SA SA SA SA SA
S 6 5 4 3 2 1 0 0
A
AD AD AD AD AD
4 3 2 1 0 1
Read Command
Control Byte
I2C Slave Address
1 X A Sr
Read bit
ACK bit (1)
SA SA SA SA SA SA SA
6 5 4 3 2 1 0 1
(4)
ACK bit
Read Data bits
ACK bit (5)
Stop bit (2, 3)
D D D D D D D D
D D D D D D D D
A 15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A P
Control Byte
Read bits
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: At the falling edge of the SCL pin for the Read command ACK bit, the MCP47FVBXX device updates
the value of the specified device register.
3: This command sequence does not need to terminate (using the Stop bit), and the Read command can
be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”).
4: Master Device is responsible for A/A signal. If an A signal occurs, the MCP47FVBXX will abort this
transfer and release the bus.
5: The Master Device will Not Acknowledge, and the MCP47FVBXX will release the bus so the Master
Device can generate a Stop or Repeated Start condition.
FIGURE 7-4:
Read Command - Single Memory Address.
Start bit
I2C™ Slave Address
Read bit
ACK bit (1)
SA SA SA SA SA SA SA
S 6 5 4 3 2 1 0 1
Control Byte
ACK bit (2)
Read Data bits
ACK bit (3, 4)
Stop bit (5)
D D D D D D D D
D D D D D D D D
A 15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A
P
Read bits
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: Master Device is responsible for A/A signal. If a A signal occurs, the MCP47FVBXX will abort this transfer and release the bus.
3: The Master Device will Not Acknowledge, and the MCP47FVBXX will release the bus so the Master
Device can generate a Stop or Repeated Start condition.
4: At the falling edge of the SCL pin for the Read command ACK bit, the MCP47FVBXX device updates
the value of the specified device register.
5: This command sequence does not need to terminate (using the Stop bit), and the Read command can
be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”).
FIGURE 7-5:
DS20005405A-page 56
Read Command - Last Memory Address Accessed.
2015 Microchip Technology Inc.
MCP47FVBXX
Write 1 Byte Command
S Slave Address
Master
R A
/ C
W K Command
A
C
K
S S S S S S S S 0 1 A A A A A C C x 1
A A A A A A A
D D D D D 1 0
6 5 4 3 2 1 0
4 3 2 1 0
S
r Slave Address
R A
/ C
W K Data Byte
A
C
K Data Byte
A
C
K P
S S S S S S S S 1 1 D D D D D D D D 1 D D D D D D D D 1 P
r A A A A A A A
1 1 1 1 1 1 0 0
0 0 0 0 0 0 0 0
6 5 4 3 2 1 0
5 4 3 2 1 0 9 8
7 6 5 4 3 2 1 0
Master (Continued)
Ex.1 (No Command Error)
Master
S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1
MCP47FVBXXA0
0
0
I2C™ Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0
Master (Continued)
S 0 0 0 0 1 0 0 1 1
MCP47FVBXXA0 (Continued)
I2C Bus (Continued)
1
1 P
0 d d d d d d d d 0 d d d d d d d d 0
S 0 0 0 0 0 0 0 1 0 d d d d d d d d 0 d d d d d d d d 0 P
Ex.2 (With Command Error)
Master
S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1
MCP47FVBXXA0
I2C Bus
0
1
S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1
Master (Continued)
S 1 1 0 0 0 0 0 1 1
MCP47FVBXXA0 (Continued)
I2C Bus (Continued)
1
1 P
0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1
S 1 1 0 0 0 0 0 1 0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1 P
Note 1: Once a Command Error has occurred (Example 2), the MCP47FVBXX will NACK until a Start condition
occurs.
2: For Command Error case (Example 2), the data read is from the register of the last valid address loaded
into the device.
FIGURE 7-6:
I2C ACK/NACK Behavior (Read Command Example).
2015 Microchip Technology Inc.
DS20005405A-page 57
MCP47FVBXX
Start bit
I2C™ Slave Address
ACK bit (1)
Write bit
(1)
Repeated Start bit
ACK bit
Memory Address Command
SA SA SA SA SA SA SA
S 6 5 4 3 2 1 0 0
A
AD AD AD AD AD
4 3 2 1 0 1
1 X A Sr
Read Command
Control Byte
ACK bit (5)
I2C Slave Address
Read bit
ACK bit (1)
SA SA SA SA SA SA SA
6 5 4 3 2 1 0 1
(4)
ACK bit
Read Data bits
D D D D D D D D
D D D D D D D D
A 15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A
Control Byte
Read bits
ACK bit (5)
ACK bit (4) Read Data bits
D D D D D D D D
D D D D D D D D
15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A
Read bits
ACK bit (4) Read Data bits
ACK bit (5)
Stop bit (2, 3)
D D D D D D D D
D D D D D D D D
15 14 13 12 11 10 09 08 A 07 06 05 04 03 02 01 00 A
P
Read bits
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: At the falling edge of the SCL pin for the Read command ACK bit, the MCP47FVBXX device updates
the value of the specified device register.
3: This command sequence does not need to terminate (using the Stop bit), and the Read command can
be repeated (see continuous read format, Section 7.2.2 “Continuous Reads”).
4: Master Device is responsible for A / A signal. If a A signal occurs, the MCP47FVBXX will abort this
transfer and release the bus.
5: The Master Device will Not Acknowledge, and the MCP47FVBXX will release the bus so the Master
Device can generate a Stop or Repeated Start condition.
FIGURE 7-7:
DS20005405A-page 58
Continuous Read Command Of Specified Address.
2015 Microchip Technology Inc.
MCP47FVBXX
7.3
The other two I2C Specification command codes (04h
and 00h) are not supported, and therefore those
commands are Not Acknowledged.
General Call Commands
The MCP47FVBXX acknowledges the General Call
Address command (00h in the first byte). General Call
commands can be used to communicate to all devices
on the I2C bus (at the same time) that understand the
General Call command. The meaning of the general
call address is always specified in the second byte (see
Figure 7-8).
If these 7-bit commands conflict with other I2C devices
on the bus, then the customer will need two I2C buses
and ensure that the devices are on the correct bus for
their desired application functionality.
Note:
If the second byte has a ‘1’ in the LSb, the specification
intends this to indicate a “Hardware General Call”. The
MCP47FVBXX will ignore this byte and all following
bytes (and A), until a Stop bit (P) is encountered.
The MCP47FVBXX devices support the following I2C
General Call commands:
Refer to the NXP specification #UM10204,
Rev. 03 19 June 2007 document for more
details on the General Call specifications.
The I2C specification does not allow
‘00000000’ (00h) in the second byte.
• General Call Reset (06h)
• General Call Wake-up (0Ah)
The General Call Reset command format is specified
by the I2C Specification. The General Call Wake-Up
command is a Microchip-defined format. The General
Call Wake-Up command will have all devices wake-up
(that is, exit the Power-Down mode).
Second Byte
S 0 0
0
0
0 0
0
0 A X X X X X
General Call Address
X
X
0
A P
“7-bit Command”
Reserved 7-bit Commands (By I2C™ Specification - NXP specification # UM10204, Rev. 03 19 June 2007)
‘0000 011’b - Reset and write programmable part of slave address by hardware.
‘0000 010’b - Write programmable part of slave address by hardware (Not Implemented).
‘0000 000’b - NOT Allowed
MCP47FVBXX 7-bit Commands
‘0000 011’b - Device Reset (subset of I2C Reserved Command).
‘0000 101’b - DAC Output Exit Power-Down State (PD1:PD0 = ‘00’).
The Following is a “Hardware General Call” Format
Second Byte
S 0
0 0
0
0
0 0
General Call Address
FIGURE 7-8:
0
A X X X X X
“7-bit Command”
X
n occurrences of (Data + A)
X
1
A X X X X X X X X A P
This indicates a “Hardware General Call”
MCP47FVBXX will ignore this byte and
all following bytes (and A), until
a Stop bit (P) is encountered.
General Call Formats.
2015 Microchip Technology Inc.
DS20005405A-page 59
MCP47FVBXX
7.3.1
GENERAL CALL RESET
7.3.2
2
The I C General Call Reset command forces a reset
event. This is similar to the Power-on Reset, except
that the reset delay timer is not started. This command
allows multiple MCP47FVBXX devices to be reset
synchronously.
The I C General Call Wake-up command forces the
device to exit from it’s Power-Down state (forces the
PDxB:PDxA bits to ‘00’). This command allows multiple
MCP47FVBXX devices to wake-up synchronously.
The device performs General Call Wake-up if the
second byte (after the General Call Address) is
“00001010” (0Ah). At the acknowledgment of this
byte, the device will perform the following task:
The device performs General Call Reset if the second
byte is “00000110” (06h). At the acknowledgment of
this byte, the device will abort the current conversion
and perform the following tasks:
• The device’s volatile power-down bits
(PDxB:PDxA) are forced to ‘00’.
• Internal Reset similar to a Power-on Reset (POR).
The device default settings are loaded into the
DAC registers and analog output is available
immediately (following the Acknowledgment
pulse).
• The VOUT will be available immediately, but after a
short time delay following the Acknowledgment
pulse. The VOUT value is determined by the
EEPROM contents.
Start bit
GENERAL CALL WAKE-UP
2
ACK bit (1, 2)
Stop bit (3)
Write bit
ACK bit (1)
General Call Address
S 0
0
0
0
0
0
0 A 0
0
0
0
0
0
1 1
0
A P
General Call Reset Command
Control Byte
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: At the falling edge of the SCL pin for the General Call Wake-Up command ACK bit, the
MCP47FVBXX device is reset.
3: This command sequence does not need to terminate (using the Stop bit), and the General
Call Wake-Up command can be repeated, or the General Call Reset command can be sent.
FIGURE 7-9:
General Call Reset Command.
Start bit
ACK bit (1, 2)
Stop bit (3)
Write bit
ACK bit (1)
General Call Address
S 0
0
0
0
0
0
Control Byte
0
0 A 0
0
0
0
1
0 1
0
A P
General Call Wake-Up Command
Note 1: The Acknowledge bit is generated by the MCP47FVBXX.
2: At the falling edge of the SCL pin for the General Call Wake-Up command ACK bit, the volatile
power-down bits (PDxB:PDxA) are forced to ‘00’.
3: This command sequence does not need to terminate (using the Stop bit), and the General
Call Wake-Up command can be repeated, or the General Call Reset command can be sent.
FIGURE 7-10:
DS20005405A-page 60
General Call Wake-Up Command.
2015 Microchip Technology Inc.
MCP47FVBXX
TYPICAL APPLICATIONS
The MCP47FVBXX family of devices are general purpose, single/dual-channel voltage output DACs for various applications where a precision operation with
low-power is needed.
Applications generally suited for the devices are:
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Portable Instrumentation (Battery-Powered)
Motor Control
8.1
Connecting to I2C BUS using
Pull-Up Resistors
The SCL and SDA pins of the MCP47FVBXX devices
are open-drain configurations. These pins require a
pull-up resistor, as shown in Figure 8-2.
The pull-up resistor values (R1 and R2) for SCL and
SDA pins depend on the operating speed (standard,
fast and high-speed) and loading capacitance of the I2C
bus line. A higher value of the pull-up resistor consumes
less power, but increases the signal transition time
(higher RC time constant) on the bus line. Therefore, it
can limit the bus operating speed. The lower resistor
value, on the other hand, consumes higher power, but
allows higher operating speed. If the bus line has higher
capacitance due to long metal traces or multiple device
connections to the bus line, a smaller pull-up resistor is
needed to compensate the long RC time constant. The
pull-up resistor is typically chosen between 1 k and
10 kranges for Standard and Fast modes, and less
than 1 kfor High-Speed mode.
2015 Microchip Technology Inc.
8.1.1
DEVICE CONNECTION TEST
The user can test the presence of the device on the I2C
bus line using a simple I2C command. This test can be
achieved by checking an acknowledge response from
the device after sending a Read or Write command.
Figure 8-1 shows an example with a Read command.
The steps are:
1.
2.
3.
Set the R/W bit “High” in the device’s address byte.
Check the ACK bit of the address byte.
If the device acknowledges (ACK = 0) the
command, then the device is connected.
Otherwise, it is not connected.
Send Stop bit.
Address Byte
SCL
1 2 3 4 5 6 7 8
SDA
A6 A5 A4 A3 A2 A1 A0 1
Start
Bit
9
ACK
8.0
Stop
Bit
Address bits
R/W
Device
Response
FIGURE 8-1:
I2C Bus Connection Test.
DS20005405A-page 61
MCP47FVBXX
8.2
Power Supply Considerations
The power source should be as clean as possible. The
power supply to the device is also used for the DAC
voltage reference internally if the internal VDD is
selected as the resistor ladder’s reference voltage
(VRxB:VRxA = ‘00’).
Any noise induced on the VDD line can affect the DAC
performance. Typical applications will require a bypass
capacitor in order to filter out high-frequency noise on
the VDD line. The noise can be induced onto the power
supply’s traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of
these noise sources on signal integrity. Figure 8-2
shows an example of using two bypass capacitors (a
10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) in parallel on the VDD line. These capacitors should
be placed as close to the VDD pin as possible (within
4 mm). If the application circuit has separate digital and
analog power supplies, the VDD and VSS pins of the
device should reside on the analog plane.
VDD
R1
VDD
C1
REF
2
8 SDA
7 SCL
VOUT0
3
6 LAT/HVC
4
5 V
SS
C2 V
Analog
Output
VOUT1
C3
1
R2
To MCU
MCP47FVBX2
C4
Optional
(a) Circuit when VDD is selected as reference
(Note: VDD is connected to the reference circuit internally.)
VDD
C1
C2
R1
VDD
VREF
C5
1
VREF 2
VOUT0
3
VOUT1
4
C6
Optional
Analog
Output
8 SDA
7 SCL
R2
To MCU
6 LAT/HVC
5
VSS
MCP47FVBX2
C3
C4
Optional
(b) Circuit when external reference is used.
R1 and R2 are I2C™ pull-up resistors:
R1 and R2:
5 k - 10 k for fSCL = 100 kHz to 400 kHz
~700 for fSCL = 3.4 MHz
C1 :
0.1 µF capacitor
C2 :
10 µF capacitor
Tantalum
C3 :
~ 0.1 µF
Optional to reduce noise
in VOUT pin.
C4 :
0.1 µF capacitor
Ceramic
C5 :
10 µF capacitor
Tantalum
C6 :
0.1 µF capacitor
Ceramic
FIGURE 8-2:
DS20005405A-page 62
Ceramic
Example Circuit.
2015 Microchip Technology Inc.
MCP47FVBXX
8.3
Application Examples
The MCP47FVBXX devices are rail-to-rail output DACs
designed to operate with a VDD range of 2.7V to 5.5V.
The internal output op amplifier is robust enough to
drive common, small-signal loads directly, thus
eliminating the cost and size of external buffers for
most applications. The user can use the gain of 1 or 2
of the output op amplifier by setting the Configuration
register bits. Internal VDD can be used as the reference
or use an external reference. Various user options and
easy-to-use features make the devices suitable for various modern DAC applications.
Application examples include:
•
•
•
•
•
•
•
•
•
•
Decreasing Output Step Size
Building a “Window” DAC
Bipolar Operation
Selectable Gain and Offset Bipolar Voltage Output
Designing a Double-Precision DAC
Building Programmable Current Source
Serial Interface Communication Times
Software I2C Interface Reset Sequence
Power Supply Considerations
Layout Considerations
8.3.1
8.3.1.1
Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve small step size are to use
a lower VREF pin voltage or a voltage divider on the
DAC’s output.
Using an external voltage reference (VREF) is an option
if the external reference is available with the desired
output voltage range. However, when using a low-voltage reference voltage, occasionally the noise floor
causes a SNR error that is intolerable. Using a voltage
divider method is another option, and provides some
advantages when external voltage reference needs to
be very low, or when the desired output voltage is not
available. In this case, a larger value reference voltage
is used, while two resistors scale the output range
down to the precise desired level.
Figure 8-3 illustrates this concept. A bypass capacitor
on the output of the voltage divider plays a critical
function in attenuating the output noise of the DAC and
the induced noise from the environment.
VDD
DC SET POINT OR CALIBRATION
A common application for the devices is a
digitally-controlled set point and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP47FVB2X provides 4096 output
steps. If voltage reference is 4.096V (where Gx = ‘0’),
the LSb size is 1 mV. If a smaller output step size is
desired, a lower external voltage reference is needed.
Optional
VREF VDD
RSENSE
VCC+
R1
MCP47FVBXX
VTRIP Comp.
VO
C1
R2
I2C™
VOUT
VCC–
2-wire
FIGURE 8-3:
Example Circuit Of Set Point
or Threshold Calibration.
EQUATION 8-1:
VOUT AND VTRIP
CALCULATIONS
VOUT = VREF • G •
DAC Register Value
2N
R2
V trip = V OUT --------------------
R 1 + R 2
2015 Microchip Technology Inc.
DS20005405A-page 63
MCP47FVBXX
8.3.1.2
Building a “Window” DAC
8.4
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
If the threshold is not near VREF, 2 • VREF, or VSS, then
creating a “window” around the threshold has several
advantages. One simple method to create this “window”
is to use a voltage divider network with a pull-up and
pull-down resistor. Figure 8-4 and Figure 8-6 illustrate
this concept.
Bipolar Operation
Bipolar operation is achievable by utilizing an external
operational amplifier. This configuration is desirable
due to the wide variety and availability of op amps. This
allows a general purpose DAC, with its cost and
availability advantages, to meet almost any desired
output voltage range, power and noise performance.
Figure 8-5 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC's output to a selected
offset. Note that R4 can be tied to VDD instead of VSS if
a higher offset is desired.
Optional
VREF VDD
Optional
VREF VDD
VCC+
RSENSE
R1
MCP47FVBXX
VTRIP Comp.
VOUT
I2C™
2-wire
MCP47FVBXX
VCC+
R3
C1
R2
VCC+
R3
VO
VOUT
I2C™
VOA+
VO
C1
R4
VCC–
2-wire
VCC–
R2
VIN
R1
VCC–
FIGURE 8-4:
DAC.
Single-Supply “Window”
FIGURE 8-5:
Digitally-Controlled Bipolar
Voltage Source Example Circuit.
EQUATION 8-2:
VOUT AND VTRIP
CALCULATIONS
EQUATION 8-3:
VOUT = VREF • G •
DAC Register Value
VOUT = VREF • G •
2N
V OUT R23 + V 23 R1
V TRIP = --------------------------------------------R 1 + R23
Thevenin
Equivalent
VOUT, VOA+, AND VO
CALCULATIONS
VOA+ =
R2R3
R23 = ------------------R2 + R3
VOUT
2N
VOUT • R4
R3 + R4
VO = VOA+ • (1 +
VCC+ R2 + V CC- R 3
V23 = -----------------------------------------------------R 2 + R3
DAC Register Value
R2
R1
) - VDD • (
R2
R1
)
R1
VTRIP
R23
V23
DS20005405A-page 64
2015 Microchip Technology Inc.
MCP47FVBXX
8.5
Selectable Gain and Offset Bipolar
Voltage Output
In some applications, precision digital control of the
output range is desirable. Figure 8-6 illustrates how to
use the DAC devices to achieve this in a bipolar or
single-supply application.
This circuit is typically used for linearizing a sensor
whose slope and offset varies.
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
8.5.1
BIPOLAR DAC EXAMPLE
Optional
VCC+
Optional
VREF VDD
R5
MCP47FVBXX
VO
I2C™
2-wire
The equation can be simplified to:
R2
FIGURE 8-6:
Bipolar Voltage Source with
Selectable Gain and Offset.
EQUATION 8-6:
VOUT, VOA+, AND VO
CALCULATIONS
VOUT = VREF • G •
VOA+ =
DAC Register Value
R3 + R4
EQUATION 8-5:
R4
2
2.05V + 0.5 4.096V
------------------------ = ------------------------------------------------------- = -- R3 + R 4
1.5 4.096V
3
If R4 = 20 k, then R3 = 10 k
R2
R1
) - VIN • (
Offset Adjust
EQUATION 8-7:
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
Step 4: Next, solve for R3 and R4 by setting the
DAC to 4096, knowing that the output
needs to be +2.05V.
2N
VOUT • R4 + VCC- • R5
VO = VOA+ • ( 1 +
R2
1
------ = --R1
2
VCC–
C1 = 0.1 µF
EQUATION 8-4:
– R2
– 2.05
--------- = ----------------R1
4.096V
C1
R4
R1
Step 2: Calculate the resolution needed:
Step 3: The amplifier gain (R2/R1), multiplied by
full-scale VOUT (4.096V), must be equal to
the desired minimum output to achieve bipolar operation. Since any gain can be realized
by choosing resistor values (R1 + R2), the
VREF value must be selected first. If a VREF
of 4.096V is used, solve for the amplifier’s
gain by setting the DAC to 0, knowing that
the output needs to be -2.05V.
VOUT
VIN
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V.
Since 212 = 4096, 12-bit resolution is desired.
VOA+
VCC–
An output step size of 1 mV, with an output range of
±2.05V, is desired for a particular application.
4.1V/1 mV = 4100
VCC+
R3
Thevenin
Equivalent
R2
R1
)
Gain Adjust
BIPOLAR “WINDOW” DAC
USING R4 AND R5
V CC+ R 4 + VCC- R5
V 45 = --------------------------------------------R 4 + R5
VOUT R 45 + V 45 R 3
VIN+ = --------------------------------------------R3 + R 45
R4R5
R45 = ------------------R4 + R5
R2
R2
V O = V IN+ 1 + ------ – V A ------
R1
R 1
Offset Adjust Gain Adjust
2015 Microchip Technology Inc.
DS20005405A-page 65
MCP47FVBXX
8.6
Designing a Double-Precision
DAC
8.7
Building Programmable Current
Source
Figure 8-7 shows an example design of a single-supply
voltage output capable of up to 24-bit resolution. This
requires two 12-bit DACs. This design is simply a
voltage divider with a buffered output.
Figure 8-8 shows an example of building a
programmable current source using a voltage follower.
The current sensor resistor is used to convert the DAC
voltage output into a digitally-selectable current source.
As an example, if a similar application to the one
developed in Section 8.5.1 “Bipolar DAC Example”
required a resolution of 1 µV instead of 1 mV, and a
range of 0V to 4.1V, then 12-bit resolution would not be
adequate.
The smaller RSENSE is, the less power dissipated
across it. However, this also reduces the resolution that
the current can be controlled.
Step 1: Calculate the resolution needed:
VDD
(or VREF)
Optional
4.1V/1 µV = 4.1 x 106.
Since 222 = 4.2 x 106, 22-bit resolution is
desired. Since DNL = ±1.0 LSb, this design
can be attempted with the 12-bit DAC.
Step 2: Since DAC1’s VOUT1 has a resolution of
1 mV, its output only needs to be “pulled”
1/1000 to meet the 1 µV target. Dividing
VOUT0 by 1000 would allow the application
to compensate for DAC1’s DNL error.
Step 3: If R2 is 100, then R1 needs to be 100 k.
Step 4: The resulting transfer function is shown in
the equation of Example 8-8.
VREF
VDD
VOUT
Load
VCC+
IL
MCP47FVBXX
Ib
VCC–
I2C™
2-wire
IL
Ib = ----
RSENSE
V OUT
I L = --------------- ------------R sense + 1
where Common-Emitter Current Gain
Optional
VDD
VREF
MCP47FVBX2
(DAC0)
I2C™
2-wire
FIGURE 8-8:
Source.
VOUT0
R1
Digitally-Controlled Current
VCC+
VOUT
Optional
VREF
VDD
0.1 µF
R2
MCP47FVBX2
(DAC1)
VCC–
VOUT1
I2C
2-wire
FIGURE 8-7:
Simple Double Precision
DAC using MCP47FVBX2.
EQUATION 8-8:
VOUT =
VOUT CALCULATION
VOUT0 * R2 + VOUT1 * R1
R1 + R2
Where:
VOUT0 = (VREF G DAC0 register Value)/4096
VOUT1 = (VREF G DAC1 register Value)/4096
Gx = Selected Op Amp Gain
DS20005405A-page 66
2015 Microchip Technology Inc.
MCP47FVBXX
8.8
Serial Interface Communication
Times
Table 8-1 shows time/frequency of the supported
operations of the I2C serial interface for the different
serial interface operational frequencies. This, along
with the VOUT output performance (such as slew rate),
would be used to determine your application’s volatile
DAC register update rate.
TABLE 8-1:
SERIAL INTERFACE TIMES / FREQUENCIES
Command
# of Bit
Clocks
Code
Operation
HV
Mode
C
1
C
0
0
0
(2)
Single
0
0
(2)
Continuous
1
1
(2)
Random
1
1
(2)
Continuous
1
1
(2)
General Call Reset
Command
— —
General Call Wake-up
Command
— —
Write Command
(Normal and HighVoltage)(5)
Read Command
(Normal and HighVoltage)(5)
Note 1:
2:
3:
4:
5:
(1)
Data Update Rate
(8-bit/10-bit/12-bit)
(Data Words/Second)
Comments
100
kHz
400 kHz
3.4 MHz(4)
38
2,632
10,526
89,474
27n +
11
3,559
14,235
120,996
48
2,083
8,333
70,833
18n +
11
4,762
19,048
161,905
Last
Address
29
3,448
13,793
117,241
(2)
Single
20
5,000
20,000
170,000
Note 3
(2)
Single
20
5,000
20,000
170,000
Note 3
For 10 data words
For 10 data words
“n” indicates the number of times the command operation is to be repeated.
This command can be either normal voltage or high voltage.
Determined by General Call command byte after the I2C General Call address.
There is a minimal overhead to enter into 3.4 MHz mode.
High-Voltage commands are supported for serial interface compatibility with the MCP47FEBXX devices.
2015 Microchip Technology Inc.
DS20005405A-page 67
MCP47FVBXX
This sequence does not affect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
This technique is documented in AN1028.
At times, it may become necessary to perform a
Software Reset Sequence to ensure the MCP47FVBXX
device is in a correct and known I2C interface state. This
technique only resets the I2C state machine.
This is useful if the MCP47FVBXX device powers-up in
an incorrect state (due to excessive bus noise, etc), or
if the master device is reset during communication.
Figure 8-9 shows the communication sequence to
software reset the device.
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
S
P
Nine bits of ‘1’
Start bit
Stop bit
Start bit
FIGURE 8-9:
Format.
Software Reset Sequence
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
master device. In this mode, the device is monitoring
the data bus in Receive mode and can detect if the
Start bit forces an internal Reset.
8.10
Design Considerations
In the design of a system with the MCP47FVBXX
devices, the following considerations should be taken
into account:
• Power Supply Considerations
• Layout Considerations
8.10.1
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-10 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as close
(within 4 mm) to the device power pin (VDD) as possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP47FVBXX is driving an A bit
on the I2C bus, or is in Output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP47FVBXX holding the
bus low. By sending out nine ‘1’ bits, it is ensured that
the device will see an A bit (the master device does not
drive the I2C bus low to acknowledge the data sent by
the MCP47FVBXX), which also forces the
MCP47FVBXX to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the master
device was reset while sending a Write command to the
MCP47FVBXX, AND then as the master device returns
to normal operation and issues a Start condition, while
the MCP47FVBXX is issuing an acknowledge. In this
case, if the 2nd Start bit is not sent (and the Stop bit was
sent) the MCP47FVBXX could initiate a write cycle.
Note:
The potential for this erroneous write
ONLY occurs if the master device is reset
while sending a Write command to the
MCP47FVBxx.
The Stop bit terminates the current I2C bus activity. The
MCP47FVBXX waits to detect the next Start condition.
DS20005405A-page 68
POWER SUPPLY
CONSIDERATIONS
VDD
0.1 µF
VDD
0.1 µF
VREF
VOUT
VSS
FIGURE 8-10:
Connections.
SCL
SDA
PIC® Microcontroller
Note:
MCP47FVBXX
Software I2C Interface Reset
Sequence
8.9
VSS
Typical Microcontroller
2015 Microchip Technology Inc.
MCP47FVBXX
LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
• Noise
• PCB Area Requirements
8.10.2.1
8.10.2.2
PACKAGE FOOTPRINT(1)
TABLE 8-2:
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP47FVBXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the typical package
dimensions and area for the different package options.
Package
Pins
8.10.2
Type
Package Footprint
Code
Dimensions
(mm)
Area (mm2)
Length Width
8
TSSOP
Note 1:
ST
3.00
4.40
13.20
Does not include recommended land
pattern dimensions. Dimensions are
typical values.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors should be terminated to the
analog ground plane.
Note:
Breadboards and wire-wrapped boards
are not recommended.
2015 Microchip Technology Inc.
DS20005405A-page 69
MCP47FVBXX
NOTES:
DS20005405A-page 70
2015 Microchip Technology Inc.
MCP47FVBXX
9.0
DEVELOPMENT SUPPORT
9.2
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-2 lists
some of these documents.
Development support can be classified into two groups.
These are:
• Development Tools
• Technical Documentation
9.1
Technical Documentation
Development Tools
Several development tools are available to assist in your
design and evaluation of the MCP47FVBXX devices.
The currently available tools are shown in Table 9-1.
Figure 9-1 shows how the TSSOP20EV bond-out PCB
can be populated to easily evaluate the MCP47FVBXX
devices. The 8-pin and 20-pin TSSOP packages have
the same pin pitch (0.65 mm BSC) and package width
(4.40 mm typ.), and the 8-pin TSSOP package can be
placed on the 20-pin TSSOP footprint. Device evaluation can use the PICkit™ Serial Analyzer to control the
DAC output registers and state of the configuration,
control and status register.
The TSSOP20EV boards may be purchased directly
from the Microchip web site at www.microchip.com.
TABLE 9-1:
DEVELOPMENT TOOLS (Note 1)
Board Name
Part #
Comment
20-Pin TSSOP and SSOP Evaluation Board
TSSOP20EV
14-Pin SOIC/TSSOP/DIP Evaluation Board
SOIC14EV
SOIC-8 Evaluation Board
SOIC8EV
Note 1:
Most Flexible option - Recommended Bond-out PCB
Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.
TABLE 9-2:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1326
Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications
DS01326
—
Signal Chain Design Guide
DS21825
—
Analog Solutions for Automotive Applications Design Guide
DS01005
2015 Microchip Technology Inc.
DS20005405A-page 71
MCP47FVBXX
MCP47FVBXX-A0E/ST
installed in U3 (bottom 8 pins of TSSOP-20 footprint)
Connected to
Digital Ground
(DGND) Plane
Connected to
Digital Power (VL) Plane
47FVB
1.0 µF
VDD
0
4.7k
4.7k
VREF
NC/VOUT1
0
Two blue wire jumpers to connect
PICkit™ Serial interface (I2C™) to device pins
DS20005405A-page 72
SCL
LAT/HVC
VOUT0
FIGURE 9-1:
SDA
VSS
1x6 male header, with 90° right angle
MCP47FVBXX Evaluation Board Circuit Using TSSOP20EV.
2015 Microchip Technology Inc.
MCP47FVBXX
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
8-Lead TSSOP (4.4 mm)
Example
AAAC
E449
256
XYWW
Device Number
Code
Device Number
Code
MCP47FVB01A0-E/ST
AAAA
MCP47FVB12A0-E/ST
AAAE
MCP47FVB01A0T-E/ST
AAAA
MCP47FVB12A0T-E/ST
AAAE
MCP47FVB01A1-E/ST
AABN
MCP47FVB12A1-E/ST
AACA
MCP47FVB01A1T-E/ST
AABN
MCP47FVB12A1T-E/ST
AACA
MCP47FVB01A2-E/ST
AABP
MCP47FVB12A2-E/ST
AACB
MCP47FVB01A2T-E/ST
AABP
MCP47FVB12A2T-E/ST
AACB
MCP47FVB01A3-E/ST
AABQ
MCP47FVB12A3-E/ST
AACC
MCP47FVB01A3T-E/ST
AABQ
MCP47FVB12A3T-E/ST
AACC
MCP47FVB02A0-E/ST
AAAD
MCP47FVB21A0-E/ST
AAAC
MCP47FVB02A0T-E/ST
AAAD
MCP47FVB21A0T-E/ST
AAAC
MCP47FVB02A1-E/ST
AABX
MCP47FVB21A1-E/ST
AABU
MCP47FVB02A1T-E/ST
AABX
MCP47FVB21A1T-E/ST
AABU
MCP47FVB02A2-E/ST
AABY
MCP47FVB21A2-E/ST
AABV
MCP47FVB02A2T-E/ST
AABY
MCP47FVB21A2T-E/ST
AABV
MCP47FVB02A3-E/ST
AABZ
MCP47FVB21A3-E/ST
AABW
MCP47FVB02A3T-E/ST
AABZ
MCP47FVB21A3T-E/ST
AABW
MCP47FVB11A0-E/ST
AAAB
MCP47FVB22A0-E/ST
AAAF
MCP47FVB11A0T-E/ST
AAAB
MCP47FVB22A0T-E/ST
AAAF
MCP47FVB11A1-E/ST
AABR
MCP47FVB22A1-E/ST
AACD
MCP47FVB11A1T-E/ST
AABR
MCP47FVB22A1T-E/ST
AACD
MCP47FVB11A2-E/ST
AABS
MCP47FVB22A2-E/ST
AACE
MCP47FVB11A2T-E/ST
AABS
MCP47FVB22A2T-E/ST
AACE
MCP47FVB11A3-E/ST
AABT
MCP47FVB22A3-E/ST
AACF
MCP47FVB11A3T-E/ST
AABT
MCP47FVB22A3T-E/ST
AACF
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015 Microchip Technology Inc.
DS20005405A-page 73
MCP47FVBXX
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DS20005405A-page 74
2015 Microchip Technology Inc.
MCP47FVBXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2015 Microchip Technology Inc.
DS20005405A-page 75
MCP47FVBXX
NOTES:
DS20005405A-page 76
2015 Microchip Technology Inc.
MCP47FVBXX
APPENDIX A:
REVISION HISTORY
Revision A (May 2015)
• Original release of this document.
2015 Microchip Technology Inc.
DS20005405A-page 77
MCP47FVBXX
APPENDIX B:
I2C SERIAL
INTERFACE
This I2C interface is a two-wire interface that allows
multiple devices to be connected to this two-wire bus.
Figure B-1 shows a typical I2C interface connection.
Typical I2C™ Interface Connections
Slave
Master
SCL
SCL
SDA
SDA
Other Devices
FIGURE B-1:
B.1
Typical I2C Interface.
Overview
A device that sends data onto the bus is defined as a
transmitter, and a device receiving data is defined as a
receiver. The bus has to be controlled by a master
device which generates the serial clock (SCL), controls
the bus access and generates the Start and Stop
conditions. Devices that do not generate a serial clock
work as slave devices. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
Communication is initiated by the master (microcontroller), which sends the Start bit followed by the
slave address byte. The first byte transmitted is always
the slave address byte, which contains the device
code, the address bits and the R/W bit.
The I2C serial protocol allows multiple master devices
on the I2C bus. This is referred to as “Multi-Master”. For
this, all Master devices must support Multi-Master
operation. In this configuration, all master devices monitor their communication. If they detect that they wish to
transmit a bit that is a logic high but is detected as a
logic low (some other master device driving), they “get
off” the bus. That is, they stop their communication and
continue to listen to determine if the communication is
directed towards them.
The I2C serial protocol only defines the field types, field
lengths, timings, etc. of a frame. The frame content
defines the behavior of the device. For details on the
frame content (commands/data), refer to Section 7.0,
Device Commands.
The I2C serial protocol does define some commands
called “General Call Addressing”, which allows the
master device to communicate to all slave devices on
the I2C bus.
Note:
Refer
to
the
NXP
specification
#UM10204, Rev. 06 4 April 2014
document for more details on the
I2C specifications.
The I2C interface specifies different communication bit
rates. These are referred to as standard, fast or highspeed modes and the MCP47FVBXX supports these
three modes. The clock rates (bit rate) of these modes
are:
• Standard mode: up to 100 kHz (kbit/s)
• Fast mode: up to 400 kHz (kbit/s)
• High-Speed mode (HS mode): up to 3.4 MHz
(Mbit/s)
The I2C protocol supports two addressing modes:
• 7-bit slave addressing
• 10-bit slave addressing (allows more devices on
I2C bus)
Only 7-bit slave addressing will be discussed in this
section.
DS20005405A-page 78
2015 Microchip Technology Inc.
MCP47FVBXX
B.2
B.3.1.2
Signal Descriptions
The I2C interface uses two pins (signals). These are:
• SDA (Serial Data)
• SCL (Serial Clock)
B.2.1
SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the Start (Restart) and Stop conditions, the high or low state of the SDA pin can only
change when the clock signal on the SCL pin is low.
During the high period of the clock, the SDA pin’s value
(high or low) must be stable. Changes in the SDA pin’s
value while the SCL pin is high will be interpreted as a
Start or a Stop condition.
B.2.2
SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin.
Depending on the clock rate mode, the interface will
display different characteristics.
B.3
B.3.1
I2C BIT STATES AND SEQUENCE
I2C
Figure B-8 shows the
transfer sequence, while
Figure B-7 shows the bit definitions. The serial clock is
generated by the master. The following definitions are
used for the bit states:
• Start Bit (S)
• Data Bit
• Acknowledge (A) Bit (driven low) /
No Acknowledge (A) bit (not driven low)
• Repeated Start Bit (Sr)
• Stop Bit (P)
1st Bit
SCL
S
FIGURE B-2:
SCL
Data Bit
FIGURE B-3:
B.3.1.3
2nd Bit
Data Bit.
Acknowledge (A) Bit
The A bit (see Figure B-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically, the slave
device will supply an A response after the Start bit and
8 “data” bits have been received. An A bit has the SDA
signal low, while the A bit has the SDA signal high.
SDA
FIGURE B-4:
D0
A
8
9
Acknowledge Waveform.
Table B-1 shows some of the conditions where the
slave device issues the A or Not A (A).
If an error condition occurs (such as an A instead of A),
then a Start bit must be issued to reset the command
state machine.
Event
The Start bit (see Figure B-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “high”.
2nd Bit
1st Bit
SDA
TABLE B-1:
Start Bit
SDA
The SDA signal may change state while the SCL signal
is low. While the SCL signal is high, the SDA signal
MUST be stable (see Figure B-3).
SCL
I2C Operation
B.3.1.1
Data Bit
MCP47FVBXX A/A
RESPONSES
Acknowledge
Bit Response
General Call
A
Slave Address
valid
A
Slave Address
not valid
A
Bus Collision
N/A
Comment
I2C™ module
Resets, or a “Don’t
Care” if the collision occurs on the
Master’s “Start bit”
Start Bit.
2015 Microchip Technology Inc.
DS20005405A-page 79
MCP47FVBXX
B.3.1.4
B.3.1.5
Repeated Start Bit
The Repeated Start bit (see Figure B-5) indicates the
current master device wishes to continue
communicating with the current slave device without
releasing the I2C bus. The Repeated Start condition is
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
The Stop bit (see Figure B-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “high”.
A Stop bit should reset the I2C interface of the slave
device.
SDA A/A
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “high”.
SCL
P
Note 1: A bus collision during the Repeated Start
condition occurs if:
FIGURE B-6:
Transmit Mode.
•SDA is sampled low when SCL goes
from low to high.
•SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data ‘1’.
B.3.2
Stop Condition Receive or
CLOCK STRETCHING
“Clock Stretching” is something the receiving device
can do, to allow additional time to “respond” to the
“data” that has been received.
B.3.3
ABORTING A TRANSMISSION
If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally
accomplished with a Start or Stop condition. This is done
so that noisy transmissions (usually an extra Start or Stop
condition) are aborted before they corrupt the device.
1st Bit
SDA
Stop Bit
SCL
Sr = Repeated Start
FIGURE B-5:
Waveform.
Repeat Start Condition
SDA
SCL
S
FIGURE B-7:
1st Bit
2nd Bit
3rd Bit
4th Bit
5th Bit
6th Bit
7th Bit
8th Bit
A/A
P
Typical 8-Bit I2C Waveform Format.
SDA
SCL
Start
Condition
FIGURE B-8:
DS20005405A-page 80
Data allowed
to change
Data or
A valid
Stop
Condition
I2C Data States and Bit Sequence.
2015 Microchip Technology Inc.
MCP47FVBXX
B.3.4
B.3.6
SLOPE CONTROL
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmitt Trigger at SDA
and SCL inputs.
B.3.5
DEVICE ADDRESSING
The I2C Slave Address control byte is the first byte
received following the Start condition from the master
device. This byte has 7-bits to specify the Slave
Address and the Read/Write control bit.
Figure B-9 shows the I2C slave address byte format,
which contains the seven address bits and a read/write
(R/W) bit.
Acknowledge bit
Start bit
A6
Read/Write bit
A5
A4
A3
A2
A1
A0 R/W ACK
7-bit Slave Address
Address Byte
FIGURE B-9:
Byte.
I2C Slave Address Control
HS MODE
2
The I C specification requires that a High-Speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by the master sending
a special address byte following the Start bit. This byte
is referred to as the High-Speed Master Mode Code
(HSMMC).
The device can now communicate at up to 3.4 Mbit/s
on SDA and SCL lines. The device will switch out of the
HS mode on the next Stop condition.
The master code is sent as follows:
1.
2.
3.
Start condition (S)
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the High-Speed (HS)
mode master.
No Acknowledge (A)
After switching to High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgments. The master device
can then either issue a Repeated Start bit to address a
different device (at High-Speed) or a Stop bit to return
to Fast/Standard bus speed. After the Stop bit, any
other master device (in a multi-master system) can
arbitrate for the I2C bus.
See Figure B-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the NXP I2C specification.
B.3.6.1
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
B.3.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
F/S-mode
HS-mode
S ‘0 0 0 0 1 X X X’b
A Sr ‘Slave Address’ R/W A
HS Select Byte
Control Byte
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
P = Stop bit (Stop condition terminates HS Mode)
FIGURE B-10:
P
“Data”
A/A
Command/Data Byte(s)
F/S-mode
HS-mode continues
Sr ‘Slave Address’ R/W A
Control Byte
HS Mode Sequence.
2015 Microchip Technology Inc.
DS20005405A-page 81
MCP47FVBXX
B.3.7
GENERAL CALL
For details on the operation of the MCP47FVBXX’s
General Call commands, see Section 7.3, General
Call Commands.
The General Call is a method the “Master” device can
use to communicate with all other “Slave” devices. In a
Multi-Master application, the other Master devices are
operating in Slave mode. The General Call address
has two documented formats. These are shown in
Figure B-11.
Note:
The I2C specification documents three 7-bit command
bytes.
Only one General Call command per issue
of the General Call control byte. Any
additional General Call commands are
ignored and Not Acknowledged.
The I2C specification does not allow ‘00000000’ (00h)
in the second byte. Also ‘00000100’ and ‘00000110’
functionality is defined by the specification. Lastly a
data byte with a ‘1’ in the LSb indicates a “Hardware
General Call”.
Second Byte
S 0 0 0 0
0 0 0 0
General Call Address
A x
x x x
x x
x 0 A P
“7-bit Command”
Reserved 7-bit Commands (By I2C Specification – NXP specification # UM10204, Rev. 06, 4 April 2014)
‘0000 011’b - Reset and write programmable part of slave address by hardware
‘0000 010’b - Write programmable part of slave address by hardware
‘0000 000’b - NOT Allowed
The Following is a “Hardware General Call” format
Second Byte
S 0 0 0 0
0
0
0 0
General Call Address
FIGURE B-11:
DS20005405A-page 82
A x
x x
x x
x x 1
“Master Address”
n occurrences of (Data + A)
A x
x x
x x
x x x
A P
This indicates a “Hardware General Call”
General Call Formats.
2015 Microchip Technology Inc.
MCP47FVBXX
C.1
TERMINOLOGY
Resolution
The resolution is the number of DAC output states that
divide the full-scale range. For the 12-bit DAC, the
resolution is 212, meaning the DAC code ranges from
0 to 4095.
Note:
C.2
When there are 2N resistors in the resistor
ladder and 2N tap points, the full scale
DAC register code is resistor element
(1 LSb) from the source reference voltage
(VDD or VREF).
Least Significant Bit (LSb)
This is the voltage difference between two successive
codes. For a given output voltage range, it is divided by
the resolution of the device (Equation C-1). The range
may be VDD (or VREF) to VSS (ideal), the DAC register
codes across the linear range of the output driver
(Measured 1), or full-scale to zero-scale (Measured 2).
EQUATION C-1:
Ideal
VLSb(IDEAL) =
LSb VOLTAGE
CALCULATION
VDD
or
2N
C.3
Monotonic Operation
Monotonic operation means that the device’s output
voltage (VOUT) increases with every 1 code step (LSb)
increment (from VSS to the DAC’s reference voltage
(VDD or VREF)).
VS64
40h
VS63
3Fh
Wiper Code
APPENDIX C:
3Eh
VS3
03h
VS1
02h
01h
VS0
00h
VW (@ tap)
n=?
VW = VSn + VZS(@ Tap 0)
n=0
Voltage (VW ~= VOUT)
FIGURE C-1:
VW (VOUT).
VREF
2N
Measured 1
VLSb(Measured) =
VOUT(@4000) - VOUT(@100)
(4000 - 100)
Measured 2
VOUT(@FS) - VOUT(@ZS)
VLSb =
2N - 1
2N = 4096 (MCP47FVB2x)
= 1024 (MCP47FVB1x)
= 256 (MCP47FVB0x)
2015 Microchip Technology Inc.
DS20005405A-page 83
MCP47FVBXX
C.4
Full-Scale Error (EFS)
The Full-Scale Error (see Figure C-3) is the error on
the VOUT pin relative to the expected VOUT voltage
(theoretical) for the maximum device DAC register
code (code FFFh for 12-bit, code 3FFh for 10-bit, and
code FFh for 8-bit) (see Equation C-2). The error is
dependent on the resistive load on the VOUT pin (and
where that load is tied to, such as VSS or VDD). For
loads (to VSS) greater than specified, the full-scale
error will be greater.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION C-2:
EFS =
Total Unadjusted Error (ET)
The Total Unadjusted Error (ET) is the difference
between the ideal and measured VOUT voltage. Typically, calibration of the output voltage is implemented
to improve system performance.
The error in bits is determined by the theortical voltage
step size to give an error in LSb.
Equation C-4 shows the Total Unadjusted Error
calculation
EQUATION C-4:
FULL SCALE ERROR
VOUT(@FS) - VIDEAL(@FS)
VLSb(IDEAL)
Where:
EFS is expressed in LSb
VOUT(@FS) is the VOUT voltage when the DAC
register code is at Full scale.
VIDEAL(@FS) is the ideal output voltage when the
DAC register code is at Full scale.
VLSb(IDEAL) is the theoretical voltage step size.
C.5
C.6
Zero-Scale Error (EZS)
The Zero-Scale Error (see Figure C-2) is the difference
between the ideal and measured VOUT voltage with the
DAC register code equal to 000h (Equation C-3). The
error is dependent on the resistive load on the VOUT pin
(and where that load is tied to, such as VSS or VDD). For
loads (to VDD) greater than specified, the zero scale
error will be greater.
ET =
TOTAL UNADJUSTED
ERROR CALCULATION
( VOUT_Actual(@code) - VOUT_Ideal(@Code) )
VLSb(Ideal)
Where:
ET is expressed in LSb.
VOUT_Actual(@code) = The measured DAC
output voltage at the
specified code
VOUT_Ideal(@code) = The calculated DAC
output voltage at the
specified code
( code * VLSb(Ideal) )
VLSb(Ideal) = VREF/# Steps
12-bit = VREF/4096
10-bit = VREF/1024
8-bit = VREF/256
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION C-3:
EZS =
ZERO SCALE ERROR
VOUT(@ZS)
VLSb(IDEAL)
Where:
EFS is expressed in LSb
VOUT(@ZS) is the VOUT voltage when the DAC
register code is at Zero-scale.
VLSb(IDEAL) is the theoretical voltage step size.
DS20005405A-page 84
2015 Microchip Technology Inc.
MCP47FVBXX
C.7
Offset Error (EOS)
The offset error is the delta voltage of the VOUT voltage
from the ideal output voltage at the specified code.
This code is specified where the output amplifier is in
the linear operating range; for the MCP47FVBXX we
specify code 100 (decimal). Offset error does not
include gain error, which is illustrated in Figure C-2.
This error is expressed in mV. Offset error can be negative or positive. The offset error can be calibrated by
software in application circuits.
C.9
Gain Error (EG)
Gain error is a calculation based on the ideal slope
using the voltage boundaries for the linear range of the
output driver (ex code 100 and code 4000) (see
Figure C-3). The Gain error calculation nullifies the
device’s offset error.
The gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. The gain error is usually expressed as percent
of full-scale range (% of FSR) or in LSb. FSR is the
ideal Full Scale voltage of the DAC (see Equation C-5).
Gain Error (EG)
(@ code = 4000)
VREF
Actual
Transfer
Function
VOUT
VOUT
Actual
Transfer
Function
Zero-Scale
Error (EZS)
Ideal Transfer
Function shifted by
Offset Error
(crosses at start of
defined linear range)
Ideal Transfer
Function
0
100
Offset
Error (EOS)
FIGURE C-2:
Error).
C.8
Full-Scale
Error (EFS)
Ideal Transfer
Function
4000
DAC Input Code
Offset Error (Zero Gain
Offset Error Drift (EOSD)
The Offset error drift is the variation in offset error due
to a change in ambient temperature. The offset error
drift is typically expressed in ppm/°C or µV/°C.
0
100
4000
DAC Input Code
4095
FIGURE C-3:
Error Example.
Gain Error and Full-Scale
EQUATION C-5:
EXAMPLE GAIN ERROR
EG =
( VOUT(@4000) - VOS - VOUT_Ideal(@4000) )
VFull-Scale Range
* 100
Where:
EG is expressed in %of Full-Scale Range (FSR)
VOUT(@4000) = The measured DAC
output voltage at the
specified code.
VOUT_Ideal(@4000) = The calculated DAC
output voltage at the
specified code.
( 4000 * VLSb(Ideal) )
VOS = Measured offset voltage.
VFull Scale Range = Expected Full-Scale
output value (such as the
VREF voltage).
C.10
Gain-Error Drift (EGD)
The Gain-error drift is the variation in gain error due to
a change in ambient temperature. The gain error drift is
typically expressed in ppm/°C (of full scale range).
2015 Microchip Technology Inc.
DS20005405A-page 85
MCP47FVBXX
C.11
Integral Nonlinearity (INL)
The Integral Nonlinearity (INL) error is the maximum
deviation of an actual transfer function from an ideal
transfer function (straight line) passing through the
defined end-points of the DAC transfer function (after
offset and gain errors have been removed).
In the MCP47FVBXX, INL is calculated using the
defined end points, DAC code 100 and code 4000. INL
can be expressed as a percentage of Full-Scale Range
(FSR) or in LSb. INL is also called relative accuracy.
Equation C-6 shows how to calculate the INL error in
LSb and Figure C-4 shows an example of INL accuracy.
Positive INL means higher VOUT voltage than ideal.
Negative INL means lower VOUT voltage than ideal.
C.12
Differential Nonlinearity (DNL)
The Differential Nonlinearity (DNL) error (see
Figure C-5) is the measure of step size between codes
in actual transfer function. The ideal step size between
codes is 1 LSb. A DNL error of zero would imply that
every code is exactly 1 LSb wide. If the DNL error is less
than 1 LSb, the DAC guarantees monotonic output and
no missing codes. Equation C-7 shows how to calculate
the DNL error between any two adjacent codes in LSb.
EQUATION C-7:
DNL ERROR
( VOUT(code = n+1) - VOUT(code = n) )
EDNL =
VLSb(Measured)
-1
Where:
EQUATION C-6:
INL ERROR
-V
)
(V
EINL = OUT Calc_Ideal
VLSb(Measured)
Where:
INL is expressed in LSb
VCalc_Ideal = Code * VLSb(Measured) + VOS
VOUT(Code = n) = The measured DAC output
voltage with a given DAC
register code
VLSb(Measured) = For Measured:
(VOUT(4000) - VOUT(100))/3900
VOS = Measured offset voltage
7
DNL = 0.5 LSb
6
5
DNL = 2 LSb
Analog 4
Output
(LSb) 3
7
INL = < -1 LSb
6
INL = - 1 LSb
5
Analog 4
Output
(LSb) 3
DNL is expressed in LSb
VOUT(Code = n) = The measured DAC output
voltage with a given DAC
register code
VLSb(Measured) = For Measured:
(VOUT(4000) - VOUT(100))/3900
2
1
0
000 001 010
INL = 0.5 LSb
011 100 101 110 111
DAC Input Code
Ideal Transfer Function
2
Actual Transfer Function
1
FIGURE C-5:
0
000 001 010
DNL Accuracy.
011 100 101 110 111
DAC Input Code
Ideal Transfer Function
Actual Transfer Function
FIGURE C-4:
DS20005405A-page 86
INL Accuracy.
2015 Microchip Technology Inc.
MCP47FVBXX
C.13
Settling Time
The Settling time is the time delay required for the VOUT
voltage to settle into its new output value. This time is
measured from the start of code transition, to when the
VOUT voltage is within the specified accuracy.
In the MCP47FVBXX, the settling time is a measure of
the time delay until the VOUT voltage reaches within 0.5
LSb of its final value, when the volatile DAC Register
changes from 1/4 to 3/4 of the full-scale range (12-bit
device: 400h to C00h).
C.14
Digital Feed-through
The digital feed-through is the glitch that appears at the
analog output caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec and is measured with a full-scale change
(Example: all 0s to all 1s and vice versa) on the digital
input pins. The digital feed-through is measured when
the DAC is not being written to the output register.
C.16
-3 dB Bandwidth
This is the frequency of the signal at the VREF pin that
causes the voltage at the VOUT pin to fall -3 dB value
from a static value on the VREF pin. The output
decreases due to the RC characteristics of the resistor
ladder and the characteristics of the output buffer.
Power-Supply Sensitivity (PSS)
PSS indicates how the output of the DAC is affected by
changes in the supply voltage. PSS is the ratio of the
change in VOUT to a change in VDD for mid-scale output
of the DAC. The VOUT is measured while the VDD is
varied from 5.5V to 2.7V as a step (VREF voltage held
constant), and expressed in %/%, which is the %
change of the DAC output voltage with respect to the %
change of the VDD voltage.
EQUATION C-8:
Major-Code Transition Glitch
Major-code transition glitch is the impulse energy
injected into the DAC analog output when the code in
the DAC register changes state. It is normally specified
as the area of the glitch in nV-Sec, and is measured
when the digital code is changed by 1 LSb at the major
carry transition (Example: 011...111 to 100...
000, or 100... 000 to 011 ... 111).
C.15
C.17
PSS =
PSS CALCULATION
( VOUT(@5.5V) - VOUT(@2.7V) ) / VOUT(@5.5V) )
(5.5V - 2.7V) / 5.5V
Where:
PSS is expressed in % / %.
VOUT(@5.5V) = The measured DAC output
voltage with VDD = 5.5V
VOUT(@2.7V) = The measured DAC output
voltage with VDD = 2.7V
C.18
Power-Supply Rejection Ratio
(PSRR)
PSRR indicates how the output of the DAC is affected
by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full-scale
output of the DAC. The VOUT is measured while the
VDD is varied +/- 10% (VREF voltage held constant),
and expressed in dB or µV/V.
C.19
VOUT Temperature Coefficient
The VOUT temperature coefficient quantifies the error in
the resistor ladder’s resistance ratio (DAC Register
code value) and Output Buffer due to temperature drift.
C.20
Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end output voltage (Nominal output
voltage VOUT) due to temperature drift. For a DAC, this
error is typically not an issue due to the ratiometric
aspect of the output.
C.21
Noise Spectral Density
Noise Spectral Density is a measurement of the
device’s internally generated random noise, and is
characterized as a spectral density (voltage per √Hz).
It is measured by loading the DAC to the mid-scale
value and measuring the noise at the VOUT pin. It is
measured in nV/√Hz.
2015 Microchip Technology Inc.
DS20005405A-page 87
MCP47FVBXX
NOTES:
DS20005405A-page 88
2015 Microchip Technology Inc.
MCP47FVBXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
PART NO.
XX
Device
Address
Options
Device:
X
Tape and Temperature
Reel
Range
/XX
Package
MCP47FVB01: Single-Channel 8-Bit NV DAC
with External + Internal References
MCP47FVB02:
Dual-Channel 8-Bit NV DAC
with External + Internal References
MCP47FVB11:
Single-Channel 10-Bit NV DAC
with External + Internal References
MCP47FVB12:
Dual-Channel 10-Bit NV DAC
with External + Internal References
MCP47FVB21: Single-Channel 12-Bit NV DAC
with External + Internal References
MCP47FVB22: Dual-Channel 12-Bit NV DAC
with External + Internal References
Address
Options:
A0
=
“1100000” I2C Address
A1
=
“1100001” I2C Address
A2
=
“1100010” I2C Address
A3
=
“1100011” I2C Address
Tape and Reel:
T
Blank
=
=
Tape and Reel
Tube
Temperature
Range:
E
=
-40°C to +125°C
Package:
ST
=
Plastic Thin Shrink Small Outline
package (TSSOP), 8-lead
2015 Microchip Technology Inc.
Examples:
a) MCP47FVB01A0T-E/ST: 8-bit VOUT resolution,
I2C Address “1100000”, Tape
and Reel, extended temp., 8LD
TSSOP package
b) MCP47FVB01A3T-E/ST: 8-bit VOUT resolution,
I2C Address “1100011”, Tape
and Reel, extended temp., 8LD
TSSOP package
a) MCP47FVB11A0-E/ST:
10-bit VOUT resolution,
I2C Address “1100000”, Tube,
extended temp., 8LD TSSOP
package
b) MCP47FVB11A3T-E/ST: 10-bit VOUT resolution, I2C
Address “1100011”, Tape and
Reel, extended temp., 8LD
TSSOP package
a) MCP47FVB21A0T-E/ST: 12-bit VOUT resolution,
I2C Address “1100000”, Tape
and Reel, extended temp.,
8LD TSSOP package
b) MCP47FVB21A3T-E/ST: 12-bit VOUT resolution,
I2C Address “1100011”, Tape
and Reel, extended temp.,
8LD TSSOP package
DS20005405A-page 89
MCP47FVBXX
NOTES:
DS20005405A-page 90
2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63277-365-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005405A-page 91
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Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
01/27/15
DS20005405A-page 92
2015 Microchip Technology Inc.