PDF Data Sheet Rev. A

Blackfin Dual Core
Embedded Processor
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
FEATURES
MEMORY
Dual-core symmetric high-performance Blackfin processor,
up to 500 MHz per core
Each core contains two 16-bit MACs, two 40-bit ALUs, and a
40-bit barrel shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Pipelined Vision Processor provides hardware to process signal and image algorithms used for pre- and co-processing
of video frames in ADAS or other video processing
applications
Accepts a range of supply voltages for I/O operation. See
Operating Conditions on Page 52
Off-chip voltage regulator interface
349-ball BGA package (19 mm × 19 mm), RoHS compliant
Each core contains 148K bytes of L1 SRAM memory (processor core-accessible) with multi-parity bit protection
Up to 256K bytes of L2 SRAM memory with ECC protection
Dynamic memory controller provides 16-bit interface to a
single bank of DDR2 or LPDDR DRAM devices
Static memory controller with asynchronous memory interface that supports 8-bit and 16-bit memories
4 Memory-to-memory DMA streams, 2 of which feature CRC
protection
Flexible booting options from flash, SD EMMC, and SPI memories and from SPI, link port and UART hosts
Memory management unit provides memory protection
SYSTEM CONTROL BLOCKS
PERIPHERALS
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
EVENT
CONTROL
DUAL
WATCHDOG
2× TWI
8× TIMER
1× COUNTER
L2 MEMORY
CORE 0
CORE 1
B
B
148K BYTE
PARITY BIT PROTECTED
L1 SRAM
INSTRUCTION/DATA
148K BYTE
PARITY BIT PROTECTED
L1 SRAM
INSTRUCTION/DATA
2× PWM
32K BYTE
ROM
256K BYTE
ECCPROTECTED
SRAM
3× SPORT
1× ACM
2× UART
112
GP
I/O
EMMC/RSI
DMA SYSTEM
1× CAN
2× EMAC
WITH
2× IEEE 1588
EXTERNAL
BUS
INTERFACES
2× SPI
DYNAMIC
MEMORY
CONTROLLER
STATIC
MEMORY
CONTROLLER
CRC
HARDWARE
FUNCTIONS
LPDDR
DDR2
16
FLASH
SRAM
PIPELINED
VISION PROCESSOR
VIDEO
SUBSYSTEM
4× LINK PORT
3× PPI
PIXEL
COMPOSITOR
16
USB 2.0 HS OTG
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
TABLE OF CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Processor — Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 59
Blackfin Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Processor — Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Processor Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Video Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Processor Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Additional Processor Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADSP-BF60x 349-Ball CSP_BGA Ball Assignments . . . . . . 106
Power and Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
349-Ball CSP_BGA Ball Assignment (Numerical by Ball
Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
System Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Related Signal Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ADSP-BF60x Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . 19
349-Ball CSP_BGA Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . 23
GP I/O Multiplexing for 349-Ball CSP_BGA . . . . . . . . . . . . . . . . . 33
ADSP-BF60x Designer Quick Reference . . . . . . . . . . . . . . . . . . . . . . 37
349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin
Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
349-Ball CSP_BGA Ball Configuration . . . . . . . . . . . . . . . . . . . 110
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
REVISION HISTORY
2/14—Rev. 0 to Rev. A
Added the system clock output specification and additional
peripheral external clocks in Clock Related Operating Conditions on Page 53. These changes affect the following peripheral
timing sections.
Enhanced Parallel Peripheral Interface Timing . . . . . . . . . . . . . . 74
Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Serial Ports—External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Serial Peripheral Interface (SPI) Port—Master Timing . . . . 86
Serial Peripheral Interface (SPI) Port—Slave Timing . . . . . . 88
ADC Controller Module (ACM) Timing . . . . . . . . . . . . . . . . . . . . . 96
Additional revisions include the following.
Corrected S0SEL and S1SEL in Figure 8 Clock Relationships
and Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Revised the dynamic and static current tables CCLK Dynamic
Current per core (mA, with ASF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Static Current—IDD_DEEPSLEEP (mA) . . . . . . . . . . . . . . . . . . . . . 58
Corrected the tWARE parameter in Asynchronous Page Mode
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Corrected the signal names in the following figures:
DDR2 SDRAM Clock and Control Cycle Timing . . . . . . . . . . . 69
DDR2 SDRAM Controller Input AC Timing . . . . . . . . . . . . . . . . 70
Mobile DDR SDRAM Clock and Control Cycle Timing . . . 72
Added Figure 29 and updated Table 42 in Enhanced Parallel
Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Corrected the tHSPIDM, tSDSCIM, tSPICLK, tHDSM, and tSPITDM
specifications in Serial Peripheral Interface (SPI) Port—Master
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Corrected the tHDSPID specification in Serial Peripheral Interface
(SPI) Port—Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Corrected tSRDYSCKM1 in Serial Peripheral Interface (SPI) Port—
SPI_RDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Revised all parameters in Timer Cycle Timing . . . . . . . . . . . . . . . 94
Corrected the timing diagram in ADC Controller Module
(ACM) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Removed TWI signals in footnote 3 in JTAG Test And Emulation Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Added models to Automotive Products . . . . . . . . . . . . . . . . . . . . . 112
Corrected the timing diagram in Bus Request/Bus Grant . 69
Rev. A | Page 2 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
GENERAL DESCRIPTION
The processors offer performance up to 500 MHz, as well as low
static power consumption. Produced with a low-power and lowvoltage design methodology, they provide world-class power
management and performance.
By integrating a rich set of industry-leading system peripherals
and memory (shown in Table 1), Blackfin processors are the
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leadingedge signal processing in one integrated package. These applications span a wide array of markets, from automotive systems to
embedded industrial, instrumentation and power/motor control applications.
Maximum Speed Grade (MHz)2
Maximum SYSCLK (MHz)
ADSP-BF609
ADSP-BF608
ADSP-BF607
ADSP-BF606
1
8
2
3
2
1
3
1
1
2
2
1
4
2
Package Options
1
ADSP-BF609
ADSP-BF608
64K
16K
32K
32K
4K
256K
32K
500
250
349-Ball CSP_BGA
VGA is 640 × 480 pixels per frame. HD is 1280 × 960 pixels per frame.
Maximum speed grade is not available with every possible SYSCLK selection.
BLACKFIN PROCESSOR CORE
As shown in Figure 1, the processor integrates two Blackfin processor cores. Each core, shown in Figure 2, contains two 16-bit
multipliers, two 40-bit accumulators, two 40-bit ALUs, four
video ALUs, and a 40-bit shifter. The computation units process
8-, 16-, or 32-bit data from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
No
1
1
No
N/A
VGA
640
HD
1280
112
400
ADSP-BF607
ADSP-BF606
Processor Feature
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L2 Data SRAM
128K
L2 Boot ROM
2
Table 1. Processor Comparison
Processor Feature
Up/Down/Rotary Counters
Timer/Counters with PWM
3-Phase PWM Units (4-pair)
SPORTs
SPIs
USB OTG
Parallel Peripheral Interface
Removable Storage Interface
CAN
TWI
UART
ADC Control Module (ACM)
Link Ports
Ethernet MAC (IEEE 1588)
Pixel Compositor (PIXC)
Pipelined Vision Processor
(PVP) Video Resolution1
Maximum PVP Line Buffer Size
GPIOs
Table 1. Processor Comparison (Continued)
Memory (bytes, per core)
The ADSP-BF60x processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
Rev. A | Page 3 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADDRESS ARITHMETIC UNIT
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
32
32
P1
P0
TO MEMORY
DA1
DA0
I3
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
16
ALIGN
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
A0
32
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware supports zero-overhead looping.
The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions
with data dependencies.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The data memory holds data,
and a dedicated scratchpad data memory stores stack and local
variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
INSTRUCTION SET DESCRIPTION
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
Rev. A | Page 4 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core
processor resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Control of all asynchronous and synchronous events to the
processor is handled by two subsystems: the Core Event
Controller (CEC) and the System Event Controller (SEC).
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
PROCESSOR INFRASTRUCTURE
The following sections provide information on the primary
infrastructure components of the ADSP-BF609 processor.
DMA Controllers
The processor uses Direct Memory Access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processor can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of processor activity.
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each Memory-tomemory DMA stream uses two channels, where one channel is
the source channel, and the second is the destination channel.
All DMAs can transport data to and from all on-chip and offchip memories. Programs can use two types of DMA transfers,
descriptor-based or register-based. Register-based DMA allows
the processor to directly program DMA control registers to initiate a DMA transfer. On completion, the control registers may
be automatically updated with their original setup values for
continuous transfer. Descriptor-based DMA transfers require a
set of parameters stored within memory to initiate a DMA
sequence. Descriptor-based DMA transfers allow multiple
DMA sequences to be chained together and a DMA channel can
be programmed to automatically set up and start another DMA
transfer after the current sequence completes.
The DMA controller supports the following DMA operations.
• A single linear buffer that stops on completion.
• A linear buffer with negative, positive or zero stride length.
• A circular, auto-refreshing buffer that interrupts when each
buffer becomes full.
• A similar buffer that interrupts on fractional buffers (for
example, 1/2, 1/4).
• 1D DMA – uses a set of identical ping-pong buffers defined
by a linked ring of two-word descriptor sets, each containing a link pointer and an address.
• 1D DMA – uses a linked list of 4 word descriptor sets containing a link pointer, an address, a length, and a
configuration.
• 2D DMA – uses an array of one-word descriptor sets, specifying only the base DMA address.
• 2D DMA – uses a linked list of multi-word descriptor sets,
specifying everything.
CRC Protection
The two CRC protection modules allow system software to periodically calculate the signature of code and/or data in memory,
the content of memory-mapped registers, or communication
message objects. Dedicated hardware circuitry compares the
signature with pre calculated values and triggers appropriate
fault events.
For example, every 100 ms the system software might initiate
the signature calculation of the entire memory contents and
compare these contents with expected, pre calculated values. If a
mismatch occurs, a fault condition can be generated (via the
processor core or the trigger routing unit).
The CRC is a hardware module based on a CRC32 engine that
computes the CRC value of the 32-bit data words presented to
it. Data is provided by the source channel of the memory-tomemory DMA (in memory scan mode) and is optionally forwarded to the destination channel (memory transfer mode).
The main features of the CRC peripheral are:
• Memory scan mode
• Memory transfer mode
• Data verify mode
• Data fill mode
• User-programmable CRC32 polynomial
• Bit/byte mirroring option (endianness)
• Fault/error interrupt mechanisms
• 1D and 2D fill block to initialize array with constants.
• 32-bit CRC signature of a block of a memory or MMR
block.
Rev. A | Page 5 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Event Handling
The processor provides event handling that supports both nesting and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The processor provides support
for five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated either by the software watchdog timer, by the
NMI input signal to the processor, or by software. The
NMI event is frequently used as a power-down indicator to
initiate an orderly shutdown of the system.
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers. For more information, see the
ADSP-BF60x Processor Programmer’s Reference.
System Event Controller (SEC)
The SEC manages the enabling, prioritization, and routing of
events from each system interrupt or fault source. Additionally,
it provides notification and identification of the highest priority
active system interrupt request to each core and routes system
fault sources to its integrated fault management unit.
Trigger Routing Unit (TRU)
The TRU provides system-level sequence control without core
intervention. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers). Slave endpoints can
be configured to respond to triggers in various ways. Common
applications enabled by the TRU include:
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
• Software triggering
• Synchronization of concurrent activities
Pin Interrupts
Every port pin on the processor can request interrupts in either
an edge-sensitive or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO
operation. Six system-level interrupt channels (PINT0–5) are
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin-by-pin basis. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and
interrupt management. This includes masking, identification,
and clearing of requests. These registers also enable access to the
respective pin states and use of the interrupt latches, regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers:
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers – A “write one to modify” mechanism allows any combination of individual
GPIO pins to be modified in a single instruction, without
affecting the level of any other GPIO pins.
• GPIO interrupt mask registers – Allow each individual
GPIO pin to function as an interrupt to the processor.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers – Specify whether individual pins are level- or edge-sensitive and specify—if
edge-sensitive—whether just the rising edge or both the rising and falling edges of the signal are significant.
Pin Multiplexing
The processor supports a flexible multiplexing scheme that multiplexes the GPIO pins with various peripherals. A maximum of
4 peripherals plus GPIO functionality is shared by each GPIO
pin. All GPIO pins have a bypass path feature – that is, when the
output enable and the input enable of a GPIO pin are both
active, the data signal before the pad driver is looped back to the
receive path for the same GPIO pin. For more information, see
GP I/O Multiplexing for 349-Ball CSP_BGA on Page 33.
MEMORY ARCHITECTURE
The processor views memory as a single unified 4G byte address
space, using 32-bit addresses. All resources, including internal
memory, external memory, and I/O control registers, occupy
separate sections of this common address space. The memory
portions of this address space are arranged in a hierarchical
structure to provide a good cost/performance balance of some
very fast, low-latency core-accessible memory as cache or
SRAM, and larger, lower-cost and performance interface-accessible memory systems. See Figure 3 and Figure 4.
Rev. A | Page 6 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Figure 3. ADSP-BF606 Internal/External Memory Map
Rev. A | Page 7 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Figure 4. ADSP-BF607/ADSP-BF608/ADSP-BF609 Internal/External Memory Map
Rev. A | Page 8 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Internal (Core-Accessible) Memory
Booting
The L1 memory system is the highest-performance memory
available to the Blackfin processor cores.
The processor has several mechanisms for automatically loading
internal and external memory after a reset. The boot mode is
defined by the SYS_BMODE input pins dedicated for this purpose. There are two categories of boot modes. In master boot
modes, the processor actively loads data from parallel or serial
memories. In slave boot modes, the processor receives data
from external host devices.
Each core has its own private L1 memory. The modified Harvard architecture supports two concurrent 32-bit data accesses
along with an instruction fetch at full processor speed which
provides high bandwidth processor performance. In each core a
64K-byte block of data memory partners with an 80K-byte
memory block for instruction storage. Each data block is multibanked for efficient data exchange through DMA and can be
configured as SRAM. Alternatively, 16K bytes of each block can
be configured in L1 cache mode. The four-way set-associative
instruction cache and the 2 two-way set-associative data caches
greatly accelerate memory access performance, especially when
accessing external memories.
The L1 memory domain also features a 4K-byte scratchpad
SRAM block which is ideal for storing local variables and the
software stack. All L1 memory is protected by a multi-parity bit
concept, regardless of whether the memory is operating in
SRAM or cache mode.
Outside of the L1 domain, L2 and L3 memories are arranged
using a Von Neumann topology. The L2 memory domain is a
unified instruction and data memory and can hold any mixture
of code and data required by the system design. The L2 memory
domain is accessible by both Blackfin cores through a dedicated
64-bit interface. It operates at SYSCLK frequency.
The processor features up to 256K bytes of L2 SRAM which is
ECC-protected and organized in eight banks. Individual banks
can be made private to any of the cores or the DMA subsystem.
There is also a 32K-byte single-bank ROM in the L2 domain. It
contains boot code and safety functions.
Static Memory Controller (SMC)
The SMC can be programmed to control up to four banks of
external memories or memory-mapped devices, with very flexible timing parameters. Each bank occupies a 64M byte segment
regardless of the size of the device used, so that these banks are
only contiguous if each is fully populated with 64M bytes of
memory.
Dynamic Memory Controller (DMC)
The DMC includes a controller that supports JESD79-2E compatible double data rate (DDR2) SDRAM and JESD209A low
power DDR (LPDDR) SDRAM devices.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. Onchip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core functions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
The boot modes are shown in Table 2. These modes are implemented by the SYS_BMODE bits of the reset configuration
register and are sampled during power-on resets and softwareinitiated resets.
Table 2. Boot Modes
SYS_BMODE Setting
000
001
010
011
100
101
110
111
Boot Mode
No boot/Idle
Memory
RSI0 Master
SPI0 Master
SPI0 Slave
Reserved
LP0 Slave
UART0 Slave
VIDEO SUBSYSTEM
The following sections describe the components of the processor’s video subsystem. These blocks are shown with blue
shading in Figure 1 on Page 1.
Video Interconnect (VID)
The Video Interconnect provides a connectivity matrix that
interconnects the Video Subsystem: three PPIs, the PIXC, and
the PVP. The interconnect uses a protocol to manage data
transfer among these video peripherals.
Pipelined Vision Processor (PVP)
The PVP engine provides hardware implementation of signal
and image processing algorithms that are required for
co-processing and pre-processing of monochrome video frames
in ADAS applications, robotic systems, and other machine
applications.
The PVP works in conjunction with the Blackfin cores. It is
optimized for convolution and wavelet based object detection
and classification, and tracking and verification algorithms. The
PVP has the following processing blocks.
• Four 5 × 5 16-bit convolution blocks optionally followed by
down scaling
• A 16-bit cartesian-to-polar coordinate conversion block
• A pixel edge classifier that supports 1st and 2nd derivative
modes
• An arithmetic unit with 32-bit addition, multiply and
divide
Rev. A | Page 9 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
• A 32-bit threshold block with 16 thresholds, a histogram,
and run-length encoding
• Two 32-bit integral blocks that support regular and diagonal integrals
• An up- and down-scaling unit with independent scaling
ratios for horizontal and vertical components
• Input and output formatters for compatibility with many
data formats, including Bayer input format
The PVP can form a pipe of all the constituent algorithmic
modules and is dynamically reconfigurable to form different
pipeline structures.
The PVP supports the simultaneous processing of up to four
data streams. The memory pipe stream operates on data
received by DMA from any L1, L2, or L3 memory. The three
camera pipe streams operate on a common input received
directly from any of the three PPI inputs. Optionally, the PIXC
can convert color data received by the PPI and forward luma
values to the PVP’s monochrome engine. Each stream has a
dedicated DMA output. This preprocessing concept ensures
careful use of available power and bandwidth budgets and frees
up the processor cores for other tasks.
The PVP provides for direct core MMR access to all control/status registers. Two hardware interrupts interface to the system
event controller. For optimal performance, the PVP allows register programming through its control DMA interface, as well as
outputting selected status registers through the status DMA
interface. This mechanism enables the PVP to automatically
process job lists completely independent of the Blackfin cores.
Pixel Compositor (PIXC)
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decode.
• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is
enabled, endianness can be configured to change the order
of packing/unpacking of bytes/words.
• RGB888 can be converted to RGB666 or RGB565 for transmit modes.
• Various de-interleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data.
• Configurable LCD data enable (DEN) output available on
Frame Sync 3.
PROCESSOR SAFETY FEATURES
The ADSP-BF60x processor has been designed for functional
safety applications. While the level of safety is mainly dominated by the system concept, the following primitives are
provided by the devices to build a robust safety concept.
Dual Core Supervision
The processor has been implemented as dual-core devices to
separate critical tasks to large independency. Software models
support mutual supervision of the cores in symmetrical fashion.
Multi-Parity-Bit-Protected L1 Memories
In the processor’s L1 memory space, whether SRAM or cache,
each word is protected by multiple parity bits to detect the single
event upsets that occur in all RAMs. This applies both to L1
instruction and data memory spaces.
The pixel compositor (PIXC) provides image overlays with
transparent-color support, alpha blending, and color space conversion capabilities for output to TFT LCDs and NTSC/PAL
video encoders. It provides all of the control to allow two data
streams from two separate data buffers to be combined,
blended, and converted into appropriate forms for both LCD
panels and digital video outputs. The main image buffer provides the basic background image, which is presented in the
data stream. The overlay image buffer allows the user to add
multiple foreground text, graphics, or video objects on top of
the main image or video data stream.
ECC-Protected L2 Memories
Parallel Peripheral Interface (PPI)
While parity bit and ECC protection mainly protect against random soft errors in L1 and L2 memory cells, the CRC engines can
be used to protect against systematic errors (pointer errors) and
static content (instruction code) of L1, L2 and even L3 memories (DDR2, LPDDR). The processors feature two CRC engines
which are embedded in the memory-to-memory DMA controllers. CRC check sums can be calculated or compared on the fly
during memory transfers, or one or multiple memory regions
can be continuously scrubbed by single DMA work unit as per
DMA descriptor chain instructions. The CRC engine also protects data loaded during the boot process.
The processor provides up to three parallel peripheral interfaces
(PPIs), supporting data widths up to 24 bits. The PPI supports
direct connection to TFT LCD panels, parallel analog-to-digital
and digital-to-analog converters, video encoders and decoders,
image sensor modules and other general-purpose peripherals.
The following features are supported in the PPI module:
• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, 18 bits, and 24 bits per clock.
• Various framed, non-framed, and general-purpose operating modes. Frame syncs can be generated internally or can
be supplied by an external device.
Error correcting codes (ECC) are used to correct single event
upsets. The L2 memory is protected with a Single Error CorrectDouble Error Detect (SEC-DED) code. By default ECC is
enabled, but it can be disabled on a per-bank basis. Single-bit
errors are transparently corrected. Dual-bit errors can issue a
system event or fault if enabled. ECC protection is fully transparent to the user, even if L2 memory is read or written by 8-bit
or 16-bit entities.
CRC-Protected Memories
Rev. A | Page 10 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Memory Protection
The Blackfin cores feature a memory protection concept, which
grants data and/or instruction accesses from enabled memory
regions only. A supervisor mode vs. user mode programming
model supports dynamically varying access rights. Increased
flexibility in memory page size options supports a simple
method of static memory partitioning.
System Protection
All system resources and L2 memory banks can be controlled by
either the processor cores, memory-to-memory DMA, or the
system debug unit (SDU). A system protection unit (SPU)
enables write accesses to specific resources that are locked to
any of four masters: Core 0, Core 1, Memory DMA, and the System Debug Unit. System protection is enabled in greater
granularity for some modules (L2, SEC and GPIO controllers)
through a global lock concept.
Watchpoint Protection
The primary purpose of watchpoints and hardware breakpoints
is to serve emulator needs. When enabled, they signal an emulator event whenever user-defined system resources are accessed
or a core executes from user-defined addresses. Watchpoint
events can be configured such that they signal the events to the
other Blackfin core or to the fault management unit.
Dual Watchdog
The two on-chip watchdog timers each may supervise one
Blackfin core.
Bandwidth Monitor
All DMA channels that operate in memory-to-memory mode
(Memory DMA, PVP Memory Pipe DMA, PIXC DMA) are
equipped with a bandwidth monitor mechanism. They can signal a system event or fault when transactions tend to starve
because system buses are fully loaded with higher-priority
traffic.
Signal Watchdogs
The eight general-purpose timers feature two new modes to
monitor off-chip signals. The Watchdog Period mode monitors
whether external signals toggle with a period within an expected
range. The Watchdog Width mode monitors whether the pulse
widths of external signals are in an expected range. Both modes
help to detect incorrect undesired toggling (or lack thereof) of
system-level signals.
Up/Down Count Mismatch Detection
The up/down counter can monitor external signal pairs, such as
request/grant strobes. If the edge count mismatch exceeds the
expected range, the up/down counter can flag this to the processor or to the fault management unit.
Fault Management
The fault management unit is part of the system event controller
(SEC). Any system event, whether a dual-bit uncorrectable ECC
error, or any peripheral status interrupt, can be defined as being
a “fault”. Additionally, the system events can be defined as an
interrupt to the cores. If defined as such, the SEC forwards the
event to the fault management unit which may automatically
reset the entire device for reboot, or simply toggle the SYS_
FAULT output pins to signal off-chip hardware. Optionally, the
fault management unit can delay the action taken via a keyed
sequence, to provide a final chance for the Blackfin cores to
resolve the crisis and to prevent the fault action from being
taken.
ADDITIONAL PROCESSOR PERIPHERALS
The processor contains a rich set of peripherals connected to the
core via several high-bandwidth buses, providing flexibility in
system configuration as well as excellent overall system performance (see the block diagram on Page 1). The processors
contain high-speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip
peripherals or external sources, and power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
The following sections describe additional peripherals that were
not described in the previous sections.
Timers
The processor includes several timers which are described in the
following sections.
General-Purpose Timers
There is one GP timer unit and it provides eight general-purpose programmable timers. Each timer has an external pin that
can be configured either as a pulse width modulator (PWM) or
timer output, as an input to clock the timer, or as a mechanism
for measuring pulse widths and periods of external events.
These timers can be synchronized to an external clock input on
the TMRx pins, an external clock TMRCLK input pin, or to the
internal SCLK0.
The timer units can be used in conjunction with the UARTs and
the CAN controller to measure the width of the pulses in the
data stream to provide a software auto-baud detect function for
the respective serial channels.
The timers can generate interrupts to the processor core, providing periodic events for synchronization to either the system
clock or to external signals. Timer events can also trigger other
peripherals via the TRU (for instance, to signal a fault).
Core Timers
Each processor core also has its own dedicated timer. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generating periodic operating
system interrupts.
Watchdog Timers
Each core includes a 32-bit timer, which may be used to implement a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state, via generation of a hardware reset, nonmaskable interrupt
(NMI), or general-purpose interrupt, if the timer expires before
Rev. A | Page 11 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
being reset by software. The programmer initializes the count
value of the timer, enables the appropriate interrupt, then
enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value.
This protects the system from remaining in an unknown state
where software, which would normally reset the timer, has
stopped running due to an external noise condition or software
error.
Serial ports operate in five modes:
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog generated reset.
ACM Interface
3-Phase PWM Units
The Pulse Width Modulator (PWM) module is a flexible and
programmable waveform generator. With minimal CPU intervention the PWM peripheral is capable of generating complex
waveforms for motor control, Pulse Coded Modulation (PCM),
Digital to Analog Conversion (DAC), power switching and
power conversion. The PWM module has 4 PWM pairs capable
of 3-phase PWM generation for source inverters for AC induction and DC brush less motors.
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
• Packed I2S mode
• Left-justified mode
The ADC control module (ACM) provides an interface that
synchronizes the controls between the processor and an analogto-digital converter (ADC). The analog-to-digital conversions
are initiated by the processor, based on external or internal
events.
The ACM allows for flexible scheduling of sampling instants
and provides precise sampling signals to the ADC.
Figure 5 shows how to connect an external ADC to the ACM
and one of the SPORTs.
The two 3-phase PWM generation units each feature:
• 16-bit center-based PWM generation unit
SPORTx
• Programmable PWM pulse width
• Single update mode with option for asymmetric duty
SPT_AD1
SPT_AD0
SPT_CLK
SPT_FS
ADSP-BF60x
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
transition to full ON and full OFF states
ACM
ACM_CLK
ACM_FS
ACM_A[2:0]
ACM_A3
ACM_A4
• Dedicated asynchronous PWM shutdown signal
Link Ports
Four DMA-enabled, 8-bit-wide link ports can connect to the
link ports of other DSPs or processors. Link ports are bidirectional ports having eight data lines, an acknowledge line and a
clock line.
RANGE
SGL/DIFF
A[2:0]
ADC
CS
ADSCLK
DOUTA
DOUTB
Serial Ports (SPORTs)
Three synchronous serial ports that provide an inexpensive
interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices’ AD183x family of audio codecs,
ADCs, and DACs. The serial ports are made up of two data
lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a
dedicated DMA channel.
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configuration, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
SPORT
SELECT
MUX
Figure 5. ADC, ACM, and SPORT Connections
The ACM synchronizes the ADC conversion process, generating the ADC controls, the ADC conversion start signal, and
other signals. The actual data acquisition from the ADC is done
by a peripheral such as a SPORT or a SPI.
The processor interfaces directly to many ADCs without any
glue logic required.
General-Purpose Counters
A 32-bit counter is provided that can operate in general-purpose up/down count modes and can sense 2-bit quadrature or
binary codes as typically emitted by industrial drives or manual
thumbwheels. Count direction is either controlled by a levelsensitive input pin or by two edge detectors.
Rev. A | Page 12 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
A third counter input can provide flexible zero marker support
and can alternatively be used to input the push-button signal of
thumb wheels. All three pins have a programmable debouncing
circuit.
Internal signals forwarded to each general-purpose timer enable
these timers to measure the intervals between count events.
Boundary registers enable auto-zero operation or simple system
warning by interrupts when programmable count values are
exceeded.
Serial Peripheral Interface (SPI) Ports
The processors have two SPI-compatible ports that allow the
processor to communicate with multiple SPI-compatible
devices.
In its simplest mode, the SPI interface uses three pins for transferring data: two data pins (Master Output-Slave Input, MOSI,
and Master Input-Slave Output, MISO) and a clock pin (serial
clock, SPI_CLK). A SPI chip select input pin (SPI_SS) lets other
SPI devices select the processor, and seven SPI chip select output pins (SPI_SEL7–1) let the processor select other SPI devices.
The SPI select pins are reconfigured general-purpose I/O pins.
Using these pins, the SPI port provides a full-duplex, synchronous serial interface, which supports both master/slave modes
and multimaster environments.
In a multi-master or multi-slave SPI system, the MOSI and
MISO data output pins can be configured to behave as open
drain outputs (using the ODM bit) to prevent contention and
possible damage to pin drivers. An external pull-up resistor is
required on both the MOSI and MISO pins when this option is
selected.
To help support the Local Interconnect Network (LIN) protocols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a programmable inter-frame space.
The capabilities of the UARTs are further extended with support for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
TWI Controller Interface
The processors include a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI module is compatible with the
widely used I2C bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitration. The TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
Removable Storage Interface (RSI)
The removable storage interface (RSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), secure digital input/output cards (SDIO). The following list describes the main features of the RSI controller.
• Support for a single MMC, SD memory, SDIO card
When ODM is set and the SPI is configured as a master, the
MOSI pin is three-stated when the data driven out on MOSI is a
logic-high. The MOSI pin is not three-stated when the driven
data is a logic-low. Similarly, when ODM is set and the SPI is
configured as a slave, the MISO pin is three-stated if the data
driven out on MISO is a logic-high.
• Support for 1-bit and 4-bit SD modes
The SPI port’s baud rate and clock phase/polarities are programmable, and it has integrated DMA channels for both
transmit and receive data streams.
• Card interface clock generation from SCLK0
• Support for 1-bit, 4-bit, and 8-bit MMC modes
• Support for eMMC 4.3 embedded NAND flash devices
• A ten-signal external interface with clock, command, and
up to eight data lines
• SDIO interrupt and read wait features
Controller Area Network (CAN)
UART Ports
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.
A CAN controller implements the CAN 2.0B (active) protocol.
This protocol is an asynchronous communications protocol
used in both industrial and automotive control systems. The
CAN protocol is well suited for control applications due to its
capability to communicate reliably over a network. This is
because the protocol incorporates CRC checking, message error
tracking, and fault node confinement.
The CAN controller offers the following features:
• 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit).
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats.
Rev. A | Page 13 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
consumption mode).
• Interrupts, including: TX complete, RX complete, error
and global.
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from a system clock through a programmable divider.
10/100 Ethernet MAC
The processor can directly connect to a network by way of an
embedded fast Ethernet media access controller (MAC) that
supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M
bits/sec) operation. The 10/100 Ethernet MAC peripheral on the
processor is fully compliant to the IEEE 802.3-2002 standard
and it provides programmable features designed to minimize
supervision, bus use, or message processing by the rest of the
processor system.
(PTP_TSYNC). This engine provides hardware assisted time
stamping to improve the accuracy of clock synchronization
between PTP nodes. The main features of the engine are:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 protocol standards
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
• Lock adjustment
• Automatic detection of IPv4 and IPv6 packets, as well as
PTP messages
• Multiple input clock sources (SCLK0, RMII clock, external
clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
USB 2.0 On-the-Go Dual-Role Device Controller
• Flow control
The USB 2.0 OTG dual-role device controller provides a lowcost connectivity solution for the growing adoption of this bus
standard in industrial applications, as well as consumer mobile
devices such as cell phones, digital still cameras, and MP3 players. The USB 2.0 controller allows these devices to transfer data
using a point-to-point USB connection without the need for a
PC host. The module can operate in a traditional USB peripheral-only mode as well as the host mode presented in the Onthe-Go (OTG) supplement to the USB 2.0 specification.
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
The USB clock (USB_CLKIN) is provided through a dedicated
external crystal or crystal oscillator.
Some standard features are:
• Support and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Media access management (in half-duplex operation)
Some advanced features are:
• Automatic checksum computation of IP header and IP
payload fields of RX frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
The USB On-the-Go dual-role device controller includes a
Phase Locked Loop with programmable multipliers to generate
the necessary internal clocking frequency for USB.
POWER AND CLOCK MANAGEMENT
• TX DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
The processor provides four operating modes, each with a different performance/power profile. When configured for a 0 V
internal supply voltage (VDD_INT), the processor enters the hibernate state. Control of clocking to each of the processor
peripherals also reduces power consumption. See Table 5 for a
summary of the power settings for each mode.
• Convenient frame alignment modes
Crystal Oscillator (SYS_XTAL)
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
The processor can be clocked by an external crystal (Figure 6), a
sine wave input, or a buffered, shaped clock derived from an
external clock oscillator. If an external clock is used, it should be
a TTL compatible signal and must not be halted, changed, or
operated below the specified frequency during normal operation. This signal is connected to the processor’s SYS_CLKIN
pin. When an external clock is used, the SYS_XTAL pin must be
left unconnected. Alternatively, because the processor includes
an on-chip oscillator circuit, an external crystal may be used.
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• Advanced power management
• Magic packet detection and wakeup frame filtering
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
processor includes hardware support for IEEE 1588 with an
integrated precision time protocol synchronization engine
For fundamental frequency operation, use the circuit shown in
Figure 6. A parallel-resonant, fundamental frequency, microprocessor grade crystal is connected across the SYS_CLKIN and
XTAL pins. The on-chip resistance between SYS_CLKIN and
the XTAL pin is in the 500 kΩ range. Further parallel resistors
are typically not recommended.
Rev. A | Page 14 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
BLACKFIN
BLACKFIN
TO PLL
CIRCUITRY
TO USB PLL
ȍ2
ȍ
USB_CLKIN
5-12 pf1, 2
SYS_CLKIN
SYS_XTAL
ȍ *
FOR OVERTONE
OPERATION ONLY:
18 pF*
NOTES:
1. CAPACITANCE VALUE SHOWN INCLUDES BOARD PARASITICS
2. VALUES ARE A PRELIMINARY ESTIMATE.
18 pF *
Figure 7. External USB Crystal Connection
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
5(6,67259$/8(6+28/'%(5('8&('72ȍ
Figure 6. External Crystal Connection
The crystal should be chosen so that its rated load capacitance
matches the nominal total capacitance on this node. A series
resistor may be added between the USB_CLKIN pin and the
parallel crystal and capacitor combination, in order to further
reduce the drive level of the crystal.
The two capacitors and the series resistor shown in Figure 6 fine
tune phase and amplitude of the sine frequency. The capacitor
and resistor values shown in Figure 6 are typical values only.
The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB physical
layout. The resistor value depends on the drive level specified by
the crystal manufacturer. The user should verify the customized
values based on careful investigations on multiple devices over
temperature range.
The parallel capacitor and the series resistor shown in Figure 7
fine tune phase and amplitude of the sine frequency. The capacitor and resistor values shown in Figure 7 are typical values
only. The capacitor values are dependent upon the crystal manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on
“EE-168.”
Clock Generation
USB Crystal Oscillator
Writing to the CGU control registers does not affect the behavior of the PLL immediately. Registers are first programmed with
a new value, and the PLL logic executes the changes so that it
transitions smoothly from the current conditions to the new
ones.
The USB can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator. If an external clock is used, it should be a TTL
compatible signal and must not be halted, changed, or operated
below the specified frequency during normal operation. This
signal is connected to the processor’s USB_CLKIN pin. Alternatively, because the processor includes an on-chip oscillator
circuit, an external crystal may be used.
For fundamental frequency operation, use the circuit shown in
Figure 7. A parallel-resonant, fundamental frequency, microprocessor grade crystal is connected between the USB_CLKIN
pin and ground. A load capacitor is placed in parallel with the
crystal. The combined capacitive value of the board trace parasitic, the case capacitance of the crystal (from crystal
manufacturer) and the parallel capacitor in the diagram should
be in the range of 8 pF to 15 pF.
The clock generation unit (CGU) generates all on-chip clocks
and synchronization signals. Multiplication factors are programmed to the PLL to define the PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks (SYSCLK, SCLK0 and
SCLK1), the LPDDR or DDR2 clock (DCLK) and the output
clock (OCLK). This is illustrated in Figure 8 on Page 54.
SYS_CLKIN oscillations start when power is applied to the VDD_
EXT pins. The rising edge of SYS_HWRST can be applied after all
voltage supplies are within specifications (see Operating Conditions on Page 52), and SYS_CLKIN oscillations are stable.
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided-down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the SYS_
CLKIN input. Clock generation faults (for example PLL unlock)
may trigger a reset by hardware. The clocks shown in Table 3
can be outputs from SYS_CLKOUT.
Rev. A | Page 15 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
See Table 5 for a summary of the power settings for each mode.
Table 3. Clock Dividers
Clock Source
CCLK (core clock)
SYSCLK (System clock)
SCLK0 (system clock for PVP, all
peripherals not covered by
SCLK1)
SCLK1 (system clock for SPORTS,
SPI, ACM)
DCLK (LPDDR/DDR2 clock)
OCLK (output clock)
CLKBUF
Divider
By 4
By 2
None
Table 5. Power Settings
None
By 2
Programmable
None, direct from SYS_CLKIN
Core
Power
On
On
On
Off
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
Power Management
As shown in Table 4, the processor supports five different power
domains, which maximizes flexibility while maintaining compliance with industry standards and conventions. There are no
sequencing requirements for the various power domains, but all
domains must be powered according to the appropriate Specifications table for processor operating conditions; even if the
feature/peripheral is not used.
Table 4. Power Domains
Power Domain
All internal logic
DDR2/LPDDR
USB
Thermal diode
All other I/O (includes SYS, JTAG, and Ports pins)
fSYSCLK,
fDCLK,
fSCLK0,
PLL
Mode/State PLL
Bypassed fCCLK
fSCLK1
Full On
Enabled No
Enabled Enabled
Active
Enabled/ Yes
Enabled Enabled
Disabled
Deep Sleep Disabled —
Disabled Disabled
Hibernate
Disabled —
Disabled Disabled
VDD Range
VDD_INT
VDD_DMC
VDD_USB
VDD_TD
VDD_EXT
The dynamic power management feature of the processor
allows the processor’s core clock frequency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor cores and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clocks and system clocks
run at the input clock (SYS_CLKIN) frequency. DMA access is
available to appropriately configured L1 memories.
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core and to all synchronous
peripherals. Asynchronous peripherals may still be running but
cannot access internal resources or external memory.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor cores and to all of the
peripherals. This setting signals the external voltage regulator
supplying the VDD_INT pins to shut off using the SYS_
EXTWAKE signal, which provides the lowest static power dissipation. Any critical information stored internally (for example,
memory contents, register contents, and other information)
must be written to a non-volatile storage device prior to removing power if the processor state is to be preserved.
Since the VDD_EXT pins can still be supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
Reset Control Unit
Reset is the initial state of the whole processor or one of the
cores and is the result of a hardware or software triggered event.
In this state, all control registers are set to their default values
and functional units are idle. Exiting a full system reset starts
with Core-0 only being ready to boot. Exiting a Core-n only
reset starts with this Core-n being ready to boot.
The Reset Control Unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional requirements and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions puts the system into an undefined state or causes
resources to stall. This is particularly important when only one
of the cores is reset (programs must ensure that there is no
pending system activity involving the core that is being reset).
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF60x Blackfin Processor Hardware Reference.
Rev. A | Page 16 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
From a system perspective reset is defined by both the reset target and the reset source as described below.
Target defined:
• Hardware Reset – All functional units are set to their
default states without exception. History is lost.
• System Reset – All functional units except the RCU are set
to their default states.
• Core-n only Reset – Affects Core-n only. The system software should guarantee that the core in reset state is not
accessed by any bus master.
Source defined:
• Hardware Reset – The SYS_HWRST input signal is
asserted active (pulled down).
• System Reset – May be triggered by software (writing to the
RCU_CTL register) or by another functional unit such as
the dynamic power management (DPM) unit (Hibernate)
or any of the system event controller (SEC), trigger routing
unit (TRU), or emulator inputs.
• Core-n-only reset – Triggered by software.
• Trigger request (peripheral).
Voltage Regulation
The processor requires an external voltage regulator to power
the VDD_INT pins. To reduce standby power consumption, the
external voltage regulator can be signaled through SYS_
EXTWAKE to remove power from the processor core. This signal is high-true for power-up and may be connected directly to
the low-true shut-down input of many common regulators.
While in the hibernate state, all external supply pins (VDD_EXT,
VDD_USB, VDD_DMC) can still be powered, eliminating the need for
external buffers. The external voltage regulator can be activated
from this power down state by asserting the SYS_HWRST pin,
which then initiates a boot sequence. SYS_EXTWAKE indicates
a wakeup to the external voltage regulator.
SYSTEM DEBUG
The processor includes various features that allow for easy system debug. These are described in the following sections.
System Watchpoint Unit
The System Watchpoint Unit (SWU) is a single module which
connects to a single system bus and provides for transaction
monitoring. One SWU is attached to the bus going to each system slave. The SWU provides ports for all system bus address
channel signals. Each SWU contains four match groups of registers with associated hardware. These four SWU match groups
operate independently, but share common event (interrupt,
trigger and others) outputs.
System Debug Unit
The System Debug Unit (SDU) provides IEEE-1149.1 support
through its JTAG interface. In addition to traditional JTAG features, present in legacy Blackfin products, the SDU adds more
features for debugging the chip without halting the core
processors.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of
Rev. A | Page 17 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF606/
ADSP-BF607/ADSP-BF608/ADSP-BF609 processors (and
related processors) can be ordered from any Analog Devices
sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
Board Support Packages for Evaluation Hardware
• ADSP-BF60x Blackfin Processor Hardware Reference
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
• Blackfin Processor Programming Reference
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• ADSP-BF60x Blackfin Processor Anomaly List
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
The Application Signal Chains page in the Circuits from the
LabTM site (http:\\www.analog.com\circuits) provides:
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules”.
Designing an Emulator-Compatible DSP Board (Target)
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
Rev. A | Page 18 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x DETAILED SIGNAL DESCRIPTIONS
Table 6 provides a detailed description of each signal.
Table 6. Detailed Signal Descriptions
Signal Name
ACM_An
ACM_CLK
ACM_FS
ACM_Tn
CAN_RX
CAN_TX
CNT_DG
Direction
Output
Output
Output
Input
Input
Output
Input
CNT_UD
Input
CNT_ZM
Input
DMC_Ann
DMC_BAn
Output
Output
DMC_CAS
Output
DMC_CK
DMC_CK
DMC_CKE
DMC_CSn
DMC_DQnn
DMC_LDM
Output
Output
Output
Output
I/O
Output
DMC_LDQS
DMC_LDQS
I/O
I/O
DMC_ODT
Output
DMC_RAS
Output
DMC_UDM
Output
DMC_UDQS
DMC_UDQS
I/O
I/O
DMC_WE
Output
Description
ADC Control Signals Function varies by mode.
Clock SCLK derived clock for connecting to an ADC.
Frame Sync Typically used as an ADC chip select.
External Trigger n Input for external trigger events.
Receive Typically an external CAN transceiver's RX output.
Transmit Typically an external CAN transceiver's TX input.
Count Down and Gate Depending on the mode of operation this input acts either as a count down
signal or a gate signal.
Count Down: This input causes the GP counter to decrement.
Gate: Stops the GP counter from incrementing or decrementing.
Count Up and Direction Depending on the mode of operation this input acts either as a count up signal
or a direction signal.
Count Up: This input causes the GP counter to increment.
Direction: Selects whether the GP counter is incrementing or decrementing.
Count Zero Marker Input that connects to the zero marker output of a rotary device or detects the
pressing of a push button.
Address n Address bus.
Bank Address Input n Defines which internal bank an ACTIVATE, READ, WRITE, or PRECHARGE command
is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or
EMR3) are loaded during the LOAD MODE REGISTER command.
Column Address Strobe Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the CAS input of dynamic memory.
Clock (complement) Complement of DMC_CK.
Clock Outputs DCLK to external dynamic memory.
Clock enable Active high clock enables. Connects to the dynamic memory’s CKE input.
Chip Select n Commands are recognized by the memory only when this signal is asserted.
Data n Bidirectional data bus.
Data Mask for Lower Byte Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on
both edges of the data strobe by the dynamic memory.
Data Strobe for Lower Byte (complement) Complement of LDQS. Not used in single-ended mode.
Data Strobe for Lower Byte DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
On-die Termination Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.
Row Address Strobe Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
Data Mask for Upper Byte Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on
both edges of the data strobe by the dynamic memory.
Data Strobe for Upper Byte (complement) Complement of UDQS. Not used in single-ended mode.
Data Strobe for Upper Byte DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
Write Enable Defines the operation for external dynamic memory to perform in conjunction with other
DMC command signals. Connect to the WE input of dynamic memory.
Rev. A | Page 19 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 6. Detailed Signal Descriptions (Continued)
Signal Name
ETH_CRS
Direction
Input
ETH_MDC
ETH_MDIO
ETH_PTPAUXIN
Output
I/O
Input
ETH_PTPCLKIN
ETH_PTPPPS
Input
Output
ETH_REFCLK
ETH_RXDn
ETH_TXDn
ETH_TXEN
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP_ACK
Input
Input
Output
I/O
Output
Input
Input
Output
Input
Input
I/O
LP_CLK
I/O
LP_Dn
PPI_CLK
PPI_Dnn
PPI_FS1
I/O
I/O
I/O
I/O
PPI_FS2
I/O
PPI_FS3
I/O
PWM_AH
PWM_AL
PWM_BH
PWM_BL
PWM_CH
PWM_CL
PWM_DH
PWM_DL
PWM_SYNC
Output
Output
Output
Output
Output
Output
Output
Output
Input
PWM_TRIPn
Px_nn
Input
I/O
Description
Carrier Sense/RMII Receive Data Valid Multiplexed on alternate clock cycles.
CRS: Asserted by the PHY when either the transmit or receive medium is not idle. De-asserted when both
are idle.
RXDV: Asserted by the PHY when the data on RXDn is valid.
Management Channel Clock Clocks the MDC input of the PHY.
Management Channel Serial Data Bidirectional data bus for PHY control.
PTP Auxiliary Trigger Input Assert this signal to take an auxiliary snapshot of the time and store it in
the auxiliary time stamp FIFO.
PTP Clock Input Optional external PTP clock input.
PTP Pulse-Per-Second Output When the Advanced Time Stamp feature is enabled, this signal is
asserted based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter
is incremented.
Reference Clock Externally supplied Ethernet clock.
Receive Data n Receive data bus.
Transmit Data n Transmit data bus.
Transmit Enable When asserted indicates that the data on TXDn is valid.
Emulation Output JTAG emulation flag.
Clock JTAG test access port clock.
Serial Data In JTAG test access port data input.
Serial Data Out JTAG test access port data output.
Mode Select JTAG test access port mode select.
Reset JTAG test access port reset.
Acknowledge Provides handshaking. When the link port is configured as a receiver, ACK is an output.
When the link port is configured as a transmitter, ACK is an input.
Clock When the link port is configured as a receiver, CLK is an input. When the link port is configured as
a transmitter, CLK is an output.
Data n Data bus. Input when receiving, output when transmitting.
Clock Input in external clock mode, output in internal clock mode.
Data n Bidirectional data bus.
Frame Sync 1 (HSYNC) Behavior depends on PPI mode. See the PPI chapter in the processor hardware
reference for more details.
Frame Sync 2 (VSYNC) Behavior depends on PPI mode. See the PPI chapter in the processor hardware
reference for more details.
Frame Sync 3 (FIELD) Behavior depends on PPI mode. See the PPI chapter in the processor hardware
reference for more details.
Channel A High Side High side drive signal.
Channel A Low Side Low side drive signal.
Channel B High Side High side drive signal.
Channel B Low Side Low side drive signal.
Channel C High Side High side drive signal.
Channel C Low Side Low side drive signal.
Channel D High Side High side drive signal.
Channel D Low Side Low side drive signal.
PWM External Sync This input is for an externally generated sync signal. If the sync signal is internally
generated no connection is necessary.
Shutdown Input n When asserted the selected PWM channel outputs are shut down immediately.
Position n General purpose input/output. See the GP Ports chapter in the processor hardware reference
for programming information.
Rev. A | Page 20 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 6. Detailed Signal Descriptions (Continued)
Signal Name
RSI_CLK
RSI_CMD
RSI_Dn
SMC_ABEn
Direction
Output
I/O
I/O
Output
SMC_AMSn
SMC_Ann
SMC_AOE
SMC_ARDY
Output
Output
Output
Input
SMC_ARE
SMC_AWE
SMC_BG
Output
Output
Output
SMC_BGH
Output
SMC_BR
SMC_Dnn
SMC_NORCLK
SMC_NORDV
SMC_NORWT
Input
I/O
Output
Output
Input
SPI_CLK
SPI_D2
SPI_D3
SPI_MISO
I/O
I/O
I/O
I/O
SPI_MOSI
I/O
SPI_RDY
SPI_SELn
SPI_SS
I/O
Output
Input
SPT_ACLK
I/O
SPT_AD0
I/O
SPT_AD1
I/O
SPT_AFS
I/O
SPT_ATDV
Output
SPT_BCLK
I/O
SPT_BD0
I/O
Description
Clock The clock signal applied to the connected device from the RSI.
Command Used to send commands to and receive responses from the connected device.
Data n Bidirectional data bus.
Byte Enable n Indicate whether the lower or upper byte of a memory is being accessed. When an
asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 =0 and SMC_ABE0 =1.
When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1 =1 and
SMC_ABE0 =0.
Memory Select n Typically connects to the chip select of a memory device.
Address n Address bus.
Output Enable Asserts at the beginning of the setup period of a read access.
Asynchronous Ready Flow control signal used by memory devices to indicate to the SMC when further
transactions may proceed.
Read Enable Asserts at the beginning of a read access.
Write Enable Asserts for the duration of a write access period.
Bus Grant Output used to indicate to an external device that it has been granted control of the SMC
buses.
Bus Grant Hang Output used to indicate that the SMC has a pending transaction which requires control
of the bus to be restored before it can be completed.
Bus Request Input used by an external device to indicate that it is requesting control of the SMC buses.
Data n Bidirectional data bus.
NOR Clock Clock for synchronous burst mode.
NOR Data Valid Asserts for the duration of a synchronous burst mode read setup period.
NOR Wait Flow control signal used by memory devices in synchronous burst mode to indicate to the
SMC when further transactions may proceed.
Clock Input in slave mode, output in master mode.
Data 2 Used to transfer serial data in quad mode. Open drain in ODM mode.
Data 3 Used to transfer serial data in quad mode. Open drain in ODM mode.
Master In, Slave Out Used to transfer serial data. Operates in the same direction as SPI_MOSI in dual
and quad modes. Open drain in ODM mode.
Master Out, Slave In Used to transfer serial data. Operates in the same direction as SPI_MISO in dual
and quad modes. Open drain in ODM mode.
Ready Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n Used in master mode to enable the desired slave.
Slave Select Input Slave mode: acts as the slave select input. Master mode: optionally serves as an error
detection input for the SPI when there are multiple masters.
Channel A Clock Data and frame sync are driven/sampled with respect to this clock. This signal can be
either internally or externally generated.
Channel A Data 0 Primary bidirectional data I/O. This signal can be configured as an output to transmit
serial data, or as an input to receive serial data.
Channel A Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel A Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel A Transmit Data Valid This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
Channel B Clock Data and frame sync are driven/sampled with respect to this clock. This signal can be
either internally or externally generated.
Channel B Data 0 Primary bidirectional data I/O. This signal can be configured as an output to transmit
serial data, or as an input to receive serial data.
Rev. A | Page 21 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 6. Detailed Signal Descriptions (Continued)
Signal Name
SPT_BD1
Direction
I/O
SPT_BFS
I/O
SPT_BTDV
Output
SYS_BMODEn
SYS_CLKIN
SYS_CLKOUT
Input
Input
Output
SYS_EXTWAKE
Output
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_IDLEn
SYS_NMI
I/O
I/O
Input
Output
Input
SYS_PWRGD
Input
SYS_RESOUT
SYS_SLEEP
Output
Output
SYS_TDA
SYS_TDK
Input
Input
SYS_XTAL
TMR_ACIn
TMR_ACLKn
TMR_CLK
TMR_TMRn
TWI_SCL
TWI_SDA
UART_CTS
UART_RTS
UART_RX
Output
Input
Input
Input
I/O
I/O
I/O
Input
Output
Input
UART_TX
Output
USB_CLKIN
Input
USB_DM
USB_DP
USB_ID
I/O
I/O
Input
USB_VBC
Output
USB_VBUS
I/O
Description
Channel B Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
Channel B Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Channel B Transmit Data Valid This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
Boot Mode Control n Selects the boot mode of the processor.
Clock/Crystal Input Connect to an external clock source or crystal.
Processor Clock Output Outputs internal clocks. Clocks may be divided down. See the CGU chapter in
the processor hardware reference for more details.
External Wake Control Drives low during hibernate and high all other times. Typically connected to the
enable input of the voltage regulator controlling the VDD_INT supply.
Complementary Fault Complement of SYS_FAULT.
Fault Indicates internal faults or senses external faults depending on the operating mode.
Processor Hardware Reset Control Resets the device when asserted.
Core n Idle Indicator When low indicates that core n is in idle mode or being held in reset.
Non-maskable Interrupt Priority depends on the core that receives the interrupt. See the processor
hardware and programming references for more details.
Power Good Indicator When high it indicates to the processor that the VDD_INT level is within specifications such that it is safe to begin booting upon return from hibernate.
Reset Output Indicates that the device is in the reset state.
Processor Sleep Indicator When low indicates that the processor is in the deep sleep power saving
mode.
Thermal Diode Anode May be used by an external temperature sensor to measure the die temperature.
Thermal Diode Cathode May be used by an external temperature sensor to measure the die
temperature.
Crystal Output Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN.
Alternate Capture Input n Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n Provides an additional time base for use by an individual timer.
Clock Provides an additional global time base for use by all the GP timers.
Timer n The main input/output signal for each timer.
Serial Clock Clock output when master, clock input when slave.
Serial Data Receives or transmits data.
Clear to Send Flow control signal.
Request to Send Flow control signal.
Receive Receive input. Typically connects to a transceiver that meets the electrical requirements of the
device being communicated with.
Transmit Transmit output. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
Clock/Crystal Input This clock input is multiplied by a PLL to form the USB clock. See Universal Serial
Bus (USB) On-The-Go—Receive and Transmit Timing for frequency/tolerance information.
Data – Bidirectional differential data line.
Data + Bidirectional differential data line.
OTG ID Senses whether the controller is a host or device. This signal is pulled low when an A-type plug
is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is
sensed (signifying that the USB controller is the B device).
VBUS Control Controls an external voltage source to supply VBUS when in host mode. May be
configured as open drain. Polarity is configurable as well.
Bus Voltage Connects to bus voltage in host and device modes.
Rev. A | Page 22 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
349-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processors' pin definitions are shown in the table. The columns in this table provide the following information:
• Signal Name: The Signal Name column in the table
includes the Signal Name for every pin.
• Description: The Description column in the table provides
a verbose (descriptive) name for the signal.
• Port: The General-Purpose I/O Port column in the table
shows whether or not the signal is multiplexed with other
signals on a general-purpose I/O port pin.
• Pin Name: The Pin Name column in the table identifies the
name of the package pin (at power-on reset) on which the
signal is located (if a single function pin) or is multiplexed
(if a general-purpose I/O pin).
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions
Signal Name
ACM0_A0
ACM0_A1
ACM0_A2
ACM0_A3
ACM0_A4
ACM0_CLK
ACM0_FS
ACM0_T0
ACM0_T1
CAN0_RX
CAN0_TX
CNT0_DG
CNT0_UD
CNT0_ZM
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
Description
ACM0 Address 0
ACM0 Address 1
ACM0 Address 2
ACM0 Address 3
ACM0 Address 4
ACM0 Clock
ACM0 Frame Sync
ACM0 External Trigger 0
ACM0 External Trigger 1
CAN0 Receive
CAN0 Transmit
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DMC Address 0
DMC Address 1
DMC Address 2
DMC Address 3
DMC Address 4
DMC Address 5
DMC Address 6
DMC Address 7
DMC Address 8
DMC Address 9
DMC Address 10
DMC Address 11
DMC Address 12
DMC Address 13
DMC Bank Address Input 0
DMC Bank Address Input 1
DMC Bank Address Input 2
DMC Column Address Strobe
DMC Clock
DMC Clock Enable
DMC Clock (complement)
DMC Chip Select 0
Rev. A | Page 23 of 112 | February 2014
Port
F
F
F
F
F
E
E
E
G
G
G
G
G
G
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Pin Name
PF_14
PF_15
PF_12
PF_13
PF_10
PE_04
PE_03
PE_08
PG_05
PG_04
PG_01
PG_12
PG_11
PG_07
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_WE
ETH0_CRS
ETH0_MDC
ETH0_MDIO
ETH0_PTPPPS
ETH0_REFCLK
ETH0_RXD0
ETH0_RXD1
ETH0_TXD0
ETH0_TXD1
ETH0_TXEN
ETH1_CRS
ETH1_MDC
ETH1_MDIO
ETH1_PTPPPS
ETH1_REFCLK
ETH1_RXD0
ETH1_RXD1
ETH1_TXD0
ETH1_TXD1
ETH1_TXEN
ETH_PTPAUXIN
Description
DMC Data 0
DMC Data 1
DMC Data 2
DMC Data 3
DMC Data 4
DMC Data 5
DMC Data 6
DMC Data 7
DMC Data 8
DMC Data 9
DMC Data 10
DMC Data 11
DMC Data 12
DMC Data 13
DMC Data 14
DMC Data 15
DMC Data Mask for Lower Byte
DMC Data Strobe for Lower Byte
DMC Data Strobe for Lower Byte (complement)
DMC On-die Termination
DMC Row Address Strobe
DMC Data Mask for Upper Byte
DMC Data Strobe for Upper Byte
DMC Data Strobe for Upper Byte (complement)
DMC Write Enable
EMAC0 Carrier Sense/RMII Receive Data Valid
EMAC0 Management Channel Clock
EMAC0 Management Channel Serial Data
EMAC0 PTP Pulse-Per-Second Output
EMAC0 Reference Clock
EMAC0 Receive Data 0
EMAC0 Receive Data 1
EMAC0 Transmit Data 0
EMAC0 Transmit Data 1
EMAC0 Transmit Enable
EMAC1 Carrier Sense/RMII Receive Data Valid
EMAC1 Management Channel Clock
EMAC1 Management Channel Serial Data
EMAC1 PTP Pulse-Per-Second Output
EMAC1 Reference Clock
EMAC1 Receive Data 0
EMAC1 Receive Data 1
EMAC1 Transmit Data 0
EMAC1 Transmit Data 1
EMAC1 Transmit Enable
EMAC0/EMAC1 PTP Auxiliary Trigger Input
Rev. A | Page 24 of 112 | February 2014
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
C
C
C
B
B
C
C
C
C
B
E
E
E
C
G
G
E
G
G
G
C
Pin Name
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_WE
PC_05
PC_06
PC_07
PB_15
PB_14
PC_00
PC_01
PC_02
PC_03
PB_13
PE_13
PE_10
PE_11
PC_09
PG_06
PG_00
PE_15
PG_03
PG_02
PG_05
PC_11
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
ETH_PTPCLKIN
GND
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP0_ACK
LP0_CLK
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_ACK
LP1_CLK
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP2_ACK
LP2_CLK
LP2_D0
LP2_D1
LP2_D2
LP2_D3
LP2_D4
LP2_D5
LP2_D6
LP2_D7
LP3_ACK
LP3_CLK
LP3_D0
LP3_D1
LP3_D2
LP3_D3
LP3_D4
LP3_D5
Description
EMAC0/EMAC1 PTP Clock Input
Ground
Emulation Output
JTAG Clock
JTAG Serial Data Input
JTAG Serial Data Output
JTAG Mode Select
JTAG Reset
LP0 Acknowledge
LP0 Clock
LP0 Data 0
LP0 Data 1
LP0 Data 2
LP0 Data 3
LP0 Data 4
LP0 Data 5
LP0 Data 6
LP0 Data 7
LP1 Acknowledge
LP1 Clock
LP1 Data 0
LP1 Data 1
LP1 Data 2
LP1 Data 3
LP1 Data 4
LP1 Data 5
LP1 Data 6
LP1 Data 7
LP2 Acknowledge
LP2 Clock
LP2 Data 0
LP2 Data 1
LP2 Data 2
LP2 Data 3
LP2 Data 4
LP2 Data 5
LP2 Data 6
LP2 Data 7
LP3 Acknowledge
LP3 Clock
LP3 Data 0
LP3 Data 1
LP3 Data 2
LP3 Data 3
LP3 Data 4
LP3 Data 5
Rev. A | Page 25 of 112 | February 2014
Port
C
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
B
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
A
A
E
E
F
F
F
F
F
F
F
F
E
E
F
F
F
F
F
F
Pin Name
PC_13
GND
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_01
PB_00
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PB_02
PB_03
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PE_08
PE_09
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PE_07
PE_06
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
LP3_D6
LP3_D7
PA_00 – PA_15
PB_00 – PB_15
PC_00 – PC_15
PD_00 – PD_15
PE_00 – PE_15
PF_00 – PF_15
PG_00 – PG_15
PPI0_CLK
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D18
PPI0_D19
PPI0_D20
PPI0_D21
PPI0_D22
PPI0_D23
PPI0_FS1
PPI0_FS2
PPI0_FS3
PPI1_CLK
PPI1_D00
PPI1_D01
PPI1_D02
PPI1_D03
PPI1_D04
PPI1_D05
PPI1_D06
PPI1_D07
Description
LP3 Data 6
LP3 Data 7
PORTA Position 00 through PORTA Position 15
PORTB Position 00 through PORTB Position 15
PORTC Position 00 through PORTC Position 15
PORTD Position 00 through PORTD Position 15
PORTE Position 00 through PORTE Position 15
PORTF Position 00 through PORTF Position 15
PORTG Position 00 through PORTG Position 15
EPPI0 Clock
EPPI0 Data 0
EPPI0 Data 1
EPPI0 Data 2
EPPI0 Data 3
EPPI0 Data 4
EPPI0 Data 5
EPPI0 Data 6
EPPI0 Data 7
EPPI0 Data 8
EPPI0 Data 9
EPPI0 Data 10
EPPI0 Data 11
EPPI0 Data 12
EPPI0 Data 13
EPPI0 Data 14
EPPI0 Data 15
EPPI0 Data 16
EPPI0 Data 17
EPPI0 Data 18
EPPI0 Data 19
EPPI0 Data 20
EPPI0 Data 21
EPPI0 Data 22
EPPI0 Data 23
EPPI0 Frame Sync 1 (HSYNC)
EPPI0 Frame Sync 2 (VSYNC)
EPPI0 Frame Sync 3 (FIELD)
EPPI1 Clock
EPPI1 Data 0
EPPI1 Data 1
EPPI1 Data 2
EPPI1 Data 3
EPPI1 Data 4
EPPI1 Data 5
EPPI1 Data 6
EPPI1 Data 7
Rev. A | Page 26 of 112 | February 2014
Port
F
F
A
B
C
D
E
F
G
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
E
E
E
E
D
D
E
E
E
E
E
B
C
C
C
C
C
C
C
C
Pin Name
PF_14
PF_15
PA_00 – PA_15
PB_00 – PB_15
PC_00 – PC_15
PD_00 – PD_15
PE_00 – PE_15
PF_00 – PF_15
PG_00 – PG_15
PE_09
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
PE_03
PE_04
PE_00
PE_01
PD_12
PD_15
PE_02
PE_05
PE_08
PE_07
PE_06
PB_14
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PPI1_D08
PPI1_D09
PPI1_D10
PPI1_D11
PPI1_D12
PPI1_D13
PPI1_D14
PPI1_D15
PPI1_D16
PPI1_D17
PPI1_FS1
PPI1_FS2
PPI1_FS3
PPI2_CLK
PPI2_D00
PPI2_D01
PPI2_D02
PPI2_D03
PPI2_D04
PPI2_D05
PPI2_D06
PPI2_D07
PPI2_D08
PPI2_D09
PPI2_D10
PPI2_D11
PPI2_D12
PPI2_D13
PPI2_D14
PPI2_D15
PPI2_D16
PPI2_D17
PPI2_FS1
PPI2_FS2
PPI2_FS3
PWM0_AH
PWM0_AL
PWM0_BH
PWM0_BL
PWM0_CH
PWM0_CL
PWM0_DH
PWM0_DL
PWM0_SYNC
PWM0_TRIP0
PWM0_TRIP1
Description
EPPI1 Data 8
EPPI1 Data 9
EPPI1 Data 10
EPPI1 Data 11
EPPI1 Data 12
EPPI1 Data 13
EPPI1 Data 14
EPPI1 Data 15
EPPI1 Data 16
EPPI1 Data 17
EPPI1 Frame Sync 1 (HSYNC)
EPPI1 Frame Sync 2 (VSYNC)
EPPI1 Frame Sync 3 (FIELD)
EPPI2 Clock
EPPI2 Data 0
EPPI2 Data 1
EPPI2 Data 2
EPPI2 Data 3
EPPI2 Data 4
EPPI2 Data 5
EPPI2 Data 6
EPPI2 Data 7
EPPI2 Data 8
EPPI2 Data 9
EPPI2 Data 10
EPPI2 Data 11
EPPI2 Data 12
EPPI2 Data 13
EPPI2 Data 14
EPPI2 Data 15
EPPI2 Data 16
EPPI2 Data 17
EPPI2 Frame Sync 1 (HSYNC)
EPPI2 Frame Sync 2 (VSYNC)
EPPI2 Frame Sync 3 (FIELD)
PWM0 Channel A High Side
PWM0 Channel A Low Side
PWM0 Channel B High Side
PWM0 Channel B Low Side
PWM0 Channel C High Side
PWM0 Channel C Low Side
PWM0 Channel D High Side
PWM0 Channel D Low Side
PWM0 Sync
PWM0 Shutdown Input 0
PWM0 Shutdown Input 1
Rev. A | Page 27 of 112 | February 2014
Port
C
C
C
C
C
C
C
C
D
D
B
D
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
F
F
F
F
F
F
F
F
E
E
F
Pin Name
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
PD_00
PD_01
PB_13
PD_06
PB_15
PB_00
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_07
PB_08
PB_01
PB_02
PB_03
PF_01
PF_00
PF_03
PF_02
PF_05
PF_04
PF_07
PF_06
PE_08
PE_09
PF_11
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PWM1_AH
PWM1_AL
PWM1_BH
PWM1_BL
PWM1_CH
PWM1_CL
PWM1_DH
PWM1_DL
PWM1_SYNC
PWM1_TRIP0
PWM1_TRIP1
RSI0_CLK
RSI0_CMD
RSI0_D0
RSI0_D1
RSI0_D2
RSI0_D3
RSI0_D4
RSI0_D5
RSI0_D6
RSI0_D7
SMC0_A01
SMC0_A02
SMC0_A03
SMC0_A04
SMC0_A05
SMC0_A06
SMC0_A07
SMC0_A08
SMC0_A09
SMC0_A10
SMC0_A11
SMC0_A12
SMC0_A13
SMC0_A14
SMC0_A15
SMC0_A16
SMC0_A17
SMC0_A18
SMC0_A19
SMC0_A20
SMC0_A21
SMC0_A22
SMC0_A23
SMC0_A24
SMC0_A25
Description
PWM1 Channel A High Side
PWM1 Channel A Low Side
PWM1 Channel B High Side
PWM1 Channel B Low Side
PWM1 Channel C High Side
PWM1 Channel C Low Side
PWM1 Channel D High Side
PWM1 Channel D Low Side
PWM1 Sync
PWM1 Shutdown Input 0
PWM1 Shutdown Input 1
RSI0 Clock
RSI0 Command
RSI0 Data 0
RSI0 Data 1
RSI0 Data 2
RSI0 Data 3
RSI0 Data 4
RSI0 Data 5
RSI0 Data 6
RSI0 Data 7
SMC0 Address 1
SMC0 Address 2
SMC0 Address 3
SMC0 Address 4
SMC0 Address 5
SMC0 Address 6
SMC0 Address 7
SMC0 Address 8
SMC0 Address 9
SMC0 Address 10
SMC0 Address 11
SMC0 Address 12
SMC0 Address 13
SMC0 Address 14
SMC0 Address 15
SMC0 Address 16
SMC0 Address 17
SMC0 Address 18
SMC0 Address 19
SMC0 Address 20
SMC0 Address 21
SMC0 Address 22
SMC0 Address 23
SMC0 Address 24
SMC0 Address 25
Rev. A | Page 28 of 112 | February 2014
Port
G
G
G
E
E
E
E
E
G
G
G
G
G
G
G
G
E
E
E
E
E
Not Muxed
Not Muxed
A
A
A
A
A
A
A
A
A
A
B
A
A
B
A
A
A
A
B
B
B
B
B
Pin Name
PG_03
PG_02
PG_00
PE_15
PE_13
PE_12
PE_11
PE_10
PG_05
PG_06
PG_08
PG_06
PG_05
PG_03
PG_02
PG_00
PE_15
PE_13
PE_12
PE_10
PE_11
SMC0_A01
SMC0_A02
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PB_02
PA_10
PA_11
PB_03
PA_12
PA_13
PA_14
PA_15
PB_06
PB_07
PB_08
PB_10
PB_11
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SMC0_ABE0
SMC0_ABE1
SMC0_AMS0
SMC0_AMS1
SMC0_AMS2
SMC0_AMS3
SMC0_AOE
SMC0_ARDY
SMC0_ARE
SMC0_AWE
SMC0_BGH
SMC0_BG
SMC0_BR
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
SMC0_NORCLK
SMC0_NORDV
SMC0_NORWT
SPI0_CLK
SPI0_D2
SPI0_D3
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SEL5
SPI0_SEL6
SPI0_SEL7
SPI0_SS
Description
SMC0 Byte Enable 0
SMC0 Byte Enable 1
SMC0 Memory Select 0
SMC0 Memory Select 1
SMC0 Memory Select 2
SMC0 Memory Select 3
SMC0 Output Enable
SMC0 Asynchronous Ready
SMC0 Read Enable
SMC0 Write Enable
SMC0 Bus Grant Hang
SMC0 Bus Grant
SMC0 Bus Request
SMC0 Data 0
SMC0 Data 1
SMC0 Data 2
SMC0 Data 3
SMC0 Data 4
SMC0 Data 5
SMC0 Data 6
SMC0 Data 7
SMC0 Data 8
SMC0 Data 9
SMC0 Data 10
SMC0 Data 11
SMC0 Data 12
SMC0 Data 13
SMC0 Data 14
SMC0 Data 15
SMC0 NOR Clock
SMC0 NOR Data Valid
SMC0 NOR Wait
SPI0 Clock
SPI0 Data 2
SPI0 Data 3
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Output 5
SPI0 Slave Select Output 6
SPI0 Slave Select Output 7
SPI0 Slave Select Input
Rev. A | Page 29 of 112 | February 2014
Port
B
B
Not Muxed
B
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
B
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
B
Not Muxed
Not Muxed
D
D
D
D
D
D
D
D
D
C
D
C
C
D
Pin Name
PB_04
PB_05
SMC0_AMS0
PB_01
PB_04
PB_05
SMC0_AOE_NORDV
SMC0_ARDY_NORWT
SMC0_ARE
SMC0_AWE
PB_09
PB_12
SMC0_BR
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
PB_00
SMC0_AOE_NORDV
SMC0_ARDY_NORWT
PD_04
PD_00
PD_01
PD_02
PD_03
PD_10
PD_11
PD_01
PD_00
PC_15
PD_09
PC_13
PC_12
PD_11
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SPI1_CLK
SPI1_D2
SPI1_D3
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
SPT0_ACLK
SPT0_AD0
SPT0_AD1
SPT0_AFS
SPT0_ATDV
SPT0_BCLK
SPT0_BD0
SPT0_BD1
SPT0_BFS
SPT0_BTDV
SPT1_ACLK
SPT1_AD0
SPT1_AD1
SPT1_AFS
SPT1_ATDV
SPT1_BCLK
SPT1_BD0
SPT1_BD1
SPT1_BFS
SPT1_BTDV
SPT2_ACLK
SPT2_AD0
SPT2_AD1
SPT2_AFS
SPT2_ATDV
SPT2_BCLK
SPT2_BD0
SPT2_BD1
SPT2_BFS
SPT2_BTDV
SYS_BMODE0
SYS_BMODE1
Description
SPI1 Clock
SPI1 Data 2
SPI1 Data 3
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
SPORT0 Channel A Clock
SPORT0 Channel A Data 0
SPORT0 Channel A Data 1
SPORT0 Channel A Frame Sync
SPORT0 Channel A Transmit Data Valid
SPORT0 Channel B Clock
SPORT0 Channel B Data 0
SPORT0 Channel B Data 1
SPORT0 Channel B Frame Sync
SPORT0 Channel B Transmit Data Valid
SPORT1 Channel A Clock
SPORT1 Channel A Data 0
SPORT1 Channel A Data 1
SPORT1 Channel A Frame Sync
SPORT1 Channel A Transmit Data Valid
SPORT1 Channel B Clock
SPORT1 Channel B Data 0
SPORT1 Channel B Data 1
SPORT1 Channel B Frame Sync
SPORT1 Channel B Transmit Data Valid
SPORT2 Channel A Clock
SPORT2 Channel A Data 0
SPORT2 Channel A Data 1
SPORT2 Channel A Frame Sync
SPORT2 Channel A Transmit Data Valid
SPORT2 Channel B Clock
SPORT2 Channel B Data 0
SPORT2 Channel B Data 1
SPORT2 Channel B Frame Sync
SPORT2 Channel B Transmit Data Valid
Boot Mode Control 0
Boot Mode Control 1
Rev. A | Page 30 of 112 | February 2014
Port
D
E
E
D
D
E
D
D
D
D
F
F
C
D
B
B
B
B
B
B
B
B
B
B
E
D
D
E
E
E
E
E
E
E
G
G
G
G
E
G
G
G
G
G
Not Muxed
Not Muxed
Pin Name
PD_05
PE_01
PE_00
PD_14
PD_13
PE_02
PD_12
PD_15
PD_10
PD_09
PF_08
PF_09
PC_14
PD_12
PB_05
PB_09
PB_12
PB_04
PB_06
PB_08
PB_11
PB_10
PB_07
PB_12
PE_02
PD_15
PD_12
PE_05
PE_06
PE_04
PE_01
PE_00
PE_03
PE_07
PG_04
PG_09
PG_08
PG_01
PE_14
PG_10
PG_12
PG_11
PG_07
PG_06
SYS_BMODE0
SYS_BMODE1
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SYS_BMODE2
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_IDLE0
SYS_IDLE1
SYS_NMI
SYS_PWRGD
SYS_RESOUT
SYS_SLEEP
SYS_TDA
SYS_TDK
SYS_XTAL
TM0_ACI0
TM0_ACI1
TM0_ACI2
TM0_ACI3
TM0_ACI4
TM0_ACI5
TM0_ACI6
TM0_ACLK0
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_ACLK5
TM0_ACLK6
TM0_ACLK7
TM0_CLK
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TM0_TMR6
TM0_TMR7
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
UART0_CTS
UART0_RTS
Description
Boot Mode Control 2
Clock/Crystal Input
Processor Clock Output
External Wake Control
Fault Output
Complementary Fault Output
Processor Hardware Reset Control
Core 0 Idle Indicator
Core 1 Idle Indicator
Non-maskable Interrupt
Power Good Indicator
Reset Output
Processor Sleep Indicator
Thermal Diode Anode
Thermal Diode Cathode
Crystal Output
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Capture Input 5
TIMER0 Alternate Capture Input 6
TIMER0 Alternate Clock 0
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Alternate Clock 5
TIMER0 Alternate Clock 6
TIMER0 Alternate Clock 7
TIMER0 Clock
TIMER0 Timer 0
TIMER0 Timer 1
TIMER0 Timer 2
TIMER0 Timer 3
TIMER0 Timer 4
TIMER0 Timer 5
TIMER0 Timer 6
TIMER0 Timer 7
TWI0 Serial Clock
TWI0 Serial Data
TWI1 Serial Clock
TWI1 Serial Data
UART0 Clear to Send
UART0 Request to Send
Rev. A | Page 31 of 112 | February 2014
Port
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
G
G
Not Muxed
Not Muxed
Not Muxed
G
Not Muxed
Not Muxed
Not Muxed
D
G
G
D
G
D
B
B
B
B
B
B
D
D
D
G
E
G
G
G
G
G
G
G
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
D
Pin Name
SYS_BMODE2
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_HWRST
PG_15
PG_14
SYS_NMI_RESOUT
SYS_PWRGD
SYS_NMI_RESOUT
PG_15
SYS_TDA
SYS_TDK
SYS_XTAL
PD_08
PG_14
PG_04
PD_07
PG_15
PD_06
PB_13
PB_10
PB_12
PB_09
PB_11
PB_06
PD_13
PD_14
PD_05
PG_13
PE_14
PG_04
PG_01
PG_08
PG_09
PG_07
PG_11
PG_12
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
PD_10
PD_09
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
UART0_RX
UART0_TX
UART1_CTS
UART1_RTS
UART1_RX
UART1_TX
USB0_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
VDD_DMC
VDD_EXT
VDD_INT
VDD_TD
VDD_USB
VREF_DMC
Description
UART0 Receive
UART0 Transmit
UART1 Clear to Send
UART1 Request to Send
UART1 Receive
UART1 Transmit
USB0 Clock/Crystal Input
USB0 Data –
USB0 Data +
USB0 OTG ID
USB0 VBUS Control
USB0 Bus Voltage
VDD for DMC
External VDD
Internal VDD
VDD for Thermal Diode
VDD for USB
VREF for DMC
Rev. A | Page 32 of 112 | February 2014
Port
D
D
G
G
G
G
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Pin Name
PD_08
PD_07
PG_13
PG_10
PG_14
PG_15
USB0_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
VDD_DMC
VDD_EXT
VDD_INT
VDD_TD
VDD_USB
VREF_DMC
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
GP I/O MULTIPLEXING FOR 349-BALL CSP_BGA
Table 8 through Table 14 identifies the pin functions that are
multiplexed on the general-purpose I/O pins of the 349-ball
CSP_BGA package.
Table 8. Signal Multiplexing for Port A
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
Multiplexed Function 0
SMC0_A03
SMC0_A04
SMC0_A05
SMC0_A06
SMC0_A07
SMC0_A08
SMC0_A09
SMC0_A10
SMC0_A11
SMC0_A12
SMC0_A14
SMC0_A15
SMC0_A17
SMC0_A18
SMC0_A19
SMC0_A20
Multiplexed Function 1
PPI2_D00
PPI2_D01
PPI2_D02
PPI2_D03
PPI2_D04
PPI2_D05
PPI2_D06
PPI2_D07
PPI2_D08
PPI2_D09
PPI2_D10
PPI2_D11
PPI2_D12
PPI2_D13
PPI2_D14
PPI2_D15
Multiplexed Function 2
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
Multiplexed Function 1
PPI2_CLK
PPI2_FS1
PPI2_FS2
PPI2_FS3
SMC0_ABE0
SMC0_ABE1
SPT0_ATDV
PPI2_D16
PPI2_D17
Multiplexed Function 2
LP0_CLK
LP0_ACK
LP1_ACK
LP1_CLK
SPT0_AFS
SPT0_ACLK
Multiplexed Function
Input Tap
Table 9. Signal Multiplexing for Port B
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
Multiplexed Function 0
SMC0_NORCLK
SMC0_AMS1
SMC0_A13
SMC0_A16
SMC0_AMS2
SMC0_AMS3
SMC0_A21
SMC0_A22
SMC0_A23
SMC0_BGH
SMC0_A24
SMC0_A25
SMC0_BG
ETH0_TXEN
ETH0_REFCLK
ETH0_PTPPPS
SPT0_BTDV
PPI1_FS1
PPI1_CLK
PPI1_FS3
Multiplexed Function
Input Tap
TM0_ACLK4
SPT0_BFS
SPT0_BCLK
SPT0_AD0
SPT0_BD1
SPT0_BD0
SPT0_AD1
Rev. A | Page 33 of 112 | February 2014
TM0_ACLK2
TM0_ACLK0
TM0_ACLK3
TM0_ACLK1
TM0_ACI6
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 10. Signal Multiplexing for Port C
Signal Name
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
Multiplexed Function 0
ETH0_RXD0
ETH0_RXD1
ETH0_TXD0
ETH0_TXD1
ETH0_CRS
ETH0_MDC
ETH0_MDIO
ETH1_PTPPPS
SPI0_SEL7
SPI0_SEL6
SPI1_SEL7
SPI0_SEL4
Multiplexed Function 1
PPI1_D00
PPI1_D01
PPI1_D02
PPI1_D03
PPI1_D04
PPI1_D05
PPI1_D06
PPI1_D07
PPI1_D08
PPI1_D09
PPI1_D10
PPI1_D11
PPI1_D12
PPI1_D13
PPI1_D14
PPI1_D15
Multiplexed Function 2
Multiplexed Function
Input Tap
ETH_PTPAUXIN
ETH_PTPCLKIN
Table 11. Signal Multiplexing for Port D
Signal Name
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
Multiplexed Function 0
SPI0_D2
SPI0_D3
SPI0_MISO
SPI0_MOSI
SPI0_CLK
SPI1_CLK
SPI0_SEL5
SPI0_RDY
SPI0_SEL1
SPI1_SEL1
SPI1_MOSI
SPI1_MISO
SPI1_SEL2
Multiplexed Function 1
PPI1_D16
PPI1_D17
Multiplexed Function 2
SPI0_SEL3
SPI0_SEL2
Multiplexed Function
Input Tap
TM0_ACLK7
TM0_ACI5
TM0_ACI3
TM0_ACI0
PPI1_FS2
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
SPI1_SEL4
SPI1_SEL3
PPI0_D20
SPT1_AD1
PPI0_D21
SPT1_AD0
Rev. A | Page 34 of 112 | February 2014
SPI0_SS
SPI1_SS
TM0_ACLK5
TM0_ACLK6
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 12. Signal Multiplexing for Port E
Signal Name
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
Multiplexed Function 0
SPI1_D3
SPI1_D2
SPI1_RDY
SPT1_ATDV
SPT1_BTDV
PWM0_SYNC
ETH1_MDC
ETH1_MDIO
ETH1_CRS
ETH1_RXD1
Multiplexed Function 1
PPI0_D18
PPI0_D19
PPI0_D22
PPI0_D16
PPI0_D17
PPI0_D23
PPI0_FS3
PPI0_FS2
PPI0_FS1
PPI0_CLK
PWM1_DL
PWM1_DH
PWM1_CL
PWM1_CH
SPT2_ATDV
PWM1_BL
Multiplexed Function 2
SPT1_BD1
SPT1_BD0
SPT1_ACLK
ACM0_FS/SPT1_BFS
ACM0_CLK/SPT1_BCLK
SPT1_AFS
LP3_CLK
LP3_ACK
LP2_ACK
LP2_CLK
RSI0_D6
RSI0_D7
RSI0_D5
RSI0_D4
TM0_TMR0
RSI0_D3
Multiplexed Function
Input Tap
ACM0_T0
PWM0_TRIP0
Table 13. Signal Multiplexing for Port F
Signal Name
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
Multiplexed Function 0
PWM0_AL
PWM0_AH
PWM0_BL
PWM0_BH
PWM0_CL
PWM0_CH
PWM0_DL
PWM0_DH
SPI1_SEL5
SPI1_SEL6
ACM0_A4
ACM0_A2
ACM0_A3
ACM0_A0
ACM0_A1
Multiplexed Function 1
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
Multiplexed Function 2
LP2_D0
LP2_D1
LP2_D2
LP2_D3
LP2_D4
LP2_D5
LP2_D6
LP2_D7
LP3_D0
LP3_D1
LP3_D2
LP3_D3
LP3_D4
LP3_D5
LP3_D6
LP3_D7
Rev. A | Page 35 of 112 | February 2014
Multiplexed Function
Input Tap
PWM0_TRIP1
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 14. Signal Multiplexing for Port G
Signal Name
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
PG_06
PG_07
PG_08
PG_09
PG_10
PG_11
PG_12
PG_13
PG_14
PG_15
Multiplexed Function 0
ETH1_RXD0
SPT2_AFS
ETH1_TXD1
ETH1_TXD0
SPT2_ACLK
ETH1_TXEN
ETH1_REFCLK
SPT2_BFS
SPT2_AD1
SPT2_AD0
UART1_RTS
SPT2_BD1
SPT2_BD0
UART1_CTS
UART1_RX
UART1_TX
Multiplexed Function 1
PWM1_BH
TM0_TMR2
PWM1_AL
PWM1_AH
TM0_TMR1
RSI0_CMD
RSI0_CLK
TM0_TMR5
TM0_TMR3
TM0_TMR4
SPT2_BCLK
TM0_TMR6
TM0_TMR7
SYS_IDLE1
SYS_IDLE0
Multiplexed Function 2
RSI0_D2
CAN0_TX
RSI0_D1
RSI0_D0
CAN0_RX
PWM1_SYNC
SPT2_BTDV
SYS_SLEEP
Rev. A | Page 36 of 112 | February 2014
Multiplexed Function
Input Tap
TM0_ACI2
ACM0_T1
PWM1_TRIP0
CNT0_ZM
PWM1_TRIP1
CNT0_UD
CNT0_DG
TM0_CLK
TM0_ACI1
TM0_ACI4
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x DESIGNER QUICK REFERENCE
The table provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• Reset Drive: The Reset Drive column in the table specifies
the active drive on the signal when the processor is in the
reset state.
• Signal Name: The Signal Name column in the table
includes the Signal Name for every pin.
• Type: The Pin Type column in the table identifies the I/O
type or supply type of the pin. The abbreviations used in
this column are na (None), I/O (Digital input and/or output), a (Analog), s (Supply), and g (Ground).
• Hiber Term: The Hibernate Termination column in the
table specifies the termination present when the processor
is in the hibernate state. The abbreviations used in this column are wk (Weak Keeper, weakly retains previous value
driven on the pin), pu (Pull-up resistor), or pd (Pull-down
resistor).
• Driver Type: The Driver Type column in the table identifies the driver type used by the pin. The driver types are
defined in Output Drive Currents on Page 102.
• Hiber Drive: The Hibernate Drive column in the table
specifies the active drive on the signal when the processor is
in the hibernate state.
• Int Term: The Internal Termination column in the table
specifies the termination present when the processor is not
in the reset or hibernate state. The abbreviations used in
this column are wk (Weak Keeper, weakly retains previous
value driven on the pin), pu (Pull-up resistor), or pd (Pulldown resistor).
• Power Domain: The Power Domain column in the table
specifies the power supply domain in which the signal
resides.
• Description and Notes: The Description and Notes column
in the table identifies any special requirements or characteristics for the signal. If no special requirements are listed
the signal may be left unconnected if it is not used. Also, for
multiplexed general-purpose I/O pins, this column identifies the functions available on the pin.
• Reset Term: The Reset Termination column in the table
specifies the termination present when the processor is in
the reset state. The abbreviations used in this column are
wk (Weak Keeper, weakly retains previous value driven on
the pin), pu (Pull-up resistor), or pd (Pull-down resistor).
Table 15. ADSP-BF60x Designer Quick Reference
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
B
Int
Term
none
none
none
none
none
VDD_DMC
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A02
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A03
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A04
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A05
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A06
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A07
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A08
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A09
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A10
I/O
B
none
none
none
none
none
VDD_DMC
Signal Name
DMC0_A00
Type
I/O
DMC0_A01
Driver
Type
Rev. A | Page 37 of 112 | February 2014
Description
and Notes
Desc: DMC0 Address 0.
Notes: No notes.
Desc: DMC0 Address 1.
Notes: No notes.
Desc: DMC0 Address 2.
Notes: No notes.
Desc: DMC0 Address 3.
Notes: No notes.
Desc: DMC0 Address 4.
Notes: No notes.
Desc: DMC0 Address 5.
Notes: No notes.
Desc: DMC0 Address 6.
Notes: No notes.
Desc: DMC0 Address 7.
Notes: No notes.
Desc: DMC0 Address 8.
Notes: No notes.
Desc: DMC0 Address 9.
Notes: No notes.
Desc: DMC0 Address 10.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
B
Int
Term
none
none
none
none
none
VDD_DMC
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_A13
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_BA0
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_BA1
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_BA2
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_CAS
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_CK
I/O
C
none
none
L
none
L
VDD_DMC
DMC0_CK
I/O
C
none
none
L
none
L
VDD_DMC
DMC0_CKE
I/O
B
none
none
L
none
L
VDD_DMC
DMC0_CS0
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ00
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ01
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ02
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ03
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ04
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ05
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ06
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ07
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ08
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ09
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ10
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ11
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ12
I/O
B
none
none
none
none
none
VDD_DMC
Signal Name
DMC0_A11
Type
I/O
DMC0_A12
Driver
Type
Rev. A | Page 38 of 112 | February 2014
Description
and Notes
Desc: DMC0 Address 11.
Notes: No notes.
Desc: DMC0 Address 12.
Notes: No notes.
Desc: DMC0 Address 13.
Notes: No notes.
Desc: DMC0 Bank Address Input 0.
Notes: No notes.
Desc: DMC0 Bank Address Input 1.
Notes: No notes.
Desc: DMC0 Bank Address Input 2.
Notes: For LPDDR, leave unconnected.
Desc: DMC0 Column Address Strobe.
Notes: No notes.
Desc: DMC0 Clock.
Notes: No notes.
Desc: DMC0 Clock (complement).
Notes: No notes.
Desc: DMC0 Clock enable.
Notes: No notes.
Desc: DMC0 Chip Select 0.
Notes: No notes.
Desc: DMC0 Data 0.
Notes: No notes.
Desc: DMC0 Data 1.
Notes: No notes.
Desc: DMC0 Data 2.
Notes: No notes.
Desc: DMC0 Data 3.
Notes: No notes.
Desc: DMC0 Data 4.
Notes: No notes.
Desc: DMC0 Data 5.
Notes: No notes.
Desc: DMC0 Data 6.
Notes: No notes.
Desc: DMC0 Data 7.
Notes: No notes.
Desc: DMC0 Data 8.
Notes: No notes.
Desc: DMC0 Data 9.
Notes: No notes.
Desc: DMC0 Data 10.
Notes: No notes.
Desc: DMC0 Data 11.
Notes: No notes.
Desc: DMC0 Data 12.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
B
Int
Term
none
none
none
none
none
VDD_DMC
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_DQ15
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_LDM
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_LDQS
I/O
C
none
none
none
none
none
VDD_DMC
DMC0_LDQS
I/O
C
none
none
none
none
none
VDD_DMC
DMC0_ODT
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_RAS
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_UDM
I/O
B
none
none
none
none
none
VDD_DMC
DMC0_UDQS
I/O
C
none
none
none
none
none
VDD_DMC
DMC0_UDQS
I/O
C
none
none
none
none
none
VDD_DMC
DMC0_WE
I/O
B
none
none
none
none
none
VDD_DMC
GND
g
na
none
none
none
none
none
na
JTG_EMU
I/O
A
none
none
none
none
none
VDD_EXT
JTG_TCK
I/O
na
pd
none
none
none
none
VDD_EXT
JTG_TDI
I/O
na
pu
none
none
none
none
VDD_EXT
JTG_TDO
I/O
A
none
none
none
none
none
VDD_EXT
JTG_TMS
I/O
na
pu
none
none
none
none
VDD_EXT
JTG_TRST
I/O
na
pd
none
none
none
none
VDD_EXT
Signal Name
DMC0_DQ13
Type
I/O
DMC0_DQ14
Driver
Type
Rev. A | Page 39 of 112 | February 2014
Description
and Notes
Desc: DMC0 Data 13.
Notes: No notes.
Desc: DMC0 Data 14.
Notes: No notes.
Desc: DMC0 Data 15.
Notes: No notes.
Desc: DMC0 Data Mask for Lower Byte.
Notes: No notes.
Desc: DMC0 Data Strobe for Lower Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
Desc: DMC0 Data Strobe for Lower Byte
(complement).
Notes: For single ended DDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
Desc: DMC0 On-die termination.
Notes: For LPDDR, leave unconnected.
Desc: DMC0 Row Address Strobe.
Notes: No notes.
Desc: DMC0 Data Mask for Upper Byte.
Notes: No notes.
Desc: DMC0 Data Strobe for Upper Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
Desc: DMC0 Data Strobe for Upper Byte
(complement).
Notes: For single ended DDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
Desc: DMC0 Write Enable.
Notes: No notes.
Desc: Ground.
Notes: No notes.
Desc: Emulation Output.
Notes: No notes.
Desc: JTG Clock.
Notes: Functional during reset.
Desc: JTG Serial Data Input.
Notes: Functional during reset.
Desc: JTG Serial Data Output.
Notes: Functional during reset, threestate when JTG_TRST is asserted.
Desc: JTG Mode Select.
Notes: Functional during reset.
Desc: JTG Reset.
Notes: Functional during reset.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_03
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_04
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_10
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_11
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_13
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_14
I/O
A
wk
wk
none
wk
none
VDD_EXT
PA_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PA_00
Type
I/O
PA_01
Driver
Type
Rev. A | Page 40 of 112 | February 2014
Description
and Notes
Desc: PA Position 0 | SMC0 Address 3 |
EPPI2 Data 0 | LP0 Data 0.
Notes: No notes.
Desc: PA Position 1 | SMC0 Address 4 |
EPPI2 Data 1 | LP0 Data 1.
Notes: No notes.
Desc: PA Position 2 | SMC0 Address 5 |
EPPI2 Data 2 | LP0 Data 2.
Notes: No notes.
Desc: PA Position 3 | SMC0 Address 6 |
EPPI2 Data 3 | LP0 Data 3.
Notes: No notes.
Desc: PA Position 4 | SMC0 Address 7 |
EPPI2 Data 4 | LP0 Data 4.
Notes: No notes.
Desc: PA Position 5 | SMC0 Address 8 |
EPPI2 Data 5 | LP0 Data 5.
Notes: No notes.
Desc: PA Position 6 | SMC0 Address 9 |
EPPI2 Data 6 | LP0 Data 6.
Notes: No notes.
Desc: PA Position 7 | SMC0 Address 10 |
EPPI2 Data 7 | LP0 Data 7.
Notes: No notes.
Desc: PA Position 8 | SMC0 Address 11 |
EPPI2 Data 8 | LP1 Data 0.
Notes: No notes.
Desc: PA Position 9 | SMC0 Address 12 |
EPPI2 Data 9 | LP1 Data 1.
Notes: No notes.
Desc: PA Position 10 | SMC0 Address 14 |
EPPI2 Data 10 | LP1 Data 2.
Notes: No notes.
Desc: PA Position 11 | SMC0 Address 15 |
EPPI2 Data 11 | LP1 Data 3.
Notes: No notes.
Desc: PA Position 12 | SMC0 Address 17 |
EPPI2 Data 12 | LP1 Data 4.
Notes: No notes.
Desc: PA Position 13 | SMC0 Address 18 |
EPPI2 Data 13 | LP1 Data 5.
Notes: No notes.
Desc: PA Position 14 | SMC0 Address 19 |
EPPI2 Data 14 | LP1 Data 6.
Notes: No notes.
Desc: PA Position 15 | SMC0 Address 20 |
EPPI2 Data 15 | LP1 Data 7.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_03
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_04
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_10
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_11
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PB_00
Type
I/O
PB_01
Driver
Type
Rev. A | Page 41 of 112 | February 2014
Description
and Notes
Desc: PB Position 0 | SMC0 NOR Clock |
EPPI2 Clock | LP0 Clock.
Notes: No notes.
Desc: PB Position 1 | SMC0 Memory Select
1 | EPPI2 Frame Sync 1 (HSYNC) | LP0
Acknowledge.
Notes: No notes.
Desc: PB Position 2 | SMC0 Address 13 |
EPPI2 Frame Sync 2 (VSYNC) | LP1
Acknowledge.
Notes: No notes.
Desc: PB Position 3 | SMC0 Address 16 |
EPPI2 Frame Sync 3 (FIELD) | LP1 Clock.
Notes: No notes.
Desc: PB Position 4 | SMC0 Memory Select
2 | SMC0 Byte Enable 0 | SPORT0 Channel
A Frame Sync.
Notes: No notes.
Desc: PB Position 5 | SMC0 Memory Select
3 | SMC0 Byte Enable 1 | SPORT0 Channel
A Clock.
Notes: No notes.
Desc: PB Position 6 | SMC0 Address 21 |
SPORT0 Channel A Transmit Data Valid |
TIMER0 Alternate Clock 4.
Notes: No notes.
Desc: PB Position 7 | SMC0 Address 22 |
EPPI2 Data 16 | SPORT0 Channel B Frame
Sync.
Notes: No notes.
Desc: PB Position 8 | SMC0 Address 23 |
EPPI2 Data 17 | SPORT0 Channel B Clock.
Notes: No notes.
Desc: PB Position 9 | SMC0 Bus Grant
Hang | SPORT0 Channel A Data 0 | TIMER0
Alternate Clock 2.
Notes: No notes.
Desc: PB Position 10 | SMC0 Address 24 |
SPORT0 Channel B Data 1 | TIMER0
Alternate Clock 0.
Notes: No notes.
Desc: PB Position 11 | SMC0 Address 25 |
SPORT0 Channel B Data 0 | TIMER0
Alternate Clock 3.
Notes: No notes.
Desc: PB Position 12 | SMC0 Bus Grant |
SPORT0 Channel B Transmit Data Valid |
SPORT0 Channel A Data 1 | TIMER0
Alternate Clock 1.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PB_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_00
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_01
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_03
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_04
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_10
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_11
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PB_13
Type
I/O
PB_14
Driver
Type
Rev. A | Page 42 of 112 | February 2014
Description
and Notes
Desc: PB Position 13 | EPPI1 Frame Sync 1
(HSYNC) | ETH0 Transmit Enable | TIMER0
Alternate Capture Input 6.
Notes: No notes.
Desc: PB Position 14 | EPPI1 Clock | ETH0
Reference Clock.
Notes: No notes.
Desc: PB Position 15 | EPPI1 Frame Sync 3
(FIELD) | ETH0 PTP Pulse-Per-Second
Output.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
Desc: PC Position 0 | EPPI1 Data 0 | ETH0
Receive Data 0.
Notes: No notes.
Desc: PC Position 1 | EPPI1 Data 1 | ETH0
Receive Data 1.
Notes: No notes.
Desc: PC Position 2 | EPPI1 Data 2 | ETH0
Transmit Data 0.
Notes: No notes.
Desc: PC Position 3 | EPPI1 Data 3 | ETH0
Transmit Data 1.
Notes: No notes.
Desc: PC Position 4 | EPPI1 Data 4 | ETH0
Receive Error.
Notes: No notes.
Desc: PC Position 5 | EPPI1 Data 5 | ETH0
Carrier Sense/RMII Receive Data Valid.
Notes: No notes.
Desc: PC Position 6 | EPPI1 Data 6 | ETH0
Management Channel Clock.
Notes: No notes.
Desc: PC Position 7 | EPPI1 Data 7 | ETH0
Management Channel Serial Data.
Notes: No notes.
Desc: PC Position 8 | EPPI1 Data 8.
Notes: No notes.
Desc: PC Position 9 | EPPI1 Data 9 | ETH1
PTP Pulse-Per-Second Output.
Notes: No notes.
Desc: PC Position 10 | EPPI1 Data 10.
Notes: No notes.
Desc: PC Position 11 | EPPI1 Data 11 | ETH
PTP Auxiliary Trigger Input.
Notes: No notes.
Desc: PC Position 12 | SPI0 Slave Select
Output b | EPPI1 Data 12.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PC_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_00
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_01
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_03
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_04
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_10
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_11
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PC_13
Type
I/O
PC_14
Driver
Type
Rev. A | Page 43 of 112 | February 2014
Description
and Notes
Desc: PC Position 13 | SPI0 Slave Select
Output b | EPPI1 Data 13 | ETH PTP Clock
Input.
Notes: No notes.
Desc: PC Position 14 | SPI1 Slave Select
Output b | EPPI1 Data 14.
Notes: No notes.
Desc: PC Position 15 | SPI0 Slave Select
Output b | EPPI1 Data 15.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
Desc: PD Position 0 | SPI0 Data 2 | EPPI1
Data 16 | SPI0 Slave Select Output b.
Notes: No notes.
Desc: PD Position 1 | SPI0 Data 3 | EPPI1
Data 17 | SPI0 Slave Select Output b.
Notes: No notes.
Desc: PD Position 2 | SPI0 Master In, Slave
Out.
Notes: No notes.
Desc: PD Position 3 | SPI0 Master Out,
Slave In.
Notes: No notes.
Desc: PD Position 4 | SPI0 Clock.
Notes: No notes.
Desc: PD Position 5 | SPI1 Clock | TIMER0
Alternate Clock 7.
Notes: No notes.
Desc: PD Position 6 | EPPI1 Frame Sync 2
(VSYNC) | ETH0 RMII Management Data
Interrupt | TIMER0 Alternate Capture
Input 5.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
Desc: PD Position 7 | UART0 Transmit |
TIMER0 Alternate Capture Input 3.
Notes: No notes.
Desc: PD Position 8 | UART0 Receive |
TIMER0 Alternate Capture Input 0.
Notes: No notes.
Desc: PD Position 9 | SPI1 Slave Select
Output b | UART0 Request to Send | SPI0
Slave Select Output b.
Notes: No notes.
Desc: PD Position 10 | SPI0 Ready | UART0
Clear to Send | SPI1 Slave Select Output b.
Notes: No notes.
Desc: PD Position 11 | SPI0 Slave Select
Output b | SPI0 Slave Select Input.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_14
I/O
A
wk
wk
none
wk
none
VDD_EXT
PD_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_00
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_01
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_03
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_04
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PD_12
Type
I/O
PD_13
Driver
Type
Rev. A | Page 44 of 112 | February 2014
Description
and Notes
Desc: PD Position 12 | SPI1 Slave Select
Output b | EPPI0 Data 20 | SPORT1
Channel A Data 1 | SPI1 Slave Select Input.
Notes: No notes.
Desc: PD Position 13 | SPI1 Master Out,
Slave In | TIMER0 Alternate Clock 5.
Notes: No notes.
Desc: PD Position 14 | SPI1 Master In, Slave
Out | TIMER0 Alternate Clock 6.
Notes: No notes.
Desc: PD Position 15 | SPI1 Slave Select
Output b | EPPI0 Data 21 | SPORT1
Channel A Data 0.
Notes: No notes.
Desc: PE Position 0 | SPI1 Data 3 | EPPI0
Data 18 | SPORT1 Channel B Data 1.
Notes: No notes.
Desc: PE Position 1 | SPI1 Data 2 | EPPI0
Data 19 | SPORT1 Channel B Data 0.
Notes: No notes.
Desc: PE Position 2 | SPI1 Ready | EPPI0
Data 22 | SPORT1 Channel A Clock.
Notes: No notes.
Desc: PE Position 3 | EPPI0 Data 16 |
SPORT1 Channel B Frame Sync | ACM0
Frame Sync.
Notes: No notes.
Desc: PE Position 4 | EPPI0 Data 17 |
SPORT1 Channel B Clock | ACM0 Clock.
Notes: No notes.
Desc: PE Position 5 | EPPI0 Data 23 |
SPORT1 Channel A Frame Sync.
Notes: No notes.
Desc: PE Position 6 | SPORT1 Channel A
Transmit Data Valid | EPPI0 Frame Sync 3
(FIELD) | LP3 Clock.
Notes: No notes.
Desc: PE Position 7 | SPORT1 Channel B
Transmit Data Valid | EPPI0 Frame Sync 2
(VSYNC) | LP3 Acknowledge.
Notes: No notes.
Desc: PE Position 8 | PWM0 Sync | EPPI0
Frame Sync 1 (HSYNC) | LP2
Acknowledge | ACM0 External Trigger 0.
Notes: No notes.
Desc: PE Position 9 | EPPI0 Clock | LP2
Clock | PWM0 Shutdown Input.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_13
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_14
I/O
A
wk
wk
none
wk
none
VDD_EXT
PE_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_00
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_01
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PE_10
Type
I/O
PE_11
Driver
Type
Rev. A | Page 45 of 112 | February 2014
Description
and Notes
Desc: PE Position 10 | PWM1 Channel D
Low Side | RSI0 Data 6 | ETH1
Management Channel Clock.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PE Position 11 | PWM1 Channel D
High Side | ETH1 Management Channel
Serial Data | RSI0 Data 7.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PE Position 12 | PWM1 Channel C
Low Side | RSI0 Data 5 | ETH1 RMII
Management Data Interrupt.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details. May be used to
wake the processor from hibernate or
deep sleep mode.
Desc: PE Position 13 | PWM1 Channel C
High Side | RSI0 Data 4 | ETH1 Carrier
Sense/RMII Receive Data Valid.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PE Position 14 | SPORT2 Channel A
Transmit Data Valid | TIMER0 Timer 0 |
ETH1 Receive Error.
Notes: No notes.
Desc: PE Position 15 | PWM1 Channel B
Low Side | RSI0 Data 3 | ETH1 Receive
Data 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PF Position 0 | PWM0 Channel A Low
Side | EPPI0 Data 0 | LP2 Data 0.
Notes: No notes.
Desc: PF Position 1 | PWM0 Channel A
High Side | EPPI0 Data 1 | LP2 Data 1.
Notes: No notes.
Desc: PF Position 2 | PWM0 Channel B Low
Side | EPPI0 Data 2 | LP2 Data 2.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_10
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_11
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_13
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_14
I/O
A
wk
wk
none
wk
none
VDD_EXT
PF_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_00
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_01
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PF_03
Type
I/O
PF_04
Driver
Type
Rev. A | Page 46 of 112 | February 2014
Description
and Notes
Desc: PF Position 3 | PWM0 Channel B
High Side | EPPI0 Data 3 | LP2 Data 3.
Notes: No notes.
Desc: PF Position 4 | PWM0 Channel C Low
Side | EPPI0 Data 4 | LP2 Data 4.
Notes: No notes.
Desc: PF Position 5 | PWM0 Channel C
High Side | EPPI0 Data 5 | LP2 Data 5.
Notes: No notes.
Desc: PF Position 6 | PWM0 Channel D
Low Side | EPPI0 Data 6 | LP2 Data 6.
Notes: No notes.
Desc: PF Position 7 | PWM0 Channel D
High Side | EPPI0 Data 7 | LP2 Data 7.
Notes: No notes.
Desc: PF Position 8 | SPI1 Slave Select
Output b | EPPI0 Data 8 | LP3 Data 0.
Notes: No notes.
Desc: PF Position 9 | SPI1 Slave Select
Output b | EPPI0 Data 9 | LP3 Data 1.
Notes: No notes.
Desc: PF Position 10 | ACM0 Address 4 |
EPPI0 Data 10 | LP3 Data 2.
Notes: No notes.
Desc: PF Position 11 | EPPI0 Data 11 | LP3
Data 3 | PWM0 Shutdown Input.
Notes: No notes.
Desc: PF Position 12 | ACM0 Address 2 |
EPPI0 Data 12 | LP3 Data 4.
Notes: No notes.
Desc: PF Position 13 | ACM0 Address 3 |
EPPI0 Data 13 | LP3 Data 5.
Notes: No notes.
Desc: PF Position 14 | EPPI0 Data 14 |
ACM0 Address 0 | LP3 Data 6.
Notes: No notes.
Desc: PF Position 15 | ACM0 Address 1 |
EPPI0 Data 15 | LP3 Data 7.
Notes: No notes.
Desc: PG Position 0 | PWM1 Channel B
High Side | RSI0 Data 2 | ETH1 Receive
Data 0.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PG Position 1 | SPORT2 Channel A
Frame Sync | TIMER0 Timer 2 | CAN0
Transmit.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_04
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_05
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_07
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_08
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_09
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_10
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_11
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PG_02
Type
I/O
PG_03
Driver
Type
Rev. A | Page 47 of 112 | February 2014
Description
and Notes
Desc: PG Position 2 | PWM1 Channel A
Low Side | RSI0 Data 1 | ETH1 Transmit
Data 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PG Position 3 | PWM1 Channel A
High Side | RSI0 Data 0 | ETH1 Transmit
Data 0.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PG Position 4 | SPORT2 Channel A
Clock | TIMER0 Timer 1 | CAN0 Receive |
TIMER0 Alternate Capture Input 2.
Notes: May be used to wake the processor
from hibernate or deep sleep mode.
Desc: PG Position 5 | RSI0 Command |
ETH1 Transmit Enable | PWM1 Sync |
ACM0 External Trigger 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PG Position 6 | RSI0 Clock | SPORT2
Channel B Transmit Data Valid | ETH1
Reference Clock | PWM1 Shutdown Input.
Notes: No notes.
Desc: PG Position 7 | SPORT2 Channel B
Frame Sync | TIMER0 Timer 5 | CNT0 Count
Zero Marker.
Notes: No notes.
Desc: PG Position 8 | SPORT2 Channel A
Data 1 | TIMER0 Timer 3 | PWM1
Shutdown Input.
Notes: No notes.
Desc: PG Position 9 | SPORT2 Channel A
Data 0 | TIMER0 Timer 4.
Notes: No notes.
Desc: PG Position 10 | UART1 Request to
Send | SPORT2 Channel B Clock.
Notes: No notes.
Desc: PG Position 11 | SPORT2 Channel B
Data 1 | TIMER0 Timer 6 | CNT0 Count Up
and Direction.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_14
I/O
A
wk
wk
none
wk
none
VDD_EXT
PG_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_A01
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_A02
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_AMS0
I/O
A
pu
pu
none
pu
none
VDD_EXT
SMC0_AOE_
NORDV
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_ARDY_
NORWT
I/O
na
none
none
none
none
none
VDD_EXT
SMC0_ARE
I/O
A
pu
pu
none
pu
none
VDD_EXT
SMC0_AWE
I/O
A
pu
pu
none
pu
none
VDD_EXT
SMC0_BR
I/O
na
none
none
none
none
none
VDD_EXT
SMC0_D00
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D01
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D02
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D03
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D04
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D05
I/O
A
wk
wk
none
wk
none
VDD_EXT
Signal Name
PG_12
Type
I/O
PG_13
Driver
Type
Rev. A | Page 48 of 112 | February 2014
Description
and Notes
Desc: PG Position 12 | SPORT2 Channel B
Data 0 | TIMER0 Timer 7 | CNT0 Count
Down and Gate.
Notes: No notes.
Desc: PG Position 13 | UART1 Clear to
Send | TIMER0 Clock.
Notes: No notes.
Desc: PG Position 14 | UART1 Receive | SYS
Core 1 Idle Indicator | TIMER0 Alternate
Capture Input 1.
Notes: No notes.
Desc: PG Position 15 | UART1 Transmit |
SYS Core 0 Idle Indicator | SYS Processor
Sleep Indicator | TIMER0 Alternate
Capture Input 4.
Notes: No notes.
Desc: SMC0 Address 1.
Notes: No notes.
Desc: SMC0 Address 2.
Notes: No notes.
Desc: SMC0 Memory Select 0.
Notes: No notes.
Desc: SMC0 NOR Data Valid | SMC0
Output Enable.
Notes: No notes.
Desc: SMC0 NOR Wait | SMC0
Asynchronous Ready.
Notes: Requires an external pull-up
resistor.
Desc: SMC0 Read Enable.
Notes: No notes.
Desc: SMC0 Write Enable.
Notes: No notes.
Desc: SMC0 Bus Request.
Notes: Requires an external pull-up
resistor.
Desc: SMC0 Data 0.
Notes: No notes.
Desc: SMC0 Data 1.
Notes: No notes.
Desc: SMC0 Data 2.
Notes: No notes.
Desc: SMC0 Data 3.
Notes: No notes.
Desc: SMC0 Data 4.
Notes: No notes.
Desc: SMC0 Data 5.
Notes: No notes.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
A
Int
Term
wk
wk
none
wk
none
VDD_EXT
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D08
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D09
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D10
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D11
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D12
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D13
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D14
I/O
A
wk
wk
none
wk
none
VDD_EXT
SMC0_D15
I/O
A
wk
wk
none
wk
none
VDD_EXT
SYS_BMODE0
I/O
na
none
none
none
none
none
VDD_EXT
SYS_BMODE1
I/O
na
none
none
none
none
none
VDD_EXT
SYS_BMODE2
I/O
na
none
none
none
none
none
VDD_EXT
SYS_CLKIN
a
na
none
none
none
none
none
VDD_EXT
SYS_CLKOUT
I/O
A
none
none
L
none
none
VDD_EXT
SYS_EXTWAKE I/O
A
none
none
H
none
L
VDD_EXT
SYS_FAULT
I/O
A
none
none
none
none
none
VDD_EXT
SYS_FAULT
I/O
A
none
none
none
none
none
VDD_EXT
SYS_HWRST
I/O
na
none
none
none
none
none
VDD_EXT
SYS_NMI_
RESOUT
I/O
A
none
none
L
none
none
VDD_EXT
Signal Name
SMC0_D06
Type
I/O
SMC0_D07
Driver
Type
Rev. A | Page 49 of 112 | February 2014
Description
and Notes
Desc: SMC0 Data 6.
Notes: No notes.
Desc: SMC0 Data 7.
Notes: No notes.
Desc: SMC0 Data 8.
Notes: No notes.
Desc: SMC0 Data 9.
Notes: No notes.
Desc: SMC0 Data 10.
Notes: No notes.
Desc: SMC0 Data 11.
Notes: No notes.
Desc: SMC0 Data 12.
Notes: No notes.
Desc: SMC0 Data 13.
Notes: No notes.
Desc: SMC0 Data 14.
Notes: No notes.
Desc: SMC0 Data 15.
Notes: No notes.
Desc: SYS Boot Mode Control 0.
Notes: No notes.
Desc: SYS Boot Mode Control 1.
Notes: No notes.
Desc: SYS Boot Mode Control 2.
Notes: No notes.
Desc: SYS Clock Input/Crystal Input.
Notes: Active during reset.
Desc: SYS Processor Clock Output.
Notes: No notes.
Desc: SYS External Wake Control.
Notes: Drives low during hibernate and
high all other times.
Desc: SYS Fault.
Notes: Open source, requires an external
pull-down resistor.
Desc: SYS Complementary Fault.
Notes: Open drain, requires an external
pull-up resistor.
Desc: SYS Processor Hardware Reset
Control.
Notes: Active during reset.
Desc: SYS Reset Output | SYS Nonmaskable Interrupt.
Notes: Requires an external pull-up
resistor.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
na
Int
Term
none
none
none
none
none
VDD_EXT
a
na
none
none
none
none
none
VDD_TD
SYS_TDK
a
na
none
none
none
none
none
VDD_TD
SYS_XTAL
a
na
none
none
none
none
none
VDD_EXT
TWI0_SCL
I/O
D
none
none
none
none
none
VDD_EXT
TWI0_SDA
I/O
D
none
none
none
none
none
VDD_EXT
TWI1_SCL
I/O
D
none
none
none
none
none
VDD_EXT
TWI1_SDA
I/O
D
none
none
none
none
none
VDD_EXT
USB0_CLKIN
a
na
none
none
none
none
none
VDD_USB
USB0_DM
I/O
F
none
none
none
none
none
VDD_USB
Signal Name
SYS_PWRGD
Type
I/O
SYS_TDA
Driver
Type
Rev. A | Page 50 of 112 | February 2014
Description
and Notes
Desc: SYS Power Good Indicator.
Notes: If hibernate is not used or the
internal Power Good Counter is used,
connect to VDD_EXT.
Desc: SYS Thermal Diode Anode.
Notes: Active during reset and hibernate.
If the thermal diode is not used, connect
to ground.
Desc: SYS Thermal Diode Cathode.
Notes: Active during reset and hibernate.
If the thermal diode is not used, connect
to ground.
Desc: SYS Crystal Output.
Notes: Leave unconnected if an oscillator
is used to provide SYS_CLKIN. Active
during reset. State during hibernate is
controlled by DPM_HIB_DIS.
Desc: TWI0 Serial Clock.
Notes: Open drain, requires external pullup resistor. Consult Version 2.1 of the I2C
specification for the proper resistor value.
If TWI is not used, connect to ground.
Desc: TWI0 Serial Data.
Notes: Open drain, requires external pullup resistor. Consult Version 2.1 of the I2C
specification for the proper resistor value.
If TWI is not used, connect to ground.
Desc: TWI1 Serial Clock.
Notes: Open drain, requires external pullup resistor. Consult Version 2.1 of the I2C
specification for the proper resistor value.
If TWI is not used, connect to ground.
Desc: TWI1 Serial Data.
Notes: Open drain, requires external pullup resistor. See the I2C-Bus Specification,
Version 2.1,January 2000 for the proper
resistor value. If TWI is not used, connect
to ground.
Desc: USB0 Clock/Crystal Input.
Notes: If USB is not used, connect to
ground. Active during reset.
Desc: USB0 Data –.
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the processor hardware
reference.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
F
Int
Term
none
none
none
none
none
VDD_USB
I/O
na
none
none
none
pu
none
VDD_USB
USB0_VBC
I/O
E
none
none
none
wk
none
VDD_USB
USB0_VBUS
I/O
G
none
none
none
none
none
VDD_USB
VDD_DMC
s
na
none
none
none
none
none
na
VDD_EXT
s
na
none
none
none
none
none
na
VDD_INT
s
na
none
none
none
none
none
na
VDD_TD
s
na
none
none
none
none
none
na
VDD_USB
s
na
none
none
none
none
none
na
VREF_DMC
s
na
none
none
none
none
none
na
Signal Name
USB0_DP
Type
I/O
USB0_ID
Driver
Type
Rev. A | Page 51 of 112 | February 2014
Description
and Notes
Desc: USB0 Data +.
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the processor hardware
reference.
Desc: USB0 OTG ID.
Notes: If USB is not used, connect to
ground. When USB is being used, the
internal pull-up resistor that is present
during hibernate is programmable. See
the USB chapter in the processor
hardware reference. Active during reset.
Desc: USB0 VBUS Control.
Notes: If USB is not used, pull low.
Desc: USB0 Bus Voltage.
Notes: If USB is not used, connect to
ground.
Desc: VDD for DMC.
Notes: If the DMC is not used, connect to
VDD_INT.
Desc: External VDD.
Notes: Must be powered.
Desc: Internal VDD.
Notes: Must be powered.
Desc: VDD for Thermal Diode.
Notes: If the thermal diode is not used,
connect to ground.
Desc: VDD for USB.
Notes: If USB is not used, connect to VDD_
EXT.
Desc: VREF for DMC.
Notes: If the DMC is not used, connect to
VDD_INT.
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPECIFICATIONS
For information about product specifications please contact
your ADI representative.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
Internal Supply Voltage
CCLK ≤ 500 MHz
1.19
1.25
1.32
V
VDD_EXT1
External Supply Voltage
1.8 V I/O
1.7
1.8
1.9
V
1
External Supply Voltage
3.3 V I/O
VDD_INT
VDD_EXT
VDD_DMC
VDD_USB
2
3.13
3.3
3.47
V
DDR2/LPDDR Supply Voltage
1.7
1.8
1.9
V
USB Supply Voltage
3.13
3.3
3.47
V
3.13
3.3
3.47
V
VDD_TD
Thermal Diode Supply Voltage
VIH3
High Level Input Voltage
VDD_EXT = 3.47 V
2.1
V
High Level Input Voltage
VDD_EXT = 1.9 V
0.7 × VDD_EXT
V
VIH
3
VIHTWI
4, 5
High Level Input Voltage
VIH_DDR26, 7
VIH_LPDDR
8
VDD_EXT = Maximum
0.7 × VVBUSTWI
VDD_DMC = 1.9 V
VDDR_REF + 0.25
VVBUSTWI
V
V
VDD_DMC = 1.9 V
0.8 × VDD_DMC
V
9
Differential Input Voltage
VIX = 1.075 V
0.50
V
VID_DDR29
Differential Input Voltage
VIX = 0.725 V
0.55
V
Low Level Input Voltage
VDD_EXT = 3.13 V
0.8
V
Low Level Input Voltage
VDD_EXT = 1.7 V
0.3 × VDD_EXT
V
VID_DDR2
VIL
3
VIL
3
VILTWI
4, 5
VDD_EXT = Minimum
0.3 × VVBUSTWI
V
VIL_DDR26, 7
Low Level Input Voltage
VDD_DMC = 1.7 V
VDDR_REF – 0.25
V
VIL_LPDDR8
VDD_DMC = 1.7 V
0.2 × VDD_DMC
V
TJ
Junction Temperature
TAMBIENT = 0°C to +70°C
0
+105
°C
TJ
Junction Temperature
TAMBIENT = –40°C to +85°C
–40
+105
°C
TJ
Junction Temperature
TAMBIENT = –40°C to +105°C
–40
+125
°C
1
Must remain powered (even if the associated function is not used).
If not used, connect to 1.8 V or 3.3 V.
3
Parameter value applies to all input and bidirectional signals except TWI signals, DMC0 signals and USB0 signals.
4
Parameter applies to TWI signals.
5
TWI signals are pulled up to VBUSTWI. See Table 16.
6
Parameter applies to DMC0 signals in DDR2 mode.
7
VDDR_REF is the voltage applied to pin VREF_DMC, nominally VDD_DMC/2.
8
Parameter applies to DMC0 signals in LPDDR mode.
9
Parameter applies to signals DMC0_CK, DMC0_CK, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode.
2
Table 16. TWI_VSEL Selections and VDD_EXT/VBUSTWI
VDD_EXT Nominal
VBUSTWI Min
VBUSTWI Nom
VBUSTWI Max
Unit
3.30
3.13
3.30
3.47
V
TWI001
1.80
1.70
1.80
1.90
V
TWI011
1.80
3.13
3.30
3.47
V
TWI100
3.30
4.75
5.00
5.25
V
TWI000
1
1
Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.
Rev. A | Page 52 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Clock Related Operating Conditions
Table 17 describes the core clock, system clock, and peripheral
clock timing requirements. The data presented in the tables
applies to all speed grades (found in Automotive Products on
Page 112 and Ordering Guide on Page 112) except where
expressly noted. Figure 8 provides a graphical representation of
the various clocks and their available divider values.
Table 17. Clock Operating Conditions
Parameter
Restriction
fCCLK
Core Clock Frequency
fSYSCLK
SYSCLK Frequency
Min
Typ
fCCLK ≥ fSYSCLK
1
Max
Unit
500
MHz
250
MHz
125
MHz
fSCLK0
SCLK0 Frequency
fSCLK1
SCLK1 Frequency
fSYSCLK ≥ fSCLK1
125
MHz
fDCLK
DDR2/LPDDR Clock Frequency
fSYSCLK ≥ fDCLK
250
MHz
fOCLK
Output Clock Frequency
125
MHz
fSYSCLK ≥ fSCLK0
30
2, 3
fSYS_CLKOUTJ
SYS_CLKOUT Period Jitter
fPVPCLK
PVP Clock Frequency
83.3
MHz
fNRCLKPROG
Programmed NOR Burst Clock
66.67
MHz
fPCLKPROG
Programmed PPI Clock When Transmitting Data and Frame Sync
83.3
MHz
fPCLKPROG
Programmed PPI Clock When Receiving Data or Frame Sync
fPCLKEXT
External PPI Clock When Receiving Data and Frame Sync4, 5
±1
4, 5
fPCLKEXT
External PPI Clock Transmitting Data or Frame Sync
fLCLKTPROG
Programmed Link Port Transmit Clock
fLCLKREXT
External Link Port Receive Clock4, 5
fSPTCLKPROG
Programmed SPT Clock When Transmitting Data and Frame Sync
%
62.5
MHz
fPCLKEXT ≤ fSCLK0
83.3
MHz
fPCLKEXT ≤ fSCLK0
58.8
MHz
83.3
MHz
83.3
MHz
83.3
MHz
fLCLKEXT ≤ fSCLK0
fSPTCLKPROG
Programmed SPT Clock When Receiving Data or Frame Sync
62.5
MHz
fSPTCLKEXT
External SPT Clock When Receiving Data and Frame Sync4, 5
fSPTCLKEXT ≤ fSCLK1
83.3
MHz
fSPTCLKEXT
External SPT Clock Transmitting Data or Frame Sync4, 5
fSPTCLKEXT ≤ fSCLK1
58.8
MHz
fSPICLKPROG
Programmed SPI Clock When Transmitting Data
83.3
MHz
fSPICLKPROG
Programmed SPI Clock When Receiving Data
75
MHz
fSPICLKEXT
External SPI Clock When Receiving Data4, 5
fSPICLKEXT ≤ fSCLK1
83.3
MHz
fSPICLKEXT ≤ fSCLK1
58.8
MHz
62.5
MHz
fSPICLKEXT
External SPI Clock When Transmitting Data
fACLKPROG
Programmed ACM Clock
4, 5
1
The minimum frequency for SCLK0 applies only when the USB is used.
2
SYS_CLKOUT jitter is dependent on the application system design including pin switching activity, board layout, and the jitter characteristics of the SYS_CLKIN source.
Due to the dependency on these factors the measured jitter may be higher or lower than this typical specification for each end application.
3
The value in the Typ field is the percentage of the SYS_CLKOUT period.
4
The maximum achievable frequency for any peripheral in external clock mode is dependent on being able to meet the setup and hold times in the AC timing specifications
section for that peripheral. Pay particular attention to setup and hold times for VDD_EXT = 1.8 V which may preclude the maximum frequency listed here.
5
The peripheral external clock frequency must also be less than or equal to the fSCLK (fSCLK0 or fSCLK1) that clocks the peripheral.
Table 18. Phase-Locked Loop Operating Conditions
Parameter
fPLLCLK
Min
250
PLL Clock Frequency
Rev. A | Page 53 of 112 | February 2014
Max
1000
Unit
MHz
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
CSEL
(1-32)
SYSSEL
(1-32)
SYS_CLKIN
PLL
CCLK
S0SEL
(1-8)
SCLK0
(PVP, ALL OTHER
PERIPHERALS)
S1SEL
(1-8)
SCLK1
(SPORTS, SPI, ACM)
SYSCLK
PLLCLK
DSEL
(1-32)
DCLK
OSEL
(1-128)
OCLK
Figure 8. Clock Relationships and Divider Values
Rev. A | Page 54 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ELECTRICAL CHARACTERISTICS
Parameter
VOH1
VOH1
VOH_DDR22
VOH_DDR23
VOH_LPDDR4
VOH_LPDDR5
VOH_LPDDR6
VOH_LPDDR7
VOL8
VOL8
VOL_DDR22
VOL_DDR23
VOL_LPDDR4
VOL_LPDDR5
VOL_LPDDR6
VOL_LPDDR7
IIH9
IIH_PD10
IIL11
IIL_PU12
IIH_USB013
IIL_USB013
IOZH14
IOZH15
IOZL16
IOZL_PU17
IOZH_TWI18
CIN19, 20
CIN_TWI18, 20
CIN_DDR20, 21
IDD_TD
IDD_DEEPSLEEP22, 23
Test Conditions
VDD_EXT = 1.7 V, IOH = –0.5 mA
VDD_EXT = 3.13 V, IOH = –0.5 mA
VDD_DMC = 1.70 V, IOH = –13.4 mA
VDD_DMC = 1.70 V, IOH = –6.70 mA
VDD_DMC = 1.70 V, IOH = –11.2 mA
VDD_DMC = 1.70 V, IOH = –7.85 mA
VDD_DMC = 1.70 V, IOH = –5.10 mA
VDD_DMC = 1.70 V, IOH = –2.55 mA
VDD_EXT = 1.7 V, IOL = 2.0 mA
VDD_EXT = 3.13 V, IOL = 2.0 mA
VDD_DMC = 1.70 V, IOL13.4 mA
VDD_DMC = 1.70 V, IOL = 6.70 mA
VDD_DMC = 1.70 V, IOL = 11.2 mA
VDD_DMC = 1.70 V, IOL = 7.85 mA
VDD_DMC = 1.70 V, IOL = 5.10 mA
VDD_DMC = 1.70 V, IOL = 2.55 mA
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 3.47 V
High Level Input Current with Pull- VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
down Resistor
VDD_USB = 3.47 V, VIN = 3.47 V
Low Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 0 V
Low Level Input Current with Pull-up VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
Resistor
VDD_USB = 3.47 V, VIN = 0 V
High Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 3.47 V
Low Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 0 V
Three-State Leakage Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 3.47 V
Three-State Leakage Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 1.9 V
Three-State Leakage Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 0 V
Three-State Leakage Current with VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
Pull-up Resistor
VDD_USB = 3.47 V, VIN = 0 V
Three-State Leakage Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V,
VDD_USB = 3.47 V, VIN = 5.5 V
Input Capacitance
TAMBIENT = 25°C
Input Capacitance
TAMBIENT = 25°C
Input Capacitance
TAMBIENT = 25°C
VDD_TD Current
VDD_TD = 3.3 V
VDD_INT Current in Deep Sleep Mode fCCLK = 0 MHz
fSCLK0/1 = 0 MHz
High Level Output Voltage
High Level Output Voltage
High Level Output Voltage, ds = 00
High Level Output Voltage, ds = 10
High Level Output Voltage, ds = 00
High Level Output Voltage, ds = 01
High Level Output Voltage, ds = 10
High Level Output Voltage, ds = 11
Low Level Output Voltage
Low Level Output Voltage
Low Level Output Voltage, ds = 00
Low Level Output Voltage, ds = 10
Low Level Output Voltage, ds = 00
Low Level Output Voltage, ds = 01
Low Level Output Voltage, ds = 10
Low Level Output Voltage, ds = 11
High Level Input Current
Min
VDD_EXT – 0.40
VDD_EXT – 0.40
1.388
1.311
1.300
1.300
1.300
1.300
Rev. A | Page 55 of 112 | February 2014
Typical
4.9
8.9
5.8
Table 21 on
Page 58
Max
0.400
0.400
0.312
0.390
0.400
0.400
0.400
0.400
10
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
110
μA
10
μA
100
μA
240
μA
100
μA
10
μA
10
μA
10
μA
100
μA
10
μA
6.7
9.9
6.6
1
pF
pF
pF
μA
mA
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Parameter
IDD_IDLE23
VDD_INT Current in Idle
IDD_TYP23
VDD_INT Current
IDD_HIBERNATE22, 24 Hibernate State Current
IDD_HIBERNATE22, 24 Hibernate State Current
Without USB
IDD_INT23
VDD_INT Current
Test Conditions
Min
fCCLK = 500 MHz
ASFC0 = 0.14 (Idle)
ASFC1 = 0 (Disabled)
fSYSCLK = 250 MHz, fSCLK0/1 = 125 MHz
fDCLK = 0 MHz (DDR Disabled)
fUSBCLK = 0 MHz (USB Disabled)
No PVP or DMA activity
TJ = 25°C
fCCLK = 500 MHz
ASFC0 = 1.0 (Full-on Typical)
ASFC1 = 0.86 (App)
fSYSCLK = 250 MHz, fSCLK0/1 = 125 MHz
fDCLK = 250 MHz
fUSBCLK = 0 MHz (USB Disabled)
DMA Data Rate = 124 MB/s
Medium PVP Activity
TJ = 25°C
VDD_INT = 0 V,
VDD_EXT = VDD_TD = VDD_USB = 3.3 V,
VDD_DMC = 1.8 V, VREF_DMC = 0.9 V,
TJ = 25°C, fCLKIN = 0 MHz
VDD_INT = 0 V,
VDD_EXT = VDD_TD = VDD_USB = 3.3 V,
VDD_DMC = 1.8 V, VREF_DMC = 0.9 V,
TJ = 25°C,
fCLKIN = 0 MHz, USB protection
disabled (USB0_PHY_CTL.DIS=1)
fCCLK > 0 MHz
fSCLK0/1 ≥ 0 MHz
1
Typical
137
Max
Unit
mA
357
mA
40
μA
10
μA
See IDDINT_TOT
equation
on Page 57
mA
Applies to all output and bidirectional signals except DMC0 signals, TWI signals and USB0 signals.
Applies to all DMC0 output and bidirectional signals in DDR2 full drive strength mode.
3
Applies to all DMC0 output and bidirectional signals in DDR2 half drive strength mode.
4
Applies to all DMC0 output and bidirectional signals in LPDDR full drive strength mode.
5
Applies to all DMC0 output and bidirectional signals in LPDDR three-quarter drive strength mode.
6
Applies to all DMC0 output and bidirectional signals in LPDDR half drive strength mode.
7
Applies to all DMC0 output and bidirectional signals in LPDDR one-quarter drive strength mode.
8
Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.
9
Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TDI, and JTG_TMS.
10
Applies to signals JTG_TCK and JTG_TRST.
11
Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TCK, and JTG_TRST.
12
Applies to signals JTG_TDI, JTG_TMS.
13
Applies to signal USB0_CLKIN.
14
Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_A01–02, SMC0_D00–15,
SYS_FAULT, SYS_FAULT, JTG_EMU, JTG_TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS.
15
Applies to DMC0_A[00:13], DMC0_BA[0:2], DMC0_CAS, DMC0_CS0, DMC0_DQ[00:15], DMC0_LQDS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM,
DMC0_UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE.
16
Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_FAULT, SYS_FAULT, JTG_EMU,
JTG_TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS, DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CS0, DMC0_DQ00–15, DMC0_LQDS,
DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.
17
Applies to signals SMC0_AMS0, SMC0_ARE, SMC0_AWE, and when RSI pull-up resistors are enabled, PE10–13, 15 and PG00, 02, 03, 05.
18
Applies to all TWI signals.
19
Applies to all signals, except DMC0 and TWI signals.
20
Guaranteed, but not tested.
21
Applies to all DMC0 signals.
22
See the ADSP-BF60x Blackfin Processor Hardware Reference Manual for definition of deep sleep and hibernate operating modes.
23
Additional information can be found at Total Internal Power Dissipation on Page 57.
24
Applies to VDD_EXT, VDD_DMC, VDD_USB and VDD_TD supply signals only. Clock inputs are tied high or low.
2
Rev. A | Page 56 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Total Internal Power Dissipation
IDDINT_CCLK_DYN (mA) = Table 19 × (ASFC0 + ASFC1)
Total power dissipation has two components:
The dynamic current of the PVP is determined by selecting the
appropriate use case from Table 22.
1. Static, including leakage current (deep sleep)
2. Dynamic, due to transistor switching characteristics for
each clock domain
IDDINT_PVP_DYN (mA) = Table 22
Clock Current
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and processor activity. The following equation describes the internal
current consumption.
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissipated by each clock domain is dependent on voltage (VDD_INT),
operating frequency and a unique scaling factor.
IDDINT_TOT = IDDINT_CCLK_DYN + IDDINT_SYSCLK_DYN +
IDDINT_SCLK0_DYN + IDDINT_SCLK1_DYN + IDDINT_DCLK_DYN +
IDDINT_USBCLK_DYN + IDDINT_DMA_DR_DYN +
IDDINT_DEEPSLEEP + IDDINT_PVP_DYN
IDDINT_SYSCLK_DYN (mA) = 0.187 × fSYSCLK (MHz) × VDD_INT (V)
IDDINT_SCLK0_DYN (mA) = 0.217 × fSCLK0 (MHz) × VDD_INT (V)
IDDINT_SCLK1_DYN (mA) = 0.042 × fSCLK1 (MHz) × VDD_INT (V)
IDDINT_DEEPSLEEP is the only item present that is part of the static
power dissipation component. IDDINT_DEEPSLEEP is specified as a
function of voltage (VDD_INT) and temperature (see Table 21).
IDDINT_DCLK_DYN (mA) = 0.024 × fDCLK (MHz) × VDD_INT (V)
There are eight different items that contribute to the dynamic
power dissipation. These components fall into three broad categories: application-dependent currents, clock currents and data
transmission currents.
IDDINT_USBCLK_DYN (mA) = 5 mA (if USB enabled)
Application-Dependent Current
The application-dependent currents include the dynamic current in the core clock domain and the dynamic current of the
PVP.
Core clock (CCLK) use is subject to an activity scaling factor
(ASF) that represents application code running on the processor
cores and L1/L2 memories (Table 20). The ASF is combined
with the CCLK frequency and VDD_INT dependent data in
Table 19 to calculate this portion.
The dynamic component of the USB clock is a unique case. The
USB clock contributes a near constant current value when used.
Data Transmission Current
The data transmission current represents the power dissipated
when transmitting data. This current is expressed in terms of
data rate. The calculation is performed by adding the data rate
(MB/s) of each DMA and core driven access to peripherals and
L2/external memory. This number is then multiplied by a coefficient and VDD_INT. The following equation provides an estimate
of all data transmission current.
IDDINT_DMA_DR_DYN(mA) = 0.0578 × data rate (MB/s) × VDD_INT
(V)
For details on using this equation see the related Engineer Zone
material.
Table 19. CCLK Dynamic Current per core (mA, with ASF = 1)
500
1.190
97.9
1.200
98.8
1.225
101.5
Voltage (VDD_INT)
1.250
1.275
103.9
106.7
450
88.6
89.5
91.9
94.1
96.7
98.9
100.6
400
79.3
80.1
82.2
84.3
86.5
88.6
90.1
350
70.0
70.7
72.5
74.4
76.3
78.3
79.4
300
60.6
61.2
63.0
64.6
66.3
68.0
69.1
250
51.3
51.8
53.2
54.7
56.3
57.6
58.5
200
42.0
42.4
43.6
44.8
46.0
47.2
48.2
150
32.5
32.9
34.0
34.8
35.9
37.0
37.4
100
23.2
23.5
24.2
25.0
25.7
26.5
26.9
fCCLK (MHz)
Rev. A | Page 57 of 112 | February 2014
1.300
109.3
1.320
110.8
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 20. Activity Scaling Factors (ASF)
IDDINT Power Vector
IDD-PEAK
IDD-HIGH
IDD-FULL-ON-TYP
IDD-APP
IDD-NOP
IDD-IDLE
ASF
1.34
1.25
1.00
0.86
0.72
0.14
Table 21. Static Current—IDD_DEEPSLEEP (mA)
–40
1.190
1.7
1.200
1.8
1.225
2.2
Voltage (VDD_INT)
1.250
1.275
2.5
2.7
–20
4.0
4.2
4.6
5.1
0
8.4
9.0
9.6
10.6
11.5
12.5
13.4
25
19.0
19.8
21.5
23.2
25.3
27.2
29.0
40
29.9
31.7
34.4
36.8
40.0
42.8
45.4
55
46.6
48.9
52.4
56.4
60.6
65.0
68.1
70
66.4
70.4
75.5
80.6
86.2
92.4
97.9
85
93.9
99.3
105.9
113.0
120.7
128.9
136.4
100
137.2
144.2
153.6
163.4
173.9
185.1
194.1
105
153.8
162.4
172.5
183.4
195.2
207.5
217.5
115
193.3
203.7
216.2
229.5
243.9
258.6
271.1
125
236.1
247.2
261.8
277.3
294.0
311.9
326.4
TJ (°C)
5.6
Table 22. IDDINT_PVP_DYN (mA)
PVP Activity Level
High
Medium
Low
PVPSF (PVP Scaling Factor)
42.4
20
0
Rev. A | Page 58 of 112 | February 2014
1.300
3.1
1.320
3.4
6.2
6.8
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PROCESSOR — ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 23 may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
3
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the specified voltages, and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 23. Absolute Maximum Ratings
Parameter
Internal Supply Voltage (VDD_INT)
External (I/O) Supply Voltage (VDD_EXT)
Thermal Diode Supply Voltage
(VDD_TD)
DDR2 Controller Supply Voltage
(VDD_DMC)
USB PHY Supply Voltage (VDD_USB)
Input Voltage1, 2, 3
TWI Input Voltage2, 4
USB0_Dx Input Voltage5
USB0_VBUS Input Voltage5
DDR2 Input Voltage6
Output Voltage Swing
IOH/IOL Current per Signal1
Storage Temperature Range
Junction Temperature Under Bias
Rating
–0.33 V to 1.32 V
–0.33 V to 3.63 V
–0.33 V to 3.63 V
–0.33 V to 1.90 V
–0.33 V to 3.63 V
–0.33 V to 3.63 V
–0.33 V to 5.50 V
–0.33 V to 5.25 V
–0.33 V to 6.00 V
–0.33 V to 1.90 V
–0.33 V to VDD_EXT + 0.5 V
12.5 mA (max)
–65°C to +150°C
+125°C
PROCESSOR — PACKAGE INFORMATION
The information presented in Figure 9 and Table 25 provides
details about package branding. For a complete listing of product availability, see Automotive Products on Page 112.
a
ADSP-BF609
tppZccc
vvvvvv.x n.n
#yyww country_of_origin
B
1
Applies to 100% transient duty cycle.
Applies only when VDD_EXT is within specifications. When VDD_EXT is outside
specifications, the range is VDD_EXT ± 0.2 V.
3
For other duty cycles see Table 24.
4
Applies to balls TWI_SCL and TWI_SDA.
5
If the USB is not used, connect USB0_Dx and USB0_VBUS according to Table 15
on Page 37.
6
Applies only when VDD_DMC is within specifications. When VDD_DMC is outside
specifications, the range is VDD_DMC ± 0.2 V.
2
Table 24. Maximum Duty Cycle for Input Transient Voltage1, 2
Maximum Duty Cycle (%)2
100
50
40
25
20
15
10
VIN Min (V)3
–0.33
–0.50
–0.56
–0.67
–0.73
–0.80
–0.90
VIN Max (V)3
3.63
3.80
3.86
3.97
4.03
4.10
4.20
Figure 9. Product Information on Package
Table 25. Package Brand Information
Brand Key
ADSP-BF609
t
pp
Z
ccc
vvvvvv.x
n.n
yyww
1
Applies to all signal balls with the exception of SYS_CLKIN, SYS_XTAL,
SYS_EXT_WAKE, USB0_DP, USB0_DM, USB0_VBUS, TWI signals, and
DMC0 signals.
2
Applies only when VDD_EXT is within specifications. When VDD_EXT is outside specifications, the range is VDD_EXT ± 0.2 V.
Rev. A | Page 59 of 112 | February 2014
Field Description
Product Model
Temperature Range
Package Type
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 26 and Figure 10 describe clock and reset operations. Per
the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing
specifications in Table 17 on Page 53, combinations of
SYS_CLKIN and clock multipliers must not select clock rates in
excess of the processor’s maximum instruction rate.
Table 26. Clock and Reset Timing
VDD_EXT
1.8 V/3.3 V Nominal
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
SYS_CLKIN Frequency (using a crystal)1, 2, 3
20
50
MHz
fCKIN
SYS_CLKIN Frequency (using a crystal oscillator)1, 2, 3
20
60
MHz
1
tCKINL
SYS_CLKIN Low Pulse
tCKINH
SYS_CLKIN High Pulse1
tWRST
SYS_HWRST Asserted Pulse Width Low
4
6.67
ns
6.67
ns
11 × tCKIN
ns
1
Applies to PLL bypass mode and PLL non bypass mode.
The tCKIN period (see Figure 10) equals 1/fCKIN.
3
If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz.
4
Applies after power-up sequence is complete. See Table 27 and Figure 11 for power-up reset timing.
2
tCKIN
SYS_CLKIN
tCKINL
tCKINH
tWRST
SYS_HWRST
Figure 10. Clock and Reset Timing
Rev. A | Page 60 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Power-Up Reset Timing
In Figure 11, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB,
and VDD_TD.
Table 27. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR
SYS_HWRST Deasserted after VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_TD, and SYS_
CLKIN are Stable and Within Specification
RESET
tRST_IN_PWR
CLKIN
V
DD_SUPPLIES
Figure 11. Power-Up Reset Timing
Rev. A | Page 61 of 112 | February 2014
11 × tCKIN
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Read
Table 28. Asynchronous Memory Read (BxMODE = b#00)
Parameter
Timing Requirements
tSDATARE
DATA in Setup Before SMC0_ARE High
tHDATARE
DATA in Hold After SMC0_ARE High
tDARDYARE
SMC0_ARDY Valid After SMC0_ARE Low1, 2
Switching Characteristics
tADDRARE
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_
ARE Low3
SMC0_AOE Assertion Before SMC0_ARE Low
tAOEARE
tHARE
Output4 Hold After SMC0_ARE High5
tWARE
SMC0_ARE Active Low Width6
tDAREARDY
SMC0_ARE High Delay After SMC0_ARDY
Assertion1
VDD_EXT
1.8 V/3.3 V Nominal
Max
Min
Unit
8.2
0
(RAT – 2.5) × tSCLK0 – 17.5
(PREST + RST + PREAT) × tSCLK0 – 2
ns
(RST + PREAT) × tSCLK0 – 2
RHT × tSCLK0 –2
ns
ns
RAT × tSCLK0 – 2
2.5 × tSCLK0
3.5 × tSCLK0 + 17.5
1
SMC0_BxCTL.ARDYEN bit = 1.
RAT value set using the SMC_BxTIM.RAT bits.
3
PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
2
SMC0_ARE
SMC0_AMSx
ns
ns
ns
tWARE
tHARE
tADDRARE
SMC0_Ax
tAOEARE
SMC0_AOE
tDARDYARE
tDAREARDY
SMC0_ARDY
tSDATARE
SMC0_Dx (DATA)
Figure 12. Asynchronous Read
Rev. A | Page 62 of 112 | February 2014
tHDATARE
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Flash Read
Table 29. Asynchronous Flash Read
Parameter
Switching Characteristics
tAMSADV
SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV
Low1
SMC0_NORDV Active Low Width2
tWADV
tDADVARE
SMC0_ARE Low Delay From SMC0_NORDV High3
tHARE
Output4 Hold After SMC0_ARE High5
6
tWARE
SMC0_ARE Active Low Width7
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
PREST × tSCLK0 – 2
ns
RST × tSCLK0 – 2
PREAT × tSCLK0 – 2
RHT × tSCLK0 – 2
RAT × tSCLK0 – 2
ns
ns
ns
ns
1
PREST value set using the SMC_BxETIM.PREST bits.
RST value set using the SMC_BxTIM.RST bits.
3
PREAT value set using the SMC_BxETIM.PREAT bits.
4
Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.
5
RHT value set using the SMC_BxTIM.RHT bits.
6
SMC0_BxCTL.ARDYEN bit = 0.
7
RAT value set using the SMC_BxTIM.RAT bits.
2
SMC0_Ax
SMC0_AMSx
(NOR_CE)
tAMSADV
tWADV
SMC0_NORDV
tDADVARE
Unit
tWARE
tHARE
SMC0_ARE
(NOR_OE)
SMC0_Dx
(DATA)
READ LATCHED
DATA
Figure 13. Asynchronous Flash Read
Rev. A | Page 63 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Page Mode Read
Table 30. Asynchronous Page Mode Read
VDD_EXT
1.8 V /3.3 V Nominal
Parameter
Switching Characteristics
tAV
SMC0_Ax (Address) Valid for First Address Min Width1
tAV1
SMC0_Ax (Address) Valid for Subsequent SMC0_Ax
(Address) Min Width
SMC0_NORDV Active Low Width2
tWADV
tHARE
Output3 Hold After SMC0_ARE High4
5
tWARE
SMC0_ARE Active Low Width6, 7
Min
Max
Unit
(PREST + RST + PREAT + RAT) × tSCLK0 – 2
PGWS × tSCLK0 – 2
ns
ns
RST × tSCLK0 – 2
RHT × tSCLK0 – 2
(RAT + (Nw – 1) × PGWS) × tSCLK0 – 2
ns
ns
ns
1
PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
RST value set using the SMC_BxTIM.RST bits.
3
Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.
4
RHT value set using the SMC_BxTIM.RHT bits.
5
SMC_BxCTL.ARDYEN bit = 0.
6
RAT value set using the SMC_BxTIM.RAT bits.
7
Nw = Number of 16-bit data words read.
2
READ
LATCHED
DATA
SMC0_Ax
(ADDRESS)
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
tAV
tAV1
tAV1
tAV1
A0
A0 + 1
A0 + 2
A0 + 3
SMC0_AMSx
(NOR_CE)
SMC0_AOE
NOR_ADV
tWADV
tWARE
SMC0_ARE
(NOR_OE)
tHARE
SMC0_Dx
(DATA)
D0
D1
Figure 14. Asynchronous Page Mode Read
Rev. A | Page 64 of 112 | February 2014
D2
D3
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Synchronous Burst Flash Read
f SCLK0
f NRCLKPROG = ---------------------------( BCLK + 1 )
In synchronous burst mode the programmed NOR burst clock
(fNRCLKPROG) frequency in MHz is set by the following equation
where BCLK is a field in the SMC_BxCTL register that can be
set from 0 to 3:
1
t NRCLKPROG = ------------------------------f NRPCLKPROG
Table 31. Synchronous Burst AC Timing (BxMODE = b#11)
Parameter
Timing Requirements
tNDS
DATA-In Setup Before SMC0_NORCLK High
tNDH
DATA-In Hold After SMC0_NORCLK High
tNWS
WAIT-In Setup Before SMC0_NORCLK High
WAIT-In Hold After SMC0_NORCLK High
tNWH
Switching Characteristics
tNRCLS
NOR_CLK Low Period1
tNRCHS
NOR_CLK High Period1
tNRCLK
NOR_CLK Period1
tNDO
Output Delay After SMC0_NORCLK High2
Output Hold After SMC0_NORCLK High2
tNHO
1
2
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
Unit
3
1.5
3
1.5
ns
ns
ns
ns
0.5 × tNRCLKPROG – 1
0.5 × tNRCLKPROG – 1
tNRCLKPROG – 1
ns
ns
ns
ns
ns
6
0.8
See Table 17 on Page 53 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tNRCLKPROG.
Output = SMC0_Ax (address), SMC0_NORDV, SMC0_ARE, SMC0_AMSx (N0R_CE).
Rev. A | Page 65 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SMC0_NORCLK
tNRCLS
tNDO
tNDO
tNRCLK
tNRCHS
SMC0_AMSx
tNHO
tNDO
SMC0_ABE1-0
tNDO
tNHO
SMC0_Ax
(ADDRESS)
tNDH
tNDH
tNDS
tNDS
SMC0_Dx
(DATA)
Dn
Dn+1
Dn+2
Dn+3
tNDO
tNDO
SMC0_NORDV
SMC0_AOE
tNWS
tNWH
SMC0_NORWT
tNDO
tNDO
SMC0_ARE
NOR_OE
NOTE: SMC0_NORCLK dotted line represents a free running version
of SMC0_NORCLK that is not visible on the SMC0_NORCLK pin.
Figure 15. Synchronous Burst AC Interface Timing
Rev. A | Page 66 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Write
Table 32. Asynchronous Memory Write (BxMODE = b#00)
Parameter
Timing Requirement
tDARDYAWE1
SMC0_ARDY Valid After SMC0_AWE Low2
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
(WAT – 2.5) ×
tSCLK0 – 17.5
Switching Characteristics
tENDAT
DATA Enable After SMC0_AMSx Assertion
tDDAT
DATA Disable After SMC0_AMSx Deassertion
tAMSAWE
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_AWE
Low3
tHAWE
Output4 Hold After SMC0_AWE High5
6
tWAWE
SMC0_AWE Active Low Width2
tDAWEARDY1
SMC0_AWE High Delay After SMC0_ARDY Assertion
–3
ns
(PREST + WST + PREAT) × tSCLK0 – 2
ns
ns
ns
WHT × tSCLK0 – 2
WAT × tSCLK0 – 2
2.5 × tSCLK0
ns
ns
ns
3
3.5 × tSCLK0 + 17.5
1
SMC_BxCTL.ARDYEN bit = 1.
2
WAT value set using the SMC_BxTIM.WAT bits.
3
PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
6
SMC_BxCTL.ARDYEN bit = 0.
SMC0_AWE
SMC0_ABEx
SMC0_Ax
tAMSAWE
Unit
tWAWE
tHAWE
SMC0_ARDY
tDARDYAWE
tDAWEARDY
SMC0_AMSx
SMC0_Dx (DATA)
tDDAT
tENDAT
Figure 16. Asynchronous Write
Rev. A | Page 67 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Flash Write
Table 33. Asynchronous Flash Write
Parameter
Switching Characteristics
tAMSADV
SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1
tDADVAWE
SMC0_AWE Low Delay From ADV High2
tWADV
NR_ADV Active Low Width3
tHAWE
Output4 Hold After SMC0_AWE High5
6
tWAWE
SMC0_AWE Active Low Width7
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
Unit
PREST × tSCLK0 – 2
PREAT × tSCLK0 – 2
WST × tSCLK0 – 2
WHT × tSCLK0 – 2
WAT × tSCLK0 – 2
ns
ns
ns
ns
ns
1
PREST value set using the SMC_BxETIM.PREST bits.
PREAT value set using the SMC_BxETIM.PREAT bits.
3
WST value set using the SMC_BxTIM.WST bits.
4
Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5
WHT value set using the SMC_BxTIM.WHT bits.
6
SMC_BxCTL.ARDYEN bit = 0.
7
WAT value set using the SMC_BxTIM.WAT bits.
2
NOR_A 25-1
(SMC0_Ax)
NR_CE
(SMC0_AMSx)
tAMSADV
tWADV
NR_ADV
(SMC0_AOE)
tDADVAWE
tWAWE
tHAWE
NR_WE
(SMC0_AWE)
NR_DQ 15-0
(SMC0_Dx)
Figure 17. Asynchronous Flash Write
All Accesses
Table 34. All Accesses
Parameter
Switching Characteristic
tTURN
SMC0_AMSx Inactive Width
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
(IT + TT) × tSCLK0 – 2
Rev. A | Page 68 of 112 | February 2014
Unit
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Bus Request/Bus Grant
Table 35. Bus Request/Bus Grant
Parameter
Switching Characteristics
tDBGBR
SMC0_BG Delay After SMC0_BR
tENGDAT
DATA Enable After SMC0_BG Deassertion
tDBGDAT
DATA Disable After SMC0_BG Assertion
VDD_EXT
1.8 V/3.3 V Nominal
Max
Min
2.5 × tSCLK0
–3
3.5 × tSCLK0 + 17.5
3
Unit
ns
ns
ns
SMC0_BR
tDBGBR
SMC0_BG
tDBGDAT
tENGDAT
SMC0 DATA/ADDRESS
CONTROL
Figure 18. Bus Request/Bus Grant
DDR2 SDRAM Clock and Control Cycle Timing
Table 36. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
Parameter
Switching Characteristics
tCK
Clock Cycle Time (CL = 2 Not Supported)
tCH
Minimum Clock Pulse Width
tCL
Maximum Clock Pulse Width
tIS
Control/Address Setup Relative to DMC0_CK Rise
tIH
Control/Address Hold Relative to DMC0_CK Rise
tCK
250 MHz
Max
Min
4
0.45
0.45
350
475
0.55
0.55
tCH
tCL
DMC0_CK
DMC0_CK
tIS
tIH
DMC0_Ax
DMC0 CONTROL
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00-13, AND DMC0_BA0-1.
Figure 19. DDR2 SDRAM Clock and Control Cycle Timing
Rev. A | Page 69 of 112 | February 2014
Unit
ns
tCK
tCK
ps
ps
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Read Cycle Timing
Table 37. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
Parameter
Timing Requirements
tDQSQ
tQH
tRPRE
tRPST
1
Min
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_
DQ Signals
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS
Read Preamble
Read Postamble
In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
tCK
tCH
tCL
DMC0_CKx
DMC0_CKx
tAS
tAH
DMC0_Ax
DMC0 CONTROL
tRPRE
tAC
tDQSCK
DMC0_DQSn
DMC0_DQSn
tDQSQ
tDQSQ
tQH
tRPST
tQH
DMC0_DQx
Figure 20. DDR2 SDRAM Controller Input AC Timing
Rev. A | Page 70 of 112 | February 2014
250 MHz1
Max
0.35
1.6
0.9
0.4
Unit
ns
ns
tCK
tCK
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Write Cycle Timing
Table 38. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V
Parameter
Switching Characteristics
tDQSS2
DMC0_DQS Latching Rising Transitions to Associated Clock Edges
tDS
tDH
tDSS
tDSH
tDQSH
tDQSL
tWPRE
tWPST
tIPW
tDIPW
1
2
Last Data Valid to DMC0_DQS Delay
DMC0_DQS to First Data Invalid Delay
DMC0_DQS Falling Edge to Clock Setup Time
DMC0_DQS Falling Edge Hold Time From DMC0_CK
DMC0_DQS Input High Pulse Width
DMC0_DQS Input Low Pulse Width
Write Preamble
Write Postamble
Address and Control Output Pulse Width
DMC0_DQ and DMC0_DM Output Pulse Width
Min
–0.15
0.15
0.3
0.25
0.25
0.35
0.35
0.35
0.4
0.6
0.35
250 MHz1
Max
0.15
In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
Write command to first DMC0_DQS delay = WL × tCK + tDQSS.
DMC0_CK
DMC0_CK
tIPW
DMC0_Ax
DMC0 CONTROL
tDSH
tDSS
tDQSS
DMC0_LDQS
DMC0_UDQS
tWPRE
tDQSL
tDS
tDH
DMC0_LDM
DMC0_UDM
Figure 21. DDR2 SDRAM Controller Output AC Timing
Rev. A | Page 71 of 112 | February 2014
tDQSH
tDIPW
tWPST
Unit
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Mobile DDR SDRAM Clock and Control Cycle Timing
Table 39. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
Parameter
Switching Characteristics
tCK
Clock Cycle Time (CL = 2 Not Supported)
tCH
Minimum Clock Pulse Width
tCL
Maximum Clock Pulse Width
tIS
Control/Address Setup Relative to DMC0_CK Rise
tIH
Control/Address Hold Relative to DMC0_CK Rise
200 MHz
Max
Min
5
0.45
0.45
1
1
tCK
Unit
ns
tCK
tCK
ns
ns
0.55
0.55
tCH
tCL
DMC0_CK
DMC0_CK
tIS
tIH
DMC0_Ax
DMC0 CONTROL
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00-13, AND DMC0_BA0-1.
Figure 22. Mobile DDR SDRAM Clock and Control Cycle Timing
Mobile DDR SDRAM Read Cycle Timing
Table 40. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
Parameter
Timing Requirements
tQH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS
tDQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated
DMC0_DQ Signals
Read Preamble
tRPRE
tRPST
Read Postamble
200 MHz
Max
Min
1.75
0.9
0.4
DMC0_CK
tRPRE
tRPST
DMC0_DQS
tQH
DMC0_DQS
(DATA)
Dn
Dn+1
Dn+2
tDQSQ
Figure 23. Mobile DDR SDRAM Controller Input AC Timing
Rev. A | Page 72 of 112 | February 2014
Dn+3
Unit
0.4
ns
ns
1.1
0.6
tCK
tCK
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Mobile DDR SDRAM Write Cycle Timing
Table 41. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V
Parameter
Switching Characteristics
tDQSS1
DMC0_DQS Latching Rising Transitions to Associated Clock Edges
tDS
Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns)
tDH
DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns)
tDSS
DMC0_DQS Falling Edge to Clock Setup Time
tDSH
DMC0_DQS Falling Edge Hold Time From DMC0_CK
tDQSH
DMC0_DQS Input High Pulse Width
tDQSL
DMC0_DQS Input Low Pulse Width
tWPRE
Write Preamble
tWPST
Write Postamble
tIPW
Address and Control Output Pulse Width
tDIPW
DMC0_DQ and DMC0_DM Output Pulse Width
1
Min
200 MHz
Max
0.75
0.48
0.48
0.2
0.2
0.4
0.4
0.25
0.4
2.3
1.8
1.25
Write command to first DMC0_DQS delay = WL × tCK + tDQSS.
DMC0_CK
tDSS
tDSH
tDQSS
DMC0_DQS0-1
tWPRE
tDS
tDQSL
tDH
tDQSH
tWPST
tDIPW
DMC0_DQ0-15/
DMC0_DQM0-1
Dn
Dn+1
Dn+2
Dn+3
tDIPW
DMC0 CONTROL
Write CMD
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00-13, AND DMC0_BA0-1.
tIPW
Figure 24. Mobile DDR SDRAM Controller Output AC Timing
Rev. A | Page 73 of 112 | February 2014
Unit
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Enhanced Parallel Peripheral Interface Timing
f SCLK0
f PCLKPROG = -------------------------------( VALUE + 1 )
The following tables and figures describe enhanced parallel
peripheral interface timing operations. The POLC bits in the
EPPI_CTL register may be used to set the sampling/driving
edges of the EPPI clock.
1
t PCLKPROG = -----------------------f PCLKPROG
When internally generated, the programmed PPI clock
(fPCLKPROG) frequency in MHz is set by the following equation
where VALUE is a field in the EPPI_CLKDIV register that can
be set from 0 to 65535:
When externally generated the EPPI_CLK is called fPCLKEXT:
1 t PCLKEXT = -------------------f PCLKEXT
Table 42. Enhanced Parallel Peripheral Interface—Internal Clock
Parameter
Timing Requirements
tSFSPI
External FS Setup Before EPPI_CLK
External FS Hold After EPPI_CLK
tHFSPI
tSDRPI
Receive Data Setup Before EPPI_CLK
tHDRPI
Receive Data Hold After EPPI_CLK
tSFS3GI
External FS3 Input Setup Before EPPI_CLK
Fall Edge in Clock Gating Mode
tHFS3GI
External FS3 Input Hold Before EPPI_CLK
Fall Edge in Clock Gating Mode
Switching Characteristics
tPCLKW
EPPI_CLK Width1
tPCLK
EPPI_CLK Period1
tDFSPI
Internal FS Delay After EPPI_CLK
tHOFSPI
Internal FS Hold After EPPI_CLK
tDDTPI
Transmit Data Delay After EPPI_CLK
Transmit Data Hold After EPPI_CLK
tHDTPI
1
VDD_EXT
1.8 V Nominal
Max
Min
VDD_EXT
3.3 V Nominal
Min
6.5
0
6.5
0
14
ns
ns
ns
ns
ns
0
0
ns
0.5 × tPCLKPROG – 1
tPCLKPROG – 1
0.5 × tPCLKPROG – 1
tPCLKPROG – 1
ns
ns
ns
ns
ns
ns
3.5
–0.5
3.5
–0.5
3.5
–0.5
3.5
–0.5
DATA
SAMPLED
POLC[1:0] = 10
EPPI_CLK
POLC[1:0] = 01
tDFSPI
tPCLKW
tHOFSPI
tPCLK
EPPI_FS1/2
tSDRPI
Unit
7.9
0
7.9
0
15.4
See Table 17 on Page 53 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tPCLKPROG.
FRAME SYNC
DRIVEN
Max
tHDRPI
EPPI_D00-23
Figure 25. PPI Internal Clock GP Receive Mode with Internal Frame Sync Timing
Rev. A | Page 74 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tDFSPI
tPCLKW
tHOFSPI
EPPI_FS1/2
tHDTPI
tDDTPI
EPPI_D00-23
Figure 26. PPI Internal Clock GP Transmit Mode with Internal Frame Sync Timing
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPI
tPCLKW
tHFSPI
tPCLK
EPPI_FS1/2
tSDRPI
tHDRPI
EPPI_D00-23
Figure 27. PPI Internal Clock GP Receive Mode with External Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPI
tHFSPI
tPCLKW
tPCLK
EPPI_FS1/2
tDDTPI
tHDTPI
EPPI_D00-23
Figure 28. PPI Internal Clock GP Transmit Mode with External Frame Sync Timing
EPPI_CLK
tHFS3GI
tSFS3GI
EPPI_FS3
Figure 29. Clock Gating Mode with Internal Clock and External Frame Sync Timing
Rev. A | Page 75 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 43. Enhanced Parallel Peripheral Interface—External Clock
Parameter
Timing Requirements
tPCLKW
EPPI_CLK Width1
EPPI_CLK Period1
tPCLK
tSFSPE
External FS Setup Before EPPI_CLK
tHFSPE
External FS Hold After EPPI_CLK
tSDRPE
Receive Data Setup Before EPPI_CLK
tHDRPE
Receive Data Hold After EPPI_CLK
Switching Characteristics
Internal FS Delay After EPPI_CLK
tDFSPE
tHOFSPE
Internal FS Hold After EPPI_CLK
tDDTPE
Transmit Data Delay After EPPI_CLK
tHDTPE
Transmit Data Hold After EPPI_CLK
1
VDD_EXT
1.8 V Nominal
Max
Min
(0.5 × tPCLKEXT) – 1.25
tPCLKEXT – 1.25
2
3.7
2
3.7
VDD_EXT
3.3 V Nominal
Min
Max
(0.5 × tPCLKEXT) – 1.25
tPCLKEXT – 1.25
2
3.7
2
3.7
20.1
2.4
ns
ns
ns
ns
ns
ns
15.3
2.4
20.1
2.4
15.3
2.4
Unit
ns
ns
ns
ns
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external
EPPI_CLK ideal maximum frequency see the fPCLKEXT specification in Table 17 on Page 53.
FRAME SYNC
DRIVEN
DATA
SAMPLED
POLC[1:0] = 10
EPPI_CLK
POLC[1:0] = 01
tDFSPE
tPCLKW
tHOFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 30. PPI External Clock GP Receive Mode with Internal Frame Sync Timing
FRAME SYNC
DRIVEN
DATA
DRIVEN
DATA
DRIVEN
tPCLK
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tDFSPE
tPCLKW
tHOFSPE
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 31. PPI External Clock GP Transmit Mode with Internal Frame Sync Timing
Rev. A | Page 76 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPE
tPCLKW
tHFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 32. PPI External Clock GP Receive Mode with External Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
POLC[1:0] = 11
EPPI_CLK
POLC[1:0] = 00
tSFSPE
tHFSPE
tPCLKW
tPCLK
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 33. PPI External Clock GP Transmit Mode with External Frame Sync Timing
Rev. A | Page 77 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Link Ports
In the case where VALUE = 0, fLCLKTPROG = fSCLK0. For all settings
of VALUE the following equation also holds:
In link port receive mode the link port clock is supplied externally and is called fLCLKREXT:
1 t LCLKREXT = ----------------------f LCLKREXT
1
t LCLKTPROG = --------------------------f LCLKTPROG
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path length difference between LP_Dx (data) and LP_CLK. Setup skew is the
maximum delay that can be introduced in LP_Dx relative to
LP_CLK:
(setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the
maximum delay that can be introduced in LP_CLK relative to
LP_Dx: (hold skew = tLCLKTWL min – tHLDCH – tHLDCL).
In link port transmit mode the programmed link port clock
(fLCLKTPROG) frequency in MHz is set by the following equation
where VALUE is a field in the LP_DIV register that can be set
from 1 to 255:
f SCLK0
f LCLKTPROG = -------------------------------( VALUE × 2 )
Table 44. Link Ports—Receive
Parameter
Timing Requirements
tSLDCL
Data Setup Before LP_CLK Low
tHLDCL
Data Hold After LP_CLK Low
tLCLKIW
LP_CLK Period1
LP_CLK Width Low1
tLCLKRWL
tLCLKRWH
LP_CLK Width High1
Switching Characteristic
tDLALC
LP_ACK Low Delay After LP_CLK Low2
1
2
VDD_EXT
1.8 V Nominal/3.3 V Nominal
Max
Min
2
3
tLCLKREXT – 1.5
(0.5 × tLCLKREXT) – 1.5
(0.5 × tLCLKREXT) – 1.5
Unit
ns
ns
ns
ns
ns
1.5 × tSCLK0 + 4
2.5 × tSCLK0 + 12
ns
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external LP_CLK. For the external
LP_CLK ideal maximum frequency see the fLCLKTEXT specification in Table 17 on Page 53 in Clock Related Operating Conditions.
LP_ACK goes low with tDLALC relative to rise of LP_CLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
tLCLKIW
tLCLKRWH
tLCLKRWL
LP_CLK
tHLDCL
tSLDCL
LP_D7–0
IN
tDLALC
LP_ACK (OUT)
Figure 34. Link Ports—Receive
Rev. A | Page 78 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 45. Link Ports—Transmit
Parameter
Timing Requirements
tSLACH
LP_ACK Setup Before LP_CLK Low
tHLACH
LP_ACK Hold After LP_CLK Low
Switching Characteristics
Data Delay After LP_CLK High
tDLDCH
tHLDCH
Data Hold After LP_CLK High
tLCLKTWL1
LP_CLK Width Low
1
tLCLKTWH
LP_CLK Width High
tLCLKTW1
LP_CLK Period
tDLACLK
LP_CLK Low Delay After LP_ACK
High
1
Min
VDD_EXT
1.8 V Nominal
Max
Min
2 × tSCLK0 + 17.5
0
VDD_EXT
3.3 V Nominal
Max
2 × tSCLK0 + 13.5
0
2.5
–1.5
0.4 × tLCLKTPROG
0.4 × tLCLKTPROG
tLCLKTPROG – 1.2
tSCLK0 + 4
ns
ns
2.5
0.6 × tLCLKTPROG
0.6 × tLCLKTPROG
(2 × tSCLK0) + tLCLK + 10
–1.5
0.4 × tLCLKTPROG
0.4 × tLCLKTPROG
tLCLKTPROG – 1.2
tSCLK0 + 4
0.6 × tLCLKTPROG
0.6 × tLCLKTPROG
(2 × tSCLK0) + tLCLK + 10
See Table 17 on Page 53 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tLCLKTPROG.
tLCLKTWH
tLCLKTWL
LAST BYTE
TRANSMITTED
FIRST BYTE
TRANSMITTED1
LP_CLK
tDLDCH
tHLDCH
LP_Dx
(DATA)
OUT
tSLACH
tHLACH
tDLACLK
LP_ACK (IN)
NOTES
The tSLACH and tHLACH specifications apply only to the LP_ACK falling edge. If these specifications are met,
LP_CLK would extend and the dotted LP_CLK falling edge would not occur as shown. The position of the
dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min should be used for tSLACH
and tLCLKTWH Max for tHLACH.
Figure 35. Link Ports—Transmit
Rev. A | Page 79 of 112 | February 2014
Unit
ns
ns
ns
ns
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SPT_CLK) width. In Figure 36 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the
active sampling edge.
When internally generated, the programmed SPORT clock
(fSPTCLKPROG) frequency in MHz is set by the following equation
where CLKDIV is a field in the SPORT_DIV register that can be
set from 0 to 65535:
f SCLK1
f SPTCLKPROG = ------------------------------------
( CLKDIV + 1 )
When externally generated the SPORT clock is called fSPTCLKEXT:
1
t SPTCLKPROG = ----------------------------------f SPTCLKPROG
1
t SPTCLKEXT = -----------------------------f SPTCLKEXT
Table 46. Serial Ports—External Clock
VDD_EXT
1.8 V Nominal
Parameter
Timing Requirements
tSFSE
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
tHFSE
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
tSDRE
Receive Data Setup Before Receive SPT_CLK1
tHDRE
Receive Data Hold After SPT_CLK1
tSCLKW
SPT_CLK Width2
tSPTCLK
SPT_CLK Period2
Switching Characteristics
tDFSE
Frame Sync Delay After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)3
tHOFSE
Frame Sync Hold After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)3
tDDTE
Transmit Data Delay After Transmit SPT_CLK3
tHDTE
Transmit Data Hold After Transmit SPT_CLK3
Min
VDD_EXT
3.3 V Nominal
Max
Min
Max
Unit
2
2
ns
2.7
2.7
ns
2
2.7
(0.5 × tSPTCLKEXT) – 1.5
tSPTCLKEXT – 1.5
2
2.7
(0.5 × tSPTCLKEXT) – 1.5
tSPTCLKEXT – 1.5
ns
ns
ns
ns
19.3
2
14.5
2
18.8
2
1
ns
14
2
ns
ns
ns
Referenced to sample edge.
2
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. For the external
SPT_CLK ideal maximum frequency see the fSPTCLKEXT specification in Table 17 on Page 53 in Clock Related Operating Conditions.
3
Referenced to drive edge.
Rev. A | Page 80 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 47. Serial Ports—Internal Clock
Parameter
Timing Requirements
tSFSI
Frame Sync Setup Before SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
tHFSI
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
tSDRI
Receive Data Setup Before SPT_CLK1
Receive Data Hold After SPT_CLK1
tHDRI
Switching Characteristics
tDFSI
Frame Sync Delay After SPT_CLK (Internally
Generated Frame Sync in Transmit or
Receive Mode)2
tHOFSI
Frame Sync Hold After SPT_CLK (Internally
Generated Frame Sync in Transmit or
Receive Mode)2
tDDTI
Transmit Data Delay After SPT_CLK2
tHDTI
Transmit Data Hold After SPT_CLK2
tSCLKIW
SPT_CLK Width3
tSPTCLK
SPT_CLK Period3
Min
VDD_EXT
1.8 V Nominal
Max
16.8
VDD_EXT
3.3 V Nominal
Min
Max
Unit
12
ns
0
–0.5
ns
4.8
1.5
3.4
1.5
3.5
–1
ns
ns
3.5
–1
3.5
–1
0.5 × tSPTCLKPROG – 1.5
tSPTCLKPROG – 1.5
1
Referenced to the sample edge.
Referenced to drive edge.
3
See Table 17 on Page 53 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tSPTCLKPROG.
2
Rev. A | Page 81 of 112 | February 2014
ns
3.5
–1
0.5 × tSPTCLKPROG – 1.5
tSPTCLKPROG – 1.5
ns
ns
ns
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
DATA RECEIVE—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tSFSI
tHOFSI
tHFSI
tSFSE
tHFSE
tSDRE
tHDRE
tHOFSE
SPT_A/BFS
(FRAME SYNC)
SPT_A/BFS
(FRAME SYNC)
tSDRI
tHDRI
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BDx
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
tSCLKIW
SAMPLE EDGE
tSCLKW
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tSFSE
tHOFSE
SPT_A/BFS
(FRAME SYNC)
SPT_A/BFS
(FRAME SYNC)
tDDTI
tDDTE
tHDTI
SPT_A/BDx
(DATA CHANNEL A/B)
SAMPLE EDGE
tSCLKW
tHDTE
SPT_A/BDx
(DATA CHANNEL A/B)
Figure 36. Serial Ports
Rev. A | Page 82 of 112 | February 2014
tHFSE
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 48. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDDTEN
Data Enable from External Transmit SPT_CLK1
Data Disable from External Transmit SPT_CLK1
tDDTTE
tDDTIN
Data Enable from Internal Transmit SPT_CLK1
tDDTTI
Data Disable from Internal Transmit SPT_CLK1
1
Min
VDD_EXT
1.8 V Nominal
Max
1
VDD_EXT
3.3 V Nominal
Min
Max
1
18.8
–1
14
–1
2.8
2.8
Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
tDDTEN
tDDTTE
SPT_A/BDx
(DATA
CHANNEL A/B)
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
tDDTIN
tDDTTI
SPT_A/BDx
(DATA
CHANNEL A/B)
Figure 37. Serial Ports—Enable and Three-State
Rev. A | Page 83 of 112 | February 2014
Unit
ns
ns
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
The SPT_TDV output signal becomes active in SPORT multichannel mode. During transmit slots (enabled with active
channel selection registers) the SPT_TDV is asserted for communication with external devices.
Table 49. Serial Ports—TDV (Transmit Data Valid)
VDD_EXT
1.8 V Nominal
Min
Max
Parameter
Switching Characteristics
tDRDVEN
Data-Valid Enable Delay from Drive Edge of External Clock1 2
tDFDVEN
Data-Valid Disable Delay from Drive Edge of External Clock1
tDRDVIN
Data-Valid Enable Delay from Drive Edge of Internal Clock1 –1
Data-Valid Disable Delay from Drive Edge of Internal Clock1
tDFDVIN
1
Max
2
14
–1
3.5
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
tDFDVEN
SPT_A/BTDV
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
tDRDVIN
Min
18.8
Referenced to drive edge.
tDRDVEN
VDD_EXT
3.3 V Nominal
tDFDVIN
SPT_A/BTDV
Figure 38. Serial Ports—Transmit Data Valid Internal and External Clock
Rev. A | Page 84 of 112 | February 2014
3.5
Unit
ns
ns
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 50. Serial Ports—External Late Frame Sync
VDD_EXT
1.8 V Nominal
Min
Max
Parameter
Switching Characteristics
tDDTLFSE
Data Delay from Late External Transmit Frame Sync or External
Receive Frame Sync with MCE = 1, MFD = 01
tDDTENFS
Data Enable for MCE = 1, MFD = 01
0.5
1
VDD_EXT
3.3 V Nominal
Min
18.8
0.5
The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0.
DRIVE
SAMPLE
DRIVE
SPT_A/BCLK
(SPORT CLOCK)
tHFSE/I
tSFSE/I
SPT_A/BFS
(FRAME SYNC)
tDDTE/I
tDDTENFS
SPT_A/BDx
(DATA CHANNEL A/B)
tHDTE/I
1ST BIT
tDDTLFSE
Figure 39. External Late Frame Sync
Rev. A | Page 85 of 112 | February 2014
2ND BIT
Max
Unit
14
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Note that:
Serial Peripheral Interface (SPI) Port—Master Timing
• In dual mode data transmit the SPI_MISO signal is also an
output.
Table 51 and Figure 40 describe SPI port master operations.
When internally generated, the programmed SPI clock
(fSPICLKPROG) frequency in MHz is set by the following equation
where BAUD is a field in the SPI_CLK register that can be set
from 0 to 65535:
• In quad mode data transmit the SPI_MISO, SPI_D2, and
SPI_D3 signals are also outputs.
• In dual mode data receive the SPI_MOSI signal is also an
input.
f SCLK1
f SPICLKPROG = ------------------------------
• In quad mode data receive the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also inputs.
( BAUD + 1 )
1
t SPICLKPROG = --------------------------------f SPICLKPROG
• To add additional frame delays see the documentation for
the SPI_DLY register in the hardware reference manual.
Table 51. Serial Peripheral Interface (SPI) Port—Master Timing
VDD_EXT
3.3 V Nominal
VDD_EXT
1.8 V Nominal
Min
Parameter
Max
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid to SPI_CLK Edge (Data Input 4.6
Setup)
3.2
ns
tHSPIDM
SPI_CLK Sampling Edge to Data Input Invalid 1.3
1.3
ns
0.5 × tSCLK1 – 2
0.5 × tSCLK1 – 2
ns
0.5 × tSPICLKPROG – 1.5
0.5 × tSPICLKPROG – 1.5
ns
0.5 × tSPICLKPROG – 1.5
0.5 × tSPICLKPROG – 1.5
ns
Switching Characteristics
tSDSCIM
SPI_SEL low to First SPI_CLK Edge
1
tSPICHM
SPI_CLK High Period
tSPICLM
SPI_CLK Low Period1
1
tSPICLK
SPI_CLK Period
tSPICLKPROG – 1.5
tSPICLKPROG – 1.5
ns
tHDSM
Last SPI_CLK Edge to SPI_SEL High
(0.5 × tSCLK1 ) – 1.5
(0.5 × tSCLK1 ) – 1.5
ns
tSPITDM
Sequential Transfer Delay
tSCLK1 – 1.5
tDDSPIDM
SPI_CLK Edge to Data Out Valid (Data Out
Delay)
tHDSPIDM
SPI_CLK Edge to Data Out Invalid (Data Out –1
Hold)
1
tSCLK1 – 1.5
2.6
–1
See Table 17 on Page 53 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tSPICLKPROG.
Rev. A | Page 86 of 112 | February 2014
ns
2.6
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPI_SEL
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPI_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPI_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(SPI_MISO)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPI_MOSI)
CPHA = 0
tSSPIDM
tHSPIDM
DATA INPUTS
(SPI_MISO)
Figure 40. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. A | Page 87 of 112 | February 2014
tSPITDM
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 52 and Figure 41 describe SPI port slave operations. Note
that:
• In quad mode data receive the SPI_MISO, SPI_D2, and
SPI_D3 signals are also inputs.
• In dual mode data transmit the SPI_MOSI signal is also an
output.
• In SPI slave mode the SPI clock is supplied externally and is
called fSPICLKEXT:
• In quad mode data transmit the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also outputs.
1
t SPICLKEXT = ----------------------------f SPICLKEXT
• In dual mode data receive the SPI_MISO signal is also an
input.
Table 52. Serial Peripheral Interface (SPI) Port—Slave Timing
VDD_EXT
1.8 V Nominal
Parameter
Min
Max
VDD_EXT
3.3 V Nominal
Min
Max
Unit
Timing Requirements
tSPICHS
SPI_CLK High Period1
tSPICLS
SPI_CLK Low Period
tSPICLK
SPI_CLK Period1
1
(0.5 × tSPICLKEXT) – 1.5
(0.5 × tSPICLKEXT) – 1.5
ns
(0.5 × tSPICLKEXT) – 1.5
(0.5 × tSPICLKEXT) – 1.5
ns
tSPICLKEXT – 1.5
tSPICLKEXT – 1.5
ns
tHDS
Last SPI_CLK Edge to SPI_SS Not Asserted
5
5
ns
tSPITDS
Sequential Transfer Delay
0.5 × tSPICLK – 1.5
0.5 × tSPICLK – 1.5
ns
tSDSCI
SPI_SS Assertion to First SPI_CLK Edge
11.9
10.5
ns
tSSPID
Data Input Valid to SPI_CLK Edge (Data Input 2.0
Setup)
2.0
ns
tHSPID
SPI_CLK Sampling Edge to Data Input Invalid 1.6
1.6
ns
Switching Characteristics
tDSOE
SPI_SS Assertion to Data Out Active
tDSDHI
tDDSPID
tHDSPID
SPI_CLK Edge to Data Out Invalid (Data Out 1.5
Hold)
1
0
18.8
0
SPI_SS Deassertion to Data High Impedance 0
16.3
0
SPI_CLK Edge to Data Out Valid (Data Out
Delay)
18.8
1.5
14
ns
12.5
ns
14
ns
ns
This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPI_CLK. For the external
SPI_CLK ideal maximum frequency see the fSPICLKTEXT specification in the Clock Related Operating Conditions table on Page 53.
Rev. A | Page 88 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPI_SS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tHDS
tSPICLK
SPI_CLK
(INPUT)
tDSOE
tDDSPID
tDDSPID
tHDSPID
tDSDHI
DATA OUTPUTS
(SPI_MISO)
CPHA = 1
tSSPID
tHSPID
DATA INPUTS
(SPI_MOSI)
tDSOE
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPI_MISO)
CPHA = 0
tHSPID
tSSPID
DATA INPUTS
(SPI_MOSI)
Figure 41. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. A | Page 89 of 112 | February 2014
tSPITDS
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—SPI_RDY Slave
Timing
Table 53. SPI Port—SPI_RDY Slave Timing
VDD_EXT
1.8 V/3.3 V Nominal
Min
Max
Parameter
Switching Characteristics
tDSPISCKRDYSR
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 × tSCLK1
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 × tSCLK1
tDSPISCKRDYST
3.5 × tSCLK1 + 17.5 ns
4.5 × tSCLK1 + 17.5 ns
tDSPISCKRDYSR
SPI_CLK
(CPOL = 0)
CPHA = 0
SPI_CLK
(CPOL = 1)
SPI_CLK
(CPOL = 0)
CPHA = 1
SPI_CLK
(CPOL = 1)
SPI_RDY (O)
Figure 42. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0)
tDSPISCKRDYST
SPI_CLK
(CPOL = 1)
CPHA = 0
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
CPHA = 1
SPI_CLK
(CPOL = 0)
SPI_RDY (O)
Figure 43. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1)
Rev. A | Page 90 of 112 | February 2014
Unit
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Open Drain Mode
Timing
In Figure 44 and Figure 45, the outputs can be SPI_MOSI SPI_
MISO, SPI_D2, and/or SPI_D3 depending on the mode of
operation.
Table 54. SPI Port ODM Master Mode Timing
Parameter
Switching Characteristics
tHDSPIODMM
SPI_CLK Edge to High Impedance from Data Out Valid
SPI_CLK Edge to Data Out Valid from High Impedance
tDDSPIODMM
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
–1
0
tHDSPIODMM
6
Unit
ns
ns
tHDSPIODMM
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMM
tDDSPIODMM
Figure 44. ODM Master
Table 55. SPI Port—ODM Slave Mode
Parameter
Timing Requirements
tHDSPIODMS
SPI_CLK Edge to High Impedance from Data Out Valid
SPI_CLK Edge to Data Out Valid from High Impedance
tDDSPIODMS
Min
0
tHDSPIODMS
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMS
VDD_EXT
1.8 V/3.3 V Nominal
Max
tDDSPIODMS
Figure 45. ODM Slave
Rev. A | Page 91 of 112 | February 2014
11.5
tHDSPIODMS
Unit
ns
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
SPI_RDY is used to provide flow control. The CPOL and CPHA
bits are set in SPI_CTL, while LEADX, LAGX, and STOP are in
SPI_DLY.
Table 56. SPI Port—SPI_RDY Timing
Parameter
Timing Requirements
tSRDYSCKM0 Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 0
tSRDYSCKM1 Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 1
Switching Characteristic
tSRDYSCKM Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0
(STOP, LEADX, LAGX = 0)
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD ≥ 1
(STOP, LEADX, LAGX = 0)
Time Between Assertion of SPI_RDY by Slave and First Edge
of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEADX,
LAGX = 0)
1
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
Unit
(2.5 + 1.5 × BAUD1) × tSCLK1 +
17.5
ns
(1.5 + BAUD1) × tSCLK1 + 17.5
ns
3 × tSCLK1
4 × tSCLK1 + 17.5
(4 + 1.5 × BAUD1) × tSCLK1
(5 + 1.5 × BAUD1) × tSCLK1 + ns
17.5
(3 + 0.5 × BAUD1) × tSCLK1
(4 + 0.5 × BAUD1) × tSCLK1 + ns
17.5
BAUD value set using the SPI_CLK.BAUD bits.
tSRDYSCKM0
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
Figure 46. SPI_RDY Setup Before SPI_CLK with CPHA = 0
Rev. A | Page 92 of 112 | February 2014
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
tSRDYSCKM1
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
Figure 47. SPI_RDY Setup Before SPI_CLK with CPHA = 1
tSRDYSCKM
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
Figure 48. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x
Rev. A | Page 93 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
General-Purpose Port Timing
Table 57 and Figure 49 describe general-purpose
port operations.
Table 57. General-Purpose Port Timing
Parameter
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
Min
VDD_EXT
1.8 V/3.3 V Nominal
Max
2 × tSCLK0 – 1.5
Unit
ns
tWFI
GPIO INPUT
Figure 49. General-Purpose Port Timing
Timer Cycle Timing
Table 58 and Figure 50 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an ideal maximum input fre-
quency of (fSCLK0/4) MHz. The Period Value (VALUE) is the
timer period assigned in the TMx_TMRn_PER register and can
range from 2 to 232 – 1.
Table 58. Timer Cycle Timing
VDD_EXT
3.3 V Nominal
VDD_EXT
1.8 V Nominal
Min
Parameter
Max
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low1
2 × tSCLK0 – 1.5
2 × tSCLK0 – 1.5
ns
tWH
Timer Pulse Width Input High1
2 × tSCLK0 – 1.5
2 × tSCLK0 – 1.5
ns
tSCLK0 × VALUE – 1.5
tSCLK0 × VALUE – 1.5
ns
Switching Characteristics
tHTO
1
Timer Pulse Width Output
This specification indicates the minimum instantaneous width that can be tolerated due to duty cycle variation or jitter for TMx signals in width capture and external clock
modes. The ideal maximum frequency for TMx signals is listed in Timer Cycle Timing on this page.
TMR OUTPUT
tHTO
TMR INPUT
tWH, tWL
Figure 50. Timer Cycle Timing
Rev. A | Page 94 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Up/Down Counter/Rotary Encoder Timing
Table 59. Up/Down Counter/Rotary Encoder Timing
VDD_EXT
1.8 V Nominal
Parameter
Min
Max
VDD_EXT
3.3 V Nominal
Min
Max
Unit
Timing Requirement
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width 2 × tSCLK0
2 × tSCLK0
ns
CNT_UD
CNT_DG
CNT_ZM
tWCOUNT
Figure 51. Up/Down Counter/Rotary Encoder Timing
Pulse Width Modulator (PWM) Timing
Table 60 and Figure 52 describe PWM operations.
Table 60. PWM Timing
VDD_EXT
1.8 V Nominal
Parameter
Min
Max
VDD_EXT
3.3 V Nominal
Min
Max
Unit
Timing Requirement
tES
External Sync Pulse Width
2 × tSCLK0
ns
Switching Characteristics
tDODIS
Output Inactive (OFF) After Trip Input1
tDOE
Output Delay After External Sync1, 2
1
2
2 × tSCLK0 + 5.5
15
ns
5 × tSCLK0 + 14
ns
PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is
asynchronous to the peripheral clock. For more information, see the ADSP-BF60x Blackfin Processor Hardware Reference.
PWM_SYNC
(AS INPUT)
tES
tDOE
OUTPUT
tDODIS
PWM_TRIP
Figure 52. PWM Timing
Rev. A | Page 95 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADC Controller Module (ACM) Timing
Table 61 and Figure 53 describe ACM operations.
When internally generated, the programmed ACM clock
(fACLKPROG) frequency in MHz is set by the following equation
where CKDIV is a field in the ACM_TC0 register and ranges
from 1 to 255:
1
t ACLKPROG = -------------------------f ACLKPROG
Setup cycles (SC) in Table 61 is also a field in the ACM_TC0
register and ranges from 0 to 4095. Hold Cycles (HC) is a field
in the ACM_TC1 register that ranges from 0 to 15.
f SCLK1
f ACLKPROG = -------------------------CKDIV + 1
Table 61. ACM Timing
VDD_EXT
1.8 V/3.3 V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSDR
SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK
3
ns
tHDR
SPORT DRxPRI/DRxSEC Hold After ACMx_CLK
1.5
ns
Switching Characteristics
tSCTLCS
ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS
(SC + 1) × tSCLK1 – 3
ns
tHCTLCS
ACM Control (ACMx_A[4:0]) Hold After De-assertion of CS
HC × tACLK + 0.1
ns
tACLKW
ACM Clock Pulse Width
tACLK
ACM Clock Period1
tHCSACLK
tSCSACLK
1
1
(0.5 × tACLKPROG) – 1.5
ns
tACLKPROG – 1.5
ns
CS Hold to ACMx_CLK Edge
–0.1
ns
CS Setup to ACMx_CLK Edge
tACLK – 3.5
ns
See Table 17 on Page 53 in Clock Related Operating Conditions for details on the minimum period that may be programmed for tACLKPROG.
CS
CSPOL = 1/0
tSCSACLK
ACM_CLK
CLKPOL = 1/0
tACLK
tACLKW
tHCSACLK
ACM
CONTROLS
t SCTLCS
DRxPRI/
DRxSEC
Figure 53. ACM Timing
Rev. A | Page 96 of 112 | February 2014
tSDR
tHDR
t HCTLCS
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF60x Blackfin Processor Hardware Reference
Manual.
CAN Interface
The CAN interface timing is described in the ADSP-BF60x
Blackfin Processor Hardware Reference Manual.
Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
Table 62 describes the USB On-The-Go receive and transmit
operations.
Table 62. USB On-The-Go—Receive and Transmit Timing
VDD_USB
3.3 V Nominal
Parameter
Min
Max
Unit
Timing Requirements
fUSBS
USB_XI Frequency
48
48
MHz
fsUSB
USB_XI Clock Frequency Stability
–50
+50
ppm
Rev. A | Page 97 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
RSI Controller Timing
Table 63 and Figure 54 describe RSI controller timing.
Table 63. RSI Controller Timing
Parameter
Timing Requirements
Input Setup Time
tISU
Input Hold Time
tIH
Switching Characteristics
Clock Frequency Data Transfer Mode1
fPP
Clock Low Time
tWL
tWH
Clock High Time
Clock Rise Time
tTLH
Clock Fall Time
tTHL
tODLY
Output Delay Time During Data Transfer Mode
Output Hold Time
tOH
1
Min
VDD_EXT
1.8 V Nominal
Max
11
2
VDD_EXT
3.3 V Nominal
Min
Max
Unit
9.6
2
41.67
8
8
ns
ns
41.67
MHz
ns
ns
ns
ns
ns
ns
8
8
3
3
2.5
–1
3
3
2.5
–1
tPP = 1/fPP
VOH (MIN)
tPP
RSI_CLK
tTHL
tISU
tTLH
tWL
tIH
VOL (MAX)
tWH
INPUT
tODLY
OUTPUT
NOTES:
1 INPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS.
2 OUTPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS.
Figure 54. RSI Controller Timing
Rev. A | Page 98 of 112 | February 2014
tOH
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
10/100 Ethernet MAC Controller Timing
Table 64 through Table 66 and Figure 55 through Figure 57
describe the 10/100 Ethernet MAC Controller operations.
Table 64. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
VDD_EXT
1.8 V/3.3 V Nominal
Parameter1
Min
Max
Unit
Timing Requirements
tREFCLKF
ETHx_REFCLK Frequency (fSCLK0 = SCLK0 Frequency)
None
50 + 1%
MHz
tREFCLKW
ETHx_REFCLK Width (tREFCLK = ETHx_REFCLK Period)
tREFCLK × 35%
tREFCLK × 65%
ns
tREFCLKIS
Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data In Setup)
4
ns
tREFCLKIH
RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data In Hold)
2.2
ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
tREFCLK
RMII_REF_CLK
tREFCLKW
ETHx_RXD1–0
ETHx_CRS
ETHx_RXERR
tREFCLKIS
tREFCLKIH
Figure 55. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Table 65. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
VDD_EXT
1.8 V/3.3 V Nominal
Parameter1
Min
Max
Unit
14
ns
Switching Characteristics
tREFCLKOV
RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid)
tREFCLKOH
RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold)
1
2
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
tREFCLK
RMII_REF_CLK
tREFCLKOH
ETHx_TXD1–0
ETHx_TXEN
tREFCLKOV
Figure 56. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Rev. A | Page 99 of 112 | February 2014
ns
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 66. 10/100 Ethernet MAC Controller Timing: RMII Station Management
VDD_EXT
1.8 V/3.3 V Nominal
Parameter1
Min
Max
Unit
Timing Requirements
tMDIOS
ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup)
14
ns
tMDCIH
ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold)
0
ns
Switching Characteristics
tMDCOV
ETHx_MDC Falling Edge to ETHx_MDIO Output Valid
tMDCOH
ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold)
1
tSCLK0 + 5
tSCLK0 –1
ns
ns
ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock whose minimum period is
programmable as a multiple of the system clock SCLK0. ETHx_MDIO is a bidirectional data line.
ETHx_MDC
(OUTPUT)
tMDCOH
ETHx_MDIO
(OUTPUT)
tMDCOV
ETHx_MDIO
(INPUT)
tMDIOS
tMDCIH
Figure 57. 10/100 Ethernet MAC Controller Timing: RMII Station Management
Rev. A | Page 100 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
JTAG Test And Emulation Port Timing
Table 67 and Figure 58 describe JTAG port operations.
Table 67. JTAG Port Timing
VDD_EXT
1.8 V Nominal
Min
Parameter
Max
VDD_EXT
3.3 V Nominal
Min
Max
Unit
Timing Requirements
tTCK
JTG_TCK Period
20
tSTAP
JTG_TDI, JTG_TMS Setup Before JTG_TCK High
4
4
ns
tHTAP
JTG_TDI, JTG_TMS Hold After JTG_TCK High
4
4
ns
tSSYS
System Inputs Setup Before JTG_TCK High1
12
12
ns
1
20
ns
tHSYS
System Inputs Hold After JTG_TCK High
5
5
ns
tTRSTW
JTG_TRST Pulse Width (measured in JTG_TCK cycles)2 4
4
TCK
Switching Characteristics
JTG_TDO Delay from JTG_TCK Low
tDTDO
System Outputs Delay After JTG_TCK Low
tDSYS
3
1
18
13.5
ns
22
17
ns
System Inputs = DMC0_DQ00–15, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_15–0, PG_15–0,
SMC0_ARDY_NORWT, SMC0_BR, SMC0_D15–0, SYS_BMODE0–2, SYS_HWRST, SYS_FAULT, SYS_FAULT, SYS_NMI_RESOUT, SYS_PWRGD, TWI0_SCL, TWI0_
SDA, TWI1_SCL, TWI1_SDA.
2
50 MHz Maximum.
3
System Outputs = DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ00–15, DMC0_LDM, DMC0_LDQS,
DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, JTG_EMU, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_
15–0, PG_15–0, SMC0_AMS0, SMC0_AOE_NORDV, SMC0_ARE, SMC0_AWE, SMC0_A01, SMC0_A02, SMC0_D15–0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT,
SYS_NMI_RESOUT.
tTCK
JTG_TCK
tSTAP
tHTAP
JTG_TMS
JTG_TDI
tDTDO
JTG_TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 58. JTAG Port Timing
Rev. A | Page 101 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
OUTPUT DRIVE CURRENTS
Figure 59 through Figure 64 show typical current-voltage characteristics for the output drivers of the ADSP-BF60x Blackfin
processors. The curves represent the current drive capability of
the output drivers as a function of output voltage.
100
40
VDD_EXT = 1.9V @ – 40°C
VDD_DMC = 1.9V @ – 40°C
VDD_EXT = 1.8V @ 25°C
VDD_EXT = 1.7V @ 125°C
SOURCE CURRENT (mA)
SOURCE CURRENT (mA)
20
VOH
0
VOL
– 20
80
VDD_DMC = 1.8V @ 25°C
60
VDD_DMC = 1.7V @ 125°C
40
VOH
20
0
– 20
VOL
– 40
– 60
– 40
– 80
0
0.5
1.0
1.5
2.0
0
0.5
SOURCE VOLTAGE (V)
Figure 59. Driver Type A Current (1.8 V VDD_EXT)
2.0
100
VDD_EXT = 3.465V @ – 40°C
VDD_DMC = 1.8V @ 25°C
VDD_EXT = 3.135V @ 105°C
60
SOURCE CURRENT (mA)
VOH
20
0
– 20
VOL
– 40
VDD_DMC = 1.9V @ – 40°C
80
VDD_EXT = 3.30V @ 25°C
40
SOURCE CURRENT (mA)
1.5
Figure 61. Driver Type B Current (1.8 V VDD_DMC)
80
60
1.0
SOURCE VOLTAGE (V)
– 60
VDD_DMC = 1.7V @ 125°C
40
VOH
20
0
– 20
VOL
– 40
– 60
– 80
– 80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
SOURCE VOLTAGE (V)
1.0
1.5
SOURCE VOLTAGE (V)
Figure 60. Driver Type A Current (3.3 V VDD_EXT)
Figure 62. Driver Type C Current (1.8 V VDD_DMC)
Rev. A | Page 102 of 112 | February 2014
2.0
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Output Enable Time Measurement
0
VDD_EXT = 1.9V @ – 40°C
Output balls are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
VDD_EXT = 1.8V @ 25°C
VDD_EXT = 1.7V @ 125°C
SOURCE CURRENT (mA)
–5
The output enable time tENA is the interval from the point when
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 66.
– 10
VOL
– 15
REFERENCE
SIGNAL
– 20
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
tDIS_MEASURED
tDIS
VOH
(MEASURED)
Figure 63. Driver Type D Current (1.8 V VDD_EXT)
VOL
(MEASURED)
0
tENA_MEASURED
tENA
VOH (MEASURED) ⴚ ⌬V
VOH(MEASURED)
VTRIP(HIGH)
VOL (MEASURED) + ⌬V
VTRIP(LOW)
VOL (MEASURED)
tDECAY
VDD_EXT = 3.465V @ – 40°C
tTRIP
VDD_EXT = 3.30V @ 25°C
SOURCE CURRENT (mA)
VDD_EXT = 3.135V @ 125°C
OUTPUT STOPS DRIVING
– 20
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
Figure 66. Output Enable/Disable
– 40
VOL
– 60
0
1.0
2.0
3.0
4.0
SOURCE VOLTAGE (V)
Figure 64. Driver Type D Current (3.3 V VDD_EXT)
Time tENA is calculated as shown in the equation:
TEST CONDITIONS
All Timing Requirements appearing in this data sheet were
measured under the conditions described in this section.
Figure 65 shows the measurement point for AC measurements
(except output enable/disable). The measurement point VMEAS is
VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/
2.5 V/3.3 V.
INPUT
OR
OUTPUT
VMEAS
The time tENA_MEASURED is the interval from when the reference
signal switches to when the output voltage reaches VTRIP(high)
or VTRIP(low). For VDDEXT/VDDMEM (nominal) = 1.8 V, VTRIP
(high) is 1.05 V, and VTRIP (low) is 0.75 V. For VDDEXT/VDDMEM
(nominal) = 2.5 V, VTRIP (high) is 1.5 V and VTRIP (low) is 1.0 V.
For VDDEXT/VDDMEM (nominal) = 3.3 V, VTRIP (high) is 1.9 V, and
VTRIP (low) is 1.4 V. Time tTRIP is the interval from when the output starts driving to when the output reaches the VTRIP(high) or
VTRIP(low) trip voltage.
VMEAS
Figure 65. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
t ENA = t ENA_MEASURED – t TRIP
If multiple balls (such as the data bus) are enabled, the measurement value is that of the first ball to start driving.
Output Disable Time Measurement
Output balls are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 66.
t DIS = t DIS_MEASURED – t DECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:
t DECAY = ( C L ΔV ) ⁄ I L
Rev. A | Page 103 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V
and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. CL is
the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time is tDECAY
plus the various output disable times as specified in the Timing
Specifications on Page 60.
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 67). VLOAD is equal
to (VDD_EXT)/2.
tRISE
14
tFALL
RISE AND FALL TIMES (ns)
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
16
12
10
8
6
4
2
tFALL = 1.8V @ 25°C
tRISE = 1.8V @ 25°C
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 68. Driver Type A Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (VDD_EXT = 1.8 V)
14
TESTER PIN ELECTRONICS
50:
VLOAD
T1
DUT
OUTPUT
45:
70:
ZO = 50:(impedance)
TD = 4.04 r 1.18 ns
50:
4pF
0.5pF
RISE AND FALL TIMES (ns)
tRISE
12
tFALL
10
8
6
4
2pF
2
400:
tFALL = 3.3V @ 25°C
tRISE = 3.3V @ 25°C
0
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
0
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 69. Driver Type A Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (VDD_EXT = 3.3 V)
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
1.4
tRISE DS = 10
Figure 67. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
1.2
RISE AND FALL TIMES (ns)
The graphs of Figure 68 through Figure 70 show how output
rise and fall times vary with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear outside the ranges shown.
50
1.0
tFALL DS = 10
0.8
tRISE DS = 00
0.6
tFALL DS = 00
0.4
0.2
tFALL = 1.8V @ 25°C
tRISE = 1.8V @ 25°C
0
0
5
10
15
20
25
30
35
LOAD CAPACITANCE (pF)
Figure 70. Driver Type B & C Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (VDD_DMC = 1.8 V)
Rev. A | Page 104 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ENVIRONMENTAL CONDITIONS
In Table 68, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
To determine the junction temperature on the application
printed circuit board use:
Thermal Diode
T J = T CASE + ( Ψ JT × P D )
The processor incorporates a thermal diode to monitor the die
temperature. The thermal diode is a grounded collector, PNP
Bipolar Junction Transistor (BJT). The SYS_TDA ball is connected to the emitter and the SYS_TDK ball is connected to the
base of the transistor. These balls can be used by an external
temperature sensor (such as the ADM 1021A or the LM86 or
others) to read the die temperature of the chip.
where:
TJ = Junction temperature (°C)
TCASE = Case temperature (°C) measured by customer at top
center of package.
ΨJT = From Table 68
PD = Power dissipation (see Total Internal Power Dissipation on
Page 57 for the method to calculate PD)
Table 68. Thermal Characteristics
Parameter
θJA
θJMA
θJMA
θJC
ΨJT
ΨJT
ΨJT
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
16.7
14.6
13.9
4.41
0.11
0.24
0.25
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
The technique used by the external temperature sensor is to
measure the change in VBE when the thermal diode is operated
at two different currents. This is shown in the following
equation:
kT
ΔV BE = n Q × ------ × In(N)
q
where:
nQ = multiplication factor close to 1, depending on process
variations
k = Boltzmann’s constant
T = temperature (°Kelvin)
q = charge of the electron
N = ratio of the two currents
The two currents are usually in the range of 10 micro Amperes
to 300 micro Amperes for the common temperature sensor
chips available.
Table 69 contains the thermal diode specifications using the
transistor model. Note that Measured Ideality Factor already
takes into effect variations in beta (Β).
where:
TA = Ambient temperature (°C)
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
Table 69. Thermal Diode Parameters—Transistor Model
Symbol
IFW1
IE
nQ2, 3
RT2, 4
Parameter
Forward Bias Current
Emitter Current
Transistor Ideality
Series Resistance
Min
10
10
Typ
1.006
2.8
1
Max
300
300
Unit
μA
μA
Ω
Analog Devices does not recommend operation of the thermal diode under reverse bias.
2
Not 100% tested. Specified by design characterization.
3
The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: IC = IS × (exp(qVBE/nQkT– 1), where IS = saturation current,
q = electrical charge, VBE = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4
The series resistance (RT) can be used for more accurate readings as needed.
Rev. A | Page 105 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x 349-BALL CSP_BGA BALL ASSIGNMENTS
The 349-Ball CSP_BGA Ball Assignment (Numerical by Ball
Number) table lists the CSP_BGA package by ball number for
the ADSP-BF609.
The 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin
Name) table lists the CSP_BGA package by signal.
349-BALL CSP_BGA BALL ASSIGNMENT (NUMERICAL BY BALL NUMBER)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
Pin Name
GND
USB0_DM
USB0_DP
PB_10
PB_07
PA_14
PA_12
PA_10
PA_08
PA_06
PA_04
PA_02
PA_00
SMC0_A01
SMC0_D00
SMC0_AMS0
SMC0_D03
SMC0_D04
SMC0_D07
SMC0_D10
SMC0_AWE
GND
USB0_VBUS
GND
USB0_ID
PB_11
PB_08
PA_15
PA_13
PA_11
PA_09
PA_07
PA_05
PA_03
PA_01
SMC0_A02
SMC0_D01
SMC0_D15
SMC0_D09
SMC0_D02
SMC0_D13
SMC0_D05
Ball No.
B21
B22
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D01
D02
D03
D11
D12
D20
D21
D22
E01
E02
E03
E05
E20
E21
E22
F01
F02
F03
Pin Name
GND
SMC0_AOE_NORDV
USB0_CLKIN
USB0_VBC
GND
PB_12
PB_09
PB_06
PB_05
PB_04
PB_03
PB_02
PB_01
PB_00
SMC0_BR
SMC0_D06
SMC0_D12
SMC0_ARE
SMC0_D08
SMC0_D11
SMC0_D14
GND
TWI1_SCL
TWI0_SCL
JTG_TDI
JTG_TDO
JTG_TCK
VDD_EXT
GND
SMC0_ARDY_NORWT
TWI1_SDA
TWI0_SDA
JTG_TRST
JTG_EMU
JTG_TMS
VDD_USB
DMC0_CAS
DMC0_DQ10
DMC0_DQ13
SYS_FAULT
SYS_FAULT
SYS_NMI_RESOUT
Ball No.
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F20
F21
F22
G01
G02
G03
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G20
G21
G22
H01
H02
H03
H06
H07
H16
H17
H20
H21
Pin Name
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_DMC
DMC0_CS0
DMC0_DQ15
DMC0_DQ08
GND
SYS_HWRST
SYS_BMODE2
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
SYS_CLKIN
SYS_XTAL
SYS_BMODE1
VDD_EXT
VDD_EXT
VDD_DMC
VDD_DMC
DMC0_RAS
DMC0_DQ09
Rev. A | Page 106 of 112 | February 2014
Ball No.
H22
J01
J02
J03
J06
J09
J10
J11
J12
J13
J14
J17
J20
J21
J22
K01
K02
K03
K06
K08
K09
K10
K11
K12
K13
K14
K15
K17
K20
K21
K22
L01
L02
L03
L04
L06
L08
L09
L10
L11
L12
L13
Pin Name
DMC0_DQ14
GND
SYS_PWRGD
SYS_BMODE0
VDD_EXT
GND
GND
GND
GND
GND
GND
VDD_DMC
DMC0_ODT
DMC0_DQ12
DMC0_DQ11
PC_00
SYS_EXTWAKE
PB_13
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
VDD_DMC
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
PC_02
PC_01
PB_14
VDD_EXT
VDD_EXT
GND
GND
GND
GND
GND
GND
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Ball No.
L14
L15
L17
L19
L20
L21
L22
M01
M02
M03
M04
M06
M08
M09
M10
M11
M12
M13
M14
M15
M17
M19
M20
M21
M22
N01
N02
N03
N06
N08
N09
N10
N11
N12
N13
N14
N15
N17
N20
N21
N22
P01
P02
P03
P06
P09
P10
Pin Name
GND
GND
VDD_DMC
VREF_DMC
DMC0_CK
DMC0_DQ06
DMC0_DQ07
PC_04
PC_03
PB_15
GND
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
VDD_DMC
GND
DMC0_CK
DMC0_DQ00
DMC0_DQ01
PC_06
PC_05
SYS_CLKOUT
VDD_EXT
GND
GND
GND
GND
GND
GND
GND
GND
VDD_DMC
DMC0_WE
DMC0_DQ04
DMC0_DQ03
PC_08
PC_07
PD_06
VDD_EXT
GND
GND
Ball No.
P11
P12
P13
P14
P17
P20
P21
P22
R01
R02
R03
R06
R07
R16
R17
R20
R21
R22
T01
T02
T03
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T20
T21
T22
U01
U02
U03
U06
U07
U08
U09
U10
U11
U12
U13
Pin Name
GND
GND
GND
GND
VDD_DMC
DMC0_CKE
DMC0_DQ02
DMC0_DQ05
PC_10
PC_09
PD_07
VDD_EXT
VDD_EXT
VDD_DMC
VDD_DMC
DMC0_BA2
DMC0_BA0
DMC0_A10
PC_12
PC_11
PD_08
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_DMC
VDD_DMC
DMC0_A03
DMC0_A07
DMC0_A12
PC_14
PC_13
PD_09
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_EXT
VDD_EXT
VDD_INT
Ball No.
U14
U15
U16
U17
U20
U21
U22
V01
V02
V03
V20
V21
V22
W01
W02
W03
W11
W12
W20
W21
W22
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA01
AA02
AA03
AA04
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_DMC
DMC0_A09
DMC0_A05
DMC0_A01
PD_00
PC_15
PD_10
DMC0_BA1
DMC0_A13
DMC0_A11
PD_04
PD_01
PD_12
GND
VDD_TD
DMC0_A04
DMC0_A06
DMC0_A08
PD_03
PD_02
GND
PD_15
PE_02
PE_05
PE_06
PE_07
PE_08
PE_09
SYS_TDK
SYS_TDA
PE_12
PE_10
PE_11
PG_09
PG_01
PG_04
PG_11
GND
DMC0_A00
DMC0_A02
PD_11
GND
PD_13
PE_00
Rev. A | Page 107 of 112 | February 2014
Ball No.
AA05
AA06
AA07
AA08
AA09
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Pin Name
PE_03
PF_14
PF_12
PF_10
PF_08
PF_06
PF_04
PF_02
PF_00
PG_00
PE_15
PE_14
PG_05
PG_08
PG_07
PG_13
GND
GND
GND
PD_05
PD_14
PE_01
PE_04
PF_15
PF_13
PF_11
PF_09
PF_07
PF_05
PF_03
PF_01
PE_13
PG_03
PG_06
PG_02
PG_12
PG_14
PG_15
PG_10
GND
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
349-BALL CSP_BGA BALL ASSIGNMENT (ALPHABETICAL BY PIN NAME)
Pin Name
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_WE
Ball No.
Y21
U22
Y22
T20
W20
U21
W21
T21
W22
U20
R22
V22
T22
V21
R21
V20
R20
E20
M20
P20
L20
F20
M21
M22
P21
N22
N21
P22
L21
L22
F22
H21
E21
J22
J21
E22
H22
F21
K20
K22
K21
J20
H20
G20
G21
G22
N20
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
A01
A22
AA02
AA21
AA22
AB01
AB22
B21
C20
D12
G01
J01
J09
J10
J11
J12
J13
J14
K08
K09
K10
K11
K12
K13
K14
K15
L08
L09
L10
L11
L12
L13
L14
L15
M04
M08
M09
M10
M11
M12
M13
M14
M15
M19
N08
N09
N10
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
Rev. A | Page 108 of 112 | February 2014
Ball No.
N11
N12
N13
N14
N15
P09
P10
P11
P12
P13
P14
W11
Y03
Y20
C03
B02
E02
D03
D01
D02
E03
E01
A13
B13
A12
B12
A11
B11
A10
B10
A09
B09
A08
B08
A07
B07
A06
B06
C12
C11
C10
C09
C08
C07
C06
A05
B05
Pin Name
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
Ball No.
C05
A04
B04
C04
K03
L03
M03
K01
L02
L01
M02
M01
N02
N01
P02
P01
R02
R01
T02
T01
U02
U01
V02
V01
W02
Y02
Y01
W01
AB02
P03
R03
T03
U03
V03
AA01
W03
AA03
AB03
Y04
AA04
AB04
Y05
AA05
AB05
Y06
Y07
Y08
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Pin Name
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
PG_06
PG_07
PG_08
PG_09
PG_10
PG_11
PG_12
PG_13
PG_14
PG_15
SMC0_A01
SMC0_A02
SMC0_AMS0
SMC0_AOE_NORDV
SMC0_ARDY_NORWT
SMC0_ARE
SMC0_AWE
Ball No.
Y09
Y10
Y14
Y15
Y13
AB14
AA16
AA15
AA13
AB13
AA12
AB12
AA11
AB11
AA10
AB10
AA09
AB09
AA08
AB08
AA07
AB07
AA06
AB06
AA14
Y17
AB17
AB15
Y18
AA17
AB16
AA19
AA18
Y16
AB21
Y19
AB18
AA20
AB19
AB20
A14
B14
A16
B22
D20
C16
A21
Pin Name
SMC0_BR
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_NMI_RESOUT
SYS_PWRGD
SYS_HWRST
SYS_TDA
SYS_TDK
SYS_XTAL
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
USB0_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Ball No.
C13
A15
B15
B18
A17
A18
B20
C14
A19
C17
B17
A20
C18
C15
B19
C19
B16
J03
H03
G03
H01
N03
K02
F02
F01
F03
J02
G02
Y12
Y11
H02
C22
D22
C21
D21
C01
A02
A03
B03
C02
B01
F17
G16
G17
H16
H17
J17
Pin Name
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
Rev. A | Page 109 of 112 | February 2014
Ball No.
K17
L17
M17
N17
P17
R16
R17
T16
T17
U17
D11
F06
F11
F12
G06
G07
G10
G11
G12
G13
H06
H07
J06
K06
L04
L06
M06
N06
P06
R06
R07
T06
T07
T10
T11
T12
T13
U06
U11
U12
F07
F08
F09
F10
F13
F14
F15
Pin Name
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_TD
VDD_USB
VREF_DMC
Ball No.
F16
G08
G09
G14
G15
T08
T09
T14
T15
U07
U08
U09
U10
U13
U14
U15
U16
W12
E05
L19
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
349-BALL CSP_BGA BALL CONFIGURATION
Figure 71 shows an overview of signal placement on the 349-ball
CSP_BGA package.
TOP VIEW
2
A1 BALL
PAD CORNER
1
4
6
3
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
A
B
C
D
U
E
D
F
G
D D
D D
J
D
D
L
D
H
K
GND
D
M
D
N
I/O SIGNALS
D
P
R
D D
U
D D
D
T
VDD_EXT
VDD_INT
V
T
W
Y
AA
AB
D
VDD_DMC
T
VDD_TD
U
VDD_USB
BOTTOM VIEW
22
20
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
A1 BALL
PAD CORNER
2
3
1
A
B
C
D
U
E
D
F
D D
G
D D
H
D
J
D
D
L
K
D
M
D
D
N
D D
R
D D
D
U
P
T
V
T
W
Y
AA
AB
Figure 71. 349-Ball CSP_BGA Ball Configuration
Rev. A | Page 110 of 112 | February 2014
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
OUTLINE DIMENSIONS
Dimensions for the 19 mm × 19 mm CSP_BGA package in
Figure 72 are shown in millimeters.
A1 BALL
CORNER
19.10
19.00 SQ
18.90
A1 BALL
CORNER
22 20 18 16 14 12 10 8 6 4 2
21 19 17 15 13 11 9 7 5 3 1
A
C
G
16.80
BSC SQ
J
F
H
K
L
M
N
0.80
BSC
B
D
E
P
R
T
U
W
AA
TOP VIEW
1.50
1.36
1.21
1.10 REF
V
Y
AB
BOTTOM VIEW
DETAIL A
DETAIL A
1.11
1.01
0.91
0.35 NOM
0.30 MIN
SEATING
PLANE
0.50
COPLANARITY
0.20
0.45
0.40
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.
Figure 72. 349-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-349-1)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 70 is provided as an aid to Requirements for Surface-Mount
PCB design. For industry-stan- Design and Land Pattern
dard design recommendations, Standard.
refer to IPC-7351, Generic
Table 70. BGA Data for Use with Surface-Mount Design
Package
BC-349-1
Package
Ball Attach Type
Solder Mask Defined
Rev. A | Page 111 of 112 | February 2014
Package
Solder Mask Opening
0.4 mm Diameter
Package
Ball Pad Size
0.5 mm Diameter
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
AUTOMOTIVE PRODUCTS
The models in the following table are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers
should review the product specifications section of this data sheet carefully. Contact your local ADI account representative for specific
product ordering information and to obtain the specific Automotive Reliability reports for these models.
Model1
ADBF606WCBCZ4xx
ADBF607WCBCZ5xx
ADBF608WCBCZ5xx
ADBF609WCBCZ5xx
1
2
Max. Core Clock
400 MHz
500 MHz
500 MHz
500 MHz
Temperature
Range2
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
Package
Option
BC-349-1
BC-349-1
BC-349-1
BC-349-1
Z =RoHS compliant part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 52 for the junction temperature
(TJ) specification which is the only temperature specification.
ORDERING GUIDE
Model1
ADSP-BF606KBCZ-4
ADSP-BF606BBCZ-4
ADSP-BF607KBCZ-5
ADSP-BF607BBCZ-5
ADSP-BF608KBCZ-5
ADSP-BF608BBCZ-5
ADSP-BF609KBCZ-5
ADSP-BF609BBCZ-5
1
2
Max. Core Clock
400 MHz
400 MHz
500 MHz
500 MHz
500 MHz
500 MHz
500 MHz
500 MHz
Temperature
Range2
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
Package Description
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
Package
Option
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
Z =RoHS compliant part.
Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 52 for the junction temperature
(TJ) specification which is the only temperature specification.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10659-0-02/14(A)
Rev. A | Page 112 of 112 | February 2014