AND8149/D
Understanding and Using
the NCV1124 VR Sensor
Interface
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APPLICATION NOTE
The voltage developed by the VR sensor is applied
through resistor R1 to the IN1 pin. When the VR sensor
produces no voltage (VRS = 0) the IN1 pin is biased to the
voltage developed by I1 x (R1 + RRS). When the diagnostic
pin is at GND (normal mode) the IN1 voltage is compared
by COMP1 to the voltage at the INADJ pin developed by
I2 x RADJ plus or minus VHYS. When the diagnostic pin is
at VCC (diagnostic mode) the IN1 voltage is compared to the
voltage developed by (I2 + I3) x RADJ plus VHYS.
From the comparator’s viewpoint, these voltages are
respectively VP and VN, as shown by the labels in the block
diagram at the comparator’s inputs, P and N. When VN > VP,
the comparator output will be low, transistor N1 will be off
and OUT1 will be [VCC. When VN < VP, the comparator
output will be high, transistor N1 will be on and OUT1 will
be [GND.
The NCV1124 offers a dual−channel low component
count interface solution for ground referenced variable
reluctance sensors. The product is easy to use when the basic
circuit operation is understood and when certain application
guidelines are followed. This note, along with the NCV1124
data sheet (NCV1124/D) will provide the user with the
information necessary for successful application.
Circuit Basics
Each channel of the NCV1124 has independent input bias
and clamp circuitry, and independent comparators with
Hysteresis voltage generators. Both channels share a
common reference generator for normal and diagnostic
modes. A block diagram detailing one channel is shown in
Figure 1 along with some of the external application
components. We’ll explore the circuit using one channel
and, where convenient, use a subscripted “x” to indicate
either channel.
NCV1124
VCC
DIAG
20 k
I1
(11 mA)
IN2
I2
(11 mA)
I3
(6.05 mA)
OUT2
IO1
OUT1
RRS
INP1
IN1
C1
D1
VRS
VR SENSOR
R1
P
ACTIVE
CLAMP
"VHYS
("160 mV)
N
+
-
N1
COMP1
INADJ
TO COMP2
INADJ
GND
RADJ
Figure 1. NCV1124 Block Diagram
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 1
1
Publication Order Number:
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Figure 4. For clarity, the VR sensor voltage is shown as a
triangular wave.
The polarity of VHYS is controlled by the input states of
COMP1. When VIN1 < VINADJ, VHYS has the polarity
shown in Figure 2A. When VIN1 > VINADJ, VHYS has the
polarity shown in Figure 2B.
+TRP
A
B
VINX
P
IN1
INADJ
−+
VHYS
N
IN1
INADJ
+
-
P
+−
VHYS
VIN1 t VINADJ
N
+
-
−TRP
VOUTX
Figure 2. Hysteresis Voltage States
GND
In the normal mode, VHYS is alternately added to and
subtracted from the bias voltage developed by I2 x RADJ. In
the diagnostic mode, VHYS is added to the bias voltage
developed by (I2 + I3) x RADJ. The resultant voltages are
described in the data sheet variously as "VHYS or as
the trip point ("TRP) thresholds, nominally specified as
"160 mV around the bias voltage developed by INADJ and
RADJ. Figure 3 shows the threshold and bias voltage
relationships between VINADJ and VHYS for normal and
diagnostic modes, and the bias voltage for VINX (VIN1).
Figure 4. Input vs. Threshold and Output
Responses (Normal Mode)
Let’s review the circuit basics, using Figure 1. We’ll use
the component values of RRS = 1.0 kW, R1 = 22 kW and
RADJ = 24 kW, and we’ll use the typical data sheet values:
"VHYS = "160 mV, INP1 = 11 mA, and INADJ =
KI x INP1, where KI = 1.00 in the normal mode and KI = 1.55
in the diagnostic mode. We’ll ignore C1 for the moment.
Assume that RADJ is zero, that DIAG = GND (normal
mode), and that we’ve connected a voltage source (VRS) to
IN1. Assume also that R1 and RRS are zero. OUT1 will then
go low when VRS is increased to slightly greater than
+160 mV above GND, and then go high when VRS is
decreased to slightly less than −160 mV below GND. With
the INADJ pin connected to GND (RADJ = 0), "TRP =
"VHYS and the trip points are "VHYS around GND. The
lowest INX signal we can detect is "VHYS.
Next we’ll set RADJ = 24 kW, set RRS = 1.0 kW and R1 =
22 kW. Using the equivalent RRS + R1 resistance of 23 kW
(REQ) and the 11 mA INP1 (I1) current, VIN1 (with VRS = 0)
will be 253 mV (11 mA x 23 kW). Since in the normal mode
KI = 1.00, the INADJ current is 11 mA (I2) and VINADJ is now
264 mV (11 mA x 24 kW). With INADJ biased to VINADJ,
"TRP = VINADJ " VHYS and the trip points are "VHYS
around VINADJ. OUT1 will change states when VIN1 is
slightly greater than +424 mV and when VIN1 is slightly less
than +104 mV (264 mV " 160 mV) above GND.
With REQ nearly the same as RADJ and since 253 mV <
264 mV (VIN1 < VINADJ), VHYS will be +160 mV
(Figure 2) and OUT1 will be in a high state since 253 mV <
424 mV (VIN1 < VINADJ + VHYS or VP < VN). With VIN1 =
253 mV, OUT1 will go low when VRS is slightly greater than
171 mV above VINADJ, and VHYS will change polarity to
–160 mV. When VRS is slightly less than 149 mV below
VINADJ, OUT1 will go high and VHYS will change back to
+160 mV. In the normal mode, INADJ = INP1 and with REQ
[ RADJ, the lowest INX signal we can detect is (VINADJ –
VINX) " VHYS.
+VHYS
+TRP
(I2 + I3) x RADJ
800 mV MAX
+VHYS
−VHYS
−TRP
I2 x RADJ
NORMAL
MODE
VP
VCC
VIN1 u VINADJ
VINADJ
VN
VINADJ
DIAGNOSTIC
MODE
VINX
I1 x (R1 + RRS)
Figure 3. Comparator Bias Points and Thresholds
The resistance of R1 + RRS should be substantially equal
to RADJ as prescribed by the data sheet. In the normal mode
INPX = INADJ and equal resistances at the INX and INADJ
pins will establish equal voltage bias points. The voltage
produced by the VR sensor alternates around the VINX bias
voltage. The VINX " VRS voltage (VP) is compared to the
"TRP voltage (VN) produced by the alternating polarity of
VHYS around the VINADJ bias voltage. The NCV1124’s
normal mode input vs. output responses are shown in
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AND8149/D
at the VCC pin and the INX and INADJ pins. Assuming that
diagnostics are done at power−up, and since VINADJ + VHYS
is the reference to which VINX is compared, we need to
establish VINADJ before VINX to guarantee predictable
behavior. The RC delays imposed by pre−conditioning also
need to be considered in order to obtain correct diagnostic
results. The following sections will show the circuit
behavior with and without the presence of a VR sensor and
with several circuit modifications. The sensor used with the
test circuits is a 680 mH 1.0 kW automotive−type sensing
unit. In all cases the DIAG input is held low. Be sure to note
the voltage and time scales in the graphs presented.
Now we’ll set the VRS voltage to zero volts. When VIN1
is compared to VINADJ + VHYS (the 424 mV trip point),
OUT1 will be in a high state since 253 mV < 424 mV (VP
< VN). If we increase REQ to slightly above 38.545 kW
(424 mV/11 mA) OUT1 will go to a low state (VP > VN).
Now we’ll set DIAG = VCC. Since in the diagnostic mode
KI = 1.55, the current at the INADJ pin will increase by 55%
to 17.05 mA (I2 + I3) so that the INADJ bias voltage is now
409.2 mV (17.05 mA x 24 kW) and the trip point is now
569.2 mV (VINADJ + VHYS). With VIN1 at 424 mV
(38.545 kW x 11 mA) OUT1 will be in a high state since
424 mV < 569.2 mV (VP < VN). If we further increase REQ
to slightly above 51.745 kW (569.2 mV/11 mA) OUT1 will
go to a low state (VP > VN).
These results show that we can expect to diagnose
minimum (RDMIN) and maximum (RDMAX) resistances
respectively at 38.545 kW, equivalent to [(1.00 x RADJ) +
(VHYS/INPX)] and at 51.745 kW, equivalent to [(1.55 x RADJ)
+ (VHYS/INPX)] and a resistance change of 51.745 kW –
38.545 kW =13.2 kW, equivalent to 0.55 x RADJ.
Powering Up
The slew rate of the VCC power supply must be slow
enough to allow the internal bias currents and voltages to be
correctly established. Using the test circuit in Figure 6 we
can observe the power−up behavior when a step is applied
to the VCC pin.
0−5 V STEP
+
Input Clamps
There are two clamp points associated with the inputs IN1
and IN2. Figure 5 shows the simplified clamp circuitry. The
data sheet specifies these points as positive (7.0 V typical)
and negative (−0.30 V typical.) Since VR sensors can easily
produce voltages in excess of 120 V peak, the 7.0 V clamp
prevents damage to the NCV1124 by keeping these voltages
below the breakdown voltage of the manufacturing process
for the product. Since the substrate of an integrated circuit
must always be at the lowest voltage potential, the –0.30 V
clamp prevents turn−on of parasitic elements within the IC.
IN1
IN2
24 K
C1
22 nF
C2
22 nF
INADJ
VCC
IN1
OUT1
OUT1
IN2
OUT2
OUT2
GND
DIAG
S1
Figure 6. Test Circuit 1
N1
D1
7V
R2
22 K
RADJ
NCV1124
VCC
INX
R1
22 K
+
−
The graphs of Figures 7 and 8 show the results when a
5.0 V VCC step is applied to Test Circuit 1, with and without
a VR sensor. In Figure 7 the VIN1 quickly reaches the 1.6 V
clamp point despite the 22 nF capacitor at the IN1 pin.
Because of the quick rise time of the VCC step, the INP1
current is not yet well controlled (>>11 mA.) Figure 8 shows
that when a VR sensor is present, VIN1 still quickly
approaches the 1.6 V clamp, then decays to the level defined
by INP1 x (R1 + RRS). The decay rate (tIN1) is established
by C1 x (R1 + RRS). Note that in both graphs VIN1 is
established before VINADJ (our reference node) and OUT1
remains low.
300 mV
Figure 5. Simplified Input Clamp Circuit
Circuit Dynamics
Getting predictable behavior from the NCV1124 requires
correct power−up and pre−conditioning of the comparators’
inputs. Since there is no internal power−up control circuitry,
this must be managed in the application via the components
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AND8149/D
OUT1
IN1
INADJ
VCC
Figure 7. Sensor Absent
Figure 8. Sensor Present
Experiment has shown that proper operation results with
a VCC slew rate of about 1.0 V/ms, so limiting the slew rate
to 0.5 V/ms adds sufficient margin. If the bulk filter
capacitance in the application’s 5.0 V regulator circuit isn’t
large enough to keep the slew rate to v 0.5 V/ms, a simple
RC network added to the VCC pin can do the trick. A VCC
bypass capacitor is recommended in any event. Figure 9
shows the RSLEW−CSLEW arrangement.
The NCV1124 data sheet specifies 5.0 mA maximum
operating current, so choosing RSLEW = 39 W would
produce about a 200 mV drop at the VCC pin. Recalling that
an exponential response is linear over the range of t = 0 to
t = 0.6t, set t/t = 0.6 and solve for Vt: Vt = [5.0 V−0.2 V] x
[1−e−0.6] = 2.16 V. Given the 0.5 V/ms requirement, the time
needed to reach 2.16 V is: 2.16 V/(0.5 V/ms) = 4.32 ms.
Since this time represents t/t = 0.6, we solve that t = t/0.6:
4.32 ms/0.6 = 7.2 ms. Lastly we find CSLEW = t/RSLEW =
185 nF and choose the next highest standard value, 220 nF.
Note that the choice for RSLEW only accounted for the
voltage drop produced during power−up and did not
consider additional dynamic currents during output
switching or activation of the negative INX clamps, each of
which will produce additional drops (ripple voltages) at the
VCC pin. RSLEW can be decreased and CSLEW increased to
reduce ripple voltages.
Figure 10 shows that our VCC slew rate is now 0.425 V/ms
when a 5.0 V step is applied to Test Circuit 2 (and also
reveals the intrinsic start−up delay of the NCV1124’s
internal circuitry, [130 ms for the sample tested.)
0−5 V STEP
+
RSLEW
39 W
IN1
IN2
R1
22 K
R2
22 K
RADJ
24 K
C1
22 nF
C2
22 nF
INADJ
CSLEW
220 nF
VCC
IN1
OUT1
OUT1
IN2
OUT2
OUT2
GND
DIAG
S1
NCV1124
Figure 9. Test Circuit 2
OUT1
IN1
INADJ
0.425 V/ms
VCC
Figure 10. VCC Slew v 0.5 V/ms
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AND8149/D
Figures 11 and 12 show the results when a 5.0 V VCC step
is applied to Test Circuit 2. Figure 11 shows that the VIN1
ramps linearly to the 1.6 V clamp point in about 3.0 ms due
to C1 and the now correctly established INP1 current. Since
VINADJ is already established as VIN1 ramps up, OUT1
initially goes high and then low when VIN1 crosses the +TRP
threshold. Figure 12 shows that when a VR sensor is present,
the VIN1 rises exponentially to the level defined by INP1 x
(R1 + RRS). Again, the rise rate (tIN1) is established by C1
x (R1 + RRS). In both cases VIN1 has the expected response
when the correctly established INP1 current step is applied
to a capacitor (sensor absent) or an RC combination.
OUT1
IN1
INADJ
VCC
Figure 11. Sensor Absent
Figure 12. Sensor Present
Pre−Conditioning
As described in the data sheet, R1 and C1 provide a low
pass filter and, when power−up is properly managed, also
serve to pre−condition the comparator to the correct state by
delaying the IN1 signal. We could also force VINADJ to be
quickly established regardless of the external components at
the INX inputs. Adding a capacitor (C3 in Figure 13)
between the power supply and INADJ pin does the job for
both channels. With (R1 + RRS) [ RADJ, choosing C3 = C1
gives nearly equal tINX and tINADJ time constants and
settling times under nominal circuit conditions.
The benefit of C3 comes with both a risk and a penalty.
Power supply noise could be coupled through C3 to INADJ
and thereby risk modulation of the comparators’ trip points.
The risk could be reduced by using separate a “clean” supply
or by using a voltage reference w 1.6 V (the clamp voltage.)
Of course, we’d have to be certain that these alternate
voltages are established before the NCV1124’s VCC voltage.
The penalty is the delay that results from the RADJ x C3 time
constant, tINADJ. We need to wait several time constants at
power−up and when changing from the normal mode to the
diagnostic mode before sampling OUTX.
0−5 V STEP
+
C3 22 nF
IN1
IN2
R1
22 K
R2
22 K
RADJ
24 K
C1
22 nF
C2
22 nF
INADJ
RSLEW
39 W
CSLEW
220 nF
VCC
IN1
OUT1
OUT1
IN2
OUT2
OUT2
GND
DIAG
S1
NCV1124
Figure 13. Test Circuit 3
Figures 14 and 15 show the results when a 5.0 V VCC step
is applied to Test Circuit 3. Both figures show the effect of
C3 on VINADJ. Since C3 initially appears as a short−circuit,
VINADJ is quickly brought to the power supply voltage, then
decays to the bias point defined by INADJ x RADJ. The decay
rate (tINADJ) is established RADJ x C3. Again, in both cases
VIN1 has the expected responses.
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AND8149/D
OUT1
IN1
INADJ
VCC
Figure 14. Sensor Absent
Figure 15. Sensor Present
Diagnostic Operation
Now that we’ve examined the circuit basics and the
power−up and pre−conditioning requirements, we can
examine how to interpret the NCV1124’s outputs at
power−up and when changing modes. We can also see the
impact of the component choices and how the resulting
delays (tINX and tINADJ) imposed affect diagnostics.
Each input circuit consists of a VR sensor, series resistor,
and filter capacitor. While equation 13 in the data sheet
shows how to determine the quality of the VR sensor
resistance RRS, the quality of the entire input circuit can be
assessed by including the series resistor with RRS: RRS + RX
= [(INPX x KI x RADJ) + VHYS]/INPX.
A shorted sensor or shorted filter capacitor can be
diagnosed if no change in the output occurs during normal
operation (DIAG = GND) when it is expected that the VR
sensor should produce an output voltage greater than
(VINADJ – VINX) " VHYS.
An open sensor or series resistor (Figures 11 and 14) can
be diagnosed at power−up (DIAG = GND) after the delay
that results from tINADJ and, since CV/I = t, after the delay
(tINX) that results from CX, VCLAMPX, and INPX. VIN1
eventually reaches the 1.6 V clamp voltage and VINADJ will
eventually settle to RADJ x INADJ. While Figures 12 and 15
show that OUT1 does not change state after both VIN1 and
VINADJ have settled, it is necessary to wait until after the
delays before changing the state of the DIAG input to
guarantee valid results. Setting DIAG = VCC then will not
change the output state since VINX >> (VINADJ + VHYS)
before changing the state of the diagnostic input.
A normal input circuit (Figures 12 and 15) can be
diagnosed at power−up (DIAG = GND) after the tINX delay
and after the tINADJ delay. Figures 12 and 15 also show that
OUT1 does not change state after both VIN1 and VINADJ
have settled, it is again necessary to wait before changing the
state of the DIAG input. Setting DIAG = VCC then will not
change the output state since VIN1 is already below VINADJ
before changing the state of the diagnostic input.
So how does setting DIAG = VCC give us any additional
information? When the input circuit resistances change
enough to cause VINX to be greater than VINADJ + VHYS,
OUTX will go low. When DIAG = GND, this will occur
when (RX + RRS) is just slightly greater than RDMIN =[(1.00
x RADJ) + (VHYS/INPX)]. When DIAG = VCC, this will
occur when (RX + RRS) is just slightly greater than RDMAX
= [(1.55 x RADJ) + (VHYS/INPX)].
We’ve seen, after correct power up and pre−conditioning,
that OUTX will go high and remain high if the input circuit
is good and that OUTX will go low and remain low if the
input circuit is bad. If OUTX is low after power−up, then
DIAG is switched to VCC, OUTX will go high if RDMIN =
(R1 + RRS) v RDMAX. So two samples of OUTX are needed
to know the quality of the input circuit: one after power−up
and one after changing DIAG from low to high. Table 1
summarizes diagnostic behavior.
Table 1. Diagnostic Behavior
OUTX After Power−Up
DIAG
OUTX After DIAG
H
L→H
H
GOOD
L
L→H
L→H
RDMIN v (R1 + RRS) v RDMAX
L
L→H
L
BAD
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Circuit Quality
AND8149/D
The worst−case delays for sampling OUTX occur where
R1 + RRS is just at RDMIN when VIN = VINADJ + VHYS. For
the Test Circuit 2 case in Figure 9, we need to wait several
RDMIN x C1 time constants after power−up for VINX to settle
before sampling OUTX. If we wait the typical 5t, VINX will
be near 99.4% of VINADJ + VHYS. We now only need to wait
for the mode change delay time specified in the data sheet
(20 ms max.) after changing DIAG from low to high before
again sampling OUTX.
For the Test Circuit 3 case in Figure 13, we need to wait
the longer of several RDMIN x C1 or tINADJ time constants
after power−up for VINX or VINADJ to settle before sampling
OUTX. If we wait the typical 5t, VINX will be near 99.4%
of VINADJ + VHYS (or vice−versa.) Since the INADJ current
will have a step change of 55% typical when changing from
normal mode to diagnostic mode, we need to wait an
additional 5tINADJ after changing DIAG from low to high
before again sampling OUTX.
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