TPA3107D2 HTQFP www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 15-W STEREO CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • 15-W/ch into an 8-Ω Load From a 16-V Supply Operates from 10 V to 26 V Efficient Class-D Operation Eliminates the Need for Heat Sinks Four Selectable, Fixed Gain Settings Differential Inputs Thermal and Short-Circuit Protection With Auto Recovery Feature Clock Output for Synchronization With Multiple Class-D Devices Surface Mount 10 mm × 10 mm, 64-pin HTQFP Package Televisions DESCRIPTION The TPA3107D2 is a 15-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. The TPA3107D2 can drive stereo speakers as low as 6 Ω. The high efficiency of the TPA3107D2, 87%, eliminates the need for an external heat sink when playing music. The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32, 36 dB. The outputs are fully protected against shorts to GND, VCC, and output-to-output shorts with an auto recovery feature and monitor output. Simplified Application Circuit 1 mF RINP 1 mF RINN TV Audio Processor 0.22 mF TPA3107D2 1 mF LINN 1 mF BSRN ROUTN ROUTP BSRP LINP Shutdown Control Mute Control PGNDR 10 nF VREG MUTE Gain Select MSTR/SLV Sync Control SYNC FAULT PVCCR PVCCL AVCC AGND 1 mF VBYP ROSC 100 kW GAIN1 10 V to 26 V 1 mF SHUTDOWN GAIN0 Fault Flag 0.22 mF VCLAMPR BSLN LOUTN 0.22 mF LOUTP BSLP VCLAMPL PGNDL 0.22 mF 1 mF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage VI Input voltage AVCC, PVCC –0.3 V to 30 V SHUTDOWN, MUTE –0.3 V to VCC + 0.3 V GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV, SYNC Continuous total power dissipation TA –0.3 V to VREG + 0.5 V See Dissipation Rating Table Operating free-air temperature range TJ Operating junction temperature Tstg Storage temperature range Electrostatic discharge (1) –40°C to 85°C range (2) –40°C to 150°C –65°C to 150°C Human body model (3) Charged-device model ±2 kV (all pins) (4) ±500 V (all pins) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The TPA3107D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. In accordance with JEDEC Standard 22, Test Method A114-B. In accordance with JEDEC Standard 22, Test Method C101-A (2) (3) (4) TYPICAL DISSIPATION RATINGS PACKAGE (1) 64-pin PAP (HTQFP) (1) (2) TA ≤ 25°C DERATING FACTOR 5.43 W 43.5 mW/°C (2) TA = 70°C TA = 85°C 3.47 W 2.82 W For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. This data was taken using a 2 oz trace and copper pad that is soldered directly to a 2-layer high-k PCB (EVM). These are typical values. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN MAX 10 26 Supply voltage PVCC, AVCC VIH High-level input voltage SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC VIL Low-level input voltage SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV, SYNC 0.8 SHUTDOWN, VI = VCC, VCC = 24 V 125 IIH 2 TEST CONDITIONS VCC High-level input current 2 MUTE, VI = VCC, VCC = 24 V 75 2 SHUTDOWN, VI = 0, VCC = 24 V 2 IIL Low-level input current SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0 V, VCC = 24 V 1 VOH High-level output voltage FAULT, IOH = 1 mA VOL Low-level output voltage FAULT, IOL = -1 mA fOSC Oscillator frequency ROSC Resistor = 100 kΩ RL Load Resistance TA Operating free-air temperature VREG - 0.6 µA µA V 300 kHz 85 °C Ω 6 Submit Documentation Feedback V V AGND + 0.4 –40 V V GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG, VCC = 24 V 200 UNIT TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 DC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER | VOS | PSRR ICC rDS(on) TEST CONDITIONS Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB Bypass reference for input amplifier VBYP, no load 4-V internal supply voltage VREG, no load, VCC = 10 V to 26 V DC Power supply rejection ratio VCC = 12 V to 24 V, inputs ac coupled to AGND, Gain = 36 dB Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load Quiescent supply current in mute mode MUTE = 2 V, no load Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25°C Gain GAIN1 = 2 V TYP MAX UNIT 5 50 1.1 1.25 1.45 V 3.75 4 4.25 V -70 Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load GAIN1 = 0.8 V G MIN mV dB 22 26.5 300 400 µA 8 10 mA High Side 370 Low side 370 Total 780 950 mA mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 dB dB Gain matching Between channels tON Turn-on time C(VBYP) = 1 µF, SHUTDOWN = 2 V 2% 25 ms tOFF Turn-off time C(VBYP) = 1 µF, SHUTDOWN = 0.8 V 0.1 ms DC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER | VOS | PSRR ICC rDS(on) TEST CONDITIONS Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB Bypass reference for input amplifier VBYP, no load 4-V internal supply voltage VREG, no load DC Power supply rejection ratio VCC = 12 V to 24 V, Inputs ac coupled to AGND, Gain = 36 dB Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load Quiescent supply current in mute mode MUTE = 2 V, no load Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25°C Gain GAIN1 = 2 V TYP MAX UNIT 5 50 1.1 1.25 1.45 V 3.75 4 4.25 V -70 Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load GAIN1 = 0.8 V G MIN mV dB 18 22.5 180 300 µA 7 9 mA High Side 350 Low side 350 Total 780 950 mA mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 dB dB tON Turn-on time C(VBYP) = 1 µF, SHUTDOWN = 2 V 25 ms tOFF Turn-off time C(VBYP) = 1 µF, SHUTDOWN = 0.8 V 0.1 ms Submit Documentation Feedback 3 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 AC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS KSVR Supply ripple rejection 200 mVPP ripple from 20 Hz–1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND PO Continuous output power THD+N = 0.1%, f = 1 kHz (thermally limited) THD+N Total harmonic distortion + noise f = 1 kHz, PO = 7.5 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted SNR MIN TYP MAX UNIT –70 dB 15 W 0.08% Thermal trip point Thermal hysteresis 125 µV –78 dBV –92 dB 102 dB 150 °C 20 °C AC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER KSVR Supply ripple rejection PO Continuous output power TEST CONDITIONS THD+N = 7%, f = 1 kHz 8.7 THD+N = 10%, f = 1 kHz 9.2 THD+N = 10%, f = 1 kHz, VCC = 16 V 15 Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 5 W Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted Thermal trip point Thermal hysteresis 4 TYP –70 THD+N SNR MIN 200 mVPP ripple from 20 Hz–1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND Submit Documentation Feedback MAX UNIT dB W 0.11% 125 µV –78 dBV –94 dB 96 dB 150 °C 30 °C TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 AVCC FAULT MUTE SHUTDOWN NC NC NC NC NC BSRP ROUTP ROUTP ROUTN ROUTN BSRN NC 64 PIN, HTQFP PACKAGE (TOP VIEW) 64 63 NC NC NC NC RINN RINP AGND LINP LINN GAIN0 GAIN1 MSTR/SLV NC NC NC NC 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 43 6 7 Exposed Thermal Pad 8 42 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 NC NC PVCCR PVCCR PGNDR PGNDR NC VCLAMPR VCLAMPL NC PGNDL PGNDL PVCCL PVCCL NC NC SYNC ROSC VREG VBYP AGND NC NC NC NC BSLP LOUTP LOUTP LOUTN LOUTN BSLN NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION SHUTDOWN 61 I Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with compliance to AVCC. (Active low) RINN 5 I Negative audio input for right channel. Biased at VREG/2. RINP 6 I Positive audio input for right channel. Biased at VREG/2. LINN 9 I Negative audio input for left channel. Biased at VREG/2. LINP 8 I Positive audio input for left channel. Biased at VREG/2. GAIN0 10 I Gain select least significant bit. TTL logic levels with compliance to VREG. GAIN1 11 I Gain select most significant bit. TTL logic levels with compliance to VREG. MUTE 62 I Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. (Active high) FAULT 63 O TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults. Thermal faults are not reported on this terminal. BSLP 26 I/O Bootstrap I/O for left channel, positive high-side FET. Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC. PVCCL 35, 36 LOUTP 27, 28 PGNDL 37, 38 LOUTN 29, 30 O Class-D 1/2-H-bridge negative output for left channel. BSLN 31 I/O Bootstrap I/O for left channel, negative high-side FET. VCLAMPL 40 VCLAMPR 41 BSRN 50 I/O Bootstrap I/O for right channel, negative high-side FET. ROUTN 51, 52 O Class-D 1/2-H-bridge negative output for right channel. PGNDR 43, 44 O Class-D 1/2-H-bridge positive output for left channel. Power ground for left channel H-bridge. Internally generated voltage supply for left channel bootstrap capacitor. Internally generated voltage supply for right channel bootstrap capacitor. Power ground for right channel H-bridge. Submit Documentation Feedback 5 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. ROUTP 53, 54 PVCCR 45, 46 O DESCRIPTION Class-D 1/2-H-bridge positive output for right channel. Power supply for right channel H-bridge, not connected to PVCCL or AVCC. BSRP 55 AGND 7, 21 ROSC 18 I/O MSTR/SLV 12 I Master/Slave select for determining direction of SYNC terminal. HIGH=Master mode, SYNC terminal is an output; LOW = slave mode, SYNC terminal accepts a clock input. TTL logic levels with compliance to VREG. SYNC 17 I/O Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/SLV terminal. Input signal not to exceed VREG. VBYP 20 O Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor sizing. VREG 19 O 4-V regulated output for use by internal cells, GAINx, MUTE, and MSTR/SLV pins only. Not specified for driving other external circuitry. AVCC NC Thermal Pad 6 I/O I/O Analog ground for digital/analog cells in core. 64 I/O for current setting resistor of ramp generator. High-voltage analog power supply. Not internally connected to PVCCR or PVCCL. 1-4, 13-16, 22-25, 32-34, 39, 42, 47-49, 56-60 - Bootstrap I/O for right channel, positive high-side FET. Not internally connected. - Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to AGND and PGND. Thermal vias on the PCB should connect this pad to a large copper area on an internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered to the PCB for mechanical reliability. Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 FUNCTIONAL BLOCK DIAGRAM PVCCR PVCCR VCLAMPR PVCCR VBYP BSRN VBYP AVCC AVCC Gain Control RINN RINP Gate Drive Gain Control VClamp Gen PWM Logic BSRP Gain Control 8 Gate Drive To Gain Adj. Blocks and Startup Logic ROUTP Gain FAULT SC Detect VBYP AVCC ROSC Ramp Generator SYNC Thermal Biases and Reference s MSTR/SLV VREG Startup Protection Logic VREGok PGNDR VREG PVCCL AVCC PVCCL VCCok 4V Reg VREG PVCCL SHUTDOWN TLL Input Buffer (VCC Compliant) MUTE TLL Input Buffer (VCC Compliant) VCLAMPL BSLN Gate Drive Gain Control LOUTN VClamp Gen VBYP LINP PVCCR VBYP GAIN0 GAIN1 LINN ROUTN Gate Drive Gain PVCCL BSLP PWM Logic Gain Control LOUTP PGNDL AGND Submit Documentation Feedback 7 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 TYPICAL CHARACTERISTICS TABLE OF GRAPHS (1) (2) FIGURE THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4, 5 THD+N Total harmonic distortion + noise vs Output power 6, 7, 8, 9, 10 Closed-loop response vs Frequency Output power vs Supply voltage 13 Supply current vs Total output power 14 System efficiency vs Output power Crosstalk vs Frequency 16, 17 Supply ripple rejection ratio vs Frequency 18 VCC kSVR (1) (2) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 THD+N - Total Harmonic Distortion + Noise - % 10 THD+N - Total Harmonic Distortion + Noise - % 15 All graphs were measured using the TPA3107D2 EVM. Power generated beyond normal and recommended operating conditions may require additional heatsinking. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VCC = 12 V RL = 8 W Gain = 20 dB 1 PO = 5 W 0.1 PO = 2.5 W 0.01 PO = 1 W 0.001 20 8 11, 12 100 1k 10k 20k VCC = 18 V RL = 8 W Gain = 20 dB 1 PO = 5 W 0.1 PO = 2.5 W 0.01 PO = 1 W 0.001 20 100 1k f − Frequency − Hz f − Frequency − Hz Figure 1. Figure 2. Submit Documentation Feedback 10k 20k TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 VCC = 24 V RL = 8 W Gain = 20 dB 1 0.1 PO = 1 W PO = 10 W 0.01 PO = 5 W 0.001 20 100 1k PO = 10 W 0.1 PO = 1 W 0.01 PO = 5 W 100 1k 10k 20k f − Frequency − Hz Figure 3. Figure 4. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 1 f − Frequency − Hz VCC = 24 V RL = 6 W Gain = 20 dB 1 PO = 1 W PO = 10 W 0.01 PO = 5 W 0.001 20 RL = 6 W Gain = 20 dB 0.001 20 10k 20k 10 0.1 VCC = 18 V 100 1k 10k 20k VCC = 12 V RL = 8 W Gain = 20 dB 1 10 kHz 1 kHz 0.1 20 Hz 0.01 10 m 100 m 1 f − Frequency − Hz PO − Output Power − W Figure 5. Figure 6. Submit Documentation Feedback 10 20 40 9 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 20 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 20 VCC = 18 V RL = 8 W Gain = 20 dB 1 10 kHz 1 kHz 0.1 20 Hz 0.01 10 m 100 m 10 20 1 40 1 10 kHz 1 kHz 0.1 20 Hz 0.01 10 m 100 m 10 20 40 1 PO − Output Power − W Figure 7. Figure 8. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 VCC = 18 V THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 RL = 8 W Gain = 20 dB PO − Output Power − W 70 20 VCC = 24 V 10 RL = 8 W Gain = 32 dB 10 1 10 kHz 1 kHz 0.1 20 Hz 0.01 10 m 100 m 1 10 20 30 VCC = 24 V RL = 8 W Gain = 32 dB 1 10 kHz 1 kHz 0.1 20 Hz 0.01 10 m 100 m 1 PO − Output Power − W PO − Output Power − W Figure 9. Figure 10. Submit Documentation Feedback 10 20 30 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Gain Phase VCC = 12 V RL = 8 W VI = 0.1 Vrms CI = 10 mF Gain = 32 dB RC filter = 100 W, 10 nF 10 100 1k 10 k 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 Gain Phase VCC = 24 V RL = 8 W VI = 0.1 Vrms CI = 10 mF Gain = 32 dB RC filter = 100 W, 10 nF 10 100 f - Frequency - Hz 32.5 1k 10 k f - Frequency - Hz Figure 11. Figure 12. OUTPUT POWER vs SUPPLY VOLTAGE SUPPLY CURRENT vs TOTAL OUTPUT POWER 37.5 35 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 100 k Phase − o 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 100 k Gain − dB CLOSED LOOP RESPONSE vs FREQUENCY Phase − o 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 2.5 RL = 8 Ω Gain = 32 dB RL = 8 W Gain = 20 dB 2 ICC − Supply Current − A 30 PO − Output Power − W Gain − dB CLOSED LOOP RESPONSE vs FREQUENCY 27.5 25 22.5 THD+N = 10% 20 17.5 THD+N = 1% 15 12.5 VCC = 18 V VCC = 12 V 1.5 VCC = 24 V 1 0.5 10 7.5 5 10 12 14 16 18 20 22 24 26 0 0 VCC - Supply Voltage - V 10 20 30 40 PO − Total Output Power − W Figure 13. Figure 14. Submit Documentation Feedback 11 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 SYSTEM EFFICIENCY vs OUTPUT POWER CROSSTALK vs FREQUENCY -40 100 VCC = 12 V 90 −60 80 VCC = 12 V RL = 8 Ω Gain = 20 dB VO = 1 Vrms VCC = 18 V 60 Crosstalk − dB Efficiency − % 70 VCC = 24 V 50 40 −80 R to L −100 30 L to R RL = 8 W Gain = 20 dB 20 −120 10 −140 20 0 0 5 10 15 20 25 100 Figure 15. Figure 16. CROSSTALK vs FREQUENCY SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY -40 L to R −80 −100 R to L −120 −140 20 100 1k 10k 20k −10 −20 RL = 8 W Gain = 20 dB V(RIPPLE) = 200 mVPP −30 −40 −50 −60 VCC = 12 V VCC = 18 V −70 −80 VCC = 24 V −90 −100 20 f − Frequency − Hz 100 1k f − Frequency − Hz Figure 17. 12 10k 20k 0 VCC = 24 V RL = 8 Ω Gain = 20 dB VO = 1 Vrms kSVR − Supply Ripple Rejection Ratio − dB Crosstalk − dB −60 1k f − Frequency − Hz PO − Output Power (Per Channel) − W Figure 18. Submit Documentation Feedback 10k 20k TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Shutdown and Mute Control Fault Output APPLICATION INFORMATION 33 mH 0.1 mF 8W 0.47 mF 0.1 mF 10 V - 26 V 33 mH 220nF 220nF 10 mF NC NC BSRN ROUTN ROUTP ROUTN BSRP NC NC NC RINP PGNDR AGND LINN 1 mF VCLAMPL NC GAIN1 PGNDL 220 mF 1 mF 10 V - 26 V NC LOUTN BSLN LOUTP LOUTN NC 1 mF 10 nF NC BSLP NC LOUTP PVCCL NC NC NC NC PVCCL AGND PGNDL VBYP MSTR/SLV NC 100 kW 220 mF VCLAMPR GAIN0 NC 1 mF NC TPA3107D2 LINP 1 mF NC PGNDR VREG 220nF 1 mF Synchronize Multiple Class-D Devices 1 mF PVCCR RINN SYNC 4-Step Gain Control 1 mF 10 V - 26 V PVCCR NC ROSC Single-Ended Analog Inputs NC NC NC 1 mF ROUTP NC NC SHUTDOWN MUTE AVCC NC FAULT 1 mF 220nF 33 mH 0.1 mF 8W 0.47 mF 33 mH 0.1 mF Figure 19. TPA3107D2 Application Circuit With Single-Ended Inputs Submit Documentation Feedback 13 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) CLASS-D OPERATION This section focuses on the class-D operation of the TPA3107D2. Traditional Class-D Modulation Scheme The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out-of-phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in Figure 20. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss and thus causing a high supply current. OUTP OUTN +12 V Differential Voltage Across Load 0V -12 V Current Figure 20. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an Inductive Load With No Input TPA3107D2 Modulation Scheme The TPA3107D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load. 14 Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) OUTP OUTN Differential Voltage Across Load Output = 0 V +12 V 0V -12 V Current OUTP OUTN Differential Voltage Across Load Output > 0 V +12 V 0V -12 V Current Figure 21. The TPA3107D2 Output Voltage and Current Waveforms Into an Inductive Load Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3107D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. When to Use an Output Filter for EMI Suppression Design the TPA3107D2 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter. Submit Documentation Feedback 15 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies. Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker. When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter. 33 mH OUTP L1 33 mH C2 C1 0.1 mF 0.47 mF OUTN C3 L2 0.1 mF Figure 22. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω 15 mH OUTP L1 15 mH C2 C1 0.22 mF 1 mF OUTN C3 L2 0.22 mF Figure 23. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 24. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2518121217Y3) 16 Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 APPLICATION INFORMATION (continued) Adaptive Dynamic Range Control TPA3107D2 V - Voltage = 1 V/div V - Voltage = 10 V/div TPA3107D2 Closest Competitor Closest Competitor t - Time = 100 ms/div t - Time = 20 ms/div Figure 25. 1-kHz Sine Output at 10% THD+N Figure 26. 8-kHz Sine Output at 10% THD+N The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher frequencies as shown in Figure 26. Gain setting via GAIN0 and GAIN1 inputs The gain of the TPA3107D2 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 12.8 kΩ, which is the absolute minimum input impedance of the TPA3107D2. At the lower gain settings, the input impedance could increase as high as 38.4 kΩ Table 1. Gain Setting GAIN1 GAIN0 AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ) TYP TYP 0 0 20 32 0 1 26 16 1 0 32 16 1 1 36 16 INPUT RESISTANCE Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 kΩ± 20%, to the largest value, 32 kΩ± 20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Submit Documentation Feedback 17 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Zf Ci IN Input Signal Zi The -3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 1. f = 1 2p Zi Ci (1) INPUT CAPACITOR, CI In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-pass filter with the corner frequency determined in Equation 2. -3 dB fc = 1 2p Zi Ci fc (2) The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3. Ci = 1 2p Zi fc (3) In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. If the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network (CI) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly. Power Supply Decoupling, CS The TPA3107D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF to 1 µF placed as close as possible to the device VCC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 µF or greater placed near the audio power amplifier is recommended. The 220 µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF capacitor on the AVCC terminal is adequate. 18 Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Bootstrap Capacitors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the application circuit diagram in Figure 19.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. VCLAMP Capacitors To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 40) and VCLAMPR (pin 41) to ground and must be rated for at least 16 V. The voltages at the VCLAMPx terminals may vary with VCC and may not be used for powering any other circuitry. Internal Regulated 4-V Supply (VREG) The VREG terminal (pin 19) is the output of an internally generated 4-V supply, used for the oscillator, preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator stable. This regulated voltage can be used to control GAIN0, GAIN1, MSTR/SLV, and MUTE terminals, but should not be used to drive external circuitry. VBYP Capacitor Selection The internal bias generator (VBYP) nominally provides a 1.25-V internal bias for the preamplifier stages. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers. The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance. During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer. When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV is equal to VBYP. For example, a 1-µF capacitor on VBYP would take 5 ms to reach the value of VBYP and begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1-µF capacitor on the VBYP terminal. A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25-V bias generator. A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop performance, the VBYP capacitor should be greater than or equal to the input capacitors. ROSC Resistor Selection The resistor connected to the ROSC terminal controls the class-D output switching frequency using Equation 4: 1 FOSC = 2 x ROSC x COSC (4) COSC is an internal capacitor that is nominally equal to 20 pF. Variation over process and temperature can result in a ±15% change in this capacitor value. For example, if ROSC is fixed at 100 kΩ, the frequency from device to device with this fixed resistance could vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC resistor should also be considered to determine the range of expected switching frequencies from device to device. It is recommended that 1% tolerance resistors be used. Submit Documentation Feedback 19 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Differential Input The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3107D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3107D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. SHUTDOWN OPERATION The TPA3107D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the power supply voltage. MUTE Operation The MUTE pin is an input for controlling the output state of the TPA3107D2. A logic high on this terminal disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources. The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level. The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 27. TPA3107D2 External GPIO Control MUTE FAULT Figure 27. External MUTE Control 20 Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 MSTR/SLV and SYNC operation The MSTR/SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching. When the MSTR/SLV terminal is high, the output switching frequency is determined by the selection of the resistor connected to the ROSC terminal (see ROSC Resistor Selection). The SYNC terminal becomes an output in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to another TPA3107D2, configured in the slave mode. The output switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are switching at slightly different frequencies. When the MSTR/SLV terminal is low, the output switching frequency is determined by the incoming square wave on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compatible square wave from another TPA3107D2 configured in the master mode or from an external GPIO. If connecting to an external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation, and the maximum amplitude is 4 V. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE The TPA3107D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates. The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 27. THERMAL PROTECTION Thermal protection on the TPA3107D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device begins normal operation at this point with no external system interaction. Submit Documentation Feedback 21 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 PRINTED-CIRCUIT BOARD (PCB) LAYOUT GENERAL GUIDELINES Because the TPA3107D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance. • Decoupling capacitors—The high-frequency 1-µF decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. The VBYP capacitor, VREG capacitor, and VCLAMP capacitor should also be placed as close to the device as possible. Large bulk power supply decoupling capacitors should be placed near the TPA3107D2 on the PVCCL, PVCCR, and AVCC terminals. • Grounding—The AVCC decoupling capacitor, VREG capacitor, VBYP capacitor, and ROSC resistor should each be grounded to analog ground. The PVCC decoupling capacitors and VCLAMP capacitors should each be grounded to power ground. Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3107D2. • Output filter—The ferrite EMI filter should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. For an example layout, see the TPA3107D2 Evaluation Module User Manual, (SLOU190). Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com. BASIC MEASUREMENT SYSTEM This application note focuses on methods that use the basic equipment listed below: • Audio analyzer or spectrum analyzer • Digital multimeter (DMM) • Oscilloscope • Twisted-pair wires • Signal generator • Power resistor(s) • Linear regulated power supply • Filter components • EVM or other complete audio circuit Figure 28 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer-input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure 28(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal output. This amplifier circuit can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 28(b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers. 22 Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Power Supply Signal Generator APA RL Analyzer 20 Hz - 20 kHz (a) Basic Class-AB Power Supply Low-Pass RC Filter Signal Generator Class-D APA RL (See note A) Low-Pass RC Filter Analyzer 20 Hz - 20 kHz (b) Filter-Free and Traditional Class-D A. For efficiency measurements with filter-free Class-D, RL should be an inductive load like a speaker. Figure 28. Audio Measurement Systems The TPA31071D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave. DIFFERENTIAL INPUT AND BTL OUTPUT All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor. A block diagram of the measurement circuit is shown in Figure 29. The differential input is a balanced input, meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output. Submit Documentation Feedback 23 TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Evaluation Module Audio Power Amplifier Generator Analyzer Low-Pass RC Filter CIN VGEN RGEN RIN ROUT RIN ROUT CIN RGEN RL Low-Pass RC Filter Twisted-Pair Wire RANA CANA RANA CANA Twisted-Pair Wire Figure 29. Differential Input, BTL Output Measurement Circuit The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs: • Use a balanced source to supply the input signal. • Use an analyzer with balanced inputs. • Use twisted-pair wire for all connections. • Use shielding when the system environment is noisy. • Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 2). Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C. Table 2. Recommended Minimum Wire Size for Power Cables DC POWER LOSS (MW) AWG Size AC POWER LOSS (MW) POUT (W) RL(Ω) 10 4 18 22 16 40 18 42 2 4 18 22 3.2 8 3.7 8.5 1 8 22 28 2 8 2.1 8.1 < 0.75 8 22 28 1.5 6.1 1.6 6.2 CLASS-D RC LOW-PASS FILTER An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx). The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 30. RL is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops. 24 Submit Documentation Feedback TPA3107D2 www.ti.com SLOS509A – OCTOBER 2006 – REVISED NOVEMBER 2006 Load AP Analyzer Input RC Low-Pass Filters RFILT CFILT RL VL= VIN CANA RANA CANA RANA VOUT RFILT CFILT To APA GND Figure 30. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs The transfer function for this circuit is shown in Equation 5 where ωO = REQCEQ, REQ = RFILT || RANA and CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement bandwidth, to avoid attenuating the audio signal. Equation 6 provides this cutoff frequency, fC. The value of RFILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A general rule is that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement error to less than 1% for RANA ≥ 10 kΩ. ( ) VOUT VIN ( = RANA RANA + RFILT 1 + j ) ( ) w wO (5) fc = Ö2 x fmax (6) An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same cutoff frequency. See Table 3 for the recommended filter component values. Once fC is determined and RFILT is selected, the filter capacitance is calculated using . When the calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum desired value calculated in Equation 7. 1 CFILT = 2p x fc x RFILT (7) Table 3 shows recommended values of RFILT and CFILT based on common component values. The value of fC was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57,000 pF, but the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and fC is 34 kHz, which is above the desired value of 28 kHz. Table 3. Typical RC Measurement Filter Values MEASUREMENT RFILT Efficiency 1000 Ω 5,600 pF All other measurements 100 Ω 56,000 pF Submit Documentation Feedback CFILT 25 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPA3107D2PAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-5A-260C-24 HR TPA3107D2PAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-5A-260C-24 HR TPA3107D2PAPT ACTIVE HTQFP PAP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-5A-260C-24 HR TPA3107D2PAPTG4 ACTIVE HTQFP PAP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-5A-260C-24 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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