DG3157 Vishay Siliconix New Product High-Speed, Low rON, SPDT Analog Switch (2:1 Multiplexer/Demultiplexer Bus Switch) FEATURES D Direct Cross to Industry Standard SN74LVC1G3157 NC7SB3157, NLASB3175, Pl5A3157, and STG3157 D SC-70 6-Lead Package D 1.65-V to 5.5-V VCC Operation D 5-W Connection Between Ports D Minimal Propagation Delay D Break-Before-Make Switching D Zero Bounce In Flow-Through Mode DESCRIPTION The DG3157 is a high-speed single-pole double-throw, low power, TTL-Compatible bus switch. Using sub-micro CMOS technology, the DG3157 achieves low on-resistance and negligible propagation delay. The DG3157 can handle both analog and digital signals and permits signals with amplitudes of up to VCC to be transmitted in either direction. When the Select pin is low, B0 is connected to the output A pin. When the Select pin is high, B1 is connected to the output A pin. The path that is open will have a high-impedance state with respect to the output. Make-before-break is guaranteed. An eptiaxial layer prevents latch-up. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION TRUTH TABLE SC-70 6- Pin Logic Input (S) Function B1 1 6 S 0 B0 Connected to A GND 2 5 V+ 1 3 4 B1 Connected to A B0 A Top View Device Marking: G1 Document Number: 72648 S-32552—Rev. A, 15-Dec-03 ORDERING INFORMATION Temp Range Package Part Number -40 to 85°C SC70-6 DG3157DL www.vishay.com 1 DG3157 Vishay Siliconix New Product ABSOLUTE MAXIMUM RATINGS Reference to GND V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 V S, A, Ba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+ + 0.3 V) Continuous Current (Any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . "50 mA Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "200 mA (Pulsed at 1 ms, 10% duty cycle) Storage Temperature (D Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Power Dissipation (Packages)b 6-Pin SC70c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mW Notes: a. Signals on A, or B or S exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 3.1 mW/_C above 70_C SPECIFICATIONS Test Conditions Otherwise Unless Specified Parameter Symbol Limits −40 to 85_C V+ = 3.0 V, VS = 0.25 V to 0.7 V+e Tempa Minb V+ = 1.65 to 1.95 V Full 0.75 V+ V+ = 2.3 to 5.5 V Full 0.7 V+ V+ = 1.65 to 1.95 V Full V+ = 2.3 to 5.5 V Full Typc Maxb Unit DC Characteristics High Level Input Voltage VSH Low Level Input Voltage VSL V+ = 4.5 V On Resistance RON V+ = 3.0 30V On Resistance Matching Between Channels Input Leakage Current RFLAT DRON Full 6 7 VBN = 2.3 V, IA = −30 mA Full 6 12 VBN = 4.5 V, IA = −30 mA Full 9 15 VBN = 0 V, IA = 24 mA Full 8 9 VBN = 3.0 V, IA = −24 mA Full 12 20 VBN = 0 V, IA = 8 mA Full 9 12 Full 13 30 VBN = 0 V, IA = 4 mA Full 12 20 VBN = 1.8 V, IA = −4 mA Full 18 50 V+ = 4.5 V, IA = −30 mA Room 6 V+ = 3.0 V, IA = −24 mA Room 12 V+ = 2.3 V, IZ = −8 mA Room 22 V+ = 1.65 V, IA = −4 mA Room 90 V+ = 4.5 V, VBN = 3.15 V, IA = −30 mA Room 0.32 V+ = 3.0 V, VBN = 2.1 V, IA = −24 mA Room 0.31 V+ = 2.3 V, VBN = 1.6 V, IA = −8 mA Room 0.30 V+ = 1.65 V, VBN = 1.15 V, IA = −4 mA Room V+ = 1.65 1 65 V 0 < VBN < V+ IS V+ = 5 5.5 5V V, VA = 5.5 55V Off Stage Switch Leakage IBN(off) BN( ff) V+ = 5 5.5 5V V, VA/VB = 0 V/5.5 V/5 5 V On State Switch Leakage IBN(on) BN( ) V+ = 5 5.5 5V V, VA/VB = 0 V/5.5 V/5 5 V V 0.3 V+ VBN = 0 V, IA = 30 mA VBN = 2.3 V, IA = −8 mA V+ = 2.3 23V On Resistance Fltaness 0.25 V+ W 0.29 Room −0.1 0.1 Full −1.0 −1.0 Room −0.1 0.1 Full −1.0 −1.0 Room −0.1 0.1 Full −1.0 −1.0 Full 1.8 5.5 mA Power Supply Power Supply Range Quiescent Supply Current www.vishay.com 2 V+ I+ V+ = 5 5.5 5V V, VA = VB = V+ or GND Room 1 Full 10 mA Document Number: 72648 S-32552—Rev. A, 15-Dec-03 DG3157 Vishay Siliconix New Product SPECIFICATIONS Test Conditions Otherwise Unless Specified Parameter Symbol V+ = 3.0 V, VS = 0.25 V to 0.7 V+e Limits −40 to 85_C Tempa Minb Typc Maxb Unit AC Electrical Characteristice Prop Delay Timef tPHL/tPLH VA = 0 V V+ =1.65 to 1.95 V Full V+ =2.3 to 2.7 V Full 1.2 V+ =3.0 to 3.6 V Full 0.8 V+ =4.5 to 5.5 V Full 0.3 Room 10.2 V+ =1.65 =1 65 to 1 1.95 95 V V+ =2.3 =2 3 to 2 2.7 7 V Output Enable Timef tPZL/tPZH VLOAD = 2 x V+ for tPZL VLOAD = 0 V for tPZH V+ =3.0 =3 0 to 3 3.6 6 V V+ =4.5 =4 5 to 5 5.5 5 V V+ =1.65 =1 65 to 1 1.95 95 V V+ =2.3 =2 3 to 2 2.7 7 V Output Disable Timef tPLZ/tPHZ VLOAD = 2 x V+ for tPLZ VLOAD = 0 V for tPHZ V+ =3.0 =3 0 to 3 3.6 6 V V+ =4.5 =4 5 to 5 5.5 5 V Break Before Make Timed Break-Before-Make Charge Injectiond tBBM Q Full 10.4 Room 5.9 Full 6.2 Room 4.1 Full 4.5 Room 2.6 Full 2.9 Room 10.2 Full 10.4 Room 5.9 Full 6.2 Room 4.1 Full 4.5 Room 2.6 Full 2.9 V+ =1.65 to 1.95 V Full 0.5 V+ =2.3 to 2.7 V Full 0.5 V+ =3.0 to 3.65 V Full 0.5 V+ =4.5 to 5.5 V Full 0.5 CL = 0.1 nF, VGEN = 0 V RGEN = 0 W ns V+ = 5 V Room 7 V+ = 3.3 V Room 3 Room −57.6 Room −58.7 u250 pC Analog Switch Characteristics Off Isolationd OIRR Crosstalkd XTALK −3-db Bandwidthd RL = 50 W, W f = 10 MHz BW RL = 50 W Room Control Pin Capacitanced CIN V+ = 0 V Room 4.9 B Port Off Capacitanced CIO-B Room t6.5 Room t18.5 dB MHz Capacitance A Port Capacitance When Switch Enabled CIO-A(on) V+ = 5 V pF Notes: a. b. c. d. e. f. Room = 25°C, Full = as determined by the operating suffix. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. Typical values are for design aid only, not guaranteed nor subject to production testing. Guarantee by design, nor subjected to production test. VIN = input voltage to perform proper function. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch. Document Number: 72648 S-32552—Rev. A, 15-Dec-03 www.vishay.com 3 DG3157 Vishay Siliconix New Product LOGIC DIAGRAM (POSITIVE LOGIC) B S B 1 6 4 A 3 Figure 1. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) rON vs. VA vs. VCC 40 rON − On Resistance (W) 35 30 V+ = 1.65 V, IS = 4 mA 25 20 V+ = 2.3 V, IS = 8 mA 15 V+ = 3.0 V, IS = 24 mA V+ = 4.5 V, IS = 30 mA 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VA (V) www.vishay.com 4 Document Number: 72648 S-32552—Rev. A, 15-Dec-03 DG3157 Vishay Siliconix New Product AC LOADING AND WAVEFORMS VLD RL 500 W From Output Under Test CL 50 pF SW Open GND RL 500 W TEST SW tPLH/tPHL Open tPLZ/tPZL VLD tPHZ/tPZH GND Load Circuit Figure 2. AC Test Circuit tr = 2.5 ns tf = 2.5 ns 90% Switch Input 90% 1.5 V tf = 2.5 ns 3.0 V 10% 1.5 V 1.5 V 10% tPZL GND tw 3.0 V 90% 10% 10% GND tPLZ VLD 2 tPHL tPLH VOH Output 90% Logic Input 1.5 V tr = 2.5 ns 1.5 V 1.5 V Output VOL + 0.3 V Waveform 1 SW at VLD 1.5 V VOL tPZH tPHZ VOH VOL Output Waveform 2 SW at GND Propagation Delay Times 1.5 V VOH −0.3 V 0V Enable and Disable Time—Low- and High-Level Enabling Figure 3. AC Waveforms Notes: a. b. c. d. e. f. g. h. i. CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W. The outputs are measured one at a time with one transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as tdis. tPLH and tPHL are the same as tdis. VLD = 2 V+. Document Number: 72648 S-32552—Rev. A, 15-Dec-03 www.vishay.com 5 DG3157 Vishay Siliconix New Product TEST CIRCUITS V+ Logic Input V+ COM NO VNO VIN tr <5 ns tf <5 ns H VINL VO NC VNC RL 50 W IN CL 35 pF GND VNC = VNO VO 90% Switch 0V Output tD tD CL (includes fixture and stray capacitance) Figure 4. Break-Before-Make Interval V+ V+ Rgen NC or NO + COM IN Vgen VOUT IN CL = 1 nF VIN = 0 − V+ DVOUT VOUT On On Off GND Q = DVOUT x CL IN depends on switch configuration: input polarity determined by sense of switch. Figure 5. Charge Injection V+ V+ 10 nF 10 nF V+ V+ NC or NO IN COM COM RL COM 0V, 2.4 V Meter 0 V, 2.4 V IN HP4192A Impedance Analyzer or Equivalent NC or NO GND GND Analyzer V COM Off Isolation + 20 log V NOńNC Figure 6. Off-Isolation www.vishay.com 6 f = 1 MHz Figure 7. Channel Off/On Capacitance Document Number: 72648 S-32552—Rev. A, 15-Dec-03