AN204450
Traveo™ Family, MB9D560 Setting Clock System
Associated Part Family:
Series Name
Product Number
MB9D560
MB9DF564MAE/F565MAE/F566MAE
MB9DF564MGE/F565MGE/F566MGE
This application note is intended for persons who are considering the use of Traveo family MB9D560 and describes
how to set up the clock system when it operated at maximum frequency (200MHz) to MB9D560.
Contents
1
Introduction ............................................................... 1
1.1
Environment of Development........................... 1
2
Clock System............................................................ 1
3
System Clock Change Operating ............................. 3
3.1
The Wait Cycle Count of TCFLASH ................. 4
1
4
5
3.2
System Clock Setting....................................... 6
Reference ............................................................... 14
Document History ................................................... 15
Introduction
This application note is intended for persons who are considering the use of Traveo family MB9D560.
It is necessary to use a specific procedure to set the clock system of MB9D560.
This application note describes how to set up the clock system when it operated at maximum frequency (200MHz) to
MB9D560.
1.1
Environment of Development
Contents is described in this application note has been developed in the environment shown in Table 1.
Table 1. Environment of Development
Microcomputer
MB9DF566MGB
Integrated Development Environments
2
MULTI v6.1.4
Evaluation Board
MB2198-770-02-E0
Optimization
Optimize for Speed
Clock System
The clock system supplies the clocks for MCU operation.
The external/built-in oscillating clocks of the MCU are generically called source clocks. A source clock is a clock used
to generate an internal operating clock for MCU operation.
The clock system generates the following source clocks.
Fast-CR clock
Slow-CR clock
Main clock/Main clock divided by 2
PLL clock
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Document No. 002-04450 Rev. *A
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Traveo™ Family, MB9D560 Setting Clock System
External/built-in oscillation circuits generate a Fast-CR clock, Slow-CR clock and Main clock. A Main clock divided by
2 is generated by the division of the main clock.
And the main clock and the built-in PLL oscillation circuits generate a PLL clock.
When using the main clock and PLL clock can monitor clock by clock supervisor.
An area that uses internal operating clocks generated from the same source clock is called a clock domain. A clock
domain contains 1 or more internal operating clocks.
The clock system supplies clocks to the following clock domains.
Clock domain 0 (system area)
Clock domain 4 (external output clock area)
The source clock used in each clock domain can be selected. In each clock domain, the selected source clock is
divided, and the resulting clocks are distributed within the MCU as internal operating clocks.
Figure 1. Clock System Block Diagram
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Traveo™ Family, MB9D560 Setting Clock System
3
System Clock Change Operating
This is the procedure to change the system clock of RUN mode in Figure 2.
If it makes a change of system clock, it must be synchronized between the cores. See the application note of caution
of 2CPU mode.
Figure 2. System Clock Change Procedure
[CPU0]
[CPU1]
START
START
Setting wait cycle count of TCFLASH
Setting wait cycle count of TCFLASH
TCFLASH wait cycle count of CPU1
setting completion?
Yes
Setting completion
notification
Wait cycle count setting completion
notification of TCFLASH
No
Setting source clock timer
Setting clock supervisor
(Main clock, PLL clock)
Setting clock gear
Setting to clock domain
in the RUN state
RUN profile settings apply
(RUN profile Update)
Yes
Reflection of RUN profile
settings is complete?
No
Clock gear operation start
Yes
Clock gear operation
is complete?
No
The notification of the completion for the
clock setting to the other core
Setting completion
notification
Clock setting of CPU0
was complete?
Yes
No
END
END
: Operate at Fast-CR clock
: Operate at PLL clock during the clock gear up operation
: Operate at PLL clock set in RUN profile
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Traveo™ Family, MB9D560 Setting Clock System
3.1
The Wait Cycle Count of TCFLASH
If the operating frequency of the system is higher than the maximum operating frequency of the flash memory
(80MHz), it is necessary to insert wait cycles when accessing the flash memory. Wait cycles can be inserted by
setting an appropriate value in FAWC [1:0] in the TCFCFGn_FCFGR register.
The procedure is described in Figure 3.
Two TCFLASH is equipped in this microcomputer, it is necessary to set wait cycle count of TCFLASH connected with
each core.
It is necessary to set wait cycle count before the change of system clock.
Figure 3. TCFLASH Wait Cycle Count Change Procedure
START
TCFLASH configuration
protection key register
← 0xCF61F1A5
Copy the wait cycle count
setting process to RAM
Flash wait control bit
← wait cycle count
The wait cycle count
setting process
Reads the register of TCFLASH
(Dummy read)
END
DMB instruction execution
(Prefetch prevention)
Release of write protection to the TCFLASH
configuration register (TCFCFGn_FCFGR).
Wait to be reflected after
setting wait cycle count.
Reads the register of TCFLASH
(Dummy read)
: Processing which is operated in the ROM
DMB instruction execution
(Prefetch prevention)
: Processing which is operated in the RAM
3.1.1
Ad va n c e P r e p a r a t i o n o f W a i t C y c l e C o n f i g u r a t i o n
Access to TCFLASH (Data readout or program execution) is prohibited during setting wait cycle count. Therefore, the
wait cycle count setting process is necessary to operate in RAM. It is describes the procedure to operate wait cycle
count setting process in RAM in the following.
1.
Prepare a section of wait cycle count setting process in ROM and RAM.
2.
Implement the wait cycle count setting process while specifying the sections (RAM) that was created in step 1.
3.
Implement the process of copying the data of the section (ROM) that was created in step 1 to section that you
created in step 1 (RAM).
4.
Implement a process to run the copied wait cycle count setting process in section that you created in step 1
(RAM) after executing the processes that have been implemented in step 3
The example is described in Figure 4, Figure 5.
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Traveo™ Family, MB9D560 Setting Clock System
Figure 4. Configuration Example of TCFLASH Wait Cycle Count (CPU0)
[ CPU0 ]
sample.ld
MEMORY
{
tcmram_tcm
tcflash_bsect_tcm
tcflash_ssectb_tcm
tcflash_ssecta_tcm
eam
tcflash_bsect_cpu0
tcflash_ssectb_cpu0
tcflash_ssecta_cpu0
: ORIGIN = 0x00000000, LENGTH = 0x020000
: ORIGIN = 0x00800000, LENGTH = 0x100000
: ORIGIN = 0x00FE0000, LENGTH = 0x010000
: ORIGIN = 0x00FF0000, LENGTH = 0x010000
: ORIGIN = 0x02800000, LENGTH = 0x001000
: ORIGIN = 0x05000000, LENGTH = 0x100000
: ORIGIN = 0x05FE0000, LENGTH = 0x010000
: ORIGIN = 0x05FF0000, LENGTH = 0x010000}
sample.c
Procedure 1
If another section is present in the same
sector of the ROM, it must be define as the
section of the end.
SECTIONS
{
#define TCFLASH_KEY_UNLOCK
#define TCFLASH_WAIT
#define MCU_SECT_START_ADDRESS(sect)
#define MCU_SECT_END_ADDRESS(sect)
#define MCU_FLASH_ADDRESS_AXI2TCM(addr)
(0xCF61F1A5)
(2)
(uint32_t)&__ghsstart_##sect
(uint32_t)&__ghsend_##sect
(0x00800000 + (((uint32_t)(addr)) - 0x05000000))
extern void *__ghsstart_FLASHWAITSET;
extern void *__ghsend_FLASHWAITSET;
extern void *__ghsstart_ROM_FLASHWAITSET;
extern void *__ghsend_ROM_FLASHWAITSET;
void Start_PreInit(void);
void CopyTcflashConfigureFunction(void);
void ConfigureMemoriesTcflash(void);
.ROM.FLASHWAITSET
ROM_NOCOPY(.FLASHWAITSET) ALIGN(32)
.FLASHWAITSET
ALIGN(32)
: > tcflash_bsect_cpu0
: > tcmram_tcm
__ghsstart_FLASHWAITSET
= ADDR(.FLASHWAITSET);
__ghsend_FLASHWAITSET
= ENDADDR(.FLASHWAITSET);
__ghsstart_ROM_FLASHWAITSET = ADDR(.ROM.FLASHWAITSET);
__ghsend_ROM_FLASHWAITSET = ENDADDR(.ROM.FLASHWAITSET);}
void Start_PreInit(void)
{
CopyTcflashConfigureFunction();
ConfigureMemoriesTcflash();
}
Procedure 4
Procedure 3
void CopyTcflashConfigureFunction(void)
{
volatile uint32_t *pu32RamStart;
volatile uint32_t *pu32RomEnd;
volatile uint32_t *pu32RomAddr;
Definition for refer to the address
of each section from a .c file.
pu32RamStart
= (uint32_t*)MCU_SECT_START_ADDRESS(FLASHWAITSET);
pu32RomEnd
pu32RomAddr
= (uint32_t*)MCU_FLASH_ADDRESS_AXI2TCM(MCU_SECT_END_ADDRESS(ROM_FLASHWAITSET));
= (uint32_t*)MCU_FLASH_ADDRESS_AXI2TCM(MCU_SECT_START_ADDRESS(ROM_FLASHWAITSET));
for ( ; pu32RomAddr < pu32RomEnd; pu32RomAddr++)
{
// Copy from ROM to RAM
*pu32RamStart = *pu32RomAddr;pu32
RamStart++;}
}
Address that are defined in .ld file is the address for writing
via AXI.
So, it is converted to an address for reading via TCM.
}
#pragma ghs section text=".FLASHWAITSET"
void ConfigureMemoriesTcflash(void)
{
uint32_t u32Dummy;
Procedure 2
TCFCFG0_FCPROTKEY = TCFLASH_KEY_UNLOCK;
TCFCFG0_FCFGR_FAWC = TCFLASH_WAIT;
u32Dummy = TCFCFG0_FCFGR;
__asm("DMB");
u32Dummy = TCFCFG0_FCFGR;
__asm("DMB");
}
#pragma ghs section text=default
Figure 5. Configuration Example of TCFLASH Wait Cycle Count (CPU1)
[ CPU1 ]
sample.ld
MEMORY
{
tcmram_tcm
tcflash_bsect_tcm
tcflash_ssectb_tcm
tcflash_ssecta_tcm
eam
tcflash_bsect_cpu1
tcflash_ssectb_cpu1
tcflash_ssecta_cpu1
}
:
:
:
:
:
:
:
:
ORIGIN = 0x00000000, LENGTH = 0x020000
ORIGIN = 0x00800000, LENGTH = 0x100000
ORIGIN = 0x00FE0000, LENGTH = 0x010000
ORIGIN = 0x00FF0000, LENGTH = 0x010000
ORIGIN = 0x02800000, LENGTH = 0x001000
ORIGIN = 0x07000000, LENGTH = 0x100000
ORIGIN = 0x07FE0000, LENGTH = 0x010000
ORIGIN = 0x07FF0000, LENGTH = 0x010000
SECTIONS
{
.ROM.FLASHWAITSET ROM_NOCOPY(.FLASHWAITSET)
.FLASHWAITSET
sample.c
Procedure 1
If another section is present in the same
sector of the ROM, it must be define as the
section of the end.
#define TCFLASH_KEY_UNLOCK
#define TCFLASH_WAIT
#define MCU_SECT_START_ADDRESS(sect)
#define MCU_SECT_END_ADDRESS(sect)
#define MCU_FLASH_ADDRESS_AXI2TCM(addr)
(0xCF61F1A5)
(2)
(uint32_t)&__ghsstart_##sect
(uint32_t)&__ghsend_##sect
(0x00800000 + (((uint32_t)(addr)) - 0x07000000))
extern void *__ghsstart_FLASHWAITSET;
extern void *__ghsend_FLASHWAITSET;
extern void *__ghsstart_ROM_FLASHWAITSET;
extern void *__ghsend_ROM_FLASHWAITSET;
void Start_PreInit(void);
void CopyTcflashConfigureFunction(void);
void ConfigureMemoriesTcflash(void);
ALIGN(32)
: > tcflash_bsect_cpu1
ALIGN(32)
: > tcmram_tcm
void Start_PreInit(void)
{
CopyTcflashConfigureFunction();
Procedure 4
Procedure 3
__ghsstart_FLASHWAITSET
= ADDR(.FLASHWAITSET);
__ghsend_FLASHWAITSET
= ENDADDR(.FLASHWAITSET);
__ghsstart_ROM_FLASHWAITSET = ADDR(.ROM.FLASHWAITSET);
__ghsend_ROM_FLASHWAITSET = ENDADDR(.ROM.FLASHWAITSET);
ConfigureMemoriesTcflash();
}
void CopyTcflashConfigureFunction(void)
{
volatile uint32_t *pu32RamStart;
volatile uint32_t *pu32RomEnd;
volatile uint32_t *pu32RomAddr;
}
pu32RamStart = (uint32_t*)MCU_SECT_START_ADDRESS(FLASHWAITSET);
Definition for refer to the address
of each section from a .c file.
pu32RomEnd = (uint32_t*)MCU_FLASH_ADDRESS_AXI2TCM(MCU_SECT_END_ADDRESS(ROM_FLASHWAITSET));
pu32RomAddr = (uint32_t*)MCU_FLASH_ADDRESS_AXI2TCM(MCU_SECT_START_ADDRESS(ROM_FLASHWAITSET));
for ( ; pu32RomAddr < pu32RomEnd; pu32RomAddr++)
{
// Copy from ROM to RAM
*pu32RamStart = *pu32RomAddr;
pu32RamStart++;
}
Address that are defined in .ld file is the address for writing
via AXI.
So, it is converted to an address for reading via TCM.
}
#pragma ghs section text=".FLASHWAITSET"
void ConfigureMemoriesTcflash(void)
{
uint32_t u32Dummy;
Procedure 2
TCFCFG1_FCPROTKEY = TCFLASH_KEY_UNLOCK;
TCFCFG1_FCFGR_FAWC = TCFLASH_WAIT;
u32Dummy = TCFCFG1_FCFGR;
__asm("DMB");
u32Dummy = TCFCFG1_FCFGR;
__asm("DMB");
}
#pragma ghs section text=default
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Traveo™ Family, MB9D560 Setting Clock System
3.1.2
The Wait Cycle Count Calculation
The wait cycle count is calculated from the following equation.
(System operating frequency / Maximum operating frequency of TCFLASH) - 1 = Wait cycle count (*)
If the calculated result is a decimal, integer values are determined by rounding up the decimal part.
Ex. ) System operating frequency: 200MHz, Maximum operating frequency of TCFLASH: 80MHz
(System operating frequency / Maximum operating frequency of TCFLASH)- 1
= 200 / 80 - 1
=3-1
=2
3.2
System Clock Setting
This microcontroller operates in the Fast-CR clock after power-on. It performs the setting mentioned in this chapter
for changing frequency of the system clock. After that, it is necessary to reflect the setting to the RUN profile. After
RUN profile settings, the frequency of the system clock change gradually over a number of steps that is set by
operating the clock gear.
All cores sets do not access the peripherals during the frequency change of the system clock. It may cause a
malfunction.
All registers that are described in this chapter is locked the writing. It is necessary to perform after unlock to write the
unlock code (0x5CACCE55) to the protection key setting register (SYSC_PROTKEYR) when writing to the register.
Every time unlock is required when performing the writing.
3.2.1
Source Clock Timer
The source clock timer is for gating the clock output until the end of the clock oscillation stabilization wait time. In
order to use the source clock timer, it is necessary to set Table 2 register. Example of this setting is described in
Table 2 when changing the system clock to the PLL clock (200MHz) from the high-speed CR clock.
Table 2. Example of Source Clock Timer Setting (PLL clock 200MHz when used)
Register Abbreviation
Bit name
PSCL
SYSC_MOCTCPR
*1
CMPR
SYSC_ MOCTTRGR
SYSC_PLLSTCNTR
1.
*4
*2
CGCPT
PLLSTABS
*5
Settings
Value
Select the division ratio of the input clock of the main
clock timer.
0110(b) *3
The compare value of the main clock timer.
1D4C(h) *3
Change the timer settings / Start the timer counting.
1(b)
PLL stabilization wait time selection.
1111(b)
Setting is reflected by writing a "1" to CGCPT of SYSC_MOCTTRGR.
It is necessary to complete the setting before writing "1" to CGCPT of SYSC_MOCTTRGR.
2.
It is prohibited to be changed during timer operation.
3.
The main clock is the setting that assumes the 16MHz.
4.
Bits which are not described are not required change.
5.
Do not change setting after PLL clock oscillation is set to enable
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Traveo™ Family, MB9D560 Setting Clock System
3.2.2
C l o c k S u p e r vi s o r
If you use the clock supervisor, the clock supervisor can detect the stopped clocks and occurrences of frequencyrange abnormalities. To detect the abnormal using the clocks of 2 systems are used: one clock becomes the
monitoring target, and the other clock is a reference clock for measuring a certain time period.
The clock supervisor is equipped with the following supervisors. Each of them is independent and can be separately
set to enabled or disabled.
Main clock supervisor
PLL clock supervisor
Sub-system PLL clock supervisor (Flex Ray/RDC PLL）
This application note describes how to use main clock supervisor and PLL clock supervisor. It refers to the hardware
manual when using sub-system PLL clock supervisor.
Setting procedure is described in Figure 6 when using the Main clock supervisor and PLL clock supervisor. Clock
supervisor start operating after the oscillation stabilization wait of clock to be monitored.
Figure 6. Clock Supervisor Setting Procedure
START
User reset factor clear
(Main Clock Supervisor)
User reset factor clear
(PLL Clock Supervisor)
Since user reset factor register is not cleared
by a reset other than power-on reset,
there is a need to clear before clock supervisor use.
If the clock that flag is set is set to clock domain,
it becomes profile error.
Setting main clock supervisor
upper-limit threshold and The
lower-limit threshold
Setting main clock supervisor
reference period and the
judgment selection
Setting PLL clock supervisor
upper-limit threshold and the
lower-limit threshold
Setting PLL clock supervisor
reference period
Setting clock supervisor enable
(Main clock, PLL clock)
≈
Profile settings apply
(Profile Update)
END
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Traveo™ Family, MB9D560 Setting Clock System
Clock Supervisor Setting Example
In order to use clock supervisor, it is necessary to set the register of Table 3. The example is described in Table 3
when using clock supervisor under the following conditions.
It is not include setting at the time of PSS state in Table 3. The reference clock of the main clock supervisor at the
time of PSS is possible to select the Slow-CR clock. Method of using Slow-CR clock as a reference clock refers to the
hardware manual.
Clock supervisor to be used：Main clock supervisor, PLL clock supervisor
Main clock supervisor use conditions
Main clock frequency：16MHz
Fast-CR clock frequency：6～10MHz (typ：8MHz)
Acceptable main clock frequency range：4～20MHz
Reference clock count period：60
PLL clock supervisor use conditions
PLL clock frequency：200MHz
Main clock frequency：8MHz
Acceptable PLL clock frequency range：80～500MHz
Reference clock count period：12
Table 3. Clock Supervisor Setting Example (Main clock/PLL clock when used)
Register Abbreviation
Bit name
Frequency range upper-limit threshold value of Main clock
UPTHR
(Reference clock：Fast-CR clock）
SYSC_ CSVMOCFGR00
*1、*2
Frequency range lower-limit threshold value of Main clock
LOWTHR
(Reference clock：Fast-CR clock）
Selection of Operation at abnormal state detection of Main clock
JDGSEL
(Reference clock：Fast-CR clock）
SYSC_ CSVMOCFGR01
*1
REFCLKWND
*2、*5
Frequency range lower-limit threshold value of PLL clock
LOWTHR
*5
(Reference clock：Fast-CR clock）
(Reference clock：Main clock）
SYSC_ CSVPLLCFGR0
SYSC_ CSVPLLCFGR1
Reference clock count period of Main clock supervisor
Frequency range upper-limit threshold value of PLL clock
UPTHR
(Reference clock：Main clock）
REFCLKWND
Value
(decimal)
Settings
Reference clock count period of PLL clock supervisor
(Reference clock：Main clock）
200
24
0
*3
*3
*4
60
375
60
*3
*3
12
PLLCSVE
Enable the PLL clock supervisor
1
MOCSVE
Enable the main clock supervisor
1
SYSC_RUNCSVCFGR
1.
This register must not be modified during operation of the main clock supervisor.
2.
Set the upper-limit threshold value bit value to be greater than the lower-limit threshold value bit value.
3.
Calculation method of the threshold value refer to “Calculation of the Clock Supervisor Threshold Value”.
4.
At the abnormal state detection, it generates a reset if the main clock is selected as clock domain 0 or the
software watchdog timer. If this is not the case an interrupt is generated.
5.
This register must not be modified during operation of the PLL clock supervisor.
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Traveo™ Family, MB9D560 Setting Clock System
Calculation of the Clock Supervisor Threshold Value
Threshold value to be set in the clock supervisor is calculated from the following equation.
Acceptable the maximum value of monitoring target clock frequency / Minimum value of Reference clock frequency x
Reference clock count period
= Upper-limit threshold value
Acceptable the minimum value of monitoring target clock frequency / Maximum value of Reference clock frequency x
Reference clock count period
= Lower-limit threshold value
If it was used in the conditions in the “0.0.0Clock Supervisor Setting Example”, the setting is following.
Upper-limit threshold value of main clock supervisor
Acceptable the maximum value of main clock frequency / Minimum value of Fast-CR clock frequency x Reference
clock count period
= 20 / 6 x 60 = 200
Lower-limit threshold value of main clock supervisor
Acceptable the minimum value of main clock frequency / Maximum value of Fast-CR clock frequency x Reference
clock count period
= 4 / 10 x 60 = 24
Upper-limit threshold value of PLL clock supervisor
Acceptable the maximum value of PLL clock frequency /Minimum value of Main clock frequency x Reference clock
count period
= 500 / 16 x 12 = 375
Lower-limit threshold value of PLL clock supervisor
Acceptable the minimum value of PLL clock frequency / Maximum value of Main clock frequency x Reference clock
count period
= 80 / 16 x 12 = 60
Notes of Clock Supervisor
Profile settings are used to enable/disable the clock supervisor. Writing to the clock supervisor configuration
register alone setting is not reflected. So it must be RUN update.
If clock supervisor want stopped, it is necessary to stop the oscillation of the monitoring clock.
User reset factor register (SYSC_RSTCAUSEUR) is not cleared except during power-on reset. It must clear the
clock supervisor reset detection bit before starting clock supervisor operation.
After a reset generated by the detection of a clock abnormality, the main clock supervisor reference clock returns
to the fast-CR clock.
There is a profile error, if the clock supervisor reset detection bit of the user reset factor register
(SYSC_RSTCAUSEUR) is already set is selected as the clock monitor domain.
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Traveo™ Family, MB9D560 Setting Clock System
3.2.3
Clock Gear
The frequency of the clock gear can be gradually changed by step-by-step output of the input clock to the clock gear
circuit.
The frequency fluctuates abruptly at the time of switching from the main clock to the PLL clock, so the power supply
current also fluctuates considerably. A clock gear operation is necessary to prevent any possible occurrence of
overshoot/undershoot of the power supply current at the clock switching time.
In order to use the clock gear, it is necessary to set the register of Table 4. The example is described in Table 2 when
using clock gear under the following conditions.
Main clock frequency：16MHz
PLL clock frequency：200MHz
Loop count：256times
Step width：1
Start step：0
Table 4. Clock Gear Setting Example
Register Abbreviation
Bit name
PLLCGLP
SYSC_PLLCGCNTR
*1
Settings
Value
Loop count per one step of PLL clock gear operation
FF(h)
PLLCGSTP
*1
Step width at the PLL clock gear-up/down
00(b)
PLLCGSSN
*1
Step at the start of PLL clock gear operation
000000(b)
Start gear operation
01(b)
Clock gear operation enabled
1(b)
PLLCGSTR
PLLCGEN
*1
1.
Do not change setting after PLL clock oscillation is set to enable.
2.
It is necessary to set at the timing of operating the clock gear after application of the profile settings.
*2
Procedure of Clock Gear Operation Start
Clock gear starts the operation by performing the following steps after setting in Table 4 (Except PLLCGSTR). It is
necessary to wait until the clock gear is completed after clock gear operation start.
1.
Select the PLL clock as the domain clock.
2.
Set "01" to PLLCGSTR of PLL clock gear control register (SYSC_PLLCGCNTR).
3.
Poll the value of the clock gear status flag (PLLCGCNTR.PLLCGSTS), and wait until the clock indicates the stop
state.
Notes of Clock Gear
Setting of the clock gear control register (SYSC_PLLCGCNTR) must satisfy the condition of the “Source Clock
for the Clock Domain 0”.
The smaller step width and the larger loops count, the more gradually the frequency changes.
When clock gear operation is enabled, after the oscillation stabilization wait time of the clock gear input clock, the
clock according to the setting of PLLCGSSN is output. But it does not gear up/gear-down until the clock gear
operation start setting is performed.
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Traveo™ Family, MB9D560 Setting Clock System
3.2.4
Clock Domain of RUN Mode
Enable Setting of the Source Clock
A hardware reset results in the source clocks from the external/built-in oscillation circuits (fast-CR circuit clock, slowCR clock and main clock/main clock divided by 2) entering the oscillation-enabled state. Conversely, the PLL clock
enters the oscillation-disabled state. It is necessary to enable the oscillation of the PLL clock when changing the
source clock of the system clock to the PLL clock (200MHz). To enable PLL oscillation, the oscillation for the main
clock must already be enabled. If the oscillation for the main clock has not been enabled, a profile error occurs.
It can be set to enable the oscillation of the corresponding clock during RUN by writing "1" to the bits of register
shown in the Table 5. However, control for enabling/disabling the source clock oscillation is available only when the
system is not using the source clock. The fast-CR clock/slow-CR clock oscillation cannot be disabled in RUN.
The example is described in Table 5 when changing the source clock of the system clock to the PLL clock (200MHz).
Table 5. Source Clock Oscillation Enabled Setting Example
Register Abbreviation
Bit name
Settings
Value (decimal)
PLLEN
Enable PLL clock oscillation
1
MOSCEN
Enable Main clock oscillation
1
SCROSCEN
Enable Slow-CR clock oscillation
1
CROSCEN
Enable Fast-CR clock oscillation
1
SYSC_RUNCKSRER
PLL Clock Divider
The PLL clock is generated from the main clock. The example is described in Table 6 when generating a PLL clock
200MHz from the main clock 16MHz under the following conditions.
N-multiplier : Multiply by 25
M-divider : Divided by 2
Input clock divider : No division
Table 6. PLL Clock Divider Setting Example
Register Abbreviation
SYSC_RUNPLLCNTR
Bit name
Settings
Value (decimal)
PLLDIVN
PLL clock N-multiplier setting
24
PLLDIVM
PLL clock M-divider setting
1
PLLDIVL
PLL input clock divider setting
0
Source Clock for the Clock Domain 0
Hardware reset results in the fast-CR clock being selected as the clock used in all clock domains. It is necessary to
set the PLL clock to the source clock of clock domain 0 when changing the source clock of the system clock to the
PLL clock (200MHz). Source clock of the system clock become the PLL clock by setting the source clock of clock
domain 0 to PLL clock.
Source clock of clock domain 0 during RUN state can be selected by setting the register of Table 7. The example is
described in Table 7 when setting the source clock of clock domain 0 to PLL clock.
When switching to PLL clock, be sure to use clock gear. Switch with 50MHz or less and activate gear-up operation
Table 7. Clock Domain 0 Source Clock Setting Example
Register Abbreviation
SYSC_ RUNCKSELR0
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Bit name
CD0CSL
Settings
Clock domain 0 source clock selection
Document No. 002-04450 Rev.*A
Value (decimal)
4
11
Traveo™ Family, MB9D560 Setting Clock System
Internal Clock Oscillation Enable
Setting internal clock oscillation enable during RUN state can be changed by setting the register of Table 8. However,
there are restrictions on the following clock.
SYSCPD1 internal operation clock: Oscillation disable cannot set.
HPMPD2 internal operation clock: Oscillation disable cannot set.
CPU1 internal operation clock: Oscillation disable cannot set.
CPU0 internal operation clock: Oscillation disable cannot set.
EXTBUS internal operation clock : Set this bit to "0" due to this microcomputer has no external bus I/F.(*)
Note: Setting of EXTBUS internal operation clock become enabling by default. It is necessary to set the oscillation
disable.
The setting example is described in Table 8 when enabling other than EXTBUS internal operation clock.
Table 8. Example of Setting Internal Clock Oscillation Enable
Register Abbreviation
SYSC_RUNCKER
Bit name
Settings
ENCLKPERI7
PERI7 internal operation clock oscillation enable
1
ENCLKPERI6
PERI6 internal operation clock oscillation enable
1
ENCLKPERI5
PERI5 internal operation clock oscillation enable
1
ENCLKPERI4
PERI4 internal operation clock oscillation enable
1
ENCLKPERI1
PERI1 internal operation clock oscillation enable
1
ENCLKPERI0
PERI0 internal operation clock oscillation enable
1
ENCLKSYSCPD1
SYSCPD1 internal operation clock oscillation enable
1
*1
ENCLKEXTBUS
EXTBUS internal operation clock oscillation enable
0
*2
ENCLKMEMC
MEMC internal operation clock oscillation enable
1
ENCLKDMA
DMA internal operation clock oscillation enable
1
ENCLKHPMPD2
HPMPD2 internal operation clock oscillation enable
1
ENCLKATB
ATB internal operation clock oscillation enable
1
ENCLKDBG
DBG internal operation clock oscillation enable
1
ENCLKCPU1
CPU1 internal operation clock oscillation enable
1
*1
ENCLKCPU0
CPU0 internal operation clock oscillation enable
1
*1
1.
"0" writing is invalid.
2.
Since the initial value "1" is set, changing always "0".
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Value (decimal)
Document No. 002-04450 Rev.*A
*1
12
Traveo™ Family, MB9D560 Setting Clock System
Internal Clock Divider
Division ratio of the source clock of each internal operation clock during RUN state can be changed by setting the
registers of Table 10. However, it is necessary to set the division ratio so that the supplied clock does not exceed the
maximum operating frequency of any internal operating clock. The maximum operating frequency is described in
Table 9.
Table 9. Maximum Operating Frequencies of Internal Operating Clock
Internal Operating Clock
Maximum Operating Frequency
CLK_HPMPD2
200MHz
CLK_DMA
200MHz
CLK_MEMC
200MHz
TRC clock
100MHz
CLK_ATB
100MHz
DBG clock
50MHz
System clock
200MHz
SYSC_PD1 clock
100MHz
EXTBUS clock
200MHz
PERI7 clock
50MHz
PERI6 clock
50MHz
PERI5 clock
100MHz
PERI4 clock
100MHz
PERI1 clock
50MHz
PERI0 clock
100MHz
The setting example is described in Table 10 when operating at the maximum operating frequency. Source clock of
the system clock is the PLL clock (200MHz).
Table 10. Internal Clock Divider Setting Example
Register Abbreviation
RUNCKDIVR0
Bit name
Settings
Value (decimal)
HPMDIV
Division ratio of the HPM clock, DMA clock and MEMC
clock from the system clock
0
TRCDIV
Division ratio of the TRC clock from the system clock
1
ATBDIV
Division ratio of the ATB clock from the system clock
1
*1
DBGDIV
Division ratio of the DBG clock from the ATB clock
1
*1
SYSDIV
Division ratio of the system clock from the source clock
0
SYSCPD1DIV
Division ratio of the SYSC_PD1 clock from the HPM clock
1
EXTBUSDIV
Division ratio of the EXTBUS clock from the HPM clock
1
PERI7DIV
Division ratio of the PERI7 clock from the PERI5 clock
1
PERI6DIV
Division ratio of the PERI6 clock from the PERI4 clock
1
PERI5DIV
Division ratio of the PERI5 clock from the HPM clock
1
PERI4DIV
Division ratio of the PERI4 clock from the HPM clock
1
PERI1DIV
Division ratio of the PERI1 clock from the PERI0 clock
1
PERI0DIV
Division ratio of the PERI0 clock from the HPM clock
1
RUNCKDIVR1
RUNCKDIVR2
1.
Write invalid
2.
It is not affect to change the settings because this microcontroller not equipped EXTBUS
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Document No. 002-04450 Rev.*A
*2
13
Traveo™ Family, MB9D560 Setting Clock System
3.2.5
RUN Profile Settings Update
Setting is not reflected in the writing to the register when changing the settings of RUN / PSS profile setting
parameters (*). It is necessary to do the following steps to reflect the setting of RUN profile.
Note: See Hardware Manual.
1.
Write the settings to the register change the setting.
2.
Clear the RUN profile (main status control) update completion flag at system status flag and interrupt clear
register (SYSC_SYSICLR).
3.
Write "0xAB" to the RUN profile update trigger register of the system controller (SYSC_TRGRUNCNTR).
4.
Poll the RUN profile update completion flag bit of System Status Register, and to wait until the profile update
completed (RUNDF0 becomes "1").
If the contents of the new RUN profile do not present any problems, the control circuit will reflect the contents of the
profile, as follows.
1.
"1" is set in the system status register (SYSC_SYSSTSR: RUNSTS0).
2.
The contents of the RUN profile are copied to the APPLIED profile.
3.
Reflect the following setting in order
Clock oscillation enable/stop (including waiting for oscillation stabilization)
Clock supervisor setting changes
LVD setting changes
Clock operation settings (source clock changes, division, and ON/OFF of each clock source)
4.
Clock stop settings (source clock stop)
When RUN profile update is completed, the system status register (SYSC_SYSSTSR: RUNSTS0) is cleared to
"0".
5.
"1" is set in the system status register (SYSC_SYSSTSR: RUNDF0).
If present setting is problems, Profile error occurs, system error interrupt factor register 1 (SYSC_SYSERRIR1:
RUNERRIF0) is set. The contents of the new profile are discarded, and the circuit operates with the contents of the
profile currently in use.
See the hardware manual, about the profile error.
Notes of RUN Profile Settings
4
Profile Update is prohibited during the profile update. If the profile update again while profile is being updated, a
system error interrupt (SYSC_SYSERRIR1: RUNTRGERRIF) will be generated, and the attempted update profile
will be disabled.
Before updating the RUN profile, it is necessary to confirm the flag of the profile status register
(SYSC_SYSPROSTSR:RUNPSTS) is already cleared. When it is updated the RUN profile during a profile error
status, an NMI interrupt will be generated, and the RUN profile settings will be discarded.
During RUN profile update, it is prohibited to write access to RUN profile register group. A write access is made
to the RUN profile register group during a RUN profile update. The write data will be disabled.
Reference
1.
32-BIT MICROCONTROLLER Spansion Traveo Family MB9D560 HARDWARE MANUAL
2.
MB9D560 Series Application Notes (Dual CPU Operation)
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Document No. 002-04450 Rev.*A
14
Traveo™ Family, MB9D560 Setting Clock System
5
Document History
Document Title: AN204450 - Traveo™ Family, MB9D560 Setting Clock System
Document Number: 002-04450
Revision
ECN
Orig. of
Change
**
-
KHAS
07/16/2015
Initial Release
*A
5041474
KHAS
12/08/2015
Migrated Spansion Application Note from MB9D560_AN708-00008-1v0-E
to Cypress format
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Submission
Date
Description of Change
Document No. 002-04450 Rev.*A
15
Traveo™ Family, MB9D560 Setting Clock System
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Document No. 002-04450 Rev.*A
16