MB9D560 Series, Datasheet

The following document contains information on Cypress products. Although the document is marked
with the name “Spansion”, the company that originally developed the specification, Cypress will
continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any
changes that have been made are the result of normal document improvements and are noted in the
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will be noted in a document history page.
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Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Cypress products and solutions.
About Cypress
Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart of today’s most
advanced embedded systems, from automotive, industrial and networking platforms to highly
interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes
®
NOR flash memories, F-RAM™ and SRAM, Traveo™ microcontrollers, the industry’s only PSoC
®
programmable system-on-chip solutions, analog and PMIC Power Management ICs, CapSense
®
capacitive touch-sensing controllers, and Wireless BLE Bluetooth Low-Energy and USB connectivity
solutions, Cypress is committed to providing its customers worldwide with consistent innovation, bestin-class support and exceptional system value.
MB9D560 Series
32-bit Microcontroller
Spansion® TraveoTM Family
MB9DF564MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE
MB9DF565MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE
MB9DF566MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9D560_DS708-00001
CONFIDENTIAL
Revision 3.0
Issue Date May 15, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion
data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this
proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has
been completed, and that initial production has begun. Due to the phases of the manufacturing
process that require maintaining efficiency and quality, this document may be revised by subsequent
versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
2
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
MB9D560 Series
32-bit Microcontroller
Spansion® TraveoTM Family
MB9DF564MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE
MB9DF565MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE
MB9DF566MAE/MGE/MLE/MQE/LAE/LGE/LLE/LQE
Data Sheet (Full Production)
1. Description
MB9D560 series has SPANSION 32-bit microcontrollers for automobile motor control. They use the
®
ARM Cortex-R5 MPCore
TM
CPU that is compatible with the ARM family.
Notes:
−
−
ARM, Cortex, Thumb are the registered trademarks of ARM Limited in the EU and other countries.
MPCore, CoreSight are the trademarks of ARM Limited in the EU and other countries.
Publication Number MB9D560_DS708-00001
Revision 3.0
Issue Date May 15, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Table of Contents
1.
2.
3.
4.
5.
6.
7.
Description ............................................................................................................................................... 3
Features .................................................................................................................................................... 5
Product Lineup ...................................................................................................................................... 11
Pin Assignment...................................................................................................................................... 12
Pin Description ...................................................................................................................................... 16
I/O Circuit Type ...................................................................................................................................... 34
Handling Precautions ............................................................................................................................ 37
7.1 Precautions for Product Design .................................................................................................... 37
7.2 Precautions for Package Mounting ............................................................................................... 38
7.3 Precautions for Use Environment ................................................................................................. 40
8. Handling Devices ................................................................................................................................... 41
9. Block Diagram........................................................................................................................................ 44
10. Memory Map ........................................................................................................................................... 46
11. I/O Map.................................................................................................................................................... 49
12. Pin Statuses in CPU Status................................................................................................................... 54
13. Electrical Characteristics ...................................................................................................................... 56
13.1 Absolute Maximum Ratings .......................................................................................................... 56
13.2 Recommended Operating Conditions........................................................................................... 58
13.3 DC Characteristics........................................................................................................................ 60
13.4 AC Characteristics ........................................................................................................................ 69
13.5 A/D Converter ............................................................................................................................... 96
13.6 4 Channels Same Time Sampling A/D Converter......................................................................... 97
13.7 Flash Memory ............................................................................................................................. 100
13.8 R/D Converter............................................................................................................................. 101
14. Ordering Information ........................................................................................................................... 102
15. Part Number Option............................................................................................................................. 102
16. Package Dimensions ........................................................................................................................... 103
17. Major Changes ..................................................................................................................................... 105
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2. Features
Function
Technology
Description
−
CMOS 90nm technology
−
ARM Cortex®-R5F
−
32-bit ARM architecture
−
2-instruction issuance super scalar
−
8-stage pipeline
−
ARMv7 / Thumb®-2 instruction set
−
Floating-Point Unit (FPU)
Double precision
−
Memory protection Unit (MPU)
−
ECC support for the TCM port
16 area
1-bit error correction, 2-bit error detection ECC (SEC-DED)
−
TCM port
2 TCM ports
CPU
−
ATCM port
−
BTCM 2 ports (B0TCM, B1TCM)
−
VIC port
Low latency interrupt
−
AXI master interface
64-bit AXI interface (instruction / data access)
32-bit AXI interface (I/O access)
−
AXI slave interface
64-bit AXI interface (accessible to TCM port)
−
CPU configuration
−
Operating frequency
2 CPUs (AMP operation)
Maximum 200 MHz
−
Trace with ETM-R5
−
ARM CoreSightTM Technology
−
Debugging interface
Each CPU embedded Embedded Trace Macro (ETM), trace support of CPU operation
JTAG (5 pin )
Debugging
Support clock : maximum 20 MHz
−
Debugging security support
128-bit security key (Device security key)
−
Wakeup function on JTAG
−
User mode
Operation mode
Normal mode (internal memory activation)
−
Serial writer mode
−
Internal clock source
Fast-CR oscillation (8 MHz)
Slow-CR oscillation (100 kHz)
−
Clock control
External oscillation input
Main clock input
−
Embedded PLL
−
Oscillator stabilized timer
Main PLL (Multiplying clock of main oscillation )
Support oscillator stabilized timer for all clock source independently
After a lapse of oscillator stabilized time, it is able to use source clock timer (Except PLL for FlexRay/RDC)
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Function
Description
−
Reset level
Hardware reset (system initialization)
Software reset (programing initialization)
−
Reset factor (Hardware reset )
Power-on reset (PONR), external reset input (RSTX, NMIX+RSTX), clock stop waiting with time-out reset,
Reset control
low-voltage detection reset (internal low-voltage detection reset, 5V external low-voltage detection reset ),
watchdog reset (hardware watchdog reset, software watchdog reset ), clock supervisor reset (main clock
monitor, PLL clock monitor), software trigger hardware reset , profile error reset
−
Reset factor (software reset )
−
Device state
Software reset
RUN (Run State, CPU is operation status)
PSS (Power Saving State, CPU wait event from WFI)
Low power consumption control
−
Setting parameter of each devise state
Clock (clock source enable, clock source selection, clock divider, clock domain enable)
Clock monitor
Low-voltage detection
−
Memory protection as master except processor
−
Target master
Memory protection unit (MPU)
Timing protection unit (TPU)
DMA controller
−
8 area
−
NMI generation when violation detection
−
TPU 1 unit as CPU 1 unit
−
24-bit timer x 8 channels per unit
−
Support execution time protection, locking time protection, inter-arrival time protection, deadline protection
−
Support normal mode and over flow mode
−
Prescaler of each channels
Timer clock divider (1/1 to 1/64)
−
Independent prescaler of each channels
Timer clock divider (1/1, 1/2, 1/4, 1/16)
−
Monitor target clock
−
Monitor method
Main oscillation input , main PLL output
Clock supervisor (CSV)
Monitor of frequency range
−
Operation after error detection
Reset or NMI
−
Watchdog timer embedded
Hardware watchdog timer
Software watchdog timer
−
Hardware watchdog timer
1 unit per system
32-bit watchdog timer with window function
Clock source: fast-CR or slow-CR
Watchdog timer (WDT)
Set by boot program (BootROM maker)
Not set by user program
−
Software watchdog timer
1 unit per CPU
32-bit watchdog timer with window function
Clock source: fast-CR, slow-CR, main clock
One time set on user program (not set again)
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D a t a S h e e t
Function
Description
−
Select voltage monitor
External low-voltage detection (5V power line monitor): 3.9V, 4.1V, 4.3V
Internal low-voltage detection (1.2V power line monitor): 0.9V
Low-voltage detection (LVD)
−
Internal low-voltage detection: always valid
−
External low-voltage detection: valid/invalid set
−
External low-voltage detection: set threshold voltage independently on RUN / PSS
−
Output when low-voltage detection
External low-voltage detection: reset or NMI
Internal low-voltage detection: reset
−
Cortex-R5F ATCM connection
1 Main Flash memory as CPU 1 unit
Main Flash memory
(TCFLASH)
−
HPM connection with 64-bit AXI
−
Flash memory configuration
Interleave with 64-bit Flash 2 units
−
2 address areas
TCM (read only)
AXI (read / write)
−
Work Flash memory
(WorkFLASH)
Parallel programming support
−
Flash security
−
2 Work Flash memories
−
ECC support (SEC-DED)
−
Parallel programming support
−
Flash security
−
BTCM connection of Cortex-R5F
1 Work Flash memory as CPU 1 unit
1 main SRAM as CPU 1 unit
Main SRAM (TCRAM)
BootROM
ECC support (SEC-DED)
−
Interleave with 2 ports of B0TCM and B1TCM
−
ECC support (SEC-DED)
−
Size: 16K byte
−
Boot operation support
−
Serial writer program support
−
16 channels
−
Transfer mode
Block transfer, Burst transfer
DMA controller (DMAC)
−
Addressing mode
Fixed, increment
−
Priority between channels
Fixed, Dynamic, Round robin
−
Support normal interrupt (IRQ) and non-maskable interrupt (NMI)
−
Normal interrupt (IRQ)
Use Interrupt Request (IRQ) of Cortex-R5F
512 channels
32 level for priority
Interrupt control (IRC)
−
Support low latency interrupt response from VIC port of Cortex-R5F
−
Non-maskable interrupt (NMI)
Use fast interrupt request (FIQ) of Cortex-R5F
32 channels
16 level for priority
−
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CONFIDENTIAL
Support software interrupt generation
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D a t a S h e e t
Function
Description
−
Input
Normal interrupt (IRQ): 8 input
External interrupt (EXT-IRQ)
Non-maskable interrupt (NMI): 1 input
−
Detection method
H level , L level , rise edge, fall edge, both edge
Inter-processor communications unit
−
(IPCU)
Exclusion access memory (EAM)
Bit-band unit (BBU)
CRC
Mailbox function
Data communication for CPU core communication by 8 Mailbox
Support of interrupt between CPU core
−
Small size memory to support exclusion control on exclusion access instruction
−
Use for semaphore
−
Size: 48 byte
−
The bit operation of specified register bit on Bit band area, it is mapping 1 bit of bit band area to support bit
−
Output to register of CRC code according real time writing to input register
−
16-bit timer
band alias area for 1 byte. The target of bit band access is specified register bit on I/O area
Base timer
Any of four PWM/PPG/reload/PWC timer functions can be selected and used.
A 32-bit timer can be used in 2 channels of cascade mode as reload/PWC timer.
16-bit free-run timer (FRT)
−
16 bit up/down counter (2 channels for motor control only)
32-bit free-run timer
−
32 bit up/down counter
−
Input capture
16-bit capture register that detects rise edge, Fall edge, both edge
16-bit input capture (ICU)
Generate interrupt request after latch of counter number of 16 bit
Free-run timer with edge detection of pin input
−
Input capture
32-bit capture register that detects rise edge, fall edge, both edge
Generate interrupt request after latch of counter number of 32 bit
Free-run timer with edge detection of pin input
32-bit input capture
−
LIN sync break/sync field relation is following.
Input capture ch.0 → Multi-function serial interface ch.0
Input capture ch.1 → Multi-function serial interface ch.1
Input capture ch.2 → Multi-function serial interface ch.2
Input capture ch.3 → Multi-function serial interface ch.3
Input capture ch.4 → Multi-function serial interface ch.4
16-bit output compare (OCU)
8
CONFIDENTIAL
−
Output interrupt signal when compare with 16-bit free-run timer
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Function
Description
−
Generate variable output
Real time output
16-bit PPG waveform output
PPG uses 16-bit PPG timer of base timer
The relation is following
WFG(ch.0 to ch.5)
Base timer ch.0 → PPG0
Base timer ch.2 → PPG2
Base timer ch.4 → PPG4
Waveform generator (WFG)
WFG(ch.6 to ch.11)
Base timer ch.6 → PPG6
Base timer ch.8 → PPG8
Base timer ch.10 → PPG10
Non overlap three-phase waveform output (inverter control)
DC chopper waveform output
A/D converter (ADC)
4ch sample-hold A/D converter
−
Dead time timer function
−
GATE function
−
DTTI function
−
12-bit resolution A/D converter: 1 unit (32 channels)
−
Sampling analog value from input port of 32 channels
−
Conversion time: 1 µs
−
External trigger activation (ADTG)
−
Activation from internal timer (base timer)
−
12 bit resolution A/D converter: 2 units (8 channels )
−
UART / CSIO / LIN interface (v2.1) communication available by selecting the function
−
Transmission FIFO: 64 Byte, reception FIFO: 64 Byte
−
Reception interrupt factor (3 types)
Reception error detection (parity, over run, frame error)
Reception to FIFO for data of setting value
Multi-function serial interface (MFS)
Reception data under setting value in FIFO, idle term detection of over 8 clocks with baud rate clock
−
Transmission interrupt factor (2 types)
No transmission operation
Transmission FIFO empty (contain transmission operation)
Up/Down counter (UDC)
CAN interface
FlexRay controller
−
SPI (serial peripheral interface) support
−
LIN protocol revision 2.1 support
−
8/16-bit up/down counter (2 channels uses for R/D converter)
−
The CAN is based on the CAN protocol ver. 2.0A/B
−
64 message buffers x 3 channels
−
An identification mask is applied to each message object
−
Up to 1Mbps support
−
Clock support CAN prescaler
−
CAN wakeup functions
−
Supports FlexRay protocol specification v2.1
−
Maximum 128 message buffers
−
8K Byte message RAM
−
Variable length of message buffers
−
Each message buffer can be allocated as a part of reception buffer, transmission buffer or reception FIFO
−
Host access to the message buffer via input and output buffers
−
Filtering for slot counter, cycle counter and channels
−
Maskable interrupts are supported
R/D converter (RDC)
−
Connect to resolver interface
D/A converter (DAC)
−
10-bit resolution
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9
D a t a S h e e t
Function
Description
−
Motor vector operation accelerator
(MVA)
Assist for three-phase current normalizing, three-phase to two-phase DC conversion / two-phase to threephase AC conversion, angler calculation, PID control calculation.
−
Error detection in processing (overflow/under flow/non normalizing error of FLOP)
−
Amplitude diagnosis /angle diagnosis function of R/D converter
−
Error current diagnosis function
−
Key code supports
A part of General-purpose I/O (GPIO) register
Key code
Port pin configuration (PPC) register
Analog input control register (ADER)
4ch ADC analog input control register (ADER4CH_1, ADER4CH_0)
Analog output control register (DAC00_DAER, DAC01_DAER)
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MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
3. Product Lineup
Memory Size
Parameter
FLASH size (program)
MB9DF564
MB9DF565
MB9DF566
(512KB+128KB)2
(768KB+128KB)2
(1024KB+128KB)2
FLASH size (Work)
64KB2
64KB2
64KB2
RAM size
64KB2
96KB2
128KB2
Functions
Pin number
System clock
208 pin
176 pin
On-chip PLL clock multiplication system
Minimum instruction execution time :5 ns (200 MHz)
CR oscillator (fast/slow)
Yes
DMAC
Base timer
16 channels
12 channels (0 to 11)
6 channels (0 to 3, 6, 7)
32-bit free-run timer
5 channels
32-bit input capture
3 units (6 channels)
16-bit free-run timer
20 channels*1
16-bit input capture
16-bit output compare
Waveform generator
External interrupt
8 units (0 to 7)
7 units (0 to 6)
(15 channels (0 to 14))
(13 channels (0 to 12))
12 units (0 to 11)
9 units (0 to 5, 9 to 11)
(24 channels (0 to 23))
(18 channels (0 to 11, 18 to 23))
4 units (0 to 3)
3 units (0, 1, 3)
(24 channels (0 to 23))
(18 channels (0 to 11, 18 to 23))
8 channels (0 to 7)
6 channels (0 to 4, 7)
A/D converter
1 unit (32 channels)
4ch sample-hold A/D converter
2 units (8 channels)
R/D converter
2 units*2
D/A converter
2 channels*2
Up/Down counter
4 channels
Motor vector operation accelerator
Multi-function serial interface
2 units
5 channels (0 to 4)
CAN
FlexRay
3 channels (0, 1, 4)
3 channels
128 msb x 1 unit (ch.A / ch.B)*2
Inter-processor communications unit
Yes
Exclusive access memory
Yes
Software watchdog timer
Yes
Hardware watchdog timer
Yes
CRC
2 channels
Internal power supply low-voltage
Yes
detection
External power supply low-voltage
Yes
detection
Yes*2
Key code
Package
Debugging interface
LER208
LEP176
JTAG interface
*1: 2 channels for motor control
*2: The function is different according to the part number. See "15. Part Number Option".
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
11
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
4AN0
4AN1
4AN2
4AN3
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
FRCK12
FRCK13
FRCK14
FRCK15
RDC_W0
RDC_V0
RDC_U0
RDC_Z0
RDC_B0
RDC_A0
P026
ERDS0
DTTI2
RTO12
RTO13
RTO14
VSS
VCC12
P305
P306
P000
P001
P002
P003
P004
P005
P006
VCC5
VSS
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
AREF2 0
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
RDC_ACT0
MAG_MINUS0
MAG_PLUS0
MAG_OUT0
P430
P030
P031
P309
P310
VCC5
12
CONFIDENTIAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
IN16
IN17
IN18
IN19
IN20
IN21
V SS
V CC1 2
P3 1 1
P3 1 2
P3 1 3
P3 1 4
P3 1 5
P3 1 6
P3 1 7
P3 1 8
P3 1 9
P3 2 0
P3 2 1
P3 2 2
P3 2 3
V CC1 2
V SS
IN6
STOPWT P3 2 4
IN7
RXDA
P3 2 5
IN8
TXDA
P3 2 6
IN9
TXE NA P3 2 7
IN10 RXDB
P3 2 8
IN11 TXDB
P3 2 9
IN12 TXE NB P3 3 0
NMIX
RSTX
MD1
MD0
X0
X1
V SS
TRSTX
TCK
TDO
TDI
TMS
n SRST
INT4 SIN1
P4 0 6
SOT1
P4 0 7
SCK1
P4 0 8
INT0 RX0
P4 0 9
TX0
P4 1 0
INT1 RX1
P4 1 1
TX1
P4 1 2
INT2 RX2
P4 1 3
TX2
P4 1 4
TIOA 4
P4 1 5
TIOB4
P4 1 6
TIOA 5
P4 1 7
TIOB5
P4 1 8
V CC1 2
V SS
RTO1 5
RTO1 6
RTO1 7
DTTI3
RTO1 8
RTO1 9
RTO2 0
RTO2 1
RTO2 2
RTO2 3
INT3 SIN0
SOT0
SCK0
4ADTG0
FRCK0
FRCK1
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
TIOA 0
TIOB0
TIOA 1
TIOB1
TIOA 2
TIOB2
TIOA 3
TIOB3
FRCK1 6
FRCK1 7
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
V CC5
P3 0 4
P3 0 3
P3 0 2
P3 0 1
P3 0 0
P2 3 1
P2 3 0
P2 2 9
P2 2 8
P2 2 7
P2 2 6
P2 2 5
P2 2 4
V SS
V CC1 2
P2 2 3
P2 2 2
P2 2 1
P2 2 0
P2 1 9
P2 1 8
P2 1 7
P2 1 6
A V RH2
A V RL2
A V SS2
A V CC2
P2 1 5
P2 1 4
P2 1 3
P2 1 2
P2 1 1
P2 1 0
P2 0 9
P2 0 8
V CC1 2
V SS
P2 0 7
P2 0 6
P2 0 5
P2 0 4
P2 0 3
P2 0 2
P2 0 1
P2 0 0
P4 2 9
P4 2 8
P4 2 7
P4 2 6
P4 2 5
V CC5
A N7
A N6
A N5
A N4
A N3
A N2
A N1
A N0
MONCLK
TIOB9
TIOA 9
TIOB8
TIOA 8
A N1 5
A N1 4
A N1 3
A N1 2
A N1 1
A N1 0
A N9
A N8
A N2 3
A N2 2
A N2 1
A N2 0
A N1 9
A N1 8
A N1 7
A N1 6
TIOB11
TIOA 11
TIOB10
TIOA 10
A DTG0
A N3 1
A N3 0
A N2 9
A N2 8
A N2 7
A N2 6
A N2 5
A N2 4
MM
TIOB7
TIOA 7
TIOB6
TIOA 6
SCS4 3
SCS4 2
SCS4 1
SCS4 0
SCK4
SOT4
SIN4
FRCK7
FRCK6
FRCK5
FRCK4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
D a t a S h e e t
4. Pin Assignment
208 Pin Part Number with RDC
TOP VIEW
LER208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
VCC12
P423
P422
P421
P100
P101
P102
P103
P104
P105
P106
VCC5
VSS
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
AREF2 1
SIN_IN1
COS_IN1
SIN_OUT1
SIN_MINUS1
SIN_PLUS1
COS_PLUS1
COS_MINUS1
COS_OUT1
ＲＶＲＨ1
RVRL1
RVR1
RVSS1
RVCC1
RDC_ACT1
MAG_MINUS1
MAG_PLUS1
MAG_OUT1
P431
P131
P420
P419
VCC5
SCK3
SOT3
SIN3
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
FRCK10 IN14
FRCK9
IN13
INT6
FRCK8
4ADTG1
4AN4
4AN5
4AN6
4AN7
RDC_W1 ZIN2
RDC_V1 BIN2
RDC_U1 AIN2
RDC_Z1 ZIN3
RDC_B1 BIN3
RDC_A1 AIN3
P126
ERDS1
SCK2
SOT2
SIN2
INT5
MB9D560_DS708-00001-3v0-E, May 15, 2015
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
4AN0
4AN1
4AN2
4AN3
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
FRCK12
FRCK13
FRCK14
FRCK15
DAOUT0
ERDS0
DTTI2
RTO12
RTO13
RTO14
CONFIDENTIAL
VSS
VCC12
P305
P306
P000
P001
P002
P003
P004
P005
P006
VCC5
VSS
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
P017
P018
P019
P020
P021
P022
P023
P024
P025
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
P026
P027
P028
P029
P430
P030
P031
P309
P310
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
May 15, 2015, MB9D560_DS708-00001-3v0-E
IN1 6
IN1 7
IN1 8
IN1 9
IN2 0
IN2 1
V SS
V CC1 2
P3 1 1
P3 1 2
P3 1 3
P3 1 4
P3 1 5
P3 1 6
P3 1 7
P3 1 8
P3 1 9
P3 2 0
P3 2 1
P3 2 2
P3 2 3
V CC1 2
V SS
IN6 STOPWT P3 2 4
IN7 RXDA
P3 2 5
IN8 TXDA
P3 2 6
IN9 TXE NA P3 2 7
IN1 0 RXDB
P3 2 8
IN1 1 TXDB
P3 2 9
IN1 2 TXE NB P3 3 0
NMIX
RSTX
MD1
MD0
X0
X1
V SS
TRSTX
TCK
TDO
TDI
TMS
n SRST
INT4 SIN1
P4 0 6
SOT1
P4 0 7
SCK1
P4 0 8
INT0 RX0
P4 0 9
TX0
P4 1 0
INT1 RX1
P4 1 1
TX1
P4 1 2
INT2 RX2
P4 1 3
TX2
P4 1 4
TIOA 4
P4 1 5
TIOB4
P4 1 6
TIOA 5
P4 1 7
TIOB5
P4 1 8
V CC1 2
V SS
RTO1 5
RTO1 6
RTO1 7
DTTI3
RTO1 8
RTO1 9
RTO2 0
RTO2 1
RTO2 2
RTO2 3
INT3 SIN0
SOT0
SCK0
4ADTG0
FRCK0
FRCK1
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
TIOA 0
TIOB0
TIOA 1
TIOB1
TIOA 2
TIOB2
TIOA 3
TIOB3
FRCK1 6
FRCK1 7
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
V CC5
P3 0 4
P3 0 3
P3 0 2
P3 0 1
P3 0 0
P2 3 1
P2 3 0
P2 2 9
P2 2 8
P2 2 7
P2 2 6
P2 2 5
P2 2 4
V SS
V CC1 2
P2 2 3
P2 2 2
P2 2 1
P2 2 0
P2 1 9
P2 1 8
P2 1 7
P2 1 6
A V RH2
A V RL2
A V SS2
A V CC2
P2 1 5
P2 1 4
P2 1 3
P2 1 2
P2 1 1
P2 1 0
P2 0 9
P2 0 8
V CC1 2
V SS
P2 0 7
P2 0 6
P2 0 5
P2 0 4
P2 0 3
P2 0 2
P2 0 1
P2 0 0
P4 2 9
P4 2 8
P4 2 7
P4 2 6
P4 2 5
V CC5
TIOB7
TIOA 7
TIOB6
TIOA 6
SCS43
SCS42
SCS41
SCS40
SCK4
SOT4
SIN4
FRCK7
FRCK6
FRCK5
FRCK4
A N7
A N6
A N5
A N4
A N3
A N2
A N1
A N0
MONCLK MM
TIOB9
TIOA 9
TIOB8
TIOA 8
A N1 5
A N1 4
A N1 3
A N1 2
A N1 1
A N1 0
A N9
A N8
A N2 3
A N2 2
A N2 1
A N2 0
A N1 9
A N1 8
A N1 7
A N1 6
TIOB11
TIOA 11
TIOB10
TIOA 10
A DTG0
A N3 1
A N3 0
A N2 9
A N2 8
A N2 7
A N2 6
A N2 5
A N2 4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
D a t a S h e e t
208 Pin Part Number without RDC
TOP VIEW
LER208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
VCC12
P423
P422
P421
P100
P101
P102
P103
P104
P105
P106
VCC5
VSS
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
RVRH1
RVRL1
RVR1
RVSS1
RVCC1
P126
P127
P128
P129
P431
P131
P420
P419
VCC5
SCK3
SOT3
SIN3
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
INT6
4ADTG1
FRCK10
FRCK9
FRCK8
IN14
IN13
4AN4
4AN5
4AN6
4AN7
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
DAOUT1
ERDS1
SCK2
SOT2
SIN2
INT5
13
V SS
P3 1 4
P3 1 5
P3 1 6
P3 1 7
P3 1 8
P3 1 9
P3 2 0
P3 2 1
P3 2 2
P3 2 3
V CC12
V SS
IN6
STOPWT P3 2 4
IN7
RXDA
P3 2 5
IN8
TXDA
P3 2 6
IN9
TXE NA P3 2 7
IN1 0 RXDB
P3 2 8
IN1 1 TXDB
P3 2 9
IN1 2 TXE NB P3 3 0
NMIX
RSTX
MD1
MD0
X0
X1
V SS
TRSTX
TCK
TDO
TDI
TMS
nSRST
INT4 SIN1
P4 0 6
SOT1
P4 0 7
SCK1
P4 0 8
INT0 RX0
P4 0 9
TX0
P4 1 0
INT1 RX1
P4 1 1
TX1
P4 1 2
INT2 RX2
P4 1 3
TX2
P4 1 4
V CC12
V SS
DTTI3
RTO1 8
RTO1 9
RTO2 0
RTO2 1
RTO2 2
RTO2 3
INT3 SIN0
SOT0
SCK0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
4ADTG0
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
4 AN0
4 AN1
4 AN2
4 AN3
RDC_W0
RDC_V0
RDC_U0
RDC_Z0
RDC_B0
RDC_A0
P0 2 6
ERDS0
14
CONFIDENTIAL
VSS
VCC12
P000
P001
P002
P003
P004
P005
P006
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
AREF2 0
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
RDC_ACT0
MAG_MINUS0
MAG_PLUS0
MAG_OUT0
P430
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
IN1 6
IN1 7
IN1 8
IN1 9
IN2 0
IN2 1
TIOA 0
TIOB0
TIOA 1
TIOB1
TIOA 2
TIOB2
TIOA 3
TIOB3
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
V CC5
P3 0 0
P2 3 1
P2 3 0
P2 2 9
P2 2 8
P2 2 7
P2 2 6
P2 2 5
P2 2 4
V SS
V CC1 2
P2 2 3
P2 2 2
P2 2 1
P2 2 0
P2 1 9
P2 1 8
P2 1 7
P2 1 6
A V RH2
A V RL2
A V SS2
A V CC2
P2 1 5
P2 1 4
P2 1 3
P2 1 2
P2 1 1
P2 1 0
P2 0 9
P2 0 8
V CC1 2
V SS
P2 0 7
P2 0 6
P2 0 5
P2 0 4
P2 0 3
P2 0 2
P2 0 1
P2 0 0
P4 2 9
V CC5
A N7
A N6
A N5
A N4
A N3
A N2
A N1
A N0
MONCLK
A N1 5
A N1 4
A N1 3
A N1 2
A N1 1
A N1 0
A N9
A N8
A N2 3
A N2 2
A N2 1
A N2 0
A N1 9
A N1 8
A N1 7
A N1 6
A DTG0
A N3 1
A N3 0
A N2 9
A N2 8
A N2 7
A N2 6
A N2 5
A N2 4
MM
TIOB7
TIOA 7
TIOB6
TIOA 6
SCS4 3
SCS4 2
SCS4 1
SCS4 0
SCK4
SOT4
SIN4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
D a t a S h e e t
176 Pin Part Number with RDC
TOP VIEW
LEP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
VCC12
P1 0 0
P1 0 1
P1 0 2
P1 0 3
P1 0 4
P1 0 5
P1 0 6
P1 0 7
P1 0 8
P1 0 9
P1 1 0
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P1 1 1
P1 1 2
P1 1 3
P1 1 4
P1 1 5
P1 1 6
AREF2 1
SIN_IN1
COS_IN1
SIN_OUT1
SIN_MINUS1
SIN_PLUS1
COS_PLUS1
COS_MINUS1
COS_OUT1
RVRH1
RVRL1
RVR1
RVSS1
RVCC1
RDC_ACT1
MAG_MINUS1
MAG_PLUS1
MAG_OUT1
P4 3 1
VCC5
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO1 0
RTO1 1
4AN4
4AN5
4AN6
4AN7
4 ADTG1
RDC_W1
RDC_V1
RDC_U1
RDC_Z1
RDC_B1
RDC_A1
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
P1 2 6
ERDS1
MB9D560_DS708-00001-3v0-E, May 15, 2015
DAOUT0
ERDS0
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
INT2
INT1
ZIN0
BIN0
AIN0
ZIN1
BIN1
AIN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
INT0
VSS
VCC12
P000
P001
P002
P003
P004
P005
P006
P007
P008
P009
P010
AVRH0
AVRL0
AVR0
AVSS0
AVCC0
P011
P012
P013
P014
P015
P016
P017
P018
P019
P020
P021
P022
P023
P024
P025
RVRH0
RVRL0
RVR0
RVSS0
RVCC0
P026
P027
P028
P029
P430
VCC5
INT4
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
DTTI0
RTO0
RTO1
RTO2
RTO3
RTO4
RTO5
4AN0
4AN1
4AN2
4AN3
IN6
IN7
IN8
IN9
IN1 0
IN1 1
IN1 2
V SS
P3 1 4
P3 1 5
P3 1 6
P3 1 7
P3 1 8
P3 1 9
P3 2 0
P3 2 1
P3 2 2
P3 2 3
V CC1 2
V SS
STOPWT P3 2 4
RXDA
P3 2 5
TXDA
P3 2 6
TXE NA
P3 2 7
RXDB
P3 2 8
TXDB
P3 2 9
TXE NB
P3 3 0
NMIX
RSTX
MD1
MD0
X0
X1
V SS
TRSTX
TCK
TDO
TDI
TMS
n SRST
SIN1
P4 0 6
SOT1
P4 0 7
SCK1
P4 0 8
RX0
P4 0 9
TX0
P4 1 0
RX1
P4 1 1
TX1
P4 1 2
RX2
P4 1 3
TX2
P4 1 4
V CC1 2
V SS
DTTI3
RTO1 8
RTO1 9
RTO2 0
RTO2 1
RTO2 2
RTO2 3
SIN0
SOT0
SCK0
4ADTG0
IN1 6
IN1 7
IN1 8
IN1 9
IN2 0
IN2 1
TIOA 0
TIOB0
TIOA 1
TIOB1
TIOA 2
TIOB2
TIOA 3
TIOB3 INT3
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
V CC5
P3 0 0
P2 3 1
P2 3 0
P2 2 9
P2 2 8
P2 2 7
P2 2 6
P2 2 5
P2 2 4
V SS
V CC1 2
P2 2 3
P2 2 2
P2 2 1
P2 2 0
P2 1 9
P2 1 8
P2 1 7
P2 1 6
A V RH2
A V RL2
A V SS2
A V CC2
P2 1 5
P2 1 4
P2 1 3
P2 1 2
P2 1 1
P2 1 0
P2 0 9
P2 0 8
V CC1 2
V SS
P2 0 7
P2 0 6
P2 0 5
P2 0 4
P2 0 3
P2 0 2
P2 0 1
P2 0 0
P4 2 9
V CC5
A N7
A N6
A N5
A N4
A N3
A N2
A N1
A N0
MONCLK
A N1 5
A N1 4
A N1 3
A N1 2
A N1 1
A N1 0
A N9
A N8
A N2 3
A N2 2
A N2 1
A N2 0
A N1 9
A N1 8
A N1 7
A N1 6
A DTG0
A N3 1
A N3 0
A N2 9
A N2 8
A N2 7
A N2 6
A N2 5
A N2 4
MM
TIOB7
TIOA 7
TIOB6
TIOA 6
SCS43
SCS42
SCS41
SCS40
SCK4
SOT4
SIN4
IN5
IN4
IN3
IN2
IN1
IN0
INT7
D a t a S h e e t
176 Pin Part Number without RDC
TOP VIEW
LEP176
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
VSS
VCC12
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
AVRH1
AVRL1
AVR1
AVSS1
AVCC1
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
RVRH1
RVRL1
RVR1
RVSS1
RVCC1
P126
P127
P128
P129
P431
VCC5
DTTI1
RTO6
RTO7
RTO8
RTO9
RTO10
RTO11
4AN4
4AN5
4AN6
4AN7
4ADTG1
ZIN2
BIN2
AIN2
ZIN3
BIN3
AIN3
DAOUT1
ERDS1
15
D a t a S h e e t
5. Pin Description
Pin Number
Part Number with RDC
208 pin
176 pin
3
-
4
-
5
3
Pin Name
P305
FRCK0
P306
FRCK1
I/O Circuit
Type
E
E
P000
DTTI0
4
7
5
8
6
9
7
10
8
11
9
14
10
15
11
16
12
17
13
23
19
P001
RTO0
P002
RTO1
P003
RTO2
P004
RTO3
P005
RTO4
P006
RTO5
P007
4AN0
P008
4AN1
P009
4AN2
P010
4AN3
E
E
E
E
E
E
F
F
F
F
RDC_V0
26
27
22
23
RDC_U0
29
25
CONFIDENTIAL
Waveform generator ch.3 output pin
General-purpose I/O port
Waveform generator ch.4 output pin
General-purpose I/O port
Waveform generator ch.5 output pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 0 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 1 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 2 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 3 input pin
R/D converter unit0 W-phase output pin
R/D converter unit0 V-phase output pin
R/D converter unit0 U-phase output pin
Up/Down counter ch.0 AIN input pin
P014
General-purpose I/O port
RDC_Z0
E
R/D converter unit0 Z-phase output pin
ZIN1
Up/Down counter ch.1 ZIN input pin
P015
General-purpose I/O port
RDC_B0
E
RDC_A0
AREF20
R/D converter unit0 B-phase output pin
Up/Down counter ch.1 BIN input pin
General-purpose I/O port
E
AIN1
16
General-purpose I/O port
AIN0
P016
24
General-purpose I/O port
Waveform generator ch.2 output pin
General-purpose I/O port
E
BIN1
28
General-purpose I/O port
Waveform generator ch.1 output pin
Up/Down counter ch.0 BIN input pin
P013
21
General-purpose I/O port
Waveform generator ch.0 output pin
General-purpose I/O port
E
BIN0
25
Waveform generator output stop signal input pin 0
Up/Down counter ch.0 ZIN input pin
P012
20
General-purpose I/O port
16-bit free-run timer ch.1 external clock input pin
General-purpose I/O port
E
ZIN0
24
16-bit free-run timer ch.0 external clock input pin
4ch sample-hold A/D converter unit0 external trigger input pin
P011
RDC_W0
General-purpose I/O port
General-purpose I/O port
E
4ADTG0
6
Functions
R/D converter unit0 A-phase output pin
Up/Down counter ch.1 AIN input pin
L
R/D converter unit0 Aref output pin(RVCC0/2)
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
Pin Name
I/O Circuit
Type
Functions
208 pin
176 pin
30
26
SIN_IN0
K
R/D converter unit0 SIN coil earth leakage detection input pin
31
27
COS_IN0
K
R/D converter unit0 COS coil earth leakage detection input pin
32
28
SIN_OUT0
L
R/D converter unit0 SIN output pin
33
29
SIN_MINUS0
K
R/D converter unit0 SIN input pin-
34
30
SIN_PLUS0
K
R/D converter unit0 SIN input pin+
35
31
COS_PLUS0
K
R/D converter unit0 COS input pin+
36
32
COS_MINUS0
K
R/D converter unit0 COS input pin-
37
33
COS_OUT0
L
R/D converter unit0 COS output pin
RDC_ACT0
39
44
40
MAG_MINUS0
K
R/D converter unit0 excitation external input pin-
45
41
MAG_PLUS0
K
R/D converter unit0 excitation external input pin+
46
42
MAG_OUT0
L
47
43
P026
P430
ERDS0
E
R/D converter unit0 operation status output pin
43
E
P030
48
-
49
-
50
-
DTTI2
E
16-bit free-run timer ch.12 external clock input pin
General-purpose I/O port
RTO12
E
16-bit free-run timer ch.13 external clock input pin
P309
General-purpose I/O port
RTO13
E
RTO14
RTO15
General-purpose I/O port
E
RTO16
General-purpose I/O port
E
-
P313
RTO17
General-purpose I/O port
E
46
DTTI3
E
E
RTO18
General-purpose I/O port
E
TIOB0
48
RTO19
General-purpose I/O port
E
TIOA1
49
RTO20
General-purpose I/O port
E
TIOB1
50
RTO21
TIOA2
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
Waveform generator ch.20 output pin
Base timer ch.1 TIOB input pin
P318
62
Waveform generator ch.19 output pin
Base timer ch.1 TIOA I/O pin
P317
61
Waveform generator ch.18 output pin
Base timer ch.0 TIOB input pin
P316
60
Waveform generator output stop signal input pin 3
Base timer ch.0 TIOA output pin
P315
47
General-purpose I/O port
Waveform generator ch.17 output pin
General-purpose I/O port
TIOA0
59
Waveform generator ch.16 output pin
16-bit free-run timer ch.17 external clock input pin
P314
58
Waveform generator ch.15 output pin
16-bit free-run timer ch.16 external clock input pin
FRCK17
57
Waveform generator ch.14 output pin
16-bit free-run timer ch.15 external clock input pin
P312
-
Waveform generator ch.13 output pin
16-bit free-run timer ch.14 external clock input pin
FRCK16
56
Waveform generator ch.12 output pin
FRCK13
P311
-
Waveform generator output stop signal input pin 2
P031
FRCK15
55
Error detection output pin ch.0
FRCK12
P310
-
R/D converter unit0 excitation signal output pin
General-purpose I/O port
General-purpose I/O port
FRCK14
51
General-purpose I/O port
General-purpose I/O port
E
Waveform generator ch.21 output pin
Base timer ch.2 TIOA output pin
17
D a t a S h e e t
Pin Number
208 pin
176 pin
63
51
Pin Name
I/O Circuit
Type
P319
RTO22
General-purpose I/O port
E
TIOB2
52
RTO23
General-purpose I/O port
E
TIOA3
65
53
54
67
55
70
71
72
58
59
60
Base timer ch.3 TIOA I/O pin
General-purpose I/O port
SIN0
Multi-function serial interface ch.0 serial data input pin
INT3
E
P322
SOT0
P323
SCK0
61
E
E
62
63
General-purpose I/O port
FlexRay stop watch input pin
IN6
E
32-bit input capture ch.0 external pulse input pin
P325
General-purpose I/O port
RXDA
IN7
H
FlexRay ch.A data input pin
16-bit input capture ch.7 external pulse input pin
IN17
32-bit input capture ch.1 external pulse input pin
P326
General-purpose I/O port
TXDA
IN8
H
FlexRay ch.A data output pin
16-bit input capture ch.8 external pulse input pin
32-bit input capture ch.2 external pulse input pin
P327
General-purpose I/O port
TXENA
FlexRay ch.A operation enable output pin
IN9
H
16-bit input capture ch.9 external pulse input pin
32-bit input capture ch.3 external pulse input pin
P328
General-purpose I/O port
RXDB
FlexRay ch.B data input pin
IN10
H
16-bit input capture ch.10 external pulse input pin
32-bit input capture ch.4 external pulse input pin
P329
General-purpose I/O port
TXDB
FlexRay ch.B data output pin
IN11
H
TXENB
16-bit input capture ch.11 external pulse input pin
32-bit input capture ch.5 external pulse input pin
P330
64
16-bit input capture ch.6 external pulse input pin
IN16
IN21
76
General-purpose I/O port
Multi-function serial interface ch.0 clock I/O pin
STOPWT
IN20
75
General-purpose I/O port
Multi-function serial interface ch.0 serial data output pin
P324
IN19
74
INT3 external interrupt input pin
Base timer ch.3 TIOB input pin
IN18
73
Waveform generator ch.23 output pin
P321
TIOB3
66
Waveform generator ch.22 output pin
Base timer ch.2 TIOB input pin
P320
64
Functions
General-purpose I/O port
H
IN12
FlexRay ch.B operation enable output pin
16-bit input capture ch.12 external pulse input pin
77
65
NMIX
B
Non-maskable interrupt input pin
78
66
RSTX
B
External reset input pin
79
67
MD1
C
Mode pin 1 (with high-voltage control)
80
68
MD0
C
Mode pin 0 (with high-voltage control)
81
69
X0
82
70
X1
84
72
TRSTX
J
JTAG test reset input
85
73
TCK
J
JTAG test clock input
86
74
TDO
I
JTAG test data output
18
CONFIDENTIAL
A
Main clock oscillation input pin
Main clock oscillation output pin
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
Pin Name
I/O Circuit
Type
Functions
208 pin
176 pin
87
75
TDI
J
JTAG test data input
88
76
TMS
J
JTAG test mode status input
89
77
nSRST
J
System reset input for debugger
P406
90
78
SIN1
General-purpose I/O port
E
INT4
91
79
92
80
P407
SOT1
P408
SCK1
INT4 external interrupt input pin
E
E
P409
93
81
RX0
94
82
TX0
E
83
RX1
E
84
P412
TX1
85
RX2
E
98
86
99
-
100
-
101
-
102
-
TX2
P415
TIOA4
P416
TIOB4
P417
TIOA5
P418
TIOB5
E
-
SIN2
E
E
E
E
E
General-purpose I/O port
CAN ch.1 transmission data output pin
CAN ch.2 reception data input pin
General-purpose I/O port
CAN ch.2 transmission data output pin
General-purpose I/O port
Base timer ch.4 TIOA output pin
General-purpose I/O port
Base timer ch.4 TIOB input pin
General-purpose I/O port
Base timer ch.5 TIOA I/O pin
General-purpose I/O port
Base timer ch.5 TIOB input pin
General-purpose I/O port
E
INT5
P420
CAN ch.1 reception data input pin
INT2 external interrupt input pin
P419
106
CAN ch.0 transmission data output pin
General-purpose I/O port
INT2
P414
General-purpose I/O port
INT1 external interrupt input pin
P413
97
CAN ch.0 reception data input pin
General-purpose I/O port
E
INT1
96
General-purpose I/O port
Multi-function serial interface ch.1 clock I/O pin
INT0 external interrupt input pin
P411
95
General-purpose I/O port
Multi-function serial interface ch.1 serial data output pin
General-purpose I/O port
INT0
P410
Multi-function serial interface ch.1 serial data input pin
Multi-function serial interface ch.2 serial data input pin
INT5 external interrupt input pin
-
108
-
109
90
110
91
MAG_OUT1
L
R/D converter unit1excitation signal output pin
111
92
MAG_PLUS1
K
R/D converter unit1excitation external input pin+
112
93
MAG_MINUS1
K
R/D converter unit1excitation external input pin-
113
94
SOT2
P131
SCK2
P431
ERDS1
RDC_ACT1
P126
E
General-purpose I/O port
107
E
E
E
Multi-function serial interface ch.2 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.2 clock I/O pin
General-purpose I/O port
Error detection output pin ch.1
R/D converter unit1 operation status output pin
General-purpose I/O port
119
100
COS_OUT1
L
R/D converter unit1 COS output pin
120
101
COS_MINUS1
K
R/D converter unit1 COS input pin-
121
102
COS_PLUS1
K
R/D converter unit1 COS input pin+
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
19
D a t a S h e e t
Pin Number
Pin Name
I/O Circuit
Type
Functions
208 pin
176 pin
122
103
SIN_PLUS1
K
R/D converter unit1 SIN input pin+
123
104
SIN_MINUS1
K
R/D converter unit1 SIN input pin-
124
105
SIN_OUT1
L
R/D converter unit1 SIN output pin
125
106
COS_IN1
K
R/D converter unit1 COS coil earth leakage detection input pin
126
107
SIN_IN1
K
R/D converter unit1 SIN coil earth leakage detection input pin
127
108
AREF21
L
R/D converter unit1 Aref output pin(RVCC1/2)
P116
128
109
RDC_A1
General-purpose I/O port
E
AIN3
Up/Down counter ch.3 AIN input pin
P115
129
110
RDC_B1
General-purpose I/O port
E
BIN3
111
RDC_Z1
General-purpose I/O port
E
ZIN3
112
RDC_U1
General-purpose I/O port
E
AIN2
113
RDC_V1
General-purpose I/O port
E
BIN2
114
RDC_W1
General-purpose I/O port
E
ZIN2
139
120
140
121
141
122
142
123
145
124
146
125
147
126
148
127
149
128
150
129
P110
4AN7
P109
4AN6
P108
4AN5
P107
4AN4
P106
RTO11
P105
RTO10
P104
RTO9
P103
RTO8
P102
RTO7
P101
RTO6
130
DTTI1
4ADTG1
20
CONFIDENTIAL
R/D converter unit1 W phase output pin
Up/Down counter ch.2 ZIN input pin
F
F
F
F
E
E
E
E
E
E
P100
151
R/D converter unit1 V phase output pin
Up/Down counter ch.2 BIN input pin
P111
133
R/D converter unit1 U phase output pin
Up/Down counter ch.2 AIN input pin
P112
132
R/D converter unit1 Z phase output pin
Up/Down counter ch.3 ZIN input pin
P113
131
R/D converter unit1 B phase output pin
Up/Down counter ch.3 BIN input pin
P114
130
R/D converter unit1 A phase output pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 7 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 6 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 5 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 4 input pin
General-purpose I/O port
Waveform generator ch.11 output pin
General-purpose I/O port
Waveform generator ch.10 output pin
General-purpose I/O port
Waveform generator ch.9 output pin
General-purpose I/O port
Waveform generator ch.8 output pin
General-purpose I/O port
Waveform generator ch.7 output pin
General-purpose I/O port
Waveform generator ch.6 output pin
General-purpose I/O port
E
Waveform generator output stop signal input pin1
4ch sample-hold A/D converter unit1 external trigger input pin
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
208 pin
176 pin
152
-
Pin Name
I/O Circuit
Type
P421
General-purpose I/O port
SIN3
Multi-function serial interface ch.3 serial data input pin
INT6
E
FRCK8
153
-
154
-
-
159
-
160
-
161
-
16-bit free-run timer ch.8 external clock input pin
General-purpose I/O port
SOT3
Multi -function serial interface ch.3 serial data output pin
FRCK9
E
134
16-bit input capture ch.13 external pulse input pin
P423
General-purpose I/O port
SCK3
FRCK10
E
P425
TIOA8
P426
TIOB8
P427
TIOA9
P428
TIOB9
MONCLK
135
164
136
165
137
166
138
167
139
168
140
169
141
170
142
173
145
174
146
175
147
176
148
177
149
P200
AN0
P201
AN1
P202
AN2
P203
AN3
P204
AN4
P205
AN5
P206
AN6
P207
AN7
P208
AN8
P209
AN9
P210
AN10
P211
AN11
P212
AN12
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
Multi-function serial interface ch.3 clock I/O pin
16-bit free-run timer ch.10 external clock input pin
16-bit input capture ch.14 external pulse input pin
E
E
E
E
General-purpose I/O port
Base timer ch.8 TIOA output pin
General-purpose I/O port
Base timer ch.8 TIOB input pin
General-purpose I/O port
Base timer ch.9 TIOA I/O pin
General-purpose I/O port
Base timer ch.9 TIOB input pin
General-purpose I/O port
E
MM
163
16-bit free-run timer ch.9 external clock input pin
IN13
P429
162
INT6 external interrupt input pin
P422
IN14
158
Functions
Clock monitor output pin
Clock supervisor main clock error detection output pin
F
F
F
F
F
F
F
F
F
F
F
F
F
General-purpose I/O port
A/D converter analog 0 input pin
General-purpose I/O port
A/D converter analog 1 input pin
General-purpose I/O port
A/D converter analog 2 input pin
General-purpose I/O port
A/D converter analog 3 input pin
General-purpose I/O port
A/D converter analog 4 input pin
General-purpose I/O port
A/D converter analog 5 input pin
General-purpose I/O port
A/D converter analog 6 input pin
General-purpose I/O port
A/D converter analog 7 input pin
General-purpose I/O port
A/D converter analog 8 input pin
General-purpose I/O port
A/D converter analog 9 input pin
General-purpose I/O port
A/D converter analog 10 input pin
General-purpose I/O port
A/D converter analog 11 input pin
General-purpose I/O port
A/D converter analog 12 input pin
21
D a t a S h e e t
Pin Number
208 pin
176 pin
178
150
179
151
180
152
185
157
186
158
187
159
188
160
Pin Name
P213
AN13
P214
AN14
P215
AN15
P216
AN16
P217
AN17
P218
AN18
P219
AN19
I/O Circuit
Type
F
F
F
F
F
F
F
P220
189
190
161
162
AN20
F
196
167
168
AN21
F
169
AN22
170
171
AN23
172
P224
AN24
CONFIDENTIAL
A/D converter analog 21 input pin
A/D converter analog 22 input pin
A/D converter analog 23 input pin
Base timer ch.7 TIOB input pin
F
General-purpose I/O port
A/D converter Analog 24 input pin
P225
General-purpose I/O port
AN25
A/D converter analog 25 input pin
SIN4
F
Multi-function serial interface ch.4 serial data input pin
INT7 external interrupt input pin
P226
General-purpose I/O port
AN26
A/D converter analog 26 input pin
SOT4
F
Multi-function serial interface ch.4 serial data output pin
16-bit input capture ch.0 external pulse input pin
P227
General-purpose I/O port
AN27
A/D converter analog 27 input pin
SCK4
F
Multi-function serial interface ch.4 clock I/O pin
16-bit input capture ch.1 external pulse input pin
P228
General-purpose I/O port
AN28
A/D converter analog 28 input pin
SCS40
F
Multi-function serial interface ch.4 serial chip select 0 I/O pin
16-bit input capture ch.2 external pulse input pin
P229
General-purpose I/O port
AN29
A/D converter analog 29 input pin
SCS41
IN3
22
A/D converter analog 20 input pin
General-purpose I/O port
F
IN2
200
General-purpose I/O port
A/D converter analog 19 input pin
Base timer ch.7 TIOA I/O pin
IN1
199
General-purpose I/O port
A/D converter analog 18 input pin
General-purpose I/O port
F
IN0
198
General-purpose I/O port
A/D converter analog 17 input pin
Base timer ch.6 TIOB input pin
INT7
197
General-purpose I/O port
A/D converter analog 16 input pin
General-purpose I/O port
TIOB7
195
A/D converter analog 15 input pin
Base timer ch.6 TIOA output pin
P223
164
General-purpose I/O port
P221
TIOA7
192
General-purpose I/O port
A/D converter analog 14 input pin
TIOA6
P222
163
General-purpose I/O port
A/D converter analog 13 input pin
General-purpose I/O port
TIOB6
191
Functions
F
Multi-function serial interface ch.4 serial chip select 1 I/O pin
16-bit input capture ch.3 external pulse input pin
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
208 pin
201
176 pin
173
Pin Name
I/O Circuit
Type
P230
General-purpose I/O port
AN30
A/D converter analog 30 input pin
SCS42
F
IN4
202
174
175
P231
General-purpose I/O port
AN31
A/D converter analog 31 input pin
SCS43
F
P300
ADTG0
-
TIOA10
E
TIOB10
TIOA11
General-purpose I/O port
E
FRCK6
Base timer ch.11 TIOA I/O pin
16-bit free-run timer ch.6 external clock input pin
P304
TIOB11
Base timer ch.10 TIOB input pin
16-bit free-run timer ch.5 external clock input pin
P303
-
Base timer ch.10 TIOA output pin
General-purpose I/O port
E
FRCK5
206
A/D converter external trigger input pin
16-bit free-run timer ch.4 external clock input pin
P302
-
General-purpose I/O port
General-purpose I/O port
E
FRCK4
205
Multi-function serial interface ch.4 serial chip select 3 I/O pin
16-bit input capture ch.5 external pulse input pin
P301
204
Multi-function serial interface ch.4 serial chip select 2 I/O pin
16-bit input capture ch.4 external pulse input pin
IN5
203
Functions
General-purpose I/O port
207
-
E
18
14
AVRH0
19
15
AVRL0
-
4ch sample-hold A/D converter unit0 lower limit reference voltage
20
16
AVR0
-
4ch sample-hold A/D converter unit0 reference voltage
21
17
AVSS0
-
4ch sample-hold A/D converter unit0 analog GND
22
18
AVCC0
-
4ch sample-hold A/D converter unit0 analog power supply
134
115
AVCC1
-
4ch sample-hold A/D converter unit1 analog power supply
135
116
AVSS1
-
4ch sample-hold A/D converter unit1 analog GND
136
117
AVR1
-
4ch sample-hold A/D converter unit1 reference voltage
137
118
AVRL1
-
4ch sample-hold A/D converter unit1 lower limit reference voltage
138
119
AVRH1
-
4ch sample-hold A/D converter unit1 upper limit reference voltage
38
34
RVRH0
-
R/D converter unit0 upper limit reference voltage
39
35
RVRL0
-
R/D converter unit0 lower limit reference voltage
40
36
RVR0
-
R/D converter unit0 reference voltage
41
37
RVSS0
-
R/D converter unit0 analog GND
R/D converter unit0 analog power supply
FRCK7
Base timer ch.11 TIOB input pin
16-bit free-run timer ch.7 external clock input pin
-
4ch sample-hold A/D converter unit0 upper limit reference voltage
42
38
RVCC0
-
114
95
RVCC1
-
R/D converter unit1 analog power supply
115
96
RVSS1
-
R/D converter unit1 analog GND
116
97
RVR1
-
R/D converter unit1 reference voltage
117
98
RVRL1
-
R/D converter unit1 lower limit reference voltage
118
99
RVRH1
-
R/D converter unit1 upper limit reference voltage
181
153
AVCC2
-
A/D converter analog power supply
182
154
AVSS2
-
A/D converter analog GND
183
155
AVRL2
-
A/D converter lower limit reference voltage
184
156
AVRH2
-
A/D converter upper limit reference voltage
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
23
D a t a S h e e t
Pin Number
208 pin
176 pin
2
54
68
103
155
172
193
Pin Name
I/O Circuit
Type
Functions
2
56
87
131
VCC12
-
1.2V power supply
VCC5
-
5.0V power supply
VSS
-
GND
144
165
12
52
44
105
89
144
133
157
176
208
1
13
1
53
45
69
57
83
71
104
88
143
132
156
143
171
166
194
24
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
Part Number without RDC
208pin
176pin
3
-
4
-
5
3
Pin Name
I/O Circuit
Type
P305
FRCK0
P306
FRCK1
E
E
P000
DTTI0
6
4
7
5
8
6
9
7
10
8
11
9
14
10
15
11
16
12
17
13
23
19
24
20
RTO0
P002
RTO1
P003
RTO2
P004
RTO3
P005
RTO4
P006
RTO5
P007
4AN0
P008
4AN1
P009
4AN2
P010
4AN3
P011
ZIN0
P012
BIN0
P013
General-purpose I/O port
16-bit free-run timer ch.0 external clock input pin
General-purpose I/O port
16-bit free-run timer ch.1 external clock input pin
General-purpose I/O port
E
4ADTG0
P001
Functions
Waveform generator output stop signal input pin 0
4ch sample-hold A/D converter unit0 external trigger input pin
E
E
E
E
E
E
F
F
F
F
E
E
Waveform generator ch.0 output pin
General-purpose I/O port
Waveform generator ch.1 output pin
General-purpose I/O port
Waveform generator ch.2 output pin
General-purpose I/O port
Waveform generator ch.3 output pin
General-purpose I/O port
Waveform generator ch.4 output pin
General-purpose I/O port
Waveform generator ch.5 output pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 0 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 1 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 2 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit0 analog 3 input pin
General-purpose I/O port
Up/Down counter ch.0 ZIN input pin
General-purpose I/O port
Up/Down counter ch.0 BIN input pin
General-purpose I/O port
25
21
26
22
27
23
28
24
29
25
P017
E
General-purpose I/O port
30
26
P018
E
General-purpose I/O port
31
27
P019
E
General-purpose I/O port
32
28
P020
E
General-purpose I/O port
33
29
P021
E
General-purpose I/O port
34
30
P022
E
General-purpose I/O port
35
31
P023
E
General-purpose I/O port
36
32
P024
E
General-purpose I/O port
37
33
P025
E
General-purpose I/O port
43
39
P026
E
General-purpose I/O port
AIN0
P014
ZIN1
P015
BIN1
P016
AIN1
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
E
General-purpose I/O port
E
E
E
Up/Down counter ch.0 AIN input pin
General-purpose I/O port
Up/Down counter ch.1 ZIN input pin
General-purpose I/O port
Up/Down counter ch.1 BIN input pin
General-purpose I/O port
Up/Down counter ch.1 AIN input pin
25
D a t a S h e e t
Pin Number
Pin Name
I/O Circuit
Type
Functions
208pin
176pin
44
40
P027
E
General-purpose I/O port
45
41
P028
E
General-purpose I/O port
46
42
47
43
P029
DAOUT0
P430
ERDS0
G
E
P030
48
-
DTTI2
RTO12
RTO13
General-purpose I/O port
E
FRCK14
-
RTO14
General-purpose I/O port
E
FRCK15
-
56
-
RTO15
General-purpose I/O port
E
-
16-bit free-run timer ch.16 external clock input pin
P312
General-purpose I/O port
RTO16
E
P313
RTO17
46
DTTI3
E
RTO18
RTO19
General-purpose I/O port
E
TIOA1
62
63
64
49
50
51
52
RTO20
CONFIDENTIAL
General-purpose I/O port
E
Waveform generator ch.20 output pin
TIOB1
Base timer ch.1 TIOB input pin
P318
General-purpose I/O port
RTO21
E
Waveform generator ch.21 output pin
TIOA2
Base timer ch.2 TIOA output pin
P319
General-purpose I/O port
RTO22
E
Waveform generator ch.22 output pin
TIOB2
Base timer ch.2 TIOB input pin
P320
General-purpose I/O port
RTO23
TIOA3
26
Waveform generator ch.19 output pin
Base timer ch.1 TIOA I/O pin
P317
61
Waveform generator ch.18 output pin
Base timer ch.0 TIOB input pin
P316
48
Waveform generator output stop signal input pin 3
General-purpose I/O port
E
TIOB0
60
Waveform generator ch.17 output pin
Base timer ch.0 TIOA output pin
P315
47
General-purpose I/O port
General-purpose I/O port
E
TIOA0
59
Waveform generator ch.16 output pin
16-bit free-run timer ch.17 external clock input pin
P314
58
Waveform generator ch.15 output pin
FRCK16
FRCK17
57
Waveform generator ch.14 output pin
16-bit free-run timer ch.15 external clock input pin
P311
55
Waveform generator ch.13 output pin
16-bit free-run timer ch.14 external clock input pin
P310
51
Waveform generator ch.12 output pin
16-bit free-run timer ch.13 external clock input pin
P309
-
Waveform generator output stop signal input pin 2
General-purpose I/O port
E
FRCK13
50
Error detection output pin ch.0
16-bit free-run timer ch.12 external clock input pin
P031
-
General-purpose I/O port
General-purpose I/O port
E
FRCK12
49
General-purpose I/O port
D/A converter ch.0 analog output pin
E
Waveform generator ch.23 output pin
Base timer ch.3 TIOA I/O pin
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
208pin
65
176pin
53
Pin Name
I/O Circuit
Type
P321
General-purpose I/O port
SIN0
Multi-function serial interface ch.0 serial data input pin
INT3
E
TIOB3
66
67
54
55
P322
SOT0
P323
SCK0
58
STOPWT
IN6
E
E
59
E
60
61
62
63
16-bit input capture ch.6 external pulse input pin
General-purpose I/O port
FlexRay ch.A data input pin
IN7
H
16-bit input capture ch.7 external pulse input pin
32-bit input capture ch.1 external pulse input pin
P326
General-purpose I/O port
TXDA
FlexRay ch.A data output pin
IN8
H
16-bit input capture ch.8 external pulse input pin
32-bit input capture ch.2 external pulse input pin
P327
General-purpose I/O port
TXENA
FlexRay ch.A operation enable output pin
IN9
H
16-bit input capture ch.9 external pulse input pin
32-bit input capture ch.3 external pulse input pin
P328
General-purpose I/O port
RXDB
FlexRay ch.B data input pin
IN10
H
IN20
75
FlexRay stop watch input pin
RXDA
IN19
74
General-purpose I/O port
Multi-function serial interface ch.0 clock I/O pin
P325
IN18
73
Multi-function serial interface ch.0 serial data output pin
32-bit input capture ch.0 external pulse input pin
IN17
72
General-purpose I/O port
General-purpose I/O port
IN16
71
INT3 external interrupt input pin
Base timer ch.3 TIOB input pin
P324
70
Functions
16-bit input capture ch.10 external pulse input pin
32-bit input capture ch.4 external pulse input pin
P329
General-purpose I/O port
TXDB
FlexRay ch.B data output pin
IN11
H
IN21
32-bit input capture ch.5 external pulse input pin
P330
TXENB
16-bit input capture ch.11 external pulse input pin
General-purpose I/O port
76
64
H
77
65
NMIX
78
66
RSTX
B
External reset input pin
79
67
MD1
C
Mode pin 1 (with high-voltage control)
80
68
MD0
C
Mode pin 0 (with high-voltage control)
81
69
X0
82
70
X1
84
72
TRSTX
J
JTAG test reset input
85
73
TCK
J
JTAG test clock input
86
74
TDO
I
JTAG test data output
87
75
TDI
J
JTAG test data input
88
76
TMS
J
JTAG test mode status input
89
77
nSRST
J
System reset input for debugger
90
78
E
Multi-function serial interface ch.1 serial data input pin
IN12
16-bit input capture ch.12 external pulse input pin
B
A
P406
SIN1
INT4
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
FlexRay ch.B operation enable output pin
Non-maskable interrupt input pin
Main clock oscillation input pin
Main clock oscillation output pin
General-purpose I/O port
INT4 external interrupt input pin
27
D a t a S h e e t
Pin Number
208pin
176pin
91
79
92
80
Pin Name
P407
SOT1
P408
SCK1
I/O Circuit
Type
E
E
P409
93
81
RX0
94
82
95
83
TX0
E
E
84
P412
TX1
85
RX2
E
98
86
99
-
100
-
101
-
102
-
TX2
P415
TIOA4
P416
TIOB4
P417
TIOA5
P418
TIOB5
E
-
SIN2
E
E
E
E
E
107
-
108
-
109
90
110
91
SOT2
P131
SCK2
P431
ERDS1
P129
DAOUT1
CAN ch.2 reception data input pin
General-purpose I/O port
CAN ch.2 transmission data output pin
General-purpose I/O port
Base timer ch.4 TIOA output pin
General-purpose I/O port
Base timer ch.4 TIOB input pin
General-purpose I/O port
Base timer ch.5 TIOA I/O pin
General-purpose I/O port
Base timer ch.5 TIOB input pin
General-purpose I/O port
E
INT5
P420
General-purpose I/O port
CAN ch.1 transmission data output pin
INT2 external interrupt input pin
P419
106
CAN ch.1 reception data input pin
General-purpose I/O port
INT2
P414
General-purpose I/O port
CAN ch.0 transmission data output pin
INT1 external interrupt input pin
P413
97
CAN ch.0 reception data input pin
General-purpose I/O port
E
INT1
96
General-purpose I/O port
Multi-function serial interface ch.1 clock I/O pin
INT0 external interrupt input pin
P411
RX1
General-purpose I/O port
Multi-function serial interface ch.1 serial data output pin
General-purpose I/O port
INT0
P410
Functions
Multi-function serial interface ch.2 serial data input pin
INT5 external interrupt input pin
E
E
E
G
General-purpose I/O port
Multi-function serial interface ch.2 serial data output pin
General-purpose I/O port
Multi-function serial interface ch.2 clock I/O pin
General-purpose I/O port
Error detection output pin ch.1
General-purpose I/O port
D/A converter ch.1 analog output pin
111
92
P128
E
General-purpose I/O port
112
93
P127
E
General-purpose I/O port
113
94
P126
E
General-purpose I/O port
119
100
P125
E
General-purpose I/O port
120
101
P124
E
General-purpose I/O port
121
102
P123
E
General-purpose I/O port
122
103
P122
E
General-purpose I/O port
123
104
P121
E
General-purpose I/O port
124
105
P120
E
General-purpose I/O port
125
106
P119
E
General-purpose I/O port
126
107
P118
E
General-purpose I/O port
127
108
P117
E
General-purpose I/O port
28
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
208pin
176pin
128
109
129
110
130
111
131
112
132
113
133
114
139
120
140
121
141
122
142
123
145
124
146
125
147
126
148
127
149
128
150
129
Pin Name
I/O Circuit
Type
P116
AIN3
P115
BIN3
P114
ZIN3
P113
AIN2
P112
BIN2
P111
ZIN2
P110
4AN7
P109
4AN6
P108
4AN5
P107
4AN4
P106
RTO11
P105
RTO10
P104
RTO9
P103
RTO8
P102
RTO7
P101
RTO6
E
E
E
E
E
E
F
F
F
F
E
E
E
E
E
E
P100
151
130
DTTI1
-
-
-
-
General-purpose I/O port
Up/Down counter ch.2 AIN input pin
General-purpose I/O port
Up/Down counter ch.2 BIN input pin
General-purpose I/O port
Up/Down counter ch.2 ZIN input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 7 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 6 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 5 input pin
General-purpose I/O port
4ch sample-hold A/D converter unit1 analog 4 input pin
General-purpose I/O port
Waveform generator ch.11 output pin
General-purpose I/O port
Waveform generator ch.10 output pin
General-purpose I/O port
Waveform generator ch.9 output pin
General-purpose I/O port
Waveform generator ch.8 output pin
General-purpose I/O port
Waveform generator ch.7 output pin
General-purpose I/O port
Waveform generator ch.6 output pin
Waveform generator output stop signal input pin 1
General-purpose I/O port
Multi-function serial interface ch.3 serial data input pin
INT6
E
INT6 external interrupt input pin
16-bit free-run timer ch.8 external clock input pin
P422
General-purpose I/O port
SOT3
Multi -function serial interface ch.3 serial data output pin
FRCK9
E
16-bit free-run timer ch.9 external clock input pin
16-bit input capture ch.13 external pulse input pin
P423
General-purpose I/O port
SCK3
Multi-function serial interface ch.3 clock I/O pin
FRCK10
P425
TIOA8
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
Up/Down counter ch.3 ZIN input pin
SIN3
E
IN14
158
General-purpose I/O port
4ch sample-hold A/D converter unit1 external trigger input pin
IN13
154
General-purpose I/O port
Up/Down counter ch.3 BIN input pin
P421
FRCK8
153
General-purpose I/O port
Up/Down counter ch.3 AIN input pin
General-purpose I/O port
E
4ADTG1
152
Functions
16-bit free-run timer ch.10 external clock input pin
16-bit input capture ch.14 external pulse input pin
E
General-purpose I/O port
Base timer ch.8 TIOA output pin
29
D a t a S h e e t
Pin Number
208pin
176pin
159
-
160
-
161
-
Pin Name
P426
TIOB8
P427
TIOA9
P428
TIOB9
I/O Circuit
Type
E
E
E
P429
162
134
MONCLK
135
164
136
165
137
166
138
167
139
168
140
169
141
170
142
173
145
174
146
175
147
176
148
177
149
178
150
179
151
180
152
185
157
186
158
187
159
188
160
30
CONFIDENTIAL
P200
AN0
P201
AN1
P202
AN2
P203
AN3
P204
AN4
P205
AN5
P206
AN6
P207
AN7
P208
AN8
P209
AN9
P210
AN10
P211
AN11
P212
AN12
P213
AN13
P214
AN14
P215
AN15
P216
AN16
P217
AN17
P218
AN18
P219
AN19
General-purpose I/O port
Base timer ch.8 TIOB input pin
General-purpose I/O port
Base timer ch.9 TIOA I/O pin
General-purpose I/O port
Base timer ch.9 TIOB input pin
General-purpose I/O port
E
MM
163
Functions
Clock monitor output pin
Clock supervisor main clock error detection output pin
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
General-purpose I/O port
A/D converter analog 0 input pin
General-purpose I/O port
A/D converter analog 1 input pin
General-purpose I/O port
A/D converter analog 2 input pin
General-purpose I/O port
A/D converter analog 3 input pin
General-purpose I/O port
A/D converter analog 4 input pin
General-purpose I/O port
A/D converter analog 5 input pin
General-purpose I/O port
A/D converter analog 6 input pin
General-purpose I/O port
A/D converter analog 7 input pin
General-purpose I/O port
A/D converter analog 8 input pin
General-purpose I/O port
A/D converter analog 9 input pin
General-purpose I/O port
A/D converter analog 10 input pin
General-purpose I/O port
A/D converter analog 11 input pin
General-purpose I/O port
A/D converter analog 12 input pin
General-purpose I/O port
A/D converter analog 13 input pin
General-purpose I/O port
A/D converter analog 14 input pin
General-purpose I/O port
A/D converter analog 15 input pin
General-purpose I/O port
A/D converter analog 16 input pin
General-purpose I/O port
A/D converter analog 17 input pin
General-purpose I/O port
A/D converter analog 18 input pin
General-purpose I/O port
A/D converter analog 19 input pin
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
208pin
176pin
189
161
Pin Name
I/O Circuit
Type
P220
AN20
General-purpose I/O port
F
TIOA6
162
AN21
General-purpose I/O port
F
TIOB6
163
AN22
General-purpose I/O port
F
TIOA7
164
AN23
General-purpose I/O port
F
TIOB7
195
196
197
198
167
168
169
170
P224
AN24
171
F
172
General-purpose I/O port
AN25
A/D converter analog 25 input pin
SIN4
F
173
INT7 external interrupt input pin
P226
General-purpose I/O port
AN26
SOT4
F
174
175
204
-
16-bit input capture ch.0 external pulse input pin
General-purpose I/O port
AN27
SCK4
F
General-purpose I/O port
AN28
A/D converter analog 28 input pin
SCS40
F
Multi-function serial interface ch.4 serial chip select 0 I/O pin
16-bit input capture ch.2 external pulse input pin
P229
General-purpose I/O port
AN29
A/D converter analog 29 input pin
SCS41
F
Multi-function serial interface ch.4 serial chip select 1 I/O pin
16-bit input capture ch.3 external pulse input pin
P230
General-purpose I/O port
AN30
A/D converter analog 30 input pin
SCS42
F
Multi-function serial interface ch.4 serial chip select 2 I/O pin
16-bit input capture ch.4 external pulse input pin
P231
General-purpose I/O port
AN31
A/D converter analog 31 input pin
SCS43
F
P300
ADTG0
TIOA10
TIOB10
FRCK5
May 15, 2015, MB9D560_DS708-00001-3v0-E
Multi-function serial interface ch.4 serial chip select 3 I/O pin
16-bit input capture ch.5 external pulse input pin
E
General-purpose I/O port
A/D converter external trigger input pin
General-purpose I/O port
E
Base timer ch.10 TIOA output pin
16-bit free-run timer ch.4 external clock input pin
P302
CONFIDENTIAL
Multi-function serial interface ch.4 clock I/O pin
P228
FRCK4
-
A/D converter analog 27 input pin
16-bit input capture ch.1 external pulse input pin
P301
205
Multi-function serial interface ch.4 serial data output pin
P227
IN5
203
A/D converter analog 26 input pin
IN0
IN4
202
Multi-function serial interface ch.4 serial data input pin
INT7
IN3
201
General-purpose I/O port
A/D converter analog 24 input pin
P225
IN2
200
A/D converter analog 23 input pin
Base timer ch.7 TIOB input pin
IN1
199
A/D converter analog 22 input pin
Base timer ch.7 TIOA I/O pin
P223
192
A/D converter analog 21 input pin
Base timer ch.6 TIOB input pin
P222
191
A/D converter analog 20 input pin
Base timer ch.6 TIOA output pin
P221
190
Functions
General-purpose I/O port
E
Base timer ch.10 TIOB input pin
16-bit free-run timer ch.5 external clock input pin
31
D a t a S h e e t
Pin Number
208pin
176pin
206
-
Pin Name
I/O Circuit
Type
P303
TIOA11
General-purpose I/O port
E
FRCK6
Base timer ch.11 TIOA I/O pin
16-bit free-run timer ch.6 external clock input pin
P304
TIOB11
Functions
General-purpose I/O port
207
-
E
18
14
AVRH0
-
4ch sample-hold A/D converter unit0 upper limit reference voltage
19
15
AVRL0
-
4ch sample-hold A/D converter unit0 lower limit reference voltage
20
16
AVR0
-
4ch sample-hold A/D converter unit0 reference voltage
21
17
AVSS0
-
4ch sample-hold A/D converter unit0 analog GND
22
18
AVCC0
-
4ch sample-hold A/D converter unit0 analog power supply
134
115
AVCC1
-
4ch sample-hold A/D converter unit1 analog power supply
135
116
AVSS1
-
4ch sample-hold A/D converter unit1 analog GND
136
117
AVR1
-
4ch sample-hold A/D converter unit1 reference voltage
137
118
AVRL1
-
4ch sample-hold A/D converter unit1 lower limit reference voltage
138
119
AVRH1
-
4ch sample-hold A/D converter unit1 upper limit reference voltage
38
34
RVRH0
-
*1
39
35
RVRL0
-
*2
40
36
RVR0
-
*2
41
37
RVSS0
-
*2
42
38
RVCC0
-
*1
114
95
RVCC1
-
*1
115
96
RVSS1
-
*2
116
97
RVR1
-
*2
117
98
RVRL1
-
*2
118
99
RVRH1
-
*1
181
153
AVCC2
-
A/D converter analog power supply
182
154
AVSS2
-
A/D converter analog GND
183
155
AVRL2
-
A/D converter lower limit reference voltage
184
156
AVRH2
-
A/D converter upper limit reference voltage
VCC12
-
1.2V power supply
VCC5
-
5.0V power supply
FRCK7
2
54
68
103
155
172
193
Base timer ch.11 TIOB input pin
16-bit free-run timer ch.7 external clock input pin
2
56
87
131
144
165
12
52
44
105
89
144
133
157
176
208
32
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MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Number
208pin
176pin
Pin Name
I/O Circuit
Type
Functions
1
13
1
53
45
69
57
83
71
104
88
143
132
156
143
171
166
VSS
-
GND
194
*1: The part number without RDC does not use this pin. Connect it with the VCC5 pin.
*2: The part number without RDC does not use this pin. Connect it with the VSS pin.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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33
D a t a S h e e t
6. I/O Circuit Type
Type
Circuit
Remarks
X1
Clock input
A
X0
−
Oscillation feedback resistor: Approx. 1 MΩ
−
CMOS hysteresis input
−
With 50 kΩ pull-up resistor
Standby control signal
Pull-up resistor
B
CMOS hysteresis input
Mode input
N-ch
High withstand voltage mode input
N-ch
C
High withstand voltage control
N-ch
−
Schmitt input
−
With high withstand voltage control
−
CMOS level output
N-ch
P-ch
Digital output
D
IOH=-1/-2 mA, IOL=1/2 mA
N-ch
Pull-up control
P-ch
P-ch
Digital output
N-ch
−
General-purpose I/O port
−
CMOS level output
−
With 50 kΩ pull-up resistor
−
CMOS hysteresis input (0.7Vcc/0.3Vcc)
−
Automotive input (0.8Vcc/0.5Vcc)
IOH=-1/-2 mA, IOL=1/2 mA
E
R
CMOS hysteresis input
Automotive input
Standby control
34
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Type
Circuit
Remarks
Pull-up control
P-ch
P-ch
Digital output
N-ch
F
−
With Analog input, General-purpose I/O port
−
CMOS level output
−
With 50 kΩ pull-up resistor
−
CMOS hysteresis input (0.7Vcc/0.3Vcc)
IOH=-1/-2 mA, IOL=1/2 mA
During standby, the input value retains the
R
previous value.
CMOS hysteresis input
−
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value retains the
Automotive input
previous value.
Standby control
Analog input
Pull-up control
P-ch
P-ch
−
With Analog output , General-purpose I/O
−
CMOS level output
port
Digital output
N-ch
IOH=-1/-2 mA, IOL=1/2 mA
G
R
−
With 50 kΩ pull-up resistor
−
CMOS hysteresis input (0.7Vcc/0.3Vcc)
During standby, the input value retains the
CMOS hysteresis input
previous value.
−
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value retains the
Automotive input
previous value.
Standby control
Analog output
Pull-up control
P-ch
P-ch
Digital output
N-ch
H
−
General-purpose I/O port
−
CMOS level output
IOH=-1/-2/-4 mA, IOL=1/2/4 mA
−
With 50 kΩ pull-up resistor
−
FlexRay input (0.7Vcc/0.3Vcc)
During standby, the input value retains the
previous value.
R
FlexRay input
−
Automotive input (0.8Vcc/0.5Vcc)
During standby, the input value retains the
Automotive input
previous value.
Standby control
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
35
D a t a S h e e t
Type
Circuit
Remarks
P-ch
Digital output
I
−
IOH=-5 mA, IOL=5 mA
N-ch
J
36
CONFIDENTIAL
TTL hysteresis input
CMOS level output
−
TTL hysteresis input (2V/0.8V)
K
Analog input
−
Analog input
L
Analog output
−
Analog output
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
7. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
7.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device.
Try to prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage
the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of
operation. Such pins should be connected through an appropriate resistance to a power supply
pin or ground pin.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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37
D a t a S h e e t
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office
automation and other office equipment, industrial, communications, and measurement equipment, personal
or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely
high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with
sales representatives before such use. The company will not be responsible for damages arising from such
use without prior approval.
7.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under Spansion’s recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board
and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering
process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage
temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
38
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results
in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To
prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the
product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and
at temperatures between 5 ˚C and 30 ˚C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125 ˚C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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39
D a t a S h e e t
7.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If
high humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause
abnormal operation. In such cases, use anti-static measures or processing to prevent
discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic
radiation. Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near
combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic
gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
40
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
8. Handling Devices
For Latch-up Prevention
If a voltage higher than VCC5 or VCC12, or a voltage lower than VSS is applied to an I/O pin, or if a voltage
exceeding the ratings is applied between VCC5 to VSS and VCC12 to VSS pins, a latch-up may occur in
CMOS IC. If the latch-up occurs, the power supply current increases excessively and device elements may
be damaged by heat. Take care to prevent any voltage from exceeding the maximum ratings in device
application.
Also, the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1,
RVRH0, RVEH1) and analog input must not exceed the digital power supply (VCC5) when the power supply
to the analog system is turned on or off.
In the correct power-on sequence, turn on the digital power supply voltage (VCC5, VCC12) and analog
power supply voltages (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1, RVRH0,
RVRH1) simultaneously. Alternatively, turn on the digital power supply voltage (VCC5) first, and then turn on
the analog power supplies (AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, RVCC0, RVCC1,
RVRH0, RVRH1).
Treatment of Unused Pins
If unused input pins are left open, they may cause a permanent damage to the device due to device
malfunction or latch-up. Connect a 2 kΩ or higher resistor to each of unused input pins for pull-up or
pull-down processing.
Also, if I/O pins are not used, they must be set to the output state for releasing or they must be set to the
input state and treated in the same way as for the input pins.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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41
D a t a S h e e t
Power Supply Pins
The device is designed to ensure that if the device contains multiple VCC5, VCC12 and VSS pins, the pins
that should be at the same potential are interconnected to prevent latch-up or other malfunctions.
Further, connect these pins to an external power supply or ground to reduce unwanted radiation, prevent
strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard,
etc. As shown below, all VSS power supply pins must be treated in the similar way. If multiple VCC5 or
VCC12 or VSS systems are connected, the device cannot operate correctly even within the guaranteed
operating range.
Power Supply Input Pin
VCC
VDD
VSS
VCC5
VSS
VCC12
VSS
VCC5
VCC5
VCC12
VCC12
VSS
VCC12
VCC5
VSS
The power supply pins should be connected to VCC5, VCC12 and VSS of this device at the low impedance
from the power supply source.
In the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of C pin
is recommended to use as a bypass capacitor between VCC5, VCC12 and VSS pins
Crystal Oscillation Circuit
An external noise to the X0 or X1 pin may cause a device malfunction. The printed circuit board must be
designed to lay out X0 and X1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be
grounded to the close position to the device.
The printed circuit board artwork is recommended to surround the X0 and X1 pins by ground circuits.
Mode Pin (MD1, MD0)
Connect the MD1, MD0 mode pin to the VCC5 or VSS pin directly. To prevent an erroneous selection of test
mode caused by the noise, reduce the pattern length between each mode pin and VCC5 or VSS pin on the
printed circuit board. Also, use the low-impedance pin connection.
Notes during PLL Clock Operation
When the PLL clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may
continue to operate at the free running frequency of the self oscillator circuit built in the PLL. This operation
is not guaranteed.
42
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Treatment of R/D Converter and A/D Converter Power Supply Pins
If unuse R/D converter and A/D converter, needs connection as follows.
− AVCC0 = AVCC1= AVCC2 = AVRH0= AVRH1 = AVRH2 = RVCC0 = RVCC1 = RVRH0 =RVRH1 =
VCC5
− AVSS0 = AVSS1 = AVSS2 = AVRL0 = AVRL1 = AVRL2 = AVR0 = AVR1 = RVSS0 = RVSS1 =
RVRL0 = RVRL1 = RVR0 = RVR1 = VSS
Note on Using External Clock
The external clock is unsupported.
External direct clock input cannot use.
Power-on Sequence of R/D Converter and A/D Converter Power Supply Analog Inputs
Be sure to turn on the digital power supply (VCC5, VCC12) first, and then turn on the R/D converter and A/D
*1
*2
converter power supplies and analog inputs . Also, turn off the R/D converter and A/D converter power
*1
*2
supplies and analog inputs first, and then turn off the digital power supply (VCC5, VCC12).
When the AVRH0, AVRH1, AVRH2, RVRH0 and RVRH1 pin voltages are turned on or off, they must not
exceed AVCC0, AVCC1, AVCC2, RVCC0 and RVCC1. Even if a common analog input pin is used as an
input port, its input voltage must not exceed AVCC0, AVCC1 or AVCC2. (However, the analog power supply
voltage and digital power supply voltage can be turned on or off simultaneously.)
*1: AVCC0, AVCC1, AVCC2, AVRH0, AVRH1, AVRH2, AVRL0, AVRL1, AVRL2, RVCC0, RVCC1, RVRH0,
RVRH1, RVRL0, RVRL1
*2: MAG_PLUS0, MAG_MINUS0, COS_PLUS0, COS_MINUS0, SIN_PLUS0, SIN_MINUS0, COS_IN0,
SIN_IN0, MAG_PLUS1, MAG_MINUS1, COS_PLUS1, COS_MINUS1, SIN_PLUS1, SIN_MINUS1,
COS_IN1, SIN_IN1, 4AN0 to 4AN7, AN0 to AN31
Notes When Writing Data in a Register Having the Status Flag
When writing data in the register that has a status flag (especially, an interrupt request flag) to control
function, take care not to clear its status flag erroneously. The program must be written not to clear the flag
to the status bit, and to set the control bits to have the desired value.
Especially, if multiple control bits are used, the bit instruction cannot be used. (The bit instruction can
access to a single bit only.) The Byte, Half-word, or Word access must be used to write data in the control
bits and status flag simultaneously. During this time, take care not to clear other bits (in this case, the bits of
status flag) erroneously.
Note:
−
These points can be ignored because the bit instructions already take the points into consideration
for registers that are supported by bit-band unit. These points must be considered when using the bit
instruction for registers that are not supported by bit-band unit.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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43
D a t a S h e e t
9. Block Diagram
Debug I/F
(JTAG)
JTAG_SWCLKTCK
JTAG Wakeup
Debug Group
(CoreSightTM)
DAP
Security
Security
APB-M
APB-M
APB-S
APB-S
AHB-M
AHB-M
CLK_DBG
Debug APB
AHB2APB
(Priviledge
Protection)
APB-32
Trace Group
CLK_PERI0
CLK_ATB
AHB-32
ATB
ATB
CLK_ATB
Core Group (2-Core)
Security
Checker
ETB (Trace Buffer)
Debug APB
ETM
#1
ETM
#0
DMAC
(ch.0 to 15)
Processor
CLK_CPU1
CLK_CPU0
CPU #1
TCRAM #1
B0TCM
B1TCM
#1
TCFLASH
#1
Security
CPU #0
CortexTM -R5F
CortexTM -R5F
MPU
#1
I$
#1
ATCM
#1
LLPP(AXI32-M) AXI-S
D$
#1
MPU
#0
I$
#0
D$
#0
AHB-64
B1TCM
#0
CLK_DMA
AHB-32
CLK_PERI0
TCFLASH
Security
#0
ATCM
#0
AXI-M AXI-S LLPP(AXI32-M)
AXI-M
AHB-M
TCRAM #0
B0TCM
AXI2AHB
AHB2AXI
MPU AHB
Exclusive
Access Memory
(EAM)
AHB2AXI
AXI-S
High Performance Matrix (HPM)
AXI-64
AXI2AHB
AXI2AHB
CLK_HPM
AXI2AHB
AXI2AHB
AXI2AHB
AHB-32
CLK_PERI5
BBU
Mode control
AHB-32
CLK_SYSC_PD1
Security
BBU
AHB-64
CLK_MEMC
BBU
CAN
(ch.0 to 2)
Security
RST manage
Protection
MPU AHB
(Config, Slave)
CAN
Prescaler
DMAC
(Config, Slave)
PONR
TPU#0
State
CR
Calibration
Port Pin Config
(Config, Slave)
CRC
(ch.0 to 1)
CSV
TPU#1
Fast-CR
Resource Input Config
(Config, Slave)
GPIO
Slow-CR
LVD
IRC #0
PLL
Wakeup
detect
RAM
AHB2APB
IRC #1
Clock output
APB-32
RAM
CLK_PERI1
NMI
distribution
HW-WDT
IPCU
SW-WDT #0
Wakeup
Request #0
MFS
(ch.0 to 4)
AHB2RBus
RDC
(unit 0)
RDC
(unit 1)
DAC
(ch.0)
DAC
(ch.1)
WFG
(unit0, ch.0 to 5)
WFG
(unit1, ch.6 to 11)
16-bit OCU
(unit0 to 2, ch.0 to 5)
16-bit OCU
(unit3 to 5, ch.6 to 11)
4ch-SH ADC
(unit0, ch.0 to 3)
4ch-SH ADC
(unit1, ch.4 to 7)
MVA (unit 0)
MVA (unit 1)
16-bit ICU
(unit0 to 1, ch.0 to 3)
16-bit ICU
(unit2 to 3, ch.4 to 7)
8/16bit UDC
(ch.0 to 1)
8/16bit UDC
(ch.2 to 3)
16-bit FRT for RDC
(ch.18)
16-bit FRT for RDC
(ch.19)
16-bit FRT
(ch.0 to 5)
16-bit FRT
(ch.6 to 11)
CLK_PERI7
AHB2APB
FlexRay/RDC
Clock Control
32-bit ICU
(unit0 to 2, ch.0 to 5)
Clock Monitor
12-bit A/D Converter
(ch.0 to 31)
TCRAM #1
(Config, Slave)
Memory & Config Group
16-bit FRT
(ch.12 to 17)
WFG
(unit2 to 3, ch.12 to 23)
16-bit ICU
(unit4 to 7, ch.8 to 14)
16-bit Base Timer
[PWM/PPG/RLT/PWC]
(ch.0 to 11)
TCFLASH #1
(Config, Slave)
MCU Config Group
CLK_PERI6
16bit OCU
(unit6 to 11, ch.12 to 23)
TCFLASH #0
(Config, Slave)
TCRAM #0
(Config, Slave)
EXT-IRQ
(NMI)
Application Specific
Peripheral Group A
32-bit FRT
(ch.0 to 4)
Wakeup
Request #1
SW-WDT #1
BBU
FlexRay
(A+Bch)
AHB-32
CLK_PERI0
BootROM
Clock
AHB-32
CLK_PERI4
Application Specific
Peripheral Group B
BBU
RAM
WorkFLASH
#1
System Controller
(SYSC)
SCT
WorkFLASH
#0
Common Peripheral Group
Application Specific Peripheral Group
Resource Input
Configuration
PORT MUX (Port Pin Config)
I/O
Note:
−
44
CONFIDENTIAL
In the block diagram, block name (Config, Slave) describe bus connection for register setting of
control block.
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Group
Group Name
Description
Core Group
−
CPU and TCM connected memory group
Debug Group
−
CoreSight of Debugging group
MCU Config Group
−
System control and supervision IP group
Memory & Config Group _
−
CPU related function and memory group
Common Peripheral Group
−
Common peripheral IP group for vehicle application
Application Specific Peripheral Group
−
Product specified peripheral group
Independent IP
Name
Description
−
Bus matrix of AXI
−
Bus bridge (AXI-to-AHB, AHB-to-AXI)
DMAC
−
DMA controller
EAM
−
Exclusive access memory
Resource input configuration
−
Input selection circuit of MCU peripheral
Port MUX
−
Port MUX circuit
I/O
−
I/O circuit
HPM
Note:
−
Each master connects to HPM. Each master has different transaction ID on AXI, Out-Of-Order for
transaction completion.
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
45
D a t a S h e e t
10. Memory Map
Address
Start
Block
End
Overview
Function
64KB: 0x0000_FFFF
0x0000_0000
96KB: 0x0001_7FFF
TCRAM
128KB: 0x0001_FFFF
0x0002_0000
0x0080_0000
0x0090_0000
0x00FE_0000
0x007F_FFFF
Reserved
512KB: 0x0087_FFFF
TCFLASH
768KB: 0x008B_FFFF
large sector area
1024KB: 0x008F_FFFF
(TCM connection)
0x00FD_FFFF
0x00FF_FFFF
Memory
(Each CPU exclusive
space)
512KB: 0x0107_FFFF
0x0100_0000
Reserved
TCFLASH
small sector area
(TCM connection)
TCFLASH
768KB: 0x010B_FFFF
large sector area
1024KB: 0x010F_FFFF
(AXI connection)
0x0110_0000
0x01FD_FFFF
Reserved
0x01FE_0000
0x01FF_FFFF
small sector area
0x0200_0000
0x027F_FFFF
Reserved
TCFLASH
(AXI connection)
0x0280_0000
0x0280_0FFF
EAM
0x0280_1000
0x03FF_FFFF
Reserved
64KB: 0x0400_FFFF
0x0400_0000
96KB: 0x0401_7FFF
CPU0 space TCRAM
128KB: 0x0401_FFFF
0x0402_0000
0x047F_FFFF
Reserved
0x0480_0000
768KB: 0x048B_FFFF
large sector area
1024KB: 0x048F_FFFF
(TCM connection)
512KB: 0x0487_FFFF
CPU0 space TCFLASH
0x0490_0000
0x04FD_FFFF
Reserved
0x04FE_0000
0x04FF_FFFF
small sector area
CPU0 space TCFLASH
512KB: 0x0507_FFFF
0x0500_0000
768KB: 0x050B_FFFF
1024KB: 0x050F_FFFF
Memory
(Common space)
(TCM connection)
CPU0 space TCFLASH
large sector area
(AXI connection)
0x0510_0000
0x05FD_FFFF
Reserved
0x05FE_0000
0x05FF_FFFF
small sector area
CPU0 space TCFLASH
(AXI connection)
64KB: 0x0600_FFFF
0x0600_0000
96KB: 0x0601_7FFF
CPU1 space TCRAM
128KB: 0x0601_FFFF
0x0602_0000
0x067F_FFFF
512KB: 0x0687_FFFF
0x0680_0000
0x0690_0000
46
CONFIDENTIAL
Reserved
CPU1 space TCFLASH
768KB: 0x068B_FFFF
large sector area
1024KB: 0x068F_FFFF
(TCM connection)
0x06FD_FFFF
Reserved
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Address
Block
Start
End
0x06FE_0000
0x06FF_FFFF
Overview
Function
CPU1 space TCFLASH
small sector area
(TCM connection)
512KB: 0x0707_FFFF
0x0700_0000
CPU1 space TCFLASH
768KB: 0x070B_FFFF
large sector area
1024KB: 0x070F_FFFF
(AXI connection)
0x0710_0000
0x07FD_FFFF
Reserved
0x07FE_0000
0x07FF_FFFF
small sector area
CPU1 space TCFLASH
(AXI connection)
0x0800_0000
0x0DFF_FFFF
0x0E00_0000
0x0E00_FFFF
0x0E01_0000
0x0E01_FFFF
0x0E02_0000
0x0E0F_FFFF
0x0E10_0000
0x0E10_FFFF
0x0E11_0000
0x0E11_FFFF
0x0E12_0000
0x0E1F_FFFF
0x0E20_0000
0x0E20_FFFF
0x0E21_0000
0x0E21_FFFF
0x0E22_0000
0x0FFF_FFFF
0x1000_0000
0x9FFF_FFFF
0xA000_0000
0xA1FF_FFFF
0xA200_0000
0xA27F_FFFF
0xA280_0000
0xA2FF_FFFF
0xA300_0000
0xA37F_FFFF
Reserved
WorkFLASH0
Memory
mirror area 1
(Common space)
WorkFLASH1
mirror area 1
Reserved
WorkFLASH0 Reserved
mirror area 2
WorkFLASH1 Reserved
mirror area 2
Reserved
WorkFLASH0
mirror area 3
WorkFLASH1
mirror area 3
Reserved
Reserved
Reserved
Reserved
Bit band alias area
(Memory & Config Group)
Reserved
Bit band alias area
(MCU Config Group)
Bit band alias area
0xA380_0000
0xA47F_FFFF
(Common Peripheral
Bit band alias area
0xA480_0000
0xA7FF_FFFF
0xA800_0000
0xA87F_FFFF
Group)
Reserved
Bit band alias area
(Application Specific
Peripheral Group A)
Bit band alias area
0xA880_0000
0xA8FF_FFFF
(Application Specific
0xA900_0000
0xAFFF_FFFF
Reserved
0xB000_0000
0xBFFF_FFFF
0xC000_0000
0xEFFF_FFFF
Peripheral Group B)
0xF000_0000
0xFFFE_DFFF
0xFFFE_E000
0xFFFE_FFFF
0xFFFF_0000
0xFFFF_FFFF
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
I/O area
(Bit band area)
Reserved
I/O
Reserved
Reserved
BootROM area
Error Config
BootROM
47
D a t a S h e e t
Notes:
−
−
−
−
−
48
CONFIDENTIAL
Each CPU exclusive space define memory space for each CPU specified. The other master cannot
access (Reserved area). If the other master access to each CPU exclusive space, access from
common space.
Reserved area access cause bus error.
However, following access of reserved area will be not bus error.
0x0090_0000 to 0x00FD_FFFF
0x0110_0000 to 0x01FD_FFFF
0x0490_0000 to 0x04FD_FFFF
0x0510_0000 to 0x05FD_FFFF
0x0690_0000 to 0x06FD_FFFF
0x0710_0000 to 0x07FD_FFFF
0x1000_0000 to 0x1FFF_FFFF
0x2000_0000 to 0x2FFF_FFFF
The following area should be set device attribution or strongly ordered attribution as core access.
1. I/O area
2. Bit band alias area
3. Error Config (BootROM area)
4. WorkFLASH (when program)
5. TCFLASH (when program)
About device attribute and Strongly Ordered attribute, see "ARM®Architecture Reference Manual
ARM®v7-A and ARM®v7-R edition (ARM DDI 0406B)".
TCFLASH has a TCM-connected region and an AXI-connected region. AXI-connected region is
dedicated for flash memory programming/erasing. When read operation in user mode, use
TCM-connected region.
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
11. I/O Map
I/O Address Map (HPM, etc.)
Address
Area
Start
End
Overview
0xB000_0000
0xB03F_FFFF
Reserved
Function
Reserved
I/O Address Map (Memory & Config Group)
Address
End
0xB040_0000
0xB040_0FFF
IRC0
0xB040_1000
0xB040_1FFF
IRC1
0xB040_2000
0xB040_6FFF
Reserved
0xB040_7000
0xB040_73FF
NMI distributor
0xB040_7400
0xB040_7FFF
Reserved
Overview
Function
0xB040_8000
0xB040_83FF
TPU0
0xB040_8400
0xB040_8FFF
Reserved
0xB040_9000
0xB040_93FF
TPU1
0xB040_9400
0xB040_FFFF
Reserved
0xB041_0000
0xB041_03FF
Memory & Config Group
TCRAM0 IF
0xB041_0400
0xB041_07FF
0xB041_0800
0xB041_0FFF
Reserved
0xB041_1000
0xB041_13FF
TCFLASH0 IF
TCRAM1 IF
0xB041_1400
0xB041_17FF
TCFLASH1 IF
0xB041_1800
0xB041_1FFF
Reserved
0xB041_2000
0xB041_23FF
WorkFLASH0 IF
0xB041_2400
0xB041_27FF
WorkFLASH1 IF
0xB041_2800
0xB041_4FFF
Reserved
0xB041_5000
0xB041_5FFF
IPCU
0xB041_6000
0xB04F_FFFF
Reserved
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
Area
Start
49
D a t a S h e e t
I/O Address Map (Debug Group)
Address
50
CONFIDENTIAL
Area
Start
End
0xB050_0000
0xB050_0FFF
Overview
DAPROM
Function
0xB050_1000
0xB050_1FFF
ETB
0xB050_2000
0xB050_2FFF
CTI4
0xB050_3000
0xB050_3FFF
TPIU
0xB050_4000
0xB050_4FFF
TRACE_FUNNEL
0xB050_5000
0xB057_FFFF
Reserved
0xB058_0000
0xB058_0FFF
CORTEXROM0
0xB058_1000
0xB058_FFFF
Reserved
0xB059_0000
0xB059_0FFF
0xB059_1000
0xB059_1FFF
0xB059_2000
0xB059_2FFF
CORE1
0xB059_3000
0xB059_7FFF
Reserved
0xB059_8000
0xB059_8FFF
CTI0
0xB059_9000
0xB059_9FFF
CTI1
0xB059_A000
0xB059_BFFF
Reserved
0xB059_C000
0xB059_CFFF
ETM0
0xB059_D000
0xB059_DFFF
ETM1
0xB059_E000
0xB05F_FFFF
Reserved
Debug Group
CORE0
Reserved
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
I/O Address Map (MCU Config Group)
Address
Area
Start
End
0xB060_0000
0xB060_07FF
Overview
SYSC
Function
0xB060_0800
0xB060_0FFF
MODEC
0xB060_1000
0xB060_7FFF
Reserved
0xB060_8000
0xB060_83FF
SW-WDT0
0xB060_8400
0xB060_8FFF
0xB060_9000
0xB060_93FF
0xB060_9400
0xB060_BFFF
Reserved
0xB060_C000
0xB060_C3FF
HW-WDT
0xB060_C400
0xB061_FFFF
Reserved
0xB062_0000
0xB062_03FF
EXT-IRQ
0xB062_0400
0xB06F_FFFF
Reserved
Reserved
SW-WDT1
MCU Config Group
I/O Address Map (Common Peripheral Group)
Address
End
0xB070_0000
0xB070_3FFF
DMAC
0xB070_4000
0xB070_FFFF
Reserved
0xB071_0000
0xB071_0FFF
MPU AHB
0xB071_1000
0xB071_7FFF
Reserved
0xB071_8000
0xB071_87FF
CRC (ch.0 to 1)
0xB071_8800
0xB071_FFFF
Reserved
Overview
Function
CAN (ch.0 to 2)
0xB072_0000
0xB072_0BFF
0xB072_0C00
0xB072_7FFF
0xB072_8000
0xB072_83FF
Common Peripheral Group
0xB072_8400
0xB072_FFFF
(AHB32)
0xB073_0000
0xB073_03FF
CR calibration
0xB073_0400
0xB073_7FFF
Reserved
0xB073_8000
0xB073_8FFF
GPIO
0xB073_9000
0xB073_FFFF
Reserved
0xB074_0000
0xB074_3FFF
PPC
0xB074_4000
0xB074_7FFF
Reserved
0xB074_8000
0xB074_8FFF
RIC
0xB074_9000
0xB07F_FFFF
Reserved
0xB080_0000
0xB080_13FF
MFS (ch.0 to 4)
0xB080_1400
0xB080_7FFF
Reserved
0xB080_8000
0xB080_AFFF
0xB080_B000
0xB081_FFFF
Common Peripheral Group
0xB082_0000
0xB082_13FF
(APB)
0xB082_1400
0xB082_7FFF
Reserved
0xB082_8000
0xB080_8BFF
32-bit ICU (ch.0 to 5)
0xB082_8C00
0xB08F_FFFF
Reserved
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
Area
Start
Reserved
CAN prescaler
Reserved
Base timer (ch.0 to 11)
Reserved
32-bit FRT (ch.0 to 4)
51
D a t a S h e e t
I/O Address Map (Product Specified Peripheral Bus)
Address
52
CONFIDENTIAL
Area
Start
End
Overview
0xB090_0000
0xB0FF_FFFF
Reserved
0xB100_0000
0xB100_00FF
16-bit FRT (ch.6 to 11)
0xB100_0100
0xB100_01FF
16-bit OCU (ch.6 to 11)
0xB100_0200
0xB100_02FF
16-bit ICU (ch.4 to 7)
0xB100_0300
0xB100_03FF
4ch-SH ADC (unit1)
0xB100_0400
0xB100_04FF
0xB100_0500
0xB100_05FF
0xB100_0600
0xB100_07FF
0xB100_0800
0xB100_09FF
0xB100_0A00
0xB100_0BFF
Reserved
0xB100_0C00
0xB100_0CFF
RDC (unit1)
0xB100_0D00
0xB100_0DFF
DAC (ch.1)
0xB100_0E00
0xB100_0FFF
Reserved
0xB101_0000
0xB101_00FF
16-bit FRT (ch.12 to 17)
0xB101_0100
0xB101_01FF
16-bit OCU (ch.12 to 23)
0xB101_0200
0xB101_02FF
0xB101_0300
0xB101_03FF
Application Specific
Reserved
0xB101_0400
0xB101_05FF
Peripheral Group A
12-bit ADC (ch.0 to 31)
0xB101_0600
0xB101_06FF
(APB)
0xB101_0700
0xB101_0FFF
Reserved
0xB101_1000
0xB101_2FFF
Other (WFG)
0xB101_3000
0xB101_3FFF
0xB101_4000
0xB1FF_FFFF
0xB200_0000
0xB200_00FF
16-bit FRT (ch.0 to 5)
0xB200_0100
0xB200_01FF
16-bit OCU (ch.0 to 5)
0xB200_0200
0xB200_02FF
16-bit ICU (ch.0 to 3)
0xB200_0300
0xB200_03FF
4ch-SH ADC (unit0)
0xB200_0400
0xB200_04FF
WFG (ch.0 to 5)
0xB200_0500
0xB200_05FF
0xB200_0600
0xB200_07FF
Application Specific
Reserved
0xB200_0800
0xB200_09FF
Peripheral Group B
MVA (unit0)
(AHB-32)
Application Specific
Peripheral Group A
(AHB-32)
Function
Reserved
WFG (ch.6 to 11)
UDC (ch.2 to 3)
Reserved
MVA (unit1)
16-bit ICU (ch.8 to 14)
WFG(ch.12 to 23)
Other (ADC, CSV)
Reserved
Reserved
UDC (ch.0 to 1)
0xB200_0A00
0xB200_0BFF
0xB200_0C00
0xB200_0CFF
RDC (unit0)
Reserved
0xB200_0D00
0xB200_0DFF
DAC (ch.0)
0xB200_0E00
0xB200_0EFF
Reserved
0xB200_0F00
0xB200_0FFF
Reserved
0xB200_1000
0xB200_17FF
FlexRay (ch.A/ch.B)
0xB200_1800
0xB200_FFFF
Reserved
0xB201_0000
0xB201_00FF
0xB201_0100
0xB201_01FF
0xB201_0200
0xBFFF_FFFF
Application Specific
Peripheral Group B
(R-Bus)
Reserved
FlexRay/RDC clock control
Clock monitor
Reserved
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
I/O address Map (Error Config)
Address
Area
Start
End
0xFFFE_E000
0xFFFE_E3FF
Overview
IRC0 (NMIVASBR)
0xFFFE_E400
0xFFFE_E7FF
IRC1 (NMIVASBR)
Error Config
Function
0xFFFE_E800
0xFFFE_F7FF
0xFFFE_F800
0xFFFE_FBFF
Reserved
IRC (NMIVASBR) mirror*
0xFFFE_FC00
0xFFFE_FFFF
BootROM IF
*: CPU0 is IRC0, CPU1 is IRC1 able to access this area. The master of excepted CPU is reserved area.
Notes:
−
−
I/O address map shows maximum area for possibility. It depends on functions. The detail
information, see each address map.
It causes bus error to access to reserved area. However, following reserved area access is not
generation of bus error.
0xB018_0000 to 0xB018_03FF
0xB05C_0000 to 0xB05C_0FFF
0xB05E_0000 to 0xB05E_03FF
0xB05E_0400 to 0xB05E_07FF
0xB05E_0800 to 0xB05E_0BFF
0xB05E_0C00 to 0xB05E_0FFF
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
53
D a t a S h e e t
12. Pin Statuses in CPU Status
Pin Statuses (1/2)
54
CONFIDENTIAL
P413/RX2/INT2
98
99
100
101
102
86
-
P414/TX2
P415/TIOA4
P416/TIOB4
P417/TIOA5
P418/TIOB5
106
-
107
108
109
90
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
L
Analog output
L
Analog output
L
H/L
Analog output
H/L
Analog output
L
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Hi-Z/Input
blocked
Last status
retained*6
Input enabled
Input enabled
H/L
L*5
Analog output
L
L*5
Analog output
Analog input
Hi-Z/Input blocked
Hi-Z/Input
blocked
Input enabled
H/L
Hi-Z/Input
blocked
Hi-Z/Input blocked
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
-
-
-
-
-
-
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Hi-Z/Input
blocked
Last status
retained*6
Hi-Z/Input blocked
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input blocked
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
P419/SIN2/INT5
P420/SOT2
P131/SCK2
P431/ERDS1
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
85
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
97
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
P412/TX1
Watch mode
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
84
Stop mode
CPU sleep
96
After internal reset issuance
(Before GPORT setting)
P411/RX1/INT1
Hi-Z/Input blocked
Internal reset issuance
in progress
P410/TX0
83
Hi-Z/
Input
blocked
After internal reset issuance
(Before GPORT setting)
82
95
Internal reset issuance
in progress
94
Internal reset issuance
in progress
P409/RX0/INT0
After internal reset issuance
(Before GPORT setting)
81
Internal reset issuance
in progress
93
Internal reset issuance
in progress
P407/SOT1
P408/SCK1
With control
P406/SIN1/INT4
79
80
Without control
78
91
92
L*5
Hi-Z/
Last status
retained
Sleep mode
With control
90
Hi-Z/
Input blocked
After external
factor
releasing
*7
P305/FRCK0
P306/FRCK1
P000/DTTI0/4ADTG0
P001/RTO0
P002/RTO1
P003/RTO2
P004/RTO3
P005/RTO4
P006/RTO5
P007/4AN0
P008/4AN1
P009/4AN2
P010/4AN3
P011/RDC_W0/ZIN0
P012/RDC_V0/BIN0
P013/RDC_U0/AIN0
P014/RDC_Z0/ZIN1
P015/RDC_B0/BIN1
P016/RDC_A0/AIN1
AREF20
SIN_IN0
COS_IN0
SIN_OUT0
SIN_MINUS0
SIN_PLUS0
COS_PLUS0
COS_MINUS0
COS_OUT0
RDC_ACT0/P026
MAG_MINUS0
MAG_PLUS0
MAG_OUT0
P430/ERDS0
P030/DTTI2/FRCK12
P031/RTO12/FRCK13
P309/RTO13/FRCK14
P310/RTO14/FRCK15
P311/RTO15/FRCK16
P312/RTO16/FRCK17
P313/RTO17
P314/DTTI3/TIOA0
P315/RTO18/TIOB0
P316/RTO19/TIOA1
P317/RTO20/TIOB1
P318/RTO21/TIOA2
P319/RTO22/TIOB2
P320/RTO23/TIOA3
P321/SIN0/INT3/TIOB3
P322/SOT0
P323/SCK0
P324/STOPWT/IN6/IN16
P325/RXDA/IN7/IN17
P326/TXDA/IN8/IN18
P327/TXENA/IN9/IN19
P328/RXDB/IN10/IN20
P329/TXDB/IN11/IN21
P330/TXENB/IN12
NMIX
RSTX
MD1
MD0
X0
X1
TRSTX
TCK
TDO
TDI
TMS
nSRST
With
control
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
39
40
41
42
43
46
47
48
49
50
51
52
53
54
55
58
59
60
61
62
63
64
65
66
67
68
69
70
72
73
74
75
76
77
External factor
generation
in progress
With control
3
4
5
6
7
8
9
10
11
14
15
16
17
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
43
44
45
46
47
48
49
50
51
55
56
57
58
59
60
61
62
63
64
65
66
67
70
71
72
73
74
75
76
77
78
79
80
81
82
84
85
86
87
88
89
Without control
176
pin
With control
Pin Name
208
pin
GPORTEN control
Pin No.
Internal reset
factor*3
External reset
factor*2
Before internal reset
issuance
External reset
factor*1
After
external
factor
releasing
External
factor
generation
in progress
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input
blocked
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked*4
Hi-Z/Input
blocked
Hi-Z/Input
blocked
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Pin Statuses (2/2)
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
L
H/L
Analog output
H/L
Analog output
L
Analog output
H/L
L*5
L
L*5
Analog output
H/L
L
Analog output
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
Watch mode
High impedance enabled
(SYSC_SSPECFGR:
PSSPADCTRL=1)
Stop mode
High impedance disabled
(SYSC_SSPECFGR:
PSSPADCTRL=0)
CPU sleep
162
After internal reset issuance
(Before GPORT setting)
-
Sleep Mode
Internal reset issuance
in progress
153
154
158
159
160
161
-
Internal reset issuance
in progress
-
L*5
Internal reset issuance
in progress
152
MAG_OUT1
MAG_PLUS1
MAG_MINUS1
RDC_ACT1/P126
COS_OUT1
COS_MINUS1
COS_PLUS1
SIN_PLUS1
SIN_MINUS1
SIN_OUT1
COS_IN1
SIN_IN1
AREF21
P116/RDC_A1/AIN3
P115/RDC_B1/BIN3
P114/RDC_Z1/ZIN3
P113/RDC_U1/AIN2
P112/RDC_V1/BIN2
P111/RDC_W1/ZIN2
P110/4AN7
P109/4AN6
P108/4AN5
P107/4AN4
P106/RTO11
P105/RTO10
P104/RTO9
P103/RTO8
P102/RTO7
P101/RTO6
P100/DTTI1/4ADTG1
Internal reset
factor*3
After
external
factor
releasing
External factor
generation
in progress
Before internal reset
issuance
91
92
93
94
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
120
121
122
123
124
125
126
127
128
129
130
After internal reset issuance
(Before GPORT setting)
110
111
112
113
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
139
140
141
142
145
146
147
148
149
150
151
After external
factor
releasing
Internal reset issuance
in progress
176
pin
Internal reset issuance
in progress
208
pin
GPORTEN control
Pin Name
External
factor
generation
in progress
External reset
factor*2
After internal reset issuance
(Before GPORT setting)
External reset
factor*1
Pin No.
Analog output
Analog input
L
L
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
L
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
P421/SIN3/INT6/FRCK8
Hi-Z/Input blocked
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked*4
Last status
retained
Hi-Z/Input
blocked*4
P422/SOT3/FRCK9/IN13
P423/SCK3/FRCK10/IN14
P425/TIOA8
P426/TIOB8
P427/TIOA9
P428/TIOB9
Hi-Z/
Last status
retained
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
134
P429/MONCLK/MM
Hi-Z/Input blocked
Hi-Z/
Last status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained*8
Hi-Z/Input
blocked
Last status
retained*8
Hi-Z/Input
blocked
163
164
165
166
167
168
169
170
173
174
175
176
177
178
179
180
185
186
187
188
189
190
191
192
195
135
136
137
138
139
140
141
142
145
146
147
148
149
150
151
152
157
158
159
160
161
162
163
164
167
AN0/P200
AN1/P201
AN2/P202
AN3/P203
AN4/P204
AN5/P205
AN6/P206
AN7/P207
AN8/P208
AN9/P209
AN10/P210
AN11/P211
AN12/P212
AN13/P213
AN14/P214
AN15/P215
AN16/P216
AN17/P217
AN18/P218
AN19/P219
AN20/P220/TIOA6
AN21/P221/TIOB6
AN22/P222/TIOA7
AN23/P223/TIOB7
AN24/P224
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
196
168
AN25/P225/SIN4/INT7
Hi-Z/Input blocked
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked*4
Last status
retained
Hi-Z/Input
blocked*4
197
198
199
200
201
202
203
204
205
206
207
169
170
171
172
173
174
175
-
AN26/P226/SOT4/IN0
AN27/P227/SCK4/IN1
AN28/P228/SCS40/IN2
AN29/P229/SCS41/IN3
AN30/P230/SCS42/IN4
AN31/P231/SCS43/IN5
P300/ADTG0
P301/TIOA10/FRCK4
P302/TIOB10/FRCK5
P303/TIOA11/FRCK6
P304/TIOB11/FRCK7
Hi-Z/Last
status
retained
Hi-Z/Input blocked
Hi-Z/Last
status
retained
Hi-Z/Input
blocked
Hi-Z/Input blocked
Hi-Z/Input
blocked
Last status
retained*6
Last status
retained
Hi-Z/Input
blocked
Last status
retained
Hi-Z/Input
blocked
With control
Hi-Z/Input blocked
*1: Power-on reset, internal power supply low-voltage detection and NMIX + RSTX pin are factors.
*2: External power supply low-voltage detection and external reset are factors.
*3: Software reset and software/hardware watchdog reset are factors.
*4: When external interrupt is valid, input blocked is invalid.
*5: When I/O is initialized, "L" is output.
*6: Operation is continued according to the peripheral function.
*7: If GPORTEN bit is 0 and CPORTEN bit is 1, input is enabled.
*8: When clock monitor output pin (MONCLK) is selected, pin state becomes high impedance.
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
55
D a t a S h e e t
13. Electrical Characteristics
13.1 Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1, *2
VCC
*1, *2
Rating
Unit
Min
Max
VSS-0.3
VSS+6.0
V
Analog power supply voltage
VDD
VSS-0.3
VSS+1.8
V
Analog reference voltage*1
AVCC
VSS-0.3
VSS+6.0
V
*1
Input voltage
Analog pin input voltage*1
*1
RVCC
VSS-0.3
VSS+6.0
V
RVCC≤VCC
VSS-0.3
VSS+6.0
V
AVRH≤AVCC
RVRH
VSS-0.3
VSS+6.0
V
RVRH≤RVCC
VI
VSS-0.3
VCC+0.3
V
Analog pin input voltage*1
VIA
VSS-0.3
VCC+0.3
V
Output voltage*1
VO
VSS-0.3
VCC+0.3
V
Max total clamp current
"L" level Max output current
*3
"L" level average output current
*4
"L" level total output current*5
"H" level Max output current*3
"H" level average output current*4
"H" level total output current
*5
AVCC≤VCC
AVRH
Input voltage
Max clamp current
Remarks
ICLAMP
-
4
mA
*8
Σ|ICLAMP|
-
20
mA
*8
IOL1
-
3.5
mA
When setting to 1 mA*6
IOL2
-
7
mA
When setting to 2 mA
IOL3
-
14
mA
When setting to 4 mA*7
IOLAV1
-
1
mA
When setting to 1 mA*6
IOLAV2
-
2
mA
When setting to 2 mA
IOLAV3
-
4
mA
When setting to 4 mA*7
ΣIOL
-
40
mA
*6
IOH1
-
-3.5
mA
When setting to 1 mA*6
IOH2
-
-7
mA
When setting to 2 mA
IOH3
-
-14
mA
When setting to 4 mA*7
IOHAV1
-
-1
mA
When setting to1 mA*6
IOHAV2
-
-2
mA
When setting to 2 mA
IOHAV3
-
-4
mA
When setting to 4 mA*7
ΣIOH
-
-40
mA
*6
Power consumption
PD
-
1500
mW
Operating temperature
TA
-40
+125
°C
Storage temperature
Tstg
-55
+150
°C
*9
*1: These parameters are based on the condition that VSS=AVSS=0.0V.
*2: Caution must be taken that AVCC does not exceed VCC.
*3: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*4: The average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 10 ms period. The average value is the operation current  the operation ratio.
*5: The total output current is defined as the maximum current value flowing through all of corresponding
pins.
*6: Corresponding pins: general-purpose ports
*7: Corresponding pins: general-purpose ports of P325 to P330
*8: Corresponding pins: all general-purpose ports and analog input pin
−
−
−
56
CONFIDENTIAL
Use the devices within recommended operating conditions.
Use the devices with direct voltage (current).
The + B signal should always be applied by connecting a limiting resistor between the + B signal and
the microcontroller.
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
−
The value of the limiting resistor should be set so that the current input to the microcontroller pin
does not exceed rated values at any time regardless of instantaneously or constantly when the + B
signal is input.
−
Note that when the microcontroller drive current is low, such as in the low-power consumption
modes, the + B input potential can increase the potential at the VCC pin via a protective diode,
possibly affecting other devices.
−
Note that if the + B signal is input when the microcontroller is off (not fixed at 0V), since the power is
supplied through the pin, the microcontroller may operate incompletely.
−
Note that if the +B signal is input at power-on, since the power is supplied through the pin, the
power-on reset may not function in the power supply voltage.
−
Do not leave + B input pins open.
Sample Recommended Circuit
MB9D560 series
Protective diode
Limiting resistor current
+Ｂ input(12 to 16V)
*9: To use this product at TA=125°C, equip this on a multilayer board with four or more layers.
To equip this on a single-layer board, change the operating conditions (operating frequency, power
supply voltage, etc.) to use this at the power consumption PD=780mW or lower, or use this at TA=100°C
or lower.
Warning:
−
Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed
any of these ratings.
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
57
D a t a S h e e t
13.2 Recommended Operating Conditions
(VSS=AVSS-RVSS=0.0V)
Parameter
Symbol
Power supply voltage
*
Smoothing capacitor
Operating temperature
Value
Min
Max
Unit
Remarks
VCC
4.5
5.5
VDD
1.1
1.3
V
Recommended operation
AVCC
4.5
5.5
V
guarantee range
RVCC
4.5
5.5
V
VCC
3.7
5.5
V
VDD
1.09
1.3
V
AVCC
3.7
5.5
V
RVCC
3.7
5.5
V
CREF
0.33
1.0
µF
TA
-40
+125
°C
V
Operation guarantee range
Tolerance within ±40%
* : For connection of smoothing capacitor CREF, see the figure below.
− CREF pin connection
Decoupling capacitor
(0.01µF to 1µF)
Wire
MB9D560 series
Pin
AVRH0
AVRL0
CREF
AVR0
AVSS0
AVCC0
It should be used smoothing capacitor for between AVR1 to AVRL1, RVR0 to RVRL0,
RVR1 to RVRL1 as well.
− CREF capacitor size and A/D converter activation time
It depends on activation time of A/D converter with R/D converter and activation time of
4 channels same time sampling A/D converter by CREF capacitor seize. The
computation expression of activation time is as follows.
Activation time = 9 × CREF × 1.2k + 1μ [s]
Activation time relate with following time from activation trigger, please use smoothing
capacitor with system operation conditions.
If A/D converter of 4 channels same time sampling,
Set to "1" for ENBL bit of A/D enable setting register.
If A/D converter with R/D converter,
Set to "1" for RDCEN bit of operation control register 1.
58
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
Warning:
−
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
−
−
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device
and could result in device failure.
−
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
59
D a t a S h e e t
13.3 DC Characteristics
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0.7VCC
-
Vcc+0.3
V
0.8VCC
-
Vcc+0.3
V
0.7VCC
-
Vcc+0.3
V
Remarks
P000 to P016,
P026,
P030 to P031,
P100 to P116,
VIH1
P126, P131,
P200 to P231,
P300 toP306,
When CMOS schmitt
input level is
selected
P309 to P324,
P406 to P423,
P425 to P431
P000 to P016,
P026,
P030 to P031,
"H" level input
P100 to P116,
voltage
VIH2
P126, P131,
P200 to P231,
P300 to P306,
When automotive
input level is
selected
P309 to P330,
P406 to P423,
P425 to P431
When FlexRay input
VIH3
P325 to P330
VIH4
RSTX, NMIX
-
0.7VCC
-
Vcc+0.3
V
VIH5
MD0, MD1
-
0.7VCC
-
Vcc+0.3
V
-
2.3
-
Vcc+0.3
V
level is selected
TRSTX,
VIH6
TCK, TDI,
TMS, nSRST
60
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
VSS-0.3
-
0.3VCC
V
VSS-0.3
-
0.5VCC
V
VSS-0.3
-
0.3VCC
V
Remarks
P000 to P016,
P026,
P030 to P031,
P100 to P116,
VIL1
P126, P131,
P200 to P231,
P300 toP306,
When CMOS schmitt
input level is
selected
P309 to P324,
P406 to P423,
P425 to P431
P000 to P016,
P026,
P030 to P031,
"L" level input
P100 to P116,
voltage
VIL2
P126, P131,
P200 to P231,
P300 to P306,
When automotive
input level is
selected
P309 to P330,
P406 to P423,
P425 to P431
When FlexRay input
VIL3
P325 to P330
VIL4
RSTX, NMIX
-
VSS-0.3
-
0.3VCC
V
VIL5
MD0, MD1
-
VSS-0.3
-
0.3VCC
V
VIL6
TCK, TDI,
-
VSS-0.3
-
0.8
V
level is selected
TRSTX,
TMS, nSRST
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
61
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
VCC-0.5
-
VCC
V
VCC-0.5
-
VCC
V
Remarks
P000 to P016,
P026,
P030 to P031,
P100 to P116,
VOH1
P126, P131,
VCC=4.5V
P200 to P231,
IOH=-2.0mA
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
"H" level output
VOH2
voltage
P325 to P330
VCC=4.5V
IOH=-4.0mA
When
FlexRay
selected
P000 to P016,
P026,
P030 to P031,
P100 to P116,
VOH3
P126, P131,
VCC=4.5V
P200 to P231,
IOH=-1.0mA
VCC-0.5
-
VCC
V
VCC-0.5
-
VCC
V
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
VOH4
62
CONFIDENTIAL
TDO
VCC=4.5V
IOH=-5mA
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Min
Typ
Max
0
-
0.4
V
0
-
0.4
V
Remarks
P000 to P016,
P026,
P030 to P031,
P100 to P116,
VOL1
P126, P131,
VCC=4.5V
P200 to P231,
IOL=2.0mA
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
"L" level output
VOL2
voltage
P325 to P330
VCC=4.5V
IOL=4.0mA
When
FlexRay
selected
P000 to P016,
P026,
P030 to P031,
P100 to P116,
VOL3
P126, P131,
VCC=4.5V
P200 to P231,
IOL=1.0mA
0
-
0.4
V
0
-
0.4
V
P300 toP306,
P309 to P330,
P406 to P423,
P425 to P431
VOL4
TDO
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
VCC=4.5V
IOL=5mA
63
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Input leakage
current
Symbol
Pin Name
IIL
All input pin
RUP1
RSTX, NMIX
Conditions
VCC=AVCC=RVCC=5.5V
VSS < VI < VCC
-
Value
Unit
Min
Typ
Max
-5
-
+5
µA
25
-
100
kΩ
25
-
100
kΩ
-
5
15
pF
Remarks
P000 to P016,
P026,
P030 to P031,
P100 to P116,
Pull-up
resistance
RUP2
P126, P131,
When pull-up
P200 to P231,
resistance is selected
P300 to P306,
P309 to P330,
P406 to P423,
P425 to P431
Other than
Input capacitor
CIN
VCC, VSS,
AVCC, AVSS,
-
RVCC, RVSS
64
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
Typ
Max
Unit
Remarks
FCD0_CLK=200 MHz
FCLK_CPUx=200 MHz,
FCLK_TFCLKx=66 MHz,
FCLK_HPMPD2=200 MHz,
FCLK_DMA=200 MHz,
Normal
operations
-
104
115
mA
FCLK_MEMC=100 MHz,
FCLK_WFCLKx=200 MHz,
200MHz
FCLK_SYSCPD1=100 MHz,
FCLK_PERIy=100 MHz,
FCLK_PERIz=50 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
FCD0_CLK=160 MHz
FCLK_CPUx=160 MHz,
FCLK_TFCLKx=80 MHz,
FCLK_HPMPD2=160 MHz,
Normal
FCLK_DMA=160 MHz,
operations
-
105
116
mA
FCLK_MEMC=80 MHz,
FCLK_WFCLKx=160 MHz,
160MHz
FCLK_SYSCPD1=80 MHz,
FCLK_PERIy=80 MHz,
FCLK_PERIz=40 MHz
Power supply
current
ICC5
x=0, 1 y=0, 4, 5 z=1, 6, 7
VCC5
FCD0_CLK=200 MHz
FCLK_CPUx=200 MHz,
FCLK_TFCLKx=66 MHz,
FCLK_HPMPD2=200 MHz,
FCLK_DMA=200 MHz,
*
Flash write/erase
200MHz
-
115
126
mA
FCLK_MEMC=100 MHz,
FCLK_WFCLKx=200 MHz,
FCLK_SYSCPD1=100 MHz,
FCLK_PERIy=100 MHz,
FCLK_PERIz=50 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
FCD0_CLK=160 MHz
FCLK_CPUx=160 MHz,
FCLK_TFCLKx=80 MHz,
FCLK_HPMPD2=160 MHz,
Flash write/erase*
160MHz
FCLK_DMA=160 MHz,
-
116
127
mA
FCLK_MEMC=80 MHz,
FCLK_WFCLKx=160 MHz,
FCLK_SYSCPD1=80 MHz,
FCLK_PERIy=80 MHz,
FCLK_PERIz=40 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
*: This series has 2 types of flash; TCFLASH (4) and WorkFLASH (2); however, this is the specification when
only one of those is written/erased.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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65
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
Typ
Max
Unit
Remarks
FCD0_CLK=200 MHz
FCLK_CPUx=200 MHz,
FCLK_TFCLKx=66 MHz,
FCLK_HPMPD2=200 MHz,
FCLK_DMA=200 MHz,
Normal
operations
-
310
510
mA
FCLK_MEMC=100 MHz,
FCLK_WFCLKx=200 MHz,
200MHz
FCLK_SYSCPD1=100 MHz,
FCLK_PERIy=100 MHz,
FCLK_PERIz=50 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
FCD0_CLK=160 MHz
FCLK_CPUx=160 MHz,
FCLK_TFCLKx=80 MHz,
FCLK_HPMPD2=160 MHz,
Normal
FCLK_DMA=160 MHz,
operations
-
290
490
mA
FCLK_MEMC=80 MHz,
FCLK_WFCLKx=160 MHz,
160MHz
FCLK_SYSCPD1=80 MHz,
FCLK_PERIy=80 MHz,
FCLK_PERIz=40 MHz
Power supply
current
ICC12
x=0, 1 y=0, 4, 5 z=1, 6, 7
VCC12
FCD0_CLK=200 MHz
FCLK_CPUx=200 MHz,
FCLK_TFCLKx=66 MHz,
FCLK_HPMPD2=200 MHz,
FCLK_DMA=200 MHz,
*
Flash write/erase
200MHz
-
312
512
mA
FCLK_MEMC=100 MHz,
FCLK_WFCLKx=200 MHz,
FCLK_SYSCPD1=100 MHz,
FCLK_PERIy=100 MHz,
FCLK_PERIz=50 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
FCD0_CLK=160 MHz
FCLK_CPUx=160 MHz,
FCLK_TFCLKx=80 MHz,
FCLK_HPMPD2=160 MHz,
Flash write/erase*
160MHz
FCLK_DMA=160 MHz,
-
292
492
mA
FCLK_MEMC=80 MHz,
FCLK_WFCLKx=160 MHz,
FCLK_SYSCPD1=80 MHz,
FCLK_PERIy=80 MHz,
FCLK_PERIz=40 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
*: This series has 2 types of flash; TCFLASH (4) and WorkFlash (2); however, this is the specification when
only one of those is written/erased.
66
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin name
Conditions
Value
Min
Typ
Max
Unit
Remarks
FCD0_CLK=200 MHz
FCLK_CPUx=200 MHz,
FCLK_TFCLKx=66 MHz,
FCLK_HPMPD2=200 MHz,
CPU sleep mode
200MHz
FCLK_DMA=200 MHz,
-
40
42
mA
FCLK_MEMC=100 MHz,
FCLK_WFCLKx=200 MHz,
FCLK_SYSCPD1=100 MHz,
FCLK_PERIy=100 MHz,
FCLK_PERIz=50 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
ICCS5
Power supply
FCD0_CLK=160 MHz
FCLK_CPUx=160 MHz,
VCC5
current
FCLK_TFCLKx=80 MHz,
FCLK_HPMPD2=160 MHz,
CPU sleep mode
160MHz
FCLK_DMA=160 MHz,
-
30
32
mA
FCLK_MEMC=80 MHz,
FCLK_WFCLKx=160 MHz,
FCLK_SYSCPD1=80 MHz,
FCLK_PERIy=80 MHz,
FCLK_PERIz=40 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
Watch mode,
ICCT5
4MHz source
-
390
1030
µA
-
380
1010
µA
oscillation
ICCH5
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
Stop mode
When using crystal
TA=25°C
TA=25°C
67
D a t a S h e e t
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
Value
Min
Typ
Max
Unit
Remarks
FCD0_CLK=200 MHz
FCLK_CPUx=200 MHz,
FCLK_TFCLKx=66 MHz,
FCLK_HPMPD2=200 MHz,
CPU sleep mode
200MHz
FCLK_DMA=200 MHz,
-
220
410
mA
FCLK_MEMC=100 MHz,
FCLK_WFCLKx=200 MHz,
FCLK_SYSCPD1=100 MHz,
FCLK_PERIy=100 MHz,
FCLK_PERIz=50 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
ICCS12
Power supply
FCD0_CLK=160 MHz
FCLK_CPUx=160 MHz,
VCC12
current
FCLK_TFCLKx=80 MHz,
FCLK_HPMPD2=160 MHz,
CPU sleep mode
160MHz
FCLK_DMA=160 MHz,
-
180
360
mA
FCLK_MEMC=80 MHz,
FCLK_WFCLKx=160 MHz,
FCLK_SYSCPD1=80 MHz,
FCLK_PERIy=80 MHz,
FCLK_PERIz=40 MHz
x=0, 1 y=0, 4, 5 z=1, 6, 7
Watch mode,
ICCT12
4MHz source
-
1280
9730
µA
-
860
9530
µA
oscillation
ICCH12
68
CONFIDENTIAL
Stop mode
When using crystal
TA=25°C
TA=25°C
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
13.4 AC Characteristics
(1) Source Clock Timing
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
FC
X0, X1
tCYL
Source oscillation
clock frequency
Source oscillation
clock cycle time
CAN PLL jitter
(during lock)
Built-in slow-CR
oscillation frequency
Built-in fast-CR
oscillation frequency
Value
Unit
Remarks
Min
Typ
Max
-
4
-
20
MHz
X0, X1
-
50
-
250
ns
tPJ
-
-
-10
-
+10
ns
FCRS
-
-
50
100
150
kHz
FCRF
-
-
4
8
12
MHz
Without calibration
7.2
8
8.8
MHz
With calibration
− X0, X1 clock timing
tCYL
X0
− CAN PLL jitter
Deviation time from the ideal clock is assured per cycle out of 20,000 cycles.
t1
Ideal clock
t2
t3
tn-1
tn
Slow
t1
PLL output
t2
t3
tn-1
tn
Fast
May 15, 2015, MB9D560_DS708-00001-3v0-E
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69
D a t a S h e e t
(2) Internal Clock Timing
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Internal clock
frequency
Internal clock cycle
time
70
CONFIDENTIAL
Symbol
Pin Name
Conditions
FCD0_CLK
-
-
Value
Min
Typ
Max
0
-
200
Unit
MHz
Remarks
CD0_CLK
FCD4_CLK
-
-
0
-
200
MHz
CD4_CLK
FCLK_CPU0
-
-
0
-
200
MHz
CLK_CPU0
FCLK_CPU1
-
-
0
-
200
MHz
CLK_CPU1
FCLK_TFCLK0
-
-
0
-
80
MHz
CLK_TFCLK0
FCLK_TFCLK1
-
-
0
-
80
MHz
CLK_TFCLK1
FCLK_ATB
-
-
0
-
100
MHz
CLK_ATB
FCLK_DBG
-
-
0
-
50
MHz
CLK_DBG
FCLK_HPMPD2
-
-
0
-
200
MHz
CLK_HPMPD2
CLK_DMA
FCLK_DMA
-
-
0
-
200
MHz
FCLK_MEMC
-
-
0
-
200
MHz
CLK_MEMC
FCLK_WFCLK0
-
-
0
-
80
MHz
CLK_WFCLK0
FCLK_WFCLK1
-
-
0
-
80
MHz
CLK_WFCLK1
FCLK_SYSCPD1
-
-
0
-
100
MHz
CLK_SYSCPD1
FCLK_PERI0
-
-
0
-
100
MHz
CLK_PERI0
FCLK_PERI1
-
-
0
-
50
MHz
CLK_PERI1
FCLK_PERI4
-
-
0
-
100
MHz
CLK_PERI4
FCLK_PERI5
-
-
0
-
100
MHz
CLK_PERI5
FCLK_PERI6
-
-
0
-
50
MHz
CLK_PERI6
FCLK_PERI7
-
-
0
-
50
MHz
CLK_PERI7
FCLK_CLKO
-
-
0
-
200
MHz
tCD0_CLK
-
-
5
-
-
ns
CLK_CLKO
CD0_CLK
tCD4_CLK
-
-
5
-
-
ns
CD4_CLK
tCLK_CPU0
-
-
5
-
-
ns
CLK_CPU0
tCLK_CPU1
-
-
5
-
-
ns
CLK_CPU1
tCLK_TFCLK0
-
-
12.5
-
-
ns
CLK_TFCLK0
tCLK_TFCLK1
-
-
12.5
-
-
ns
CLK_TFCLK1
tCLK_ATB
-
-
10
-
-
ns
CLK_ATB
tCLK_DBG
-
-
20
-
-
ns
CLK_DBG
tCLK_HPMPD2
-
-
5
-
-
ns
CLK_HPMPD2
CLK_DMA
tCLK_DMA
-
-
5
-
-
ns
tCLK_MEMC
-
-
5
-
-
ns
CLK_MEMC
tCLK_WFCLK0
-
-
12.5
-
-
ns
CLK_WFCLK0
CLK_WFCLK1
tCLK_WFCLK1
-
-
12.5
-
-
ns
tCLK_SYSCPD1
-
-
10
-
-
ns
CLK_SYSCPD1
tCLK_PERI0
-
-
10
-
-
ns
CLK_PERI0
tCLK_PERI1
-
-
20
-
-
ns
CLK_PERI1
tCLK_PERI4
-
-
10
-
-
ns
CLK_PERI4
tCLK_PERI5
-
-
10
-
-
ns
CLK_PERI5
tCLK_PERI6
-
-
20
-
-
ns
CLK_PERI6
tCLK_PERI7
-
-
20
-
-
ns
CLK_PERI7
tCLK_CLKO
-
-
5
-
-
ns
CLK_CLKO
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
− Guaranteed operation range Internal operation clock frequency vs. Power supply voltage
Recommended guaranteed operation range:
Power supply voltage VCC (V)
PLL guaranteed operation range:
5.5
Guaranteed operation range:
4.5
Power supply voltage VDD (V)
3.7
1.3
1.1
1.09
2
4
200
Internal operation clock frequency FCD0_CLK(MHz)
Note: The CPU will be reset at the power supply voltage of the low-voltage detection setting voltage or less.
− Oscillation clock frequency vs. Internal operation clock frequency
Oscillation Clock
Frequency
Main Clock
PLL Multiplying
PLL Output Divider
Setting
Setting
100
2
200 MHz
200 MHz
PLL Clock
4 MHz
4 MHz
8 MHz
8 MHz
50
2
8 MHz
4 MHz
100
2
200 MHz
16 MHz
16 MHz
25
2
200 MHz
16 MHz
8 MHz
50
2
200 MHz
− Example of oscillation circuit
X0
X1
R
C1
C2
Note: when configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator
manufacturers for the design.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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71
D a t a S h e e t
AC characteristics are specified by the following measurement reference voltage values.
Input signal waveform
Hysteresis input pin (Automotive)
Output signal waveform
Output pin
0.8Vcc
2.4V
0.5Vcc
0.8V
Hysteresis input pin (CMOS schmitt)
0.7Vcc
0.3Vcc
Hysteresis input pin (FlexRay)
0.7Vcc
0.3Vcc
Hysteresis input pin (TTL)
2.0V
0.8V
72
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(3) Reset Input
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Reset input time
Width for reset input removal
Symbol
Pin Name
Conditions
tRSTL
RSTX
-
Value
Unit
Min
Max
10
-
µs
1
-
µs
Remarks
tRSTL
RSTX
0.2Vcc
May 15, 2015, MB9D560_DS708-00001-3v0-E
CONFIDENTIAL
0.2Vcc
73
D a t a S h e e t
(4) Power-on Conditions
Parameter
(TA: Recommended operating conditions, VSS=0.0V)
Symbol
Pin Name
Conditions
Level detection
-
VCC5
voltage
-
Level detection
-
hysteresis width
-
Level detection time
Power-on time
Power-off time
Value
Unit
Remarks
V
When turning
0.7
V
on power
150
mV
During
mV
voltage drop
*1
Min
Typ
Max
-
2.0
2.2
2.4
VCC12
-
0.4
-
VCC5
-
-
-
VCC12
-
-
-
50
-
-
-
-
-
30
µs
tR5
VCC5
-
0.11
-
30
ms
tR12
VCC12
-
0.05
-
0.6
ms
tOFF
VCC5
-
1
-
-
ms
*2
*1: If the fluctuation of the power supply is faster than the low-voltage detection time, there is the possibility
to generate or release after the power supply voltage has exceeded the detection voltage range.
*2: This time is to start the slope detection at next power on after power down and internal charge loss.
− Power-on , Power-off sequence
2.0V
VCC5
0.2Vcc
tR5
0.2Vcc
tOFF
1.1V
VCC12
tR12
NMIX + RSTX
Notes:
74
CONFIDENTIAL
−
Power supply input procedure
Power supply should input same time VCC5 and VCC12, or VCC5 to up step.
Also, when power supply input, VCC12 is not over voltage of VCC5.
−
Power supply shutdown procedure
Power supply should shutdown same time VCC5 and VCC12, or VCC12 to up step.
Also, when power supply shutdown, VCC12 is not over voltage of VCC5.
−
Notes: When power supply input and power supply shutdown
When power supply input, power supply voltage until achieve to recommend operation guarantee
area, same time input for NMIX pin + RSTX pin.
When power supply shutdown, power supply voltage until achieve to recommend operation
guarantee area, same time input for NMIX pin + RSTX pin.
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5) Multi-Function Serial Interface
(5-1) CSIO Timing (SMR:MD[2:0]=0b010)
(5-1-1) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "H"
(SMR:SCINV=0)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCK↓→SOT
tSLOVI
delay time
Valid SIN→SCK↑
tIVSHI
setup time
SCK↑→Valid SIN
tSHIXI
hold time
Serial clock "H" pulse
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Conditions
Unit
Max
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_PERI1+10
-
ns
2tCLK_PERI1-10
-
ns
-
30
ns
10
-
ns
20
-
ns
Remarks
Master mode
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
tSHSL
width
Value
Min
SCK0 to SCK4
Serial clock "L" pulse
tSLSH
width
SCK↓→SOT
tSLOVE
delay time
Valid SIN→SCK↑
tIVSHE
setup time
SCK↑→Valid SIN
tSHIXE
hold time
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
SCK fall time
tF
SCK0 to SCK4
-
5
ns
SCK rise time
tR
SCK0 to SCK4
-
5
ns
-
-
-
5
Mbps
-
-
-
6
Mbps
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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75
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSLOVI
VOH
VOL
SOT
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
tSLSH
SCK
VIH
tF
SOT
VIL
VIL
tR
tSLOVE
VOH
VOL
tIVSHE
SIN
VIH
VIH
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
76
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-2) Normal Synchronous Transfer (SCR:SPI=0) and Serial Clock Output Signal Detect Level "L"
(SMR:SCINV=1)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCK↑→SOT
tSHOVI
delay time
Valid SIN→SCK↓
tIVSLI
setup time
SCK↓→valid SIN
tSLIXI
hold time
Serial clock "H" pulse
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Conditions
Unit
Max
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
0
-
ns
tCLK_PERI1+10
-
ns
2tCLK_PERI1-10
-
ns
-
30
ns
10
-
ns
20
-
ns
Remarks
Master mode
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
tSHSL
width
Value
Min
SCK0 to SCK4
Serial clock "L" pulse
tSLSH
width
SCK↑→SOT
tSHOVE
delay time
valid SIN→SCK↓
tIVSLE
setup time
SCK↓→valid SIN
tSLIXE
hold time
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
SCK fall time
tF
SCK0 to SCK4
-
5
ns
SCK rise time
tR
SCK0 to SCK4
-
5
ns
-
-
-
5
Mbps
-
-
-
6
Mbps
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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77
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
tSLIXI
VIH
SIN
VIH
VIL
VIL
Master mode
tSLSH
tSHSL
SCK
VIH
VIL
tR
SOT
VIH
tF
tSHOVE
VOH
VOL
tIVSLE
SIN
VIL
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
78
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-3) SPI Compatible (SCR:SPI=1) and Serial Clock Output Signal Detect Level "H" (SMR:SCINV=0)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCK↑→SOT
tSHOVI
delay time
Valid SIN→SCK↓
tIVSLI
setup time
SCK↓→valid SIN
tSLIXI
hold time
SOT→SCK↓
tSOVLI
delay time
Serial clock "H" pulse
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Conditions
Master mode
Unit
Min
Max
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_PERI1-30
-
ns
tCLK_PERI1+10
-
ns
2tCLK_PERI1-10
-
ns
-
30
ns
10
-
ns
20
-
ns
Remarks
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
SCK0 to SCK4,
SOT0 to SOT4
tSHSL
width
Value
SCK0 to SCK4
Serial clock "L" pulse
tSLSH
width
SCK↑→SOT
tSHOVE
delay time
valid SIN→SCK↓
tIVSLE
setup time
SCK↓→valid SIN
tSLIXE
hold time
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Slave mode
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
SCK fall time
tF
SCK0 to SCK4
-
5
ns
SCK rise time
tR
SCK0 to SCK4
-
5
ns
-
-
-
5
Mbps
-
-
-
6
Mbps
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSOVLI
VOH
VOL
SOT
VOH
VOL
tSLIXI
tIVSLI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
SCK
tF
*
SOT
VIL
VOH
VIH
VIH
VIL
tSHOVE
VOH
VOL
VOL
tIVSLE
SIN
VIL
tR
tSLIXE
VIH
VIL
VIH
VIL
*: Changes when writing to TDR register
Slave mode
80
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-4) SPI Compatible (SCR:SPI=1) and Serial Clock Output Signal Detect Level "L" (SMR:SCINV=1)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0 to SCK4
SCK↓→SOT
tSLOVI
delay time
Valid SIN→SCK↑
tIVSHI
setup time
SCK↑→valid SIN
tSHIXI
hold time
SOT→SCK↑
tSOVHI
Delay time
Serial clock "H" pulse
tSHSL
width
Serial clock "L" pulse
tSLSH
width
SCK↓→SOT
tSLOVE
delay time
valid SIN→SCK↑
tIVSHE
setup time
SCK↑→valid SIN
tSHIXE
hold time
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Conditions
Master mode
IOL=-1mA, IOH=1mA)
SCK0 to SCK4,
SOT0 to SOT4
SCK0 to SCK4,
SIN0 to SIN4
Max
4tCLK_PERI1
-
ns
-30
+30
ns
30
-
ns
0
-
ns
2tCLK_PERI1-30
-
ns
tCLK_PERI1+10
-
ns
2tCLK_PERI1-10
-
ns
-
30
ns
10
-
ns
20
-
ns
Slave mode
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
SCK fall time
tF
SCK0 to SCK4
-
5
ns
SCK rise time
tR
SCK0 to SCK4
-
5
ns
-
-
-
5
Mbps
-
-
-
6
Mbps
Transfer speed
Remarks
(CL=20pF,
SOT0 to SOT4
SOT0 to SOT4
Unit
Min
(CL=50pF,
IOL=-2mA, IOH=2mA),
SCK0 to SCK4,
SCK0 to SCK4,
Value
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
t SCYC
VOH
VOH
SCK
VOL
t SOVHI
t SLOVI
VOH
VOL
SOT
VOH
VOL
t IVSHI
t SHIXI
VIH
VIL
SIN
VIH
VIL
Master mode
t SHSL
SCK
VIL
tR
*
SOT
VIH
VIH
tF
VOH
VOL
VIL
VIL
VIH
t SLOVE
VOH
VOL
t IVSHE
SIN
t SLSH
VIH
VIL
t SHIXE
VIH
VIL
*: Changes when writing to TDR register
Slave mode
82
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MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-5) When the Serial Chip Select is Used (SCSCR:CSEN=1)
− Serial clock output signal detect level "H" (SMR, SCSFR:SCINV=0)
− Serial chip select inactive level "H" (SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
SCS↓→SCK↓
tCSSI
setup time
SCK↑→SCS↑
tCSHI
hold time
Pin Name
SCK4,
SCS40 to SCS43
Conditions
Master mode
tCSDI
SCS↓→SCK↓
tCSSE
setup time
SCK↑→SCS↑
tCSHE
hold time
SCS40 to SCS43
IOL=-1mA, IOH=1mA)
SCK4,
SCS40 to SCS43
Unit
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
Remarks
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS deselect time
Value
Min
Slave mode
tCSDS*3-50
+5 tCLK_PERI1
(CL=50pF,
SCS deselect time
tCSDE
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS↓→SOT
tDSE
delay time
SCS↑→SOT
tDEE
delay time
SCS40 to SCS43,
IOL=-1mA, IOH=1mA)
SOT4
Master mode,
Round operation
SCK↓→SCS↓
tSCC
clock switch time
SCK4,
(CL=50pF,
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
3tCLK_PERI1+0
3tCLK_PERI1
+50
ns
(CL=20pF,
IOL=-1mA, IOH=1mA)
-
-
-
-
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
-
5
Mbps
-
6
Mbps
*1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
VOH
SCS output
VOL
VOL
t CSHI
t CSSI
SCK output
VOH
t CSDI
VOH
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
VIH
SCS input
VIL
VIL
t CSHE
t CSSE
VIH
SCK input
SOT
(Normal Sync
transfer)
t CSDE
t DEE
VOL
t DSE
SOT
(SPI compatible)
VIH
VOH
VOL
Slave mode
SCSx output
t SCC
SCSy output
SCK output
VOL
VOL
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are d ifferent value)
84
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-6) When the Serial Chip Select is Used (SCSCR:CSEN=1)
− Serial clock output signal detect level "L"(SMR, SCSFR:SCINV=1)
− Serial chip select inactive level "H"(SCSCR, SCSFR:CSLVL=1)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
SCS↓→SCK↑
tCSSI
setup time
SCK↓→SCS↑
tCSHI
hold time
Pin Name
SCK4,
SCS40 to SCS43
Conditions
Master mode
tCSDI
SCS↓→SCK↑
tCSSE
setup time
SCK↓→SCS↑
tCSHE
hold time
SCS deselect time
tCSDE
SCS↓→SOT
tDSE
delay time
SCS↑→SOT
tDEE
delay time
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
IOL=-1mA, IOH=1mA)
SCK4,
SCS40 to SCS43
Slave mode
(CL=50pF,
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS40 to SCS43,
Unit
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
3tCLK_PERI1+0
3tCLK_PERI1+50
ns
-
5
Mbps
-
6
Mbps
Remarks
(CL=50pF,
(CL=20pF,
SCS deselect time
Value
Min
IOL=-1mA, IOH=1mA)
SOT4
tCSDS*3-50
+5tCLK_PERI1
Master mode,
Round operation
SCK↑→SCS↓
tSCC
clock switch time
SCK4,
(CL=50pF,
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
-
-
-
-
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
*1: tCSSU =SCSTR:CSSU[7:0]  serial Chip select timing operation clock
*2: tCSHD=SCSTR:CSHD[7:0]  serial Chip select timing operation clock
*3: tCSDS=SCSTR:CSDS[15:0]  serial Chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
SCS output
VOH
VOL
t CSHI
VOL
t CSSI
VOH
t CSDI
VOH
SCK output
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
VIH
SCS input
VIL
t CSHE
VIL
t CSSE
VIH
t CSDE
VIH
SCK input
VIL
SOT
(Normal Sync
transfer)
VOL
t DSE
SOT
(SPI compatible)
t DEE
VOH
VOL
Slave mode
SCSx output
t SCC
SCSy output
SCK output
VOL
VOH
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are different value)
86
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-7) When the Serial Chip Select is Used (SCSCR:CSEN=1)
− Serial clock output signal detect level "H"(SMR, SCSFR:SCINV=0)
− Serial Chip select inactive level "L"(SCSCR, SCSFR:CSLVL=0)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
SCS↑→SCK↓
tCSSI
setup time
SCK↑→SCS↓
tCSHI
hold time
Pin Name
SCK4,
SCS40 to SCS43
Conditions
Master mode
tCSDI
SCS↑→SCK↓
tCSSE
setup time
SCK↑→SCS↓
tCSHE
hold time
SCS40 to SCS43
IOL=-1mA, IOH=1mA)
SCK4,
SCS40 to SCS43
Unit
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
Remarks
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS deselect time
Value
Min
Slave mode
tCSDS*3-50
+5tCLK_PERI1
(CL=50pF,
SCS deselect time
tCSDE
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS↑→SOT
tDSE
delay time
SCS↓→SOT
tDEE
delay time
SCS40 to SCS43,
IOL=-1mA, IOH=1mA)
SOT4
Master mode,
round operation
SCK↓→SCS↑
tSCC
clock switch time
SCK4,
(CL=50pF,
SCS40 to SCS43
IOL=-2mA,IOH=2mA),
3tCLK_PERI1+0
3tCLK_PERI1
+50
ns
(CL=20pF,
IOL=-1mA, IOH=1mA)
-
-
-
-
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
-
5
Mbps
-
6
Mbps
*1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
SCS output
VOH
VOH
VOL
t CSHI
t CSSI
SCK output
t CSDI
VOH
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
SCS input
VIH
VIH
VIH
SCK input
SOT
(SPI compatible)
VIL
t CSHE
t CSSE
SOT
(Normal Sync
transfer)
t CSDE
VIL
t DEE
VOL
t DSE
VOH
VOL
Slvae mode
SCSx output
t SCC
VOH
SCSy output
SCK output
VOL
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are different value)
88
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-1-8) When the Serial Chip Select is Used (SCSCR:CSEN=1)
− Serial clock output signal detect level "L"(SMR, SCSFR:SCINV=1)
− Serial Chip select inactive level "L"(SCSCR, SCSFR:CSLVL=0)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
SCS↑→SCK↑
tCSSI
setup time
SCK↓→SCS↓
tCSHI
hold time
Pin Name
SCK4,
SCS40 to SCS43
Conditions
Master mode
tCSDI
SCS↑→SCK↑
tCSSE
setup time
SCK↓→SCS↓
tCSHE
hold time
SCS40 to SCS43
IOL=-1mA, IOH=1mA)
SCK4,
SCS40 to SCS43
Unit
Max
tCSSU*1-50
-
ns
tCSHD*2+0
-
ns
-
ns
3tCLK_PERI1+30
-
ns
0
-
ns
3tCLK_PERI1+30
-
ns
-
40
ns
0
-
ns
Remarks
(CL=50pF,
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS deselect t time
Value
Min
Slave mode
tCSDS*3-50
+5tCLK_PERI1
(CL=50pF,
SCS deselect time
tCSDE
SCS40 to SCS43
IOL=-2mA, IOH=2mA),
(CL=20pF,
SCS↑→SOT
tDSE
delay time
SCS↓→SOT
tDEE
delay time
SCS40 to SCS43,
IOL=-1mA, IOH=1mA)
SOT4
Master mode,
Round operation
SCK↑→SCS↑
tSCC
clock switch time
SCK4,
(CL=50pF,
SCS40 to SCS43
IOL=-2mA,IOH=2mA),
3tCLK_PERI1+0
3tCLK_PERI1
+50
ns
(CL=20pF,
IOL=-1mA, IOH=1mA)
-
-
-
-
Transfer speed
CL=50pF,
IOL=-2mA, IOH=2mA
CL=20pF,
IOL=-1mA, IOH=1mA
-
5
Mbps
-
6
Mbps
*1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock
*2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock
*3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock
For details of *1, *2 and *3 above, see Hardware Manual.
Notes:
−
−
−
This is the AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to pins during testing.
The maximum baud rate is limited by the internal operation clock used and other parameters.
See Hardware Manual for details.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
SCS output
t CSDI
VOH
VOH
VOL
t CSHI
t CSSI
VOH
SCK output
VOL
SOT
(Normal Sync transfer)
SOT
(SPI compatible)
Master mode
SCS input
t CSDE
VIH
VIH
t CSHE
t CSSE
VIH
SCK input
SOT
(Normal Sync
transfer)
SOT
(SPI compatible)
VIL
VIL
VIL
t DEE
VOL
t DSE
VOH
VOL
Slave mode
SCSx output
t SCC
VOH
SCSy output
SCK output
VOH
Clock switching example by master mode round operation
(x, y = 40, 41, 42, 43: x and y are different value)
90
CONFIDENTIAL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(5-2) UART (Async Serial Interface) Timing (SMR:MD[2:0]=0b000, 0b001)
(5-2-1) When the External Clock is Selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
serial clock "L" pulse
width
serial clock "H" pulse
width
Pin Name
Value
Conditions
tSLSH
(CL=50pF,
tSHSL
SCK0 to SCK4
SCK fall time
tF
SCK rise time
tR
Max
tCLK_PERI1+10
-
ns
tCLK_PERI1+10
-
ns
-
5
ns
-
5
ns
(CL=20pF,
IOL=-1mA, IOH=1mA)
tR
SCK
IOL=-2mA, IOH=2mA),
tF
t SHSL
VIH
VIH
VIL
Unit
Min
Remarks
t SLSH
VIL
VIH
VIL
When the external clock is selected
(5-3) LIN Interface (v2.1) (LIN Communication Control Interface (v2.1)) Timing
(SMR:MD[2:0]=0b011)
(5-3-1) When the External Clock is Selected (BGR:EXT=1)
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
serial clock "L" pulse
width
serial clock "H" pulse
width
Symbol
Pin Name
tSLSH
(CL=50pF,
tSHSL
SCK0 to SCK4
SCK fall time
tF
SCK rise time
tR
IOL=-2mA, IOH=2mA),
(CL=20pF,
IOL=-1mA, IOH=1mA)
tR
SCK
Value
Conditions
VIL
tF
t SHSL
VIH
VIH
Unit
Min
Max
tCLK_PERI1+10
-
ns
tCLK_PERI1+10
-
ns
-
5
ns
-
5
ns
Remarks
t SLSH
VIL
VIL
VIH
When the external clock is selected
May 15, 2015, MB9D560_DS708-00001-3v0-E
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D a t a S h e e t
(6) Timer Input Timing
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Value
Conditions
Unit
Min
Max
4tCLK_PERI1
-
ns
-
ns
Remarks
IN16 to IN21,
TIOA0 to TIOA11,
-
TIOB0 to TIOB11
-
FRCK12 to FRCK17
Input pulse width
FRCK0 to FRCK1,
tTIWL
FRCK4 to FRCK5
4tCLK_PERI4<70ns
70
4tCLK_PERI5≥70ns
4tCLK_PERI5
IN0 to IN3,
tTIWH,
4tCLK_PERI4≥70ns
4tCLK_PERI4
IN4 to IN14,
FRCK6 to FRCK10,
-
-
ns
4tCLK_PERI5<70ns
70
4tCLK_PERI5≥70ns
4tCLK_PERI5
AIN0, BIN0, ZIN0
-
-
AIN2, BIN2, ZIN2
ns
70
4tCLK_PERI5<70ns
4tCLK_PERI4
4tCLK_PERI4≥70ns
-
70
ns
4tCLK_PERI4<70ns
− Timer input timing
INx
FRCKx
TIOAx,TIOBx
AINx,BINx,ZINx
92
CONFIDENTIAL
tTIWH
VIH
tTIWL
VIH
VIL
VIL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(7) Trigger Input Timing
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
INT0 to INT7
RX0 to RX2
ADTG0,
DTTI2 to DTTI3
tTRGH,
width
tTRGL
Unit
Max
-
200
-
ns
-
5tCLK_SYSCPD1
-
ns
-
5tCLK_PERI6
-
ns
-
ns
5tCLK_PERI5
4ADTG0,
Input pulse
Value
Min
-
DTTI0
4ADTG1,
5tCLK_PERI5≥70ns
70
5tCLK_PERI5<70ns
5tCLK_PERI4
5tCLK_PERI4≥70ns
-
-
DTTI1
Remarks
ns
70
5tCLK_PERI4<70ns
INT0 to INT7,
ADTG0,
4ADTG0, 4ADTG1,
-
1
-
µs
When stop mode
RX0 to RX2,
DTTI0 to DTTI3
− Trigger input timing
INTx
ADTGx
RXx
4ADTGx
DTTIx
VIH
May 15, 2015, MB9D560_DS708-00001-3v0-E
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tTRGL
tTRGH
VIH
VIL
VIL
93
D a t a S h e e t
(8) NMI Input Timing
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS= AVSS= RVSS=0.0V)
Parameter
Symbol
Pin Name
Conditions
tNMIL
NMIX
-
Input pulse width
Value
Min
Max
200
-
Unit
Remarks
ns
− NMIX input timing
tNMIL
NMIX
VIH
VIH
VIL
94
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VIL
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
(9) External Low-Voltage Detection
Parameter
Power supply voltage
range
Detection voltage
Symbol
Pin Name
Conditions
VDP5
VCC5
VDL
VCC5
(TA: Recommended operating conditions, VSS=AVSS=RVSS=0.0V)
Value
Unit
Min
Typ
Max
-
-
-
5.5
V
*1
3.7
3.9
4.1
V
Remarks
−
When power supply voltage falls
−
The original setting of detection
level is 4.1V±0.2V
Hysteresis width
Low voltage detection
time
Power supply voltage
fluctuation rate
VHYS
VCC5
-
75
100
150
mV
Td
-
-
-
-
30
µs
-
VCC5
-
-4
-
-
V/ms
−
When power supply voltage rises
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than
the low-voltage detection time (Td), there is the possibility to generate or release after the power supply
voltage has exceeded the detection voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VDL), be sure to suppress
fluctuation of the power supply within the limits of the power supply voltage fluctuation rate.
(10) Internal Low-Voltage Detection
Parameter
Symbol
Pin Name
Conditions
VRDP5
VCC12
Detection voltage
VRDL
Hysteresis width
Power supply voltage
range
Low voltage detection
time
Power supply voltage
fluctuation rate
(TA: Recommended operating conditions, VSS=AVSS=RVSS=0.0V)
Value
Unit
Remarks
Min
Typ
Max
-
-
-
1.3
V
VCC12
*1
0.8
0.9
1.0
V
−
When power supply voltage falls
VRHYS
VCC12
-
20
30
50
mV
−
When power supply voltage rises
TRd
-
-
-
-
30
µs
-
VCC12
-
-4
-
-
V/ms
*2
*1: If the fluctuation of the power supply has exceeded the detection voltage range within the time less than
the low-voltage detection time (TRd), there is the possibility to generate or release after the power supply
voltage has exceeded the detection voltage range.
*2: In order to perform the low-voltage detection at the detection voltage (VRDL), be sure to suppress
fluctuation of the power supply within the limits of the power supply voltage fluctuation rate.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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13.5 A/D Converter
(1) Electrical Characteristics
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Resolution
-
Non linearity error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-4.0
-
+4.0
LSB
-
-
-1.9
-
+1.9
LSB
VZT
AN0 to AN31
VFST
AN0 to AN31
Sampling time
tSMP
-
0.3
-
12
µs
*1
Compare time
tCMP
-
0.7
-
28
µs
*1
A/D conversion time
tCNV
-
1.0
-
40
µs
*1
IAIN
AN0 to AN31
-2.0
-
2.0
µA
VAVSS≤VAIN≤VAVCC
Differential linearity
error
Zero transition
voltage
Full-scale transition
voltage
Analog port input
current
Analog input voltage
Reference voltage
-1.5LSB-20
-
AVRL
+0.5LSB+20
AVRH
-1.5LSB+20
mV
1LSB=(VFST-VZT)/4094
mV
VAIN
AN0 to AN31
AVSS
-
AVRH
V
AVRH2
4.5
-
5.5
V
AVRL
AVRL2
-
0.0
-
V
-
500
680
µA
-
-
17.7
µA
-
1
2
mA
-
-
2.16
µA
-
-
4
LSB
Power supply
IAH
current
IR
AVCC2
AVRH2
IRH
channels
AVRH
-
AVRH
IA
Variation between
AVRL
+0.5LSB-20
-
AN0 to AN31
AVCC≥AVRH
*2
*2
*1: Time for each channel.
*2: The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and CPU is
stopped.
(2) Notes on Using A/D Converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient.
In this case, it is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin.
− Analog input circuit model
Comparator
Analog input
R
C
Sampling ON
12bit A/D
R
3.0kΩ (max)
C
8.30pF (max) (4.5V ≤ AVcc ≤ 5.5V)
Note: Listed values must be considered as reference values.
96
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13.6 4 Channels Same Time Sampling A/D Converter
(1) Electrical Characteristics
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Symbol
Pin Name
Resolution
-
Non linearity error
Value
Unit
Remarks
Min
Typ
Max
-
-
-
12
bit
-
-
-4.0
-
+4.0
LSB
-
-
-1.9
-
+1.9
LSB
VZT
4AN0 to 4AN7
VFST
4AN0 to 4AN7
Sampling time
tSMP
-
0.6
-
1.2
µs
*1
Compare time
tCMP
-
1.4
-
5.6
µs
*2
A/D conversion time
tCNV
-
2
-
6.8
µs
*3
IAIN
4AN0 to 4AN7
-0.7
-
0.7
µA
VAVSS≤VAIN≤VAVCC
Differential linearity
error
Zero transition
voltage
Full-scale transition
voltage
Analog port input
current
Analog input voltage
Reference voltage
current
AVRH
-1.5LSB-20
-
AVRL
+0.5LSB+20
AVRH
-1.5LSB+20
mV
1LSB=(VFST-VZT)/4094
mV
VAIN
4AN0 to 4AN7
AVSS
-
AVRH
V
AVRH
AVRH0, AVRH1
4.5
-
5.5
V
AVRL
AVRL0, AVRL1
-
0.0
-
V
-
1.0
1.5
mA
1 unit operation
-
-
27.5
µA
1 unit operation*4
-
0.5
4.0
mA
1 unit operation
-
-
4.5
µA
1 unit operation*4
IA
Power supply
AVRL
+0.5LSB-20
IAH
IR
IRH
AVCC0, AVCC1
AVRH0, AVRH1
Variation between
-
4AN0 to 4AN3
-
-
20
mV
channels
-
4AN4 to 4AN7
-
-
20
mV
AVCC≥AVRH
*1: 4 channels same time sampling time.
*2: Compare time for 4 channels.
*3: Conversion time for 4 channels.
*4: The power supply current (VCC=AVCC=5.0V) is specified if the A/D converter is not operating and CPU is
stopped.
May 15, 2015, MB9D560_DS708-00001-3v0-E
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97
D a t a S h e e t
(2) Notes on Using A/D converter
<About the output impedance of the analog input of external circuit>
When the external impedance is too high, the sampling time for analog voltages may not be sufficient.
In this case, it is recommended to connect the capacitor (approx. 0.1 µF) to the analog input pin.
− Analog input circuit model
Comparator
Analog input
R
C
Sampling ON
4-SH 12bit A/D
R
3.8kΩ (max)
C
8.30pF (max) (4.5V ≤ AVcc ≤ 5.5V)
Note: Listed values must be considered as reference values.
98
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MB9D560_DS708-00001-3v0-E, May 15, 2015
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(12-3) Definition of Terms
Resolution: Analog variation that is recognized by an A/D converter.
Linearity error: Deviation of the actual conversion characteristics from a straight line that connects the zero
transition point ("0000 0000 0000" ←→ "0000 0000 0001") to the full-scale transition point ("1111 1111 1110"
←→ "1111 1111 1111").
Differential linearity error: Deviation of the input voltage from the ideal value that is required to change the
output code by 1LSB.
Linearity error
Differential linearity error
FFF
Digital output
FFD
N+1
VFST
(Actuallymeasured
value)
004
VNT
(Actually-measured value)
003
002
Actual conversion
characteristics
Digital output
FFE
Ideal characteristics
Actual conversion
characteristics
{1 LSB (N - 1) + VZT}
Actual conversion
characteristics
N
N-1
V(N+1)T
VNT
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
N-2
001
Actual conversion
characteristics
VZT (Actually-measured value)
AVSS
(AVRL)
Analog input
AVRH
AVSS
(AVRL)
Analog input
AVRH
VNT - {1LSB×(N-1) + V ZT}
[LSB]
1LSB
V(N + 1)T - VNT
Differential linearity error of digital output N =
-1 LSB [LSB]
1LSB
VFST - VZT
1LSB =
[V]
4094
Linearity error of digital output N =
VZT: Voltage at which the digital output changes from "0x000" to "0x001".
VFST: Voltage at which the digital output changes from "0xFFE" to "0xFFF".
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13.7 Flash Memory
Value
Parameter
Min
Typ
Max
-
200
800
Unit
ms
-
300
1100
ms
-
400
2000
ms
Sector erase time
Remarks
8K Byte sector*1
Excluding internal preprogramming time
8K Byte sector *1
Including internal preprogramming time
64K Byte sector *1
Excluding internal preprogramming time
64K Byte sector *1
-
700
3700
ms
8bit writing time
-
9
288
µs
Excluding overhead time at system level*1
16bit writing time
-
12
384
µs
Excluding overhead time at system level*1
ECC writing time
-
9
288
µs
Excluding overhead time at system level*1
-
-
-
Erase cycle *2/
Data retention time
1,000 times /20 years,
10,000 times /10 years,
100,000 times / 5 years
Including internal preprogramming time
Temperature at writing/erasing
Average temperature TA=+85°C*3
*1: The guaranteed value for erase up to 100,000 cycles
*2: Number of erase cycles for each sector
*3: This value comes from the technology qualification (using Arrhenius equation to translate high
temperature measurements into normalized value at + 85°C).
Notes:
−
−
100
CONFIDENTIAL
While the Flash memory is written or erased, shutdown of the external power supply (VCC, VDD) is
prohibited.
In the application system where VCC or VDD might disappear while writing, be sure to turn the power
off by using an external low-voltage detector and NMIX pin + RSTX pin for reset input at same time.
Concretely, please execute two of the following.
1. After simultaneous input from the NMIX and RSTX pins while VDD is within the recommended
operating range, maintain VDD within the recommended operating range for at least 60 µs.
2. After simultaneous input from the NMIX and RSTX pins while VCC is within the recommended
operating range, power off VCC in observance of the standard regarding the supply voltage
fluctuation rate of the external low-voltage detector.
MB9D560_DS708-00001-3v0-E, May 15, 2015
D a t a S h e e t
13.8 R/D Converter
(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)
Parameter
Output voltage(amplitude)
Excitation signal
Output voltage(displacement)
output
output current
Frequency
Resolver response
signal*1
Excitation input
Amplitude
Maximum input frequency
Phase difference from resolver
detection signal
Angle accuracy
(conversion accuracy)
Resolution
Output delay
Angular velocity
Resolution
voltage
AREF2 output voltage
Tracking loop characteristics
(0dB cross frequency)
Tracking loop characteristics
(-3dB cross frequency)
Operating
characteristics
Max
Unit
0.4VCC-1%
0.4VCC
0.4VCC+1%
V
-0.4VCC+(VCC/2)
-
0.4VCC+(VCC/2)
V
-
-
1
mA
Remarks
-
10 or 20
-
kHz
AREF20-2.0
-
AREF20+2.0
V
Unit0
AREF21-2.0
-
AREF21+2.0
V
Unit1
-
-
24
kHz
0
-
RVCC0
V
0
-
RVCC1
V
-45
-
45
°
-4
-
4
LSB
-
12
-
bit
1.1
-
2.1
µs
-
-
4000
rps
Maximum Angular velocity
output
Reference output
Typ
Amplitude
signal*2
Angle output
Value
Min
-
-
3000
rps
rps/LSB
Setting with the register
Unit0
More than 2Vp-p
Unit1
More than 2Vp-p
Variation when
Pausing: ±1LSB
When bandwidth
1.8 kHz mode
When bandwidth
600 kHz mode
-
0.261
-
RVCC0/2-3%
-
RVCC0/2+3%
V
Unit0
RVCC1/2-3%
-
RVCC1/2+3%
V
Unit1
-
-
1.2
kHz
-
-
400
Hz
-
-
1.8
kHz
-
-
600
Hz
-
-
4000
rps
Maximum tracking rate
-
-
3000
rps
-
-
4
ms
-
-
12
ms
-
-
1,000,000
rad/s2
-
-
150,000
rad/s2
Settling time (179 degree step)
Maximum angular velocity
When bandwidth
1.8 kHz mode*3
When bandwidth
600 Hz mode*3
When bandwidth
1.8 kHz mode*3
When bandwidth
600 Hz mode*3
When bandwidth
1.8 kHz mode
When bandwidth
600 Hz mode
When bandwidth
1.8 kHz mode
When bandwidth
600 Hz mode
When bandwidth
1.8 kHz mode
When bandwidth
600 Hz mode
*1: Corresponding pin: COS_PLUS, COS_MINUS, SIN_PLUS, SIN_MINUS
*2: Corresponding pin: MAG_PLUS, MAG_MINUS
*3: When signal amplitude is nominal
May 15, 2015, MB9D560_DS708-00001-3v0-E
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101
D a t a S h e e t
14. Ordering Information
Part Number
Package
MB9DF564MxEEQ-GTE1
208-pin plastic TEQFP
MB9DF565MxEEQ-GTE1
(LER208)
MB9DF566MxEEQ-GTE1
MB9DF564LxEEQ-GTE1
176-pin plastic TEQFP
MB9DF565LxEEQ-GTE1
(LEP176)
MB9DF566LxEEQ-GTE1
Notes:
−
"x" is option number. This option is following table. The detail of package, see "16. Package
Dimensions".
15. Part Number Option
Part Number Option
R/D Converter
FlexRay
Key Code
A

-
-
G


-
L
-
-
-
Q
-

-
: Supported
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16. Package Dimensions
May 15, 2015, MB9D560_DS708-00001-3v0-E
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103
D a t a S h e e t
104
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D a t a S h e e t
17. Major Changes
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
11
3. Product Lineup
Add 176 pin product
14, 15
4. Pin Assignment
Add 176 pin product
16 to 33
5. Pin Description
Add 176 pin product
46, 47
10. Memory Map
Add address information of MB9DF564 and MB9DF565
54, 55
12. Pin Statuses in CPU Status
102
14. Ordering Information
103, 104
16. Package Dimensions
Add 176 pin product
Change package name
Add 176 pin product
Change package dimensions
Add 176 pin product
Revision 3.0
102
15. Part Number Option
May 15, 2015, MB9D560_DS708-00001-3v0-E
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Add part number option L, Q
105
D a t a S h e e t
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May 15, 2015, MB9D560_DS708-00001-3v0-E
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed,
developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high
safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical
damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport
control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is
intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third
party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices
have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety
design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and
other abnormal operating conditions. If any products described in this document represent goods or technologies subject to
certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration
Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be
required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion
product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the
information in this document.
®
®
®
TM
Copyright © 2014-2015 Cypress
All rights reserved. Spansion , the Spansion logo, MirrorBit , MirrorBit Eclipse ,
TM
TM
TM
ORNAND , Easy DesignSim , Traveo and combinations thereof, are trademarks and registered trademarks of Spansion
LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of
their respective owners.
108
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MB9D560_DS708-00001-3v0-E, May 15, 2015