S6J3110 / S6J3120 Series
How to Set up The Clock System
32-Bit Microcontroller
Spansion®Traveo™ Family
APPLICATION NOTE
Publication Number S6J3110_AN708-00014
CONFIDENTIAL
Revision 2.0
Issue Date July 31, 2015
v1.1
A P P L I C A T I O N
N O T E
Target Products
This application note is described about below products;
Series
2
CONFIDENTIAL
Product Number (Not Included Package Suffix)
S6J3110 series
S6J3118, S6J3119, S6J311A, S6J311B, S6J311C, S6J311D, S6J311E
S6J3120 series
S6J3128, S6J3129, S6J312A
S6J3110_AN708-00014-2v0-E, July 31, 2015
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Table of Contents
1.
2.
3.
4.
5.
Introduction ..................................................................................................................................... 6
Overview ........................................................................................................................................ 7
Clock Setting Procedure ............................................................................................................... 12
3.1
Clock Setting Procedure for RUN Configuration ............................................................... 12
3.1.1
RUN Profile Configuration ................................................................................ 12
3.1.2
RUN Profile Settings Update ............................................................................ 13
3.2
Clock Setting Procedure for PLL Configuration ................................................................. 15
3.2.1
Enable Setting of the Source Clock .................................................................. 15
3.2.2
Source Clock Timer Setting .............................................................................. 16
3.2.3
Clock Gear ....................................................................................................... 16
3.2.4
PLL Clock Multiplier and Divider ....................................................................... 17
3.2.5
Source Clock for the Clock Domain 0 ............................................................... 17
3.3
Clock Setting Procedure of Sample Software ................................................................... 18
Reference ..................................................................................................................................... 23
Major Changes ............................................................................................................................. 24
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Figures
Figure 2-1 Clock System Block Diagram .................................................................................................... 7
Figure 2-2 Clock Generator Block Diagram ................................................................................................ 8
Figure 2-3 PLL Clock Generator ................................................................................................................. 8
Figure 2-4 Clock Distributor Block Diagram (Clock Domain 0) ................................................................. 10
Figure 2-5 Clock Distributor Block Diagram (Clock Domain MCUC) ......................................................... 11
Figure 3-1 Setting Procedure Example for RUN Configuration ................................................................ 12
Figure 3-2 State Transition Diagram......................................................................................................... 13
Figure 3-3 Setting Procedure Example for Using PLL clock ..................................................................... 15
Figure 3-4 Clock Setting Example Using PLL in Sample Software (start.c).............................................. 18
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Tables
Table 2-1 Example of PLL Clock Configuration .......................................................................................... 9
Table 3-1 Source Clock Oscillation Enabled Setting Example .................................................................. 16
Table 3-2 Source Clock Timer Setting ...................................................................................................... 16
Table 3-3 Clock Gear Setting ................................................................................................................... 16
Table 3-4 PLL Clock Multiplier and Divider Setting Example .................................................................... 17
Table 3-5 Clock Domain 0 Source Clock Setting Example ....................................................................... 17
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1.
N O T E
Introduction
This application note describes clock setting and usage for S6J3110 / S6J3120 Series.
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2. Overview
This section explains the overview of clock system.
Figure 2-1 shows clock system diagram. Clock system is composed of 3 modules:
-
Clock Generator
-
Clock Controller
-
Clock Distributer
Figure 2-1 Clock System Block Diagram
Clock Controller
Clock Distributer
Clock Domain 0
External input
X0
Clock Domain TRC
Clock Generator
Fast-CR clock
Clock Domain x
(X=1,2,3…)
Fast-CR clock
X1
Slow-CR clock
Slow-CR clock
X0A
Main clock
X1A
Main clock
Clock Domain HSSPI
Internal Function
- CPU
- Flash
- SHE
- Peripherals
…
Sub clock
Sub clock
PLLx clock
Clock Domain MCUC
PLL clock
SSCG PLLx clock
Clock Domain CLKO
SSCG PLL clock
Clock Controller
Clock controller generates control signal from configuration register value for clock system.
Clock Generator
Figure 2-2 shows clock generator block diagram. Clock generator generates source clock from
external/internal oscillation circuit.
S6J3110 / S6J3120 series supports several type of clock source as below.
- Main clock: 4MHz
- Fast-CR clock: 4MHz
- Slow-CR clock: 100kHz
All clock sources have source clock timer for masking clock output until the end of the clock oscillation
stabilization wait time. For low power operation, user can be set clock gating to allow clock shut off for
internal circuit.
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Figure 2-2 Clock Generator Block Diagram
Clock Generator
Clock Source
Source Clock Timer
Fast-CR
Oscillation
circuit
4MHz
100KHz
X1
X0A
X1A
Source Clock
EN
Fast-CR Clock
IN
Slow-CR
Timer
Slow-CR
Oscillation
circuit
SCROSCRDY
Main
Timer
Main Clock
Oscillation
circuit
MOSCRDY
CLK
OUT
GATE
CR
Calibration
Divider
(1/40)
EN
IN
4MHz
X0
Clock Gating
CROSCRDY
Fast-CR
Timer
EN
IN
CLK OUT
GATE
CLK
GATE OUT
Slow-CR Clock
Clock
Supervisor
CSV
Main Clock
CSV
SOSCRDY
Sub
Timer
Sub Clock
Oscillation
circuit
EN
IN
1/2
CLK
GATE
SEL
Main clock /
Main clock * 1/2
CSV
Sub Clock
OUT
CSV
32kHz
PLL Clock Generator
PLL0 Clock
PLL0 circuit
PLL0 circuit
PLL0 circuit
PLL circuit
CAN PLL Clock
SSCG Clock Generator
SSCG PLL0 Clock
SSCG PLL circuit
SSCG
SSCGPLL
PLLcircuit
circuit
SSCG PLL circuit
*S6J3110 / S6J3120 series does not support Sub Oscillator
Clock generator block has several PLL multiplier circuit. Main clock or Fast-CR clock are source of PLL
clock generator. In case of using PLL clock, need to select the PLL clock divider and multiplication by
setting the register such as PLLDIVL and PLLDIVN and PLLDIVM. Figure 2-3 shows the PLL clock
generator block diagram and Table 2-1 shows the example of PLL clock setting.
Figure 2-3 PLL Clock Generator
PLLDIVM: PLL clock M divider
(13, 14, 15, ..., 199, 200)
PLLDIVL: PLL input clock divider
(1, 2, 4, 6)
PLLDIVN: PLL source clock N-multiplication factor
(13, 14, 15, ..., 199, 200)
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Table 2-1 Example of PLL Clock Configuration
Input
Input clock DIV
clock
Configuration
PLLin
PLL Multiplier
Configuration
PLLout
Output Divider
Configuration
(Set by PLLDIVL)
(Set by PLLDIVN)
(Set by PLLDIVM)
PLL Clock
Part Number
4MHz
1
4MHz
144
576MHz
4
144MHz
S6J311B, S6J311C, S6J311D, S6J311E
4MHz
1
4MHz
120
480MHz
4
120MHz
S6J311B, S6J311C, S6J311D, S6J311E
4MHz
1
4MHz
112
448MHz
4
112MHz
S6J311B, S6J311C, S6J311D, S6J311E,
S6J3128, S6J3129, S6J312A
S6J311B, S6J311C, S6J311D, S6J311E,
4MHz
1
4MHz
144
576MHz
6
96MHz
S6J3118, S6J3119, S6J311A
S6J311B, S6J311C, S6J311D, S6J311E,
4MHz
1
4MHz
120
480MHz
6
80MHz
S6J3118, S6J3119, S6J311A,
S6J3128, S6J3129, S6J312A
S6J311B, S6J311C, S6J311D, S6J311E,
4MHz
1
4MHz
120
480MHz
12
40MHz
S6J3118, S6J3119, S6J311A,
S6J3128, S6J3129, S6J312A
Notes:
−
−
Make the input clock frequency division setting so that the PLL input clock (PLLin) is at 4 MHz
Permission range of PLL output clock (PLLout) is different for each product. Make the multiplication
setting so that the PLL output clock (PLLout) is within the following.
S6J3118, S6J3119, S6J311A, S6J311B, S6J311C, S6J311D, S6J311E: 400MHz to 576MHz
S6J3128, S6J3129, S6J312A: 400MHz to 512MHz
−
Maximum of PLL clock is different for each product.
S6J311B, S6J311C, S6J311D, S6J311E: 144MHz
S6J3118, S6J3119, S6J311A: 96MHz
S6J3128, S6J3129, S6J312A: 112MHz
For more information, refer to the Datasheet and Hardware Manual for each product.
−
Clock Distributor
Clock distributor has source clock selector and clock divider for each clock domain.
S6J3110 / S6J3120 series has the following clock domains and the only 1 source clock is selected for
each clock domain. Each clock domain uses the selected source clock and divided clock of source
clock is distributed as internal operating clock.
- Clock Domain 0 (CD0)
- Clock Domain 1/2/3/4/5 (CD1/CD2/CD3/CD/4/CD5) *S6J3120 series only
- TRC Clock Domain (CD_TRC)
- HSSPI Clock Domain (CD_HSSPI) *S6J3120 series only
- MCUC Clock Domain (CD_MCUC)
- CLKO Clock Domain (CD_CLKO)
Figure 2-4 and Figure 2-5 shows clock distributer block of Clock Domain 0 and MCUC Clock Domain of
S6J3110 series. After the source clock is selected, divided clock of source clock is distributed as
internal operating clock. As for detail of clock domain block and maximum frequency of internal clock,
refer to the Datasheet and Hardware Manual of each product.
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Figure 2-4 Clock Distributor Block Diagram (Clock Domain 0)
Source Clock
<Internal Clock>
GATE
Divider
Slow-CR Clock
GATE
(1/2/3/4/5/6/7/8)
Divider
Main Clock
CPU
GATE
(1/2/3..31/32)
Fast-CR Clock
CLK_SHE
TC Flash
Work Flash
CLK_ATB
ETB
(Trace buffer)
CLK_DBG
Divider
Main Clock/
Main clock * 1/2
GATE
(1/2/4/8)
Divider
GATE
GATE
GATE
(1/2/3/4/5/6/7/8)
SHE
CLK_FCLK
GATE
(1/2/4/8)
Selector
<Internal Function>
CLK_CPU
Divider
CLK_HPM
CLK_DMA
CLK_MEMC
DEBUG
SRAM
I/O, DMA
IRC, BootROM
CLK_HPM2
Divider
PLL0 Clock
CLK_SYSC1
Divider
GATE
(1/2/3..15/16)
CLK_HAPP0A0
Divider
GATE
(1/2/3..15/16)
Divider
SSCG PLL0 Clock
(1/2/3..15/16)
GATE
(1/2/3..15/16)
Divider
(1/2/3..15/16)
Divider
(1/2/4/8)
Divider
(1/2/3..15/16)
S Divider
E (1/2/3..31/32)
L
Divider
(1/2/3..15/16)
S Divider
E (1/2/3..31/32)
L
Divider
(1/2/3..15/16)
S Divider
E (1/2/3..31/32)
L
Divider
(1/2/3..15/16)
S Divider
E (1/2/3..31/32)
L
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CLK_HAPP0A1
GATE
CLK_HAPP1B0
Divider
CD0CSL[2:0]
DEBUG
GATE
(2)
System
controller
None
None
None
CLK_HAPP1B1
None
GATE
CLK_LCP
CAN FD
GATE
GATE
CLK_LCP0
CLK_LCP0A
GATE
CLK_LCP1
GATE
CLK_LCP1A
GATE
CLK_LAPP0
GATE
None
Timer
Multi Function Serial
A/DC
None
None
None
CLK_LAPP0A
GATE
None
CLK_LAPP1
GATE
None
CLK_LAPP1A
GATE
None
* “None” means no connection to internal functions.
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Figure 2-5 Clock Distributor Block Diagram (Clock Domain MCUC)
<Internal Clock> <Internal Function>
Source Clock
CLK_SYSC0H
Divider
GATE
(1/2/3..31/32)
Fast-CR Clock
Slow-CR Clock
Main Clock
CLK_COMH
Main Clock/
Main clock * 1/2
CLK_RAM0H
Selector
CLK_RAM1H
Divider
(1/2/3..15/16)
GATE
MCU Config G
- LVD
- CSV
- RTC
- EXTIRQ
- NMI
- H/W
WDG
RAM ECC
Backup RAM 0
Backup RAM 1
CLK_SYSC0P
None
PLL0 Clock
CLK_COMP
None
* “None” means no connection to internal functions.
SSCG PLL0 Clock
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3. Clock Setting Procedure
3.1
Clock Setting Procedure for RUN Configuration
The Example of clock setting procedure for RUN configuration is described in Figure 3-1.
Figure 3-1 Setting Procedure Example for RUN Configuration
Power On
: Hardware operation
Release reset
: Software setting
Fast-CR clock generation: enable (Initial)
Wait for clock stabilization
Fast-CR clock ready
Start Fast-CR operation
RUN profile registers configuration
Start updating RUN profile
Trigger RUN profile update
(Write to “0xAB”to SYSC_TRGRUNCNTR)
Set up the RUN profile registers
configuration
RUN operation
Change the configuration
Microcontroller operates in the Fast-CR clock after power-on. In case of changing the system clock
frequency, it is necessary to set to the RUN profile by software setting.
3.1.1
RUN Profile Configuration
This product supports 2 states operation and has a wide variety of power consumption settings.
- RUN (Normal operation):
This is the state in which the CPU is operating programs.
The CPU operates in this state (programs are operating) after an initialization reset.
In this state, a RUN profile update and a transition to PSS are possible.
- PSS (Power Saving State):
This is the state in which the CPU has stopped programs and can set low power consumption.
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Figure 3-2 State Transition Diagram
For each RUN/PSS states, following items related clock system can be configured. These can be set by the
RUN profile register or PSS profile register. In case of changing the clock setting, it is necessary to update
the profile.
3.1.2
-
Source clock oscillation enable/stop
-
Clock domain control (source selection, division, and oscillation enable and stop of each domain clock)
RUN Profile Settings Update
Setting is not only reflected in the writing to the register in case of changing RUN / PSS profile setting
parameters. It is necessary to do the following steps to reflect the setting of RUN profile.
1.
2.
3.
4.
Write the settings to the register.
Clear the RUN profile update completion flag at system status flag and interrupt clear register
(SYSC0_SYSICLR).
Write "0xAB" to the RUN profile update trigger register of the system controller
(SYSC0_TRGRUNCNTR).
Poll the RUN profile update completion flag bit of System Status Register (SYSC0_SYSSTSR:
RUNDF0 bit), and wait until the completion of profile update (RUNDF0 = "1").
If the contents of the new RUN profile do not have any problems, the control circuit will reflect the contents of
the profile, as follows.
1.
2.
"1" is set in the system status register (SYSC0_SYSSTSR: RUNSTS0).
The contents of the RUN profile are copied to the APPLIED profile.
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3.
Reflect the following setting in order
−
−
−
−
−
4.
5.
N O T E
Clock oscillation enable/stop (including waiting for oscillation stabilization)
Clock supervisor setting changes
LVD setting changes
Clock operation settings (source clock changes, division, and ON/OFF of each clock source)
Clock stop settings (source clock stop)
When RUN profile update is completed, the system status register (SYSC0_SYSSTSR: RUNSTS0)
is cleared to "0".
"1" is set in the system status register (SYSC0_SYSSTSR: RUNDF0).
If present setting is problems, Profile error occurs, system error interrupt factor register 1
(SYSC0_SYSERRIR1: RUNERRIF0) is set to “1”. In this case, the contents of the new profile are discarded,
and the circuit operates with the contents of the profile currently in use.
<Note>
Profile Update is prohibited during the profile update. If the profile update again while profile is being
updated, a system error interrupt (SYSC0_SYSERRIR1: RUNTRGERRIF) will be generated, and the
attempted update profile will be disabled.
Before updating the RUN profile, it is necessary to confirm the flag of the profile status register
(SYSC0_SYSPROSTSR:RUNPSTS) is already cleared. When it is updated the RUN profile during a
profile error status, an NMI interrupt will be generated, and the RUN profile settings will be discarded.
During RUN profile update, it is prohibited to write access to RUN profile register group. A write access is
made to the RUN profile register group during a RUN profile update. The write data will be disabled and
Bus error will be occurred.
For more information about profile setting and operation, refer to the chapter LOW POWER
CONSUMPTION of Hardware manual.
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3.2
N O T E
Clock Setting Procedure for PLL Configuration
Figure 3-3 show the Setting procedure example for using PLL clock. After RUN profile settings, the
frequency of the system clock change gradually by operating the clock gear.
Figure 3-3 Setting Procedure Example for Using PLL clock
Power On
: Software setting
PLL/SSCG stabilization time
register configuration
(SYSC_PLLSSCGSTCNTR)
Clock gear control register
configuration
(SYSC_PLLxCGCNTR)
RUN profile update
RUN operation by PLL clock
Clock gear up start
(SYSC_PLLxCGCNTR)
(PLLCGSTR = 1'b1)
Check gear status
SYSC_PLLx CGCNTR (x=0/1/2/3)
Read PLLCGSTS[1:0]
No
PLLCGSTS[1:0] = 2'b10 ?
Yes
RUN operation
3.2.1
Enable Setting of the Source Clock
After the hardware reset, the source clocks from the external/built-in oscillation circuits (fast-CR circuit clock,
slow-CR clock and main clock/main clock divided by 2) enter the oscillation-enabled state. Conversely, the
PLL clock enters the oscillation-disabled state. It is necessary to enable the oscillation of the PLL clock in
case of using PLL and changing the source clock of the system clock to the PLL clock.
To enable PLL oscillation, the oscillation for the main clock must already be enabled. If the oscillation for the
main clock has not been enabled, a profile error occurs.
It can be set to enable the oscillation of the corresponding clock during RUN by writing "1" to the bits of
register shown in the Table 3-1. However, control for enabling/disabling the source clock oscillation is
available only when the system is not using the source clock. The Fast-CR clock/Slow-CR clock oscillation
cannot be disabled in RUN.
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Table 3-1 Source Clock Oscillation Enabled Setting Example
Register abbreviation
Bit name
Value (decimal)
Settings
PLLxEN
Enable PLLx clock oscillation
1
MOSCEN
Enable Main clock oscillation
1
SCROSCEN
Enable Slow-CR clock oscillation
1
CROSCEN
Enable Fast-CR clock oscillation
1
SYSC0_RUNCKSRER
3.2.2
Source Clock Timer Setting
The source clock timer is a timer for gating the clock output until the end of the clock oscillation stabilization
wait time. In order to use the source clock timer, it is necessary to set Table 3-2 register.
Table 3-2 Source Clock Timer Setting
Register abbreviation
Bit name
Settings
Select the division ratio of the input clock of the
PSCL
main clock timer.
SYSC_MOCTCPR
CMPR
The compare value of the main clock timer.
SYSC_ MOCTTRGR
CGCPT
Change the timer settings / Start the timer counting.
SYSC_PLLSSCGSTCNTR
PLLSTABS
PLL stabilization wait time selection.
3.2.3
Clock Gear
Clock Gear outputs the gear clock gradually changed by the step-by-step outputting of the input clock, so it
is possible to shift the operating frequency gradually. The frequency fluctuates abruptly at the time of
switching from the main clock to the PLL clock, so the power supply current also fluctuates considerably. A
clock gear operation is necessary to prevent overshoot/undershoot of the power supply current at the clock
switching time.
In order to use the clock gear, it is necessary to set the register of Table 3-3.
Table 3-3 Clock Gear Setting
Register abbreviation
Bit name
PLLCGLP
PLLCGSTP
SYSC_PLL0CGCNTR
Settings
*1
*1
Loop count per one step of PLL clock gear operation
Step width at the PLL clock gear-up/down
PLLCGSSN *1
Step at the start of PLL clock gear operation
PLLCGSTR
Start gear operation
PLLCGEN *1
Clock gear operation enabled
*1
Do not change setting after PLL clock oscillation is set to enable.
3.2.3.1
Procedure of Clock Gear Operation Start
Clock gear starts the operation by performing the following steps after setting in Table 3-3 (Except
PLLCGSTR). It is necessary to wait until the clock gear is completed after clock gear operation start.
1. Select the PLL clock as the domain clock.
2. Set "01" to PLLCGSTR of PLL clock gear control register (SYSC_PLL0CGCNTR).
3. Poll the value of the clock gear status flag (SYSC_PLL0CGCNTR.PLLCGSTS), and wait until the clock
indicates stop state (PLLCGSTS =”10”).
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<Note>
The smaller step width and the larger loops count, the more gradually the frequency changes.
When it sets enable of clock gear operation, after the oscillation stabilization wait time of the clock gear
input clock, the clock according to the setting of PLLCGSSN is output. But it does not gear up/gear-down
until the clock gear operation start setting is performed.
3.2.4
PLL Clock Multiplier and Divider
PLL clock multiplier and divider can be set by RUN PLLx Control Register (SYSC0_RUNPLLxCNTR).
As for example of PLL clock configuration setting, please see the Table 3-4 PLL Clock Multiplier and Divider
Setting Example.
Table 3-4 PLL Clock Multiplier and Divider Setting Example
Register abbreviation
SYSC0_RUNPLLxCNTR
3.2.5
Bit name
Settings
PLLDIVN
PLL clock N-multiplier setting
PLLDIVM
PLL clock M-divider setting
PLLDIVL
PLL input clock divider setting
Source Clock for the Clock Domain 0
Hardware reset results in the fast-CR clock being selected as the clock used in all clock domains. It is
necessary to set the PLL clock to the source clock of clock domain 0 when changing the source clock of the
system clock to the PLL clock. Source clock of the system clock become the PLL clock by setting the source
clock of clock domain 0 to PLL clock.
Source clock of clock domain 0 during RUN state can be selected by setting the register of Table 3-5. The
example is described in Table 3-5 when setting the source clock of clock domain 0 to PLL clock.
Table 3-5 Clock Domain 0 Source Clock Setting Example
Register abbreviation
SYSC1_ RUNCKSELR0
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Bit name
CD0CSL
Settings
Clock domain 0 source clock selection
Value (decimal)
4
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3.3
N O T E
Clock Setting Procedure of Sample Software
The Clock setting procedure of sample software is described in Figure 3-4.
Figure 3-4 Clock Setting Example Using PLL in Sample Software (start.c)
static void ConfigureClocks(void)
{
// At first, disable PSS profile update.
// This setting is for wakeup from shutdown mode.
// note: SYSC1 was cleared by hardware after PSS profile is updated, but SYSC0 was not cleared.
SYSC0_PROTKEYR
= SYSC_KEY_UNLOCK;
SYSC0_PSSENR_PSSEN0 = 0;
Stabilization time setting with Source Clock Timer
//-----------------------------------------------------------------//
Set main oscillator and main PLL stabilization time
Stabilization time setting for Main clock and PLL/SSCG clock.
//------------------------------------------------------------------
// Set new main oscillation stabilization time and trigger data update
SYSC0_PROTKEYR
SYSC_6.unMOCTCPR.stcField
=
=
SYSC_KEY_UNLOCK;
- Input protect key of SYSC
// unlock SYSC0
(stc_sysc_6_moctcpr_field_t){
.u4PSCL = SYSC_MAINSCT_PRESCALER,
.u16CMPR
= SYSC_MAINSCT_CMPR };
// pre-scaler
// compare value
// trigger configuration capture
compare value
- Input protect key of SYSC
SYSC0_PROTKEYR
SYSC_6.unMOCTTRGR.stcField
- Set the Prescaler and
=
=
SYSC_KEY_UNLOCK;
// unlock SYSC0
(stc_sysc_6_mocttrgr_field_t){
.u1CGCPT
- Change the main clock timer
= 1 };
setting and start the timer counting
// Set PLL / SSCG stabilization time
SYSC0_PROTKEYR
=
SYSC_KEY_UNLOCK;
- Input protect key of SYSC
// unlock SYSC0
SYSC_7.unPLLSSCGSTCNTR.stcField = (stc_sysc_7_pllsscgstcntr_field_t){ .u4PLLSTABS = SYSC_PLLST_PLLSTABS,
.u4SSCGSTABS = SYSC_PLLST_PLLSTABS, };
- Set the PLL and SSCG
stabilization time
RUN Profile configuration (Power Domain setting)
//-----------------------------------------------------------------//
Configure run profile
//-----------------------------------------------------------------// Enable power domains
SYSC0_PROTKEYR
SYSC0_1.unRUNPDCFGR.stcField
18
CONFIDENTIAL
=
=
SYSC_KEY_UNLOCK;
- Input protect key of SYSC
// unlock SYSC0
(stc_sysc0_1_runpdcfgr_field_t){
.u1PD6_1EN =
1,
// switch on PD6_1 ()
.u1PD6_0EN =
1,
// switch on PD6_0 ()
.u1PD5_3EN =
1,
// switch on PD5_3 ()
.u1PD5_2EN =
1,
// switch on PD5_2 ()
.u1PD5_1EN =
1,
// switch on PD5_1 ()
.u1PD5_0EN =
1,
// switch on PD5_0 ()
.u1PD4_1EN =
1,
// switch on PD4_1 (Backup RAM1)
.u1PD4_0EN =
1,
// switch on PD4_0 (Backup RAM0)
.u1PD3EN
=
1,
// always on (Core)
.u1PD2EN
=
1 };// always on (Peripheral)
- Power Domain enable setting.
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RUN Profile configuration (Enable Oscillator)
// Enable oscillators
- Input protect key of SYSC
SYSC0_PROTKEYR
=
SYSC_KEY_UNLOCK;
// unlock SYSC0
- Enable Oscillator setting
SYSC0_1.unRUNCKSRER.stcField
=
(stc_sysc0_1_runcksrer_field_t){
.u1SOSCEN
=
0,
// disable Sub Oscillation
(Except for sub oscillation)
.u1PLL0EN
=
1,
// enable PLL0
.u1SSCG0EN =
1,
// enable SSCG0
.u1MOSCEN
=
1,
// enable Main Oscillation
.u1CROSCEN =
1,
// RC Osc. (always on in RUN state)
.u1SCROSCEN =
1 };// Slow RC Osc. (always on in RUN state)
RUN Profile configuration (PLL/SSCG setting)
//-----------------------------------------------------------------// Write Main / SSCG PLL settings
SYSC0_PROTKEYR
=
SYSC0_1.unRUNPLL0CNTR.stcField
SYSC_KEY_UNLOCK;
=
// unlock SYSC0
(stc_sysc0_1_runpll0cntr_field_t){
.u8PLL0DIVN =
(SYSC_MAIN_PLL_DIVN),
.u4PLL0DIVM =
.u2PLL0DIVL =
SYSC0_PROTKEYR
=
SYSC_KEY_UNLOCK;
// set PLL input multiplication value
(SYSC_MAIN_PLL_DIVM),
(SYSC_PLL_DIVL)};
// set PLL output divider
// set PLL input divider
// unlock SYSC0
SYSC0_1.unRUNSSCG0CNTR0.stcField = (stc_sysc0_1_runsscg0cntr0_field_t){ .u8SSCG0DIVN = (SYSC_MAIN_SSCG_DIVN),
.u4SSCG0DIVM = (SYSC_MAIN_SSCG_DIVM),
.u2SSCG0DIVL = (SYSC_SSCG_DIVL)};
// set SSCG PLL input multiplication value
// set SSCG PLL output divider
// set SSCG PLL input divider
RUN Profile configuration (Clock gear)
// Clock gear
SYSC0_PROTKEYR
SYSC_7.unPLL0CGCNTR.stcField
=
SYSC_KEY_UNLOCK;
=
- Input protect key of SYSC
// unlock SYSC0
(stc_sysc_7_pll0cgcntr_field_t){
.u8PLLCGLP =
SYSC0_PROTKEYR
=
SYSC_KEY_UNLOCK;
SYSC_7.unSSCG0CGCNTR.stcField
=
(stc_sysc_7_sscg0cgcntr_field_t){
4,
// Loops per step
.u2PLLCGSTP =
1,
.u6PLLCGSSN =
8,
// Start step = 8
.u1PLLCGSTR =
0,
// Start gear operation
.u1PLLCGEN =
1}; // Enable
- PLL clock gear setting.
// 2 steps
// unlock SYSC0
- Input protect key of SYSC
.u8SSCGCGLP =
.u2SSCGCGSTP =
4,
1,
// Loops per step
- SSCG clock gear setting.
// 2 steps
.u6SSCGCGSSN =
8,
// Start step = 8
.u1SSCGCGSTR =
0,
// Start gear operation
.u1SSCGCGEN =
1}; // Enable
RUN Profile configuration (Clock source selection)
//-----------------------------------------------------------------// Select clock sources
SYSC0_PROTKEYR
=
SYSC_KEY_UNLOCK;
SYSC0_1.unRUNCKSELR.stcField
=
(stc_sysc0_1_runckselr_field_t){
- Input protect key of SYSC
// unlock SYSC0
.u3CDMCUCCSL= 5}; // Clock domain MCUC clock = SSCG0
- Clock domain MCUC clock
Select SSCG
SYSC1_PROTKEYR
=
SYSC_KEY_UNLOCK;
// unlock SYSC1
SYSC1.unRUNCKSELR0.stcField
=
(stc_sysc1_runckselr0_field_t){
- Input protect key of SYSC
.u4HSSPICSL =
0,
0,
// LAPP1A clock = CD0 (1=PLL0)
.u1LAPP0ACSL=
0,
// LAPP0A clock = CD0 (1=PLL0)
.u1LCP1ACSL =
July 31, 2015, S6J3110_AN708-00014-2v0-E
CONFIDENTIAL
// Hsspi clock domain = Fast CR
.u1LAPP1ACSL=
0,
// LCP1A clock = CD0 (1=PLL0)
.u1LCP0ACSL =
0,
.u3CD0CSL
5}; // Clock Domain 0 = SSCG0
=
- Clock domain 0 clock
Select SSCG
- LAPP1A/LAPP0A/LCP1A/LCP0A
Select CD0
// LCP0A clock = CD0 (1=PLL0)
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A P P L I C A T I O N
SYSC1_PROTKEYR
=
SYSC1.unRUNCKSELR2.stcField
=
SYSC_KEY_UNLOCK;
N O T E
// unlock SYSC1
(stc_sysc1_runckselr2_field_t){
.u3TRCCSL
=
5}; // TRC clock = SSCG0
RUN Profile configuration (Enable clocks)
//-----------------------------------------------------------------// Enable clocks
SYSC1_PROTKEYR
=
SYSC1.unRUNCKER1.stcField
=
SYSC1_PROTKEYR
=
- Input protect key of SYSC
// unlock SYSC1
(stc_sysc1_runcker1_field_t) {
=
SYSC1.unRUNCKER2.stcField
SYSC_KEY_UNLOCK;
SYSC_KEY_UNLOCK;
.u1ENCLKCD3B1
=
0,
// Disable CD3B1
.u1ENCLKCD3B0
=
0,
// Disable CD3B0
.u1ENCLKCD3A1
=
0,
// Disable CD3A1
.u1ENCLKCD3A0
=
0,
// Disable CD3A0
.u1ENCLKCD3
=
0,
// Disable CD3
.u1ENCLKCD2B1
=
0,
// Disable CD2B1
.u1ENCLKCD2B0
=
0,
// Disable CD2B0
.u1ENCLKCD2A1
=
0,
// Disable CD2A1
.u1ENCLKCD2A0
=
0,
// Disable CD2A0
.u1ENCLKCD2
=
0,
// Disable CD2
.u1ENCLKCD1B1
=
0,
// Disable CD1B1
.u1ENCLKCD1B0
=
0,
// Disable CD1B0
.u1ENCLKCD1A1
=
0,
// Disable CD1A1
.u1ENCLKCD1A0
=
0,
// Disable CD1A0
.u1ENCLKCD1
=
0,
// Disable CD1
.u1ENCLKHSSPI
=
0}; // Disable HSSPI
- Input protect key of SYSC
// unlock SYSC1
(stc_sysc1_runcker2_field_t) {
- Disable clocks
.u1ENCLKCD5B1
=
0,
// Disable CD5B1
.u1ENCLKCD5B0
=
0,
// Disable CD5B0
.u1ENCLKCD5A1
=
0,
// Disable CD5A1
.u1ENCLKCD5A0
=
0,
// Disable CD5A0
.u1ENCLKCD5
=
0,
// Disable CD5
.u1ENCLKCD4B1
=
0,
// Disable CD4B1
.u1ENCLKCD4B0
=
0,
// Disable CD4B0
.u1ENCLKCD4A1
=
0,
// Disable CD4A1
.u1ENCLKCD4A0
=
0,
// Disable CD4A0
.u1ENCLKCD4
=
0}; // Disable CD4
- Disable clocks
RUN Profile configuration (Clock divider setting)
//-----------------------------------------------------------------// Set clock dividers (valid setting for all main-PLL frequencies)
SYSC0_PROTKEYR
SYSC0_1.unRUNCKDIVR.stcField
=
=
SYSC_KEY_UNLOCK;
- Input protect key of SYSC
// unlock SYSC0
(stc_sysc0_1_runckdivr_field_t) {
.u4MCUCPDIV =
0,
.u5MCUCHDIV =
// MCUconfig APB clock divider = 1
3 };// MCUconfig AHB clock divider = 4
- Divider setting for Clock domain
MCUC block
// Set clock dividers (valid setting for all main-PLL frequencies)
- Input protect key of SYSC
SYSC1_PROTKEYR
=
SYSC_KEY_UNLOCK;
// unlock SYSC1
- Divider setting for following clock
SYSC1.unRUNCKDIVR0.stcField
=
(stc_sysc1_runckdivr0_field_t) {
.u3HPMDIV
=
3,
// HPM clock divider = 4
-HPM
.u5TRCDIV
=
3,
// TRC Clock divider = 4
.u2DBGDIV
=
0,
// DBG Clock divider = 1
-TRC
-DBG
.u2ATBDIV
=
1,
// ATB Clock divider = 2
.u5SYSDIV
=
0 };// System Clock divider = 1
-ATB
-System clock
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A P P L I C A T I O N
SYSC1_PROTKEYR
SYSC1.unRUNCKDIVR1.stcField
=
=
SYSC1_PROTKEYR
SYSC1.unRUNCKDIVR2.stcField
// unlock SYSC1
(stc_sysc1_runckdivr1_field_t) {
=
=
SYSC1_PROTKEYR
SYSC1.unRUNCKDIVR3.stcField
SYSC_KEY_UNLOCK;
SYSC_KEY_UNLOCK;
=
SYSC_KEY_UNLOCK;
- Input protect key of SYSC
.u4HAPP1B1DIV
=
0,
// HAPP1B1 clock divider = 1
=
0,
// HAPP1B0 Clock divider = 1
-HAPP1B1DIV / HAPP1B0DIV
.u4HAPP0A1DIV
=
0,
// HAPP0A1 Clock divider = 1
-HAPP0A1DIV / HAPP0A0DIV
.u4HAPP0A0DIV
=
0,
// HAPP0A0 Clock divider = 1
-SYSC1
.u4SYSC1DIV
=
0,
// SYSC1 Clock divider = 1
-External Bus
.u3EXTBUSDIV
=
7 };// EXTBUS Clock divider = 128
- Input protect key of SYSC
.u4LAPP1DIV
=
3,
// LAPP1 clock divider = 4
.u4LAPP0DIV
=
3,
// LAPP0 Clock divider = 4
.u4LCP1DIV
=
3,
// LCP1 Clock divider = 4
.u4LCP0DIV
=
3,
// LCP0 Clock divider = 4
.u2LCPDIV
=
1}; // LCP Clock divider = 2
=
3,
- Divider setting for following clock
-LAPP1 / LAPP0
-LCP1 / LCP0
-LCP
- Input protect key of SYSC
// unlock SYSC1
(stc_sysc1_runckdivr3_field_t) {
- Divider setting for following clock
.u4HAPP1B0DIV
// unlock SYSC1
(stc_sysc1_runckdivr2_field_t) {
=
N O T E
.u5LAPP1ADIV
// LAPP1A clock divider = 4
- Divider setting for following clock
.u5LAPP0ADIV
=
3,
// LAPP0A Clock divider = 4
-LAPP1A / LAPP0A
.u5LCP1ADIV
=
3,
// LCP1A Clock divider = 4
-LCP1A / LCP0A
.u5LCP0ADIV
=
3 };// LCP0A Clock divider = 4
RUN Profile flag clear and start updating
//------------------------------------------------------------------ Input protect key of SYSC
// Clear RUN Profile Done flag (SYSC_SYSSTSR_RUNDN)
SYSC0_PROTKEYR
=
SYSC0_SYSICLR_RUNDFCLR0
SYSC_KEY_UNLOCK;
=
- Clear the RUN profile update
// unlock SYSC0
completion flag
1;
// RUN Profile update enable
SYSC1_PROTKEYR
- Input protect key of SYSC
=
SYSC1_RUNENR_RUNEN1
SYSC_KEY_UNLOCK;
=
// unlock SYSC1
- Setting RUN Profile enable
SYSC_TRIGGER_APPLY_RUN_PROFILE;
// Write the trigger value to apply the RUN profile
SYSC0_PROTKEYR
SYSC0_TRGRUNCNTR
=
=
SYSC_KEY_UNLOCK;
- Input protect key of SYSC
// unlock SYSC0
SYSC_TRIGGER_APPLY_RUN_PROFILE;
// trigger RUN-->RUN transition
- Start updating the RUN Profile enables
RUN Profile updating check
// Wait until the RUN profile is applied
- Wait until the RUN Profile is applied
while (SYSC0_SYSSTSR_RUNDF0 == 0);
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N O T E
Start clock gear operation
//-----------------------------------------------------------------// Clock gear (Trigger)
- Input protect key of SYSC
SYSC0_PROTKEYR
=
SYSC_KEY_UNLOCK;
// unlock SYSC1
- PLL0 clock gear up start
SYSC_PLL0CGCNTR_PLLCGSTR
=
1;
// Start gear operation
while ((SYSC_PLL0CGCNTR_PLLCGSTS) != 2);
// Gear up status :
// 00-stop gear at min frequency or clock gear not used
- Check the PLL clock gear status
// 01-gear up operation
// 10-stop gear at max frequency
// 11-gear down operation
SYSC0_PROTKEYR
SYSC_SSCG0CGCNTR_SSCGCGSTR
=
SYSC_KEY_UNLOCK;
=
1;
while ((SYSC_SSCG0CGCNTR_SSCGCGSTS) != 2);
// unlock SYSC1
// Start gear operation
- Input protect key of SYSC
- SSCG0 clock gear up start
// Gear up status :
// 00-stop gear at min frequency or clock gear not used
- Check the PLL clock gear status
// 01-gear up operation
// 10-stop gear at max frequency
// 11-gear down operation
}
RUN Operation
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v1.1
A P P L I C A T I O N
4.
N O T E
Reference
[1]. 32-bit Microcontroller Spansion Traveo Family S6J3110 series HARDWARE MANUAL
[2]. 32-bit Microcontroller Spansion Traveo Family S6J3120 series HARDWARE MANUAL
[3]. 32-bit Microcontroller Spansion Traveo Family S6J3110 series Data Sheet
[4]. 32-bit Microcontroller Spansion Traveo Family S6J3120 series Data Sheet
July 31, 2015, S6J3110_AN708-00014-2v0-E
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A P P L I C A T I O N
N O T E
5. Major Changes
Page
Section
Change Results
Revision 1.0
-
-
Initial release
Revision 2.0
Page 2
24
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Target Products
Adding S6J3120 series
S6J3110_AN708-00014-2v0-E, July 31, 2015
v1.1
A P P L I C A T I O N
N O T E
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where
chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Cypress will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any
semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention
of over-current levels and other abnormal operating conditions. If any products described in this document represent goods
or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the
US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective
government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Cypress
product under development by Cypress. Cypress reserves the right to change or discontinue work on any product without
notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy,
completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other
warranty, express, implied, or statutory. Cypress assumes no liability for any damages of any kind arising out of the use of
the information in this document.
®
Copyright © 2015 Cypress Semiconductor Corp. All rights reserved. Cypress, Cypress logo, Spansion , the Spansion logo,
®
®
TM
TM
TM
TM
MirrorBit , MirrorBit Eclipse , ORNAND , Easy DesignSim , Traveo and combinations thereof, are trademarks and
registered trademarks of Cypress Semiconductor Corp. in the United States and other countries. Other names used are for
informational purposes only and may be trademarks of their respective owners.
July 31, 2015, S6J3110_AN708-00014-2v0-E
CONFIDENTIAL
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V1.1