TLE9260QX Data Sheet (5.5 MB)

System Basis Chip
TLE9260QX
Mid-Range System Basis Chip Family
Body System IC with Integrated Voltage Regulators, Power Management Functions,
HS-CAN Transceiver supporting CAN FD .
Featuring Multiple High-Side Switches and High-Voltage Wake Inputs.
Data Sheet
Rev. 1.1, 2014-09-26
Automotive Power
TLE9260QX
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
3.3
3.4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hints for Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hints for Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
4.1
4.2
4.3
4.4
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
14
15
16
5
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.2
5.2.3
5.3
System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description of State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration and SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Init Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Fail-Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SBC Development Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration and Operation of Cyclic Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Sense in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cyclic Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supervision Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
21
22
22
24
25
26
27
28
29
30
31
31
32
35
36
37
37
6
6.1
6.2
6.3
Voltage Regulator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
38
39
40
7
7.1
7.2
7.2.1
7.3
Voltage Regulator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short to Battery Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
44
44
45
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
High-Side Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over and Under Voltage Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Current Detection and Switch Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Load Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HSx Operation in Different SBC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
48
49
49
49
49
Data Sheet
2
Rev. 1.1, 2014-09-26
TLE9260QX
Table of Contents
8.2.5
8.3
PWM and Timer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.3
High Speed CAN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN OFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Receive Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CAN Wake Capable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TXD Time-out Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Dominant Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Under Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
52
52
54
54
55
55
57
57
57
58
10
10.1
10.2
10.2.1
10.2.2
10.2.2.1
10.2.2.2
10.3
Wake and Voltage Monitoring Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Measurement Function with WK1 and WK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
64
65
66
67
67
67
68
11
11.1
11.2
Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12
12.1
12.1.1
12.2
Fail Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O Functionality of FO2 and FO3 as Alternate Function . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
73
74
75
13
13.1
13.1.1
13.1.2
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.3
13.4
13.5
13.6
13.6.1
13.6.2
13.7
13.8
13.9
13.9.1
13.9.2
Supervision Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Time-Out Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Setting Check Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog during SBC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Start in SBC Stop Mode due to Bus Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VS Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Under Voltage VS and VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over Voltage VSHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC1 Over-/ Under Voltage and Under Voltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC1 Under Voltage and Under Voltage Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC1 Over Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC1 Short Circuit Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC2 Undervoltage and VCAN Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Individual Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Prewarning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
77
77
78
79
80
81
81
82
82
83
84
84
84
84
85
86
86
87
87
88
Data Sheet
3
Rev. 1.1, 2014-09-26
TLE9260QX
Table of Contents
13.9.3
13.10
SBC Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
14
14.1
14.2
14.3
14.4
14.5
14.5.1
14.6
14.6.1
14.6.2
14.7
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Failure Signalization in the SPI Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SPI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SPI Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI Status Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
General Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Family and Product Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
15
15.1
15.2
15.3
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Behavior of Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
17
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Data Sheet
4
132
132
136
137
Rev. 1.1, 2014-09-26
Mid-Range System Basis Chip Family
1
TLE9260QX
Overview
Scalable System Basis Chip Family
•
Product family with various products for complete scalable application
coverage.
•
Dedicated Data Sheets are available for the different product variants
•
Complete compatibility (hardware and software) across the family
•
TLE9263 with 2 LIN transceivers, 3 voltage regulators
•
TLE9262 with 1 LIN transceiver, 3 voltage regulators
•
TLE9261 without LIN transceivers, 3 voltage regulators
•
TLE9260 without LIN transceivers, 2 voltage regulators
•
Product variants for 5V (TLE926xQX) and 3.3V (TLE926xQXV33) output voltage for main voltage regulator
•
CAN Partial Networking variants for 5V (TLE926x-3QX) and 3.3V (TLE926x-3QXV33) output voltage
PG-VQFN-48-31
Device Description
The TLE9260QX is a monolithic integrated circuit in an exposed pad VQFN-48 (7mm x 7mm) power package with
Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI).
The device is designed for various CAN automotive applications as main supply for the microcontroller and as
interface for a CAN bus network.
To support these applications, the System Basis Chip (SBC) provides the main functions, such as a 5V lowdropout voltage regulator (LDO) for e.g. a microcontroller supply, another 5V low-dropout voltage regulator with
off-board protection for e.g. sensor supply, a HS-CAN transceiver supporting CAN FD for data transmission, highside switches with embedded protective functions and a 16-bit Serial Peripheral Interface (SPI) to control and
monitor the device. Also implemented are a configurable timeout / window watchdog circuit with a reset feature,
three Fail Outputs and an under voltage reset feature.
The device offers low-power modes in order to minimize current consumption on applications that are connected
permanently to the battery. A wake-up from the low-power mode is possible via a message on the buses, via the
bi-level sensitive monitoring/wake-up inputs as well as via cyclic wake.
The device is designed to withstand the severe conditions of automotive applications.
Type
Package
Marking
TLE9260QX
PG-VQFN-48-31
TLE9260QX
Data Sheet
5
Rev. 1.1, 2014-09-26
TLE9260QX
Overview
Key Features
•
Very low quiescent current consumption in Stop- and Sleep Mode
•
Periodic Cyclic Wake in SBC Normal- and Stop Mode
•
Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode
•
Low-Drop Voltage Regulator 5V, 250mA
•
Low-Drop Voltage Regulator 5V, 100mA, protected features for off-board usage
•
High-Speed CAN Transceiver:
–
fully compliant to ISO11898-2 and ISO11898-5
–
suitable for chokeless operation up to 500kbps
–
supporting CAN FD communication up to 2 Mbps
•
Fully compliant to “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”
Revision 1.3, 2012-05-04
•
Four High-Side Outputs 7Ω typ.
•
Dedicated supply pin for High-Side Outputs
•
Two General Purpose High-Voltage In- and Outputs (GPIOs) configurable as add. Fail Outputs, Wake Inputs,
Low-Side switches or High-Side switches
•
Three universal High-Voltage Wake Inputs for voltage level monitoring
•
Alternate High-Voltage Measurement Function, e.g. for battery voltage sensing
•
Configurable wake-up sources
•
Reset Output
•
Configurable timeout and window watchdog
•
Up to three Fail Outputs (depending on configuration)
•
Over temperature and short circuit protection feature
•
Wide supply input voltage and temperature range
•
Software compatible to all SBC families TLE926x and TLE927x
•
Green Product (RoHS compliant) & AEC Qualified
•
PG-VQFN-48 leadless exposed-pad power package with Lead Tip Inspection (LTI) feature to support
Automatic Optical Inspection (AOI)
Data Sheet
6
Rev. 1.1, 2014-09-26
TLE9260QX
Block Diagram
Block Diagram
VSHS
VS
VS
VCC1
2
VS
VCC1
HS1
HS2
High Side
HS3
HS4
FO1
FO2
VCC2
FO3/TEST
Alternative function
for FO2/3: GPIO 1/2
SDI
SDO
CLK
CSN
SPI
VCC2
Fail Safe
SBC
STATE
MACHINE
INT
Interrupt
Control
Window Watchdog
WK1
WK2
RESET
GENERATOR
WK
Alternative
function for WK 1/2:
Voltage measurement
RO
VCAN
WK
WAKE
REGISTER
TXDCAN
CAN cell
WK3
RXDCAN
CANH
WK
CANL
GND
Figure 1
Data Sheet
Block Diagram
7
Rev. 1.1, 2014-09-26
TLE9260QX
Pin Configuration
Pin Configuration
3.1
Pin Assignment
36 RXDCAN
35 TXDCAN
34 N.U.
33 N.U.
32 RO
31 INT
30 CSN
29 SDO
28 SDI
27 CLK
26 N.U.
25 N.U.
3
VCAN 37
GND 38
CANL 39
CANH 40
n.c. 41
N.U. 42
GND 43
N.U. 44
n.c. 45
n.c. 46
FO2 47
FO3/TEST 48
TLE9260
PG-VQFN-48
24 WK3
23 WK2
22 WK1
21 FO1
20 GND
19 n.c.
18 VCC2
17 VCC1
16 n.c.
15 VS
14 VS
13 VSHS
12 n.c.
11 HS4
10 HS3
9 HS2
8 HS1
7 n.c.
6 n.c.
5 N.U.
4 N.U.
3 N.U.
2 n.c.
1 GND
TLE9260 .vsd
Figure 2
Data Sheet
Pin Configuration
8
Rev. 1.1, 2014-09-26
TLE9260QX
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
Function
1
GND
Ground
2
n.c.
not connected; internally not bonded.
3
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
4
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
5
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
6
n.c.
not connected; internally not bonded.
7
n.c.
not connected; internally not bonded.
8
HS1
High Side Output 1; typ. 7Ω
9
HS2
High Side Output 2; typ. 7Ω
10
HS3
High Side Output 3; typ. 7Ω
11
HS4
High Side Output 4; typ. 7Ω
12
n.c
not connected; internally not bonded.
13
VSHS
Supply Voltage HS and GPIO1/2 in HS configuration; Supply voltage for HighSide Switches modules and respective UV-/OV supervision; Connected to
battery voltage with reverse protection diode and filter against EMC; connect
to VS if separate supply is not needed
14
VS
Supply Voltage; Supply voltage for chip internal supply and voltage
regulators; Connected to Battery Voltage with external reverse protection
Diode and Filter against EMC
15
VS
Supply Voltage; Supply voltage for chip internal supply and voltage
regulators; Connected to Battery Voltage with external reverse protection
Diode and Filter against EMC
16
n.c.
not connected; internally not bonded.
17
VCC1
Voltage Regulator Output 1
18
VCC2
Voltage Regulator Output 2
19
n.c.
not connected; internally not bonded.
20
GND
GND
21
FO1
Fail Output 1
22
WK1
Wake Input 1; Alternative function: HV-measurement function input pin
(only in combination with WK2, see Chapter 10.2.2)
23
WK2
Wake Input 2; Alternative function: HV-measurement function output pin
(only in combination with WK1, see Chapter 10.2.2)
24
WK3
Wake Input 3
25
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
26
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
27
CLK
SPI Clock Input
28
SDI
SPI Data Input; into SBC (=MOSI)
29
SDO
SPI Data Output; out of SBC (=MISO)
30
CSN
SPI Chip Select Not Input
Data Sheet
9
Rev. 1.1, 2014-09-26
TLE9260QX
Pin Configuration
Pin
Symbol
Function
31
INT
Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or Normal
Mode and for indicating failures. Active low.
During start-up used to set the SBC configuration. External pull-up sets config 1/3,
no external pull-up sets config 2/4.
32
RO
Reset Output
33
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
34
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
35
TXDCAN
Transmit CAN
36
RXDCAN
Receive CAN
37
VCAN
Supply Input; for internal HS-CAN cell
38
GND
GND
39
CANL
CAN Low Bus Pin
40
CANH
CAN High Bus Pin
41
n.c.
not connected; internally not bonded.
42
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
43
GND
Ground
44
N.U.
Not Used; Used for internal testing purpose. Do not connect, leave open
45
n.c.
not connected; internally not bonded.
46
n.c.
not connected; internally not bonded.
47
FO2
Fail Output 2 - Side Indicator; Side indicators 1.25Hz 50% duty cycle output;
Open drain. Active LOW.
Alternative Function: GPIO1; configurable pin as WK, or LS, or HS supplied by
VSHS (default is FO2, see also Chapter 12.1.1)
48
FO3/TEST
Fail Output 3 - Pulsed Light Output; Break/rear light 100Hz 20% duty cycle output;
Open drain. Active LOW
TEST; Connect to GND to activate SBC Software Development Mode;
Integrated pull-up resistor. Connect to VS with pull-up resistor or leave open for
normal operation.
Alternative Function: GPIO2; configurable pin as WK, or LS, or HS supplied by
VSHS (default is FO3, see also Chapter 12.1.1)
Cooling GND
Tab
Cooling Tab - Exposed Die Pad; For cooling purposes only, do not use as an
electrical ground.1)
1) The exposed die pad at the bottom of the package allows better power dissipation of heat from the SBC via the PCB. The
exposed die pad is not connected to any active part of the IC an can be left floating or it can be connected to GND
(recommended) for the best EMC performance.
Note: all VS Pins must be connected to battery potential or insert a reverse polarity diodes where required;
all GND pins as well as the Cooling Tab must be connected to one common GND potential;
Data Sheet
10
Rev. 1.1, 2014-09-26
TLE9260QX
Pin Configuration
3.3
Hints for Unused Pins
It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they
are disabled via SPI:
•
WK1/2/3: connect to GND and disable WK inputs via SPI
•
HSx: leave open
•
CANH/L, RXDCAN, TXDCAN: leave all pins open
•
RO / FOx: leave open
•
INT: leave open
•
TEST: connect to GND during power-up to activate SBC Development Mode;
connect to VS or leave open for normal user mode operation
•
VCC2: leave open and keep disabled
•
VCAN: connect to VCC1
•
n.c.: not connected; internally not bonded; connect to GND
•
N.U.: Not Used; Used for internal testing purposes only. Do not connect, leave open, i.e. not connected to any
potential on the board. In case N.U. pins are connected on the board an open bridge has to be foreseen to
avoid external disturbances. The bridge can be shorted by a 0 Ω resistance if signal is needed.
3.4
Hints for Alternate Pin Functions
In case of alternate pin functions, selectable via SPI, it must be ensured that the correct configurations are also
selected via SPI, in case it is not done automatically. Please consult the respective chapter. In addition, following
topics shall be considered:
•
WK1..2: The pins can be either used as HV wake / voltage monitoring inputs or for a voltage measurement
function (via bit WK_MEAS). In the second case, the WK1..2 pins shall not be used / assigned for any wake
detection nor cyclic sense functionality, i.e. WK1 and WK2 must be disabled in the register WK_CTRL_2 and
the level information is to be ignored in the register WK_LVL_STAT.
•
FO2..3: The pins can also be configured as GPIOs in the GPIO_CTRL register. In this case, the pins shall not
be used for any fail output functionality. The default function after Power on Reset (POR) is FOx.
Data Sheet
11
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Table 1
Absolute Maximum Ratings1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
VSx, max
VSx, max
-0.3
–
28
V
–
P_4.1.1
-0.3
–
40
V
Load Dump,
max. 400 ms
P_4.1.2
VCC1, max
VCC2, max
-0.3
–
5.5
V
–
P_4.1.3
-0.3
–
28
V
VCC2 = 40V for
P_4.1.4
Voltages
Supply Voltage (VS, VSHS)
Supply Voltage (VS, VSHS)
Voltage Regulator 1
Voltage Regulator 2
Load Dump,
max. 400 ms;
Wake Inputs WK1..3
Fail Pin FO1
Fail Pins FO2, FO3/TEST
VWK, max
VFO1, max
VFO2_3, max
-0.3
–
40
V
–
P_4.1.6
-0.3
–
40
V
–
P_4.1.7
-0.3
–
VS
V
–
P_4.1.23
+ 0.3
VBUS, max
Logic Input Pins (CSN, CLK, VI, max
CANH, CANL
-27
–
40
V
–
P_4.1.8
-0.3
–
VCC1
V
–
P_4.1.9
V
–
P_4.1.10
SDI, TXDCAN)
+ 0.3
Logic Output Pins (SDO, RO, VO, max
INT, RXDCAN)
VCAN Input Voltage
High Side 1...4
VVCAN, max
VHS, max
-0.3
VCC1
–
+ 0.3
-0.3
–
5.5
V
–
P_4.1.11
-0.3
–
VSHS
V
–
P_4.1.12
µA
2)
P_4.1.13
P_4.1.14
+ 0.3
Currents
Wake input WK1
Wake input WK2
IWK1,max
IWK2,max
0
-500
–
0
µA
2)
Tj
Tstg
-40
–
150
°C
–
P_4.1.15
-55
–
150
°C
–
P_4.1.16
-2
–
2
kV
HBM3)
P_4.1.17
kV
3)
P_4.1.18
4)3)
P_4.1.19
–
500
Temperatures
Junction Temperature
Storage Temperature
ESD Susceptibility
VESD,11
ESD Resistivity to GND, HSx VESD,12
ESD Resistivity to GND,
VESD,13
ESD Resistivity
-2
-8
–
2
–
8
kV
HBM
HBM
CANH, CANL
Data Sheet
12
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
Table 1
Absolute Maximum Ratings1) (cont’d)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
ESD Resistivity to GND
ESD Resistivity Pin 1,
12,13,24,25,36,37,48 (corner
pins) to GND
Symbol
VESD,21
VESD,22
Values
Min.
Typ.
Max.
-500
–
500
-750
–
750
Unit
Note /
Test Condition
Number
V
CDM5)
P_4.1.20
V
5)
P_4.1.21
CDM
1)
2)
3)
4)
Not subject to production test, specified by design.
Applies only if WK1 and WK2 are configured as alternative HV-measurement function
ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001 (1.5 kΩ, 100 pF)
For ESD “GUN” Resistivity 6KV (according to IEC61000-4-2 “gun test” (150pF, 330Ω)), will be shown in Application
Information and test report will be provided from IBEE
5) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
13
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
4.2
Functional Range
Table 2
Functional Range
Parameter
Symbol
Supply Voltage
VS,func
Values
Min.
Typ.
Max.
VPOR
–
28
Unit
Note /
Test Condition
Number
V
1)
P_4.2.1
VPOR see
section
Chapter 13.10
4.75
–
5.25
V
–
SPI frequency
VCAN,func
fSPI
–
–
4
MHz
see Chapter 14.7 P_4.2.4
for fSPI,max
Junction Temperature
Tj
-40
–
150
°C
–
CAN Supply Voltage
P_4.2.3
P_4.2.5
1) Including Power-On Reset, Over- and Under voltage Protection
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Device Behavior Outside of Specified Functional Range:
•
28V < VS,func < 40V: Device will still be functional including the state machine; the specified electrical
characteristics might not be ensured anymore. The regulators VCC1/2/3 are working properly, however, a
thermal shutdown might occur due to high power dissipation. HSx switches might be turned OFF depending
on VSHS_OV configurations. The specified SPI communication speed is ensured; the absolute maximum
ratings are not violated, however the device is not intended for continuous operation of VS >28V. The device
operation at high junction temperatures for long periods might reduce the operating life time;
•
VCAN < 4.75V: The undervoltage bit VCAN_UV will be set in the SPI register BUS_STAT_1 and the transmitter
will be disabled as long as the UV condition is present;
•
5.25V < VCAN < 5.50V: CAN transceiver still functional. However, the communication might fail due to out-ofspec operation;
•
VPOR,f < VS < 5.5V: Device will still be functional; the specified electrical characteristics might not be ensured
anymore.
–
The voltage regulators will enter the low-drop operation mode,
–
A VCC1_UV reset could be triggered depending on the Vrtx settings,
–
HSx switch behavior will depend on the respective configuration:
- HS_UV_SD_EN = ‘0’ (default): HSx will be turned OFF for VSHS < VSHS_UV and will stay OFF;
- HS_UV_SD_EN = ‘1’: HSx stays on as long as possible. An unwanted over current shut down may occur.
OC shut down bit set and the respective HSx switch will stay OFF;
–
FOx outputs will remain ON if they were enabled before VS > 5.5V,
–
The specified SPI communication speed is ensured.
Data Sheet
14
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
4.3
Thermal Resistance
Table 3
Thermal Resistance1)
Parameter
Symbol
Junction to Soldering Point
RthJSP
RthJA
Junction to Ambient
Values
Min.
Typ.
Max.
–
6
–
–
33
–
Unit
Note /
Test Condition
Number
K/W
Exposed Pad
P_4.3.1
K/W
2)
P_4.3.2
1) Not subject to production test, specified by design.
2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board for 1.5W. Board: 76.2x114.3x1.5mm³ with 2
inner copper layers (35µm thick), with thermal via array under the exposed pad contacting the first inner copper layer and
300mm2 cooling area on the bottom layer (70µm).
Data Sheet
15
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
4.4
Current Consumption
Table 4
Current Consumption
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
–
3.5
6.5
Unit
Note / Test Condition Number
mA
P_4.4.1
VS = 5.5 V to 28 V;
Tj = -40 °C to +150 °C;
SBC Normal Mode
Normal Mode current
consumption
INormal
VCC2, CAN, HSx =
OFF
SBC Stop Mode
Stop Mode current
consumption
IStop_1,25
–
44
60
µA
1)
VCC2, HSx = OFF;
CAN, WKx not wake
capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘0’
P_4.4.2
Stop Mode current
consumption
IStop_1,85
–
50
70
µA
1)2)
Tj = 85°C;
VCC2, HSx = OFF;
CAN, WKx not wake
capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘0’
P_4.4.3
Stop Mode current
consumption
(high active peak threshold)
IStop_2,25
–
64
90
µA
1)
VCC2, HSx = OFF;
CAN, WKx not wake
capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘1’
P_4.4.35
Stop Mode current
consumption
(high active peak threshold)
IStop_2,85
–
70
100
µA
1)2)
Tj = 85°C;
VCC2, HSx = OFF;
CAN, WKx not wake
capable;
Watchdog = OFF;
no load on VCC1;
I_PEAK_TH = ‘1’
P_4.4.36
Sleep Mode current
consumption
ISleep,25
–
15
25
µA
VCC2, HSx = OFF;
CAN, WKx not wake
capable
P_4.4.5
Sleep Mode current
consumption
ISleep,85
–
25
35
µA
2)
P_4.4.6
SBC Sleep Mode
Data Sheet
16
Tj = 85°C;
VCC2, HSx = OFF;
CAN, WKx not wake
capable
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition Number
Feature Incremental Current Consumption
Current consumption for CAN ICAN,rec
module, recessive state
–
2
3
mA
SBC Normal/Stop
Mode; CAN Normal
Mode; VCC1
connected to VCAN;
VTXDCAN = VCC1;
no RL on CAN
P_4.4.7
Current consumption for CAN ICAN,dom
module, dominant state
–
3
4.5
mA
2)
SBC Normal/Stop
Mode; CAN Normal
Mode; VCC1
connected to VCAN;
VTXDCAN = GND;
no RL on CAN
P_4.4.8
Current consumption for CAN ICAN,RcvOnly
module, Receive Only Mode
–
0.9
1.2
mA
2)
P_4.4.9
Current consumption for
WK1..3 wake capability
(all wake inputs)
IWake,WKx,25 –
0.2
2
µA
3)4)5)
SBC Sleep Mode; P_4.4.13
WK1..3 wake capable
(all WKx enabled);
CAN = OFF
Current consumption for
WK1..3 wake capability
(all wake inputs)
IWake,WKx,85 –
0.5
3
µA
2)3)4)5)
SBC Normal/Stop
Mode; CAN Receive
Only Mode; VCC1
connected to VCAN;
VTXDCAN = VCC1;
no RL on CAN
P_4.4.14
SBC Sleep
Mode; Tj = 85°C;
WK1..3 wake capable;
(all WKx enabled);
CAN = OFF
Current consumption for CAN IWake,CAN,25
wake capability
–
4.5
6
µA
3)
SBC Sleep Mode;
CAN wake capable;
WK1..3
P_4.4.17
Current consumption for CAN IWake,CAN,85
wake capability
–
5.5
7
µA
2)3)
P_4.4.18
SBC Sleep Mode;
Tj = 85°C;
CAN wake capable;
WK1..3
VCC2 Normal Mode current
consumption
INormal,VCC2
–
2.5
3.5
mA
VS = 5.5 V to 28 V;
P_4.4.32
Tj = -40 °C to +150 °C;
VCC2 = ON (no load)
Current consumption for
VCC2 in SBC Sleep Mode
Data Sheet
ISleep,VCC2,25 –
25
17
35
µA
1)3)
SBC Sleep Mode; P_4.4.19
VCC2 = ON (no load);
CAN,
WK1..3 = OFF
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
Table 4
Current Consumption (cont’d)
Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified)
Parameter
Symbol
Values
Min.
Current consumption for
VCC2 in SBC Sleep Mode
ISleep,VCC2,85 –
Typ.
Max.
30
40
Unit
Note / Test Condition Number
µA
1)2)3)
SBC Sleep Mode; P_4.4.20
Tj = 85°C; VCC2 = ON
(no load); CAN,
WK1..3 = OFF
Current consumption for HSx IStop,HSx,25
in SBC Stop Mode
–
525
650
µA
3)6)
Current consumption for HSx IStop,HSx,85
in SBC Stop Mode
–
575
700
µA
2)3)6)
SBC Stop Mode; P_4.4.34
Tj = 85°C;
Cyclic Sense & HSx =
ON (no load);
CAN,
WK1..3 = OFF
3)7)8)
SBC Stop Mode;
Cyclic Sense & HSx=
ON (no load);
CAN,
WK1..3 = OFF
Current consumption for
cyclic sense function
IStop,CS25
–
20
26
µA
SBC Stop Mode;
WD = OFF
Current consumption for
cyclic sense function
IStop,CS85
–
24
35
µA
2)3)7)8)
P_4.4.33
P_4.4.23
SBC Stop Mode; P_4.4.27
Tj = 85°C;
WD = OFF
Current consumption for
watchdog active in Stop
Mode
IStop,WD25
–
20
26
µA
2)
SBC Stop Mode;
Watchdog running
P_4.4.30
Current consumption for
watchdog active in Stop
Mode
IStop,WD85
–
24
35
µA
2)
SBC Stop Mode;
Tj = 85°C;
Watchdog running
P_4.4.31
Current consumption for
active fail outputs (FO1..3)
IStop,FOx
–
1.0
2.0
mA
2)
P_4.4.24
all SBC Modes;
Tj = 25°C; FOx = ON
(no load);
1) If the load current on VCC1 will exceed the configured VCC1 active peak threshold IVCC1,Ipeak1,r or IVCC1,Ipeak2,r,
the current consumption will increase by typ. 2.9mA to ensure optimum dynamic load behavior. Same applies to VCC2..
See also Chapter 6, Chapter 7.
2) Not subject to production test, specified by design.
3) Current consumption adders of features defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa (unless
otherwise specified).
4) No pull-up or pull-down configuration selected.
5) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are activated.
6) A typ. 75µA / max 125µA (Tj = 85°C) adder applies for every additionally activated HSx switch in SBC Stop Mode;
In SBC Normal Mode every HSx switch consumes the typ. 75µA / max 125µA (Tj = 85°C) without the initial adder because
the biasing is already enabled.
7) HS1 used for cyclic sense, Timer 2, 20ms period, 0.1ms on-time, no load on HS1.
In general the current consumption adder for cyclic sense in SBC Stop Mode can be calculated with below equation:
IStop,CS = 18µA + (525µA *tON/TPer)
8) Also applies to Cyclic Wake
Data Sheet
18
Rev. 1.1, 2014-09-26
TLE9260QX
General Product Characteristics
Note: There is no additional current consumption contribution due to PWM generators.
Data Sheet
19
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5
System Features
This chapter describes the system features and behavior of the TLE9260QX:
•
State machine
•
SBC mode control
•
Device configuration
•
State of supply and peripherals
•
System functions such as cyclic sense or cyclic wake
•
Supervision and diagnosis functions
The System Basis Chip (SBC) offers six operating modes:
•
SBC Init Mode: Power-up of the device and after a soft reset,
•
SBC Normal Mode: The main operating mode of the device,
•
SBC Stop Mode: The first-level power saving mode with the main voltage regulator VCC1 enabled,
•
SBC Sleep Mode: The second-level power saving mode with VCC1 disabled,
•
SBC Restart Mode: An intermediate mode after a wake event from SBC Sleep or Fail-Safe Mode or after a
failure (e.g. WD failure, VCC1 under voltage reset) to bring the microcontroller into a defined state via a reset.
Once the failure condition is not present anymore the device will automatically change to SBC Normal Mode
after a delay time (tRD1).
•
SBC Fail-Safe Mode: A safe-state mode after critical failures (e.g. WD failure, VCC1 under voltage reset) to
bring the system into a safe state and to ensure a proper restart of the system. VCC1 is disabled. It is a
permanent state until either a wake event (via CAN or WKx) occurs or the over temperature condition is not
present anymore.
A special mode, called SBC Development Mode, is available during software development or debugging of the
system. All above mentioned operating modes can be accessed in this mode. However, the watchdog counter is
stopped and does not need to be triggered. This mode can be accessed by setting the TEST pin to GND during
SBC Init Mode.
The device can be configured via hardware (external component) to determine the device behavior after a
watchdog trigger failure. See Chapter 5.1.1 for further information.
The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in
Chapter 14.The configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the TLE9260QX
is compatible to other devices of the TLE926x and TLE927x families.
Data Sheet
20
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1
Block Description of State Machine
The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register
M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the
current SBC mode.
First battery connection
SBC Soft Reset
SBC Init Mode *
Config.: settings can be changed
in this SBC mode ;
(Long open window)
Fixed: settings stay as defined in
SBC Normal Mode
WD Cyc. Sense
OFF
Config.
VCC1
ON
VCC2
OFF
FOx
inact.
CAN(3)
OFF
* The SBC Development Mode is
a super set of state machine
where the WD timer is stopped
and CAN behavior differs in SBC
Init Mode. Otherwise, there are no
differences in behavior .
Any SPI
command
Cyc. Wake
HSx
OFF
OFF
SBC Normal Mode
VCC1
ON
FOx
act/inact
Automatic
Reset is released
WD starts with long open window
SPI cmd
VCC2
config.
WD Cyc. Sense
config. config.
(3)
HSx Cyc. Wake
config. config.
CAN
config.
SPI cmd
SPI cmd
SBC Stop Mode
SBC Sleep Mode
VCC1 over voltage
Config 1/3 (if VCC_OV_RST set)
Watchdog Failure:
Config 1/3 & 1st WD failure
in Config4
VCC1
Undervoltage
VCC1
OFF
VCC2
fixed
WD
OFF.
Cyc. Sense
FOx
fixed
CAN
HSx
fixed
Cyc. Wake
Wake
capable /off
WD trigger
fixed
VCC1
ON
VCC2
fixed
WD
fixed
Cyc. Sense
FOx
fixed
CAN
fixed
HSx
fixed
Cyc. Wake
OFF
fixed
fixed
Wake up event
SBC Restart Mode
(RO pin is asserted)
VCC1
ON/
ramping
VCC2
OFF
FOx(5)
CAN
active/
fixed
(4)
woken /
OFF
WD
OFF
Cyc. Sense
HSx
OFF
Cyc. Wake
VCC1 over voltage
Config 2/4 (if VCC_OV_RST set)
OFF
After 4x consecutive VCC 1
under voltage events
(if VS > VS_UV)
OFF
SBC Fail-Safe Mode
(1) After Fail-Safe Mode entry, the device will stay for at least typ . 1s
in this mode (with RO low) after a TSD2 event and min. typ. 100ms
after other Fail-Safe Events. Only then the device can leave the
mode via a wake-up event. Wake events are stored during this time.
CAN, WKx wake-up event
OR
Release of over temperature
TSD2 after tTSD2
VCC1
OFF
(5)
FOx
active
VCC2
OFF
CAN
Wake
capable
WD
OFF
HSx
OFF
(1)
Cyc. Sense
OFF
Cyc. Wake
OFF
TSD2 event,
1st Watchdog Failure Config 2,
2nd Watchdog Failure, Config 4
VCC1 Short to GND
(3) For SBC Development Mode CAN/VCC2 are ON in SBC Init Mode
and stay ON when going from there to SBC Normal Mode
(4) See chapter CAN for detailed behavior in SBC Restart Mode
(5) See Chapter 5.1.5 and 12.1 for detailed FOx behavior
Figure 3
Data Sheet
State Diagram showing the SBC Operating Modes
21
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.1
Device Configuration and SBC Init Mode
The SBC starts up in SBC Init Mode after crossing the power-on reset VPOR,r threshold (see also Chapter 13.3)
and the watchdog will start with a long open window (tLW).
During this power-on phase following configurations are stored in the device:
•
The device behavior regarding a watchdog trigger failure and a VCC1 over voltage condition is determined by
the external circuitry on the INT pin (see below)
•
The selection of the normal device operation or the SBC Software Development Mode (watchdog disabled for
debugging purposes) will be set depending on the voltage level of the FO3/TEST pin (see also Chapter 5.1.7).
5.1.1.1
Device Configuration
The configuration selection is intended to select the SBC behavior regarding a watchdog trigger failure. Depending
on the requirements of the application, the VCC1 output shall be switched OFF and the device shall go to SBC
Fail-Safe Mode in case of a watchdog failure (1 or 2 fails). To set this configuration (Config 2/4), the INT pin does
not need an external pull-up resistor. In case VCC1 should not be switched OFF (Config 1/3), the INT pin needs
to have an external pull-up resistor connected to VCC1 (see application diagram in Chapter 15.1).
Figure 5 shows the timing diagram of the hardware configuration selection. The hardware configuration is defined
during SBC Init Mode. The INT pin is internally pulled LOW with a weak pull-down resistor during the reset delay
time tRD1, i.e.after VCC1 crosses the reset threshold VRT1 and before the RO pin goes HIGH. The INT pin is
monitored during this time (with a continuos filter time of tCFG_F) and the configuration (depending on the voltage
level at INT) is stored at the rising edge of RO.
Note: If the POR bit is not cleared then the internal pull-down resistor will be reactivated every time RO is pulled
LOW the configuration will be updated at the rising edge of RO. Therefore it is recommended to clear the
POR bit right after initialization. In case there is no stable signal at INT, then the default value ‘0’ will taken
as the config select value = SBC Fail-Safe Mode.
VS
VPOR,r
t
VCC1
VRT1,r
t
RO
Continuous Filtering with t CFG_F
tRD1
t
Configuration selection monitoring period
Figure 4
Data Sheet
Hardware Configuration Selection Timing Diagram
22
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
There are four different device configurations (Table 5) available defining the watchdog failure and the VCC1 over
voltage behavior. The configurations can be selected via the external connection on the INT pin and the SPI bit
CFG in the HW_CTRL register (see also Chapter 14.4):
•
•
CFGP = ‘1’: Config 1 and Config 3:
–
A watchdog trigger failure leads to SBC Restart Mode and depending on CFG the Fail Outputs (FOx) are
activated after the 1st (Config 1) or 2nd (Config 3) watchdog trigger failure;
–
A VCC1 over voltage detection will lead to SBC Restart Mode if VCC1_OV_RST is set.
VCC1_ OV will be set and the Fail Outputs are activated;
CFGP = ‘0’: Config 2 and Config 4:
–
A watchdog trigger failure leads to SBC Fail-Safe Mode and depending on CFG the Fail Outputs (FOx) are
activated after the 1st (Config 2) or 2nd (Config 4) watchdog trigger failure. The first watchdog trigger failure
in Config 4 will lead to SBC Restart Mode;
–
A VCC1 over voltage detection will lead to SBC Fail-Safe Mode if VCC1_OV_RST is set.
VCC1_ OV will be set and the Fail Outputs are activated;
The respective device configuration can be identified by reading the SPI bit CFG in the HW_CTRL register and
the CFGP bit in the WK_LVL_STAT register.
Table 5 shows the configurations and the device behavior in case of a watchdog trigger failure:
Table 5
Watchdog Trigger Failure Configuration
Config INT Pin (CFGP)
SPI Bit CFG Event
FOx Activation
SBC Mode Entry
1
External pull-up
1
1 x Watchdog Failure
after 1st WD Failure
SBC Restart Mode
2
No ext. pull-up
1
1 x Watchdog Failure
after 1st WD Failure
SBC Fail-Safe Mode
3
External pull-up
0
2 x Watchdog Failure
after 2nd WD Failure
SBC Restart Mode
4
No ext. pull-up
0
2 x Watchdog Failure
after 2nd WD Failure
SBC Fail-Safe Mode
Table 6 shows the configurations and the device behavior in case of a VCC1 over voltage detection when
VCC1_OV_RST is set:
Table 6
Device Behavior in Case of VCC1 Over Voltage Detection
Config INT Pin
(CFGP)
CFG Bit VCC1_O Event
V_RST
VCC1
_ OV
FOx Activation
SBC Mode Entry
1-4
any value
x
0
1 x VCC1 OV
1
no FOx activation
unchanged
1
External pull-up 1
1
1 x VCC1 OV
1
after 1st VCC1 OV SBC Restart Mode
2
No ext. pull-up
1
1
1 x VCC1 OV
1
after 1st VCC1 OV SBC Fail-Safe Mode
3
External pull-up 0
1
1 x VCC1 OV
1
after 1st VCC1 OV SBC Restart Mode
4
No ext. pull-up
1
1 x VCC1 OV
1
after 1st VCC1 OV SBC Fail-Safe Mode
0
The respective configuration will be stored for all conditions and can only be changed by powering down the device
(VS < VPOR,f).
Data Sheet
23
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.1.2
SBC Init Mode
In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In the
SBC Init Mode any valid SPI command will bring the SBC to SBC Normal Mode. During the long open window the
watchdog has to be triggered. Thereby the watchdog will be automatically configured.
A missing watchdog trigger during the long open window will cause a watchdog failure and the device will enter
SBC Restart Mode.
Wake events are ignored during SBC Init Mode and will therefore be lost.
Note: Any SPI command will bring the SBC to SBC Normal Mode even if it is a illegal SPI command (see
Chapter 14.2).
Note: For a safe start-up, it is recommended to use the first SPI command to trigger and to configure the watchdog
(see Chapter 13.2).
Note: At power up no VCC1_UV will be issued nor will FOx be triggered as long as VCC1 is below the VRT,x
threshold and if VS is below the VCC1 short circuit detection threshold VS,UV. The RO pin will be kept low as
long as VCC1 is below the selected VRT,x threshold.
Data Sheet
24
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.2
SBC Normal Mode
The SBC Normal Mode is the standard operating mode for the SBC. All configurations have to be done in SBC
Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining the
Fail-Safe Mode behavior). A wake-up event on CAN and WKx will create an interrupt on pin INT - however, no
change of the SBC mode will occur. The configuration options are listed below:
•
VCC1 is active
•
VCC2 can be switched ON or OFF (default = OFF)
•
CAN is configurable (OFF coming from SBC Init Mode; OFF or wake capable coming from SBC Restart Mode,
see also Chapter 5.1.5)
•
HS Outputs can be switched ON or OFF (default = OFF) or can be controlled by PWM; HS Outputs are OFF
coming from SBC Restart Mode
•
Wake pins show the input level and can be selected to be wake capable (interrupt)
•
Cyclic sense can be configured with HS1...4 and Timer1 or Timer 2
•
Cyclic wake can be configured with Timer1 or Timer2
•
Watchdog is configurable
•
All FOx outputs are OFF by default. Coming from SBC Restart Mode FOx can be active (due to a failure event,
e.g. watchdog trigger failure, VCC1 short circuit, etc.) or inactive (no failure occurred)
In SBC Normal Mode, there is the possibility of testing the FO outputs, i.e. to verify if setting the FO pin to low will
create the intended behavior within the system. The FO output can be enabled and then disabled again by the
microcontroller by setting the FO_ON SPI bit. This feature is only intended for testing purposes.
Data Sheet
25
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.3
SBC Stop Mode
The SBC Stop Mode is the first level technique to reduce the overall current consumption by setting the voltage
regulators VCC1, VCC2 into a low-power mode. In this mode VCC1 is still active and supplying the
microcontroller, which can enter a power down mode. The VCC2 supply, CAN mode as well as the HSx outputs
can be configured to stay enabled. All kind of settings have to be done before entering SBC Stop Mode. In SBC
Stop Mode any kind of SPI WRITE commands are ignored and the SPI_FAIL bit is set, except for changing to
SBC Normal Mode, triggering a SBC Soft Reset, refreshing the watchdog as well as for reading and clearing the
SPI status registers. A wake-up event on CAN and WKx will create an interrupt on pin INT - however, no change
of the SBC mode will occur. The configuration options are listed below:
•
VCC1 is ON
•
VCC2 is fixed as configured in SBC Normal Mode
•
CAN mode is fixed as configured in SBC Normal Mode
•
WK pins are fixed as configured in SBC Normal Mode
•
HS Outputs are fixed as configured in SBC Normal Mode
•
Cyclic sense is fixed as configured in SBC Normal Mode
•
Cyclic wake is fixed as configured in SBC Normal Mode
•
Watchdog is fixed as configured in SBC Normal Mode
•
SBC Soft Reset can be triggered
•
FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained
An interrupt is triggered on the pin INT when SBC Stop Mode is entered and not all wake source signalization flags
from WK_STAT_1 and WK_STAT_2 were cleared.
Note: If switches are enabled during SBC Stop Mode, e.g. HSx on with or without PWM, then the SBC current
consumption will increase (see Chapter 4.4).
Note: It is not possible to switch directly from SBC Stop Mode to SBC Sleep Mode. Doing so will also set the
SPI_FAIL flag and will bring the SBC into Restart Mode.
Note: When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then the wake
inputs cannot be selected as wake input sources.
Data Sheet
26
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.4
SBC Sleep Mode
The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum
needed to react on wake-up events or for the SBC to perform autonomous actions (e.g. cyclic sense). In this mode,
VCC1 is OFF and not supplying the microcontroller anymore.The VCC2 supply as well as the HSx outputs can be
configured to stay enabled. The settings have to be done before entering SBC Sleep Mode. A wake-up event on
CAN or WKx will bring the device via SBC Restart Mode into SBC Normal Mode again and signal the wake source.
The configuration options are listed below:
•
VCC1 is OFF
•
VCC2 is fixed as configured in SBC Normal Mode
•
CAN mode changes automatically from ON or Receive Only Mode to wake capable mode or can be selected
to be OFF
•
WK pins are fixed as configured in SBC Normal Mode
•
HS Outputs are fixed as configured in SBC Normal Mode
•
Cyclic sense is fixed as configured in SBC Normal Mode
•
Cyclic wake is not available
•
Watchdog is OFF
•
FOx outputs are fixed, i.e. the state from SBC Normal Mode is maintained
•
As VCC1 is OFF during SBC Sleep Mode, no SPI communication is possible;
•
The Sleep Mode entry is signalled in the SPI register DEV_STAT with the bit DEV_STAT
It is not possible to switch all wake sources off in SBC Sleep Mode. Doing so will set the SPI_FAIL flag and will
bring the SBC into SBC Restart Mode.
In order to enter SBC Sleep Mode successfully, all wake source signalization flags from WK_STAT_1 and
WK_STAT_2 need to be cleared. A failure to do so will result in an immediate wake-up from SBC Sleep Mode by
going via SBC Restart to Normal Mode.
All settings must be done before entering SBC Sleep Mode.
Note: If switches are enabled during SBC Sleep mode, e.g. HSx on with or without PWM, then the SBC current
consumption will increase (see Chapter 4.4).
Note: Cyclic Sense function will not work properly anymore in case of an overcurrent, over temperature, under- or
overvoltage (in case function is selected) event because the respective HS switch will be disabled.
Note: When WK1 and WK2 are configured for the alternate measurement function (WK_MEAS = 1) then the wake
inputs cannot be selected as wake input sources.
Data Sheet
27
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.5
SBC Restart Mode
There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the
microcontroller:
•
in case of under voltage on VCC1 in SBC Normal and in SBC Stop Mode,
•
in case of over voltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘1’,
•
due to 1st incorrect Watchdog triggering (only if Config1, Config3 or Config 4 is selected, otherwise SBC FailSafe Mode is immediately entered),
•
In case of a wake event from SBC Sleep or SBC Fail-Safe Mode or a release of over temperature shutdown
(TSD2) out of SBC Fail-Safe Mode this transition is used to ramp up VCC1 after a wake in a defined way.
From SBC Restart Mode, the SBC goes automatically to SBC Normal Mode, i.e the mode is left automatically by
the SBC without any microcontroller influence. The SBC MODE bits are cleared. As shown in Figure 35 the Reset
Output (RO) is pulled low when entering Restart Mode and is released at the transition to Normal Mode after the
reset delay time (tRD1). The watchdog timer will start with a long open window starting from the moment of the rising
edge of RO and the watchdog period setting in the register WD_CTRL will be changed to the respective default
value ‘100’.
Leaving the SBC Restart Mode will not result in changing / deactivating the Fail outputs.
The behavior of the blocks is listed below:
•
All FOx outputs are activated in case of a 1st watchdog trigger failure (if Config1 or Config2 is selected) or
in case of VCC1 over voltage detection (if VCC1_OV_RST is set)
•
VCC1 is ON or ramping up
•
VCC2 will be disabled if it was activated before
•
CAN is “woken” due to a wake event or OFF depending on previous SBC and transceiver mode (see also
Chapter 9). It is wake capable when it was in CAN Normal-, Receive Only or wake capable mode before SBC
Restart Mode
•
HS Outputs will be disabled if they were activated before
•
RO is pulled low during SBC Restart Mode
•
SPI communication is ignored by the SBC, i.e. it is not interpreted
•
The Restart Mode entry is signalled in the SPI register DEV_STAT with the bits DEV_STAT
Table 7
Reasons for Restart - State of SPI Status Bits after Return to Normal Mode
Prev. SBC Mode
Event
DEV_STAT WD_FAIL
VCC1_UV VCC1_OV VCC1_SC
Normal
1x Watchdog Failure
01
01
x
x
x
Normal
2x Watchdog Failure
01
10
x
x
x
Normal
VCC1 under voltage reset 01
xx
1
x
x
Normal
VCC1 over voltage reset
01
xx
x
1
x
Stop
1x Watchdog Failure
01
01
x
x
x
Stop
2x Watchdog Failure
01
10
x
x
x
Stop
VCC1 under voltage reset 01
xx
1
x
x
Stop
VCC1 over voltage reset
01
xx
x
1
x
Sleep
Wake-up event
10
xx
x
x
x
Fail-Safe
Wake-up event
01
see “Reasons for Fail Safe, Table 8”
Note: An over voltage event on VCC1 will only lead to SBC Restart Mode if the bit VCC1_OV_RST is set and if
CFGP = ‘1’ (Config 1/3).
Note: The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.
Data Sheet
28
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.1.6
SBC Fail-Safe Mode
The purpose of this mode is to bring the system in a safe status after a failure condition by turning off the VCC1
supply and powering off the microcontroller. After a wake event the system is then able to restart again.
The Fail-Safe Mode is automatically reached for following events:
•
after an SBC thermal shutdown (TSD2) (see also Chapter 13.9.3),
•
in case of over voltage on VCC1 if the bit VCC1_OV_RST is set and if CFGP = ‘0’,
•
after a 1st incorrect watchdog trigger in Config2 (CFG = 1) and after a 2nd incorrect watchdog trigger in Config4
(CFG = 0) (see also Chapter 5.1.1),
•
if VCC1 is shorted to GND (see also Chapter 13.7),
•
After 4 consecutive VCC1 under voltage events (only if VS > VS,UV, see Chapter 13.6).
In this case, the default wake sources (CAN, WK1...3, see also registers WK_CTRL_2, BUS_CTRL_1) are
activated, the wake events are cleared in the register WK_STAT_1, and all output drivers and all voltage
regulators are switched off. When WK1 and WK2 are configured for the alternate measurement function
(WK_MEAS = 1) then WK1 and WK2 will stay configured for the measurement function when SBC Fail-Safe Mode
is entered, i.e. they will not be activated as wake sources.
The SBC Fail-Safe Mode will be maintained until a wake event on the default wake sources occurs. To avoid any
fast toggling behavior a filter time of typ. 100ms (tFS,min) is implemented. Wake events during this time will be
stored and will automatically lead to entering SBC Restart Mode after the filter time.
In case of an VCC1 over temperature shutdown (TSD2) the SBC Restart Mode will be reached automatically after
a filter time of typ. 1s (tTSD2) without the need of a wake event.
Leaving the SBC Fail-Safe Mode will not result in deactivation of the Fail Output pins.
The following functions are influenced during SBC Fail-Safe Mode:
•
All FOx outputs are activated (see also Chapter 12)
•
VCC1 is OFF
•
VCC2 is OFF
•
CAN is wake capable
•
HS Outputs are OFF
•
WK pins are wake capable through static sense (with default 16µs filter time)
•
Cyclic sense and Cyclic wake is disabled
•
SPI communication is disabled because VCC1 is OFF
•
The Fail-Safe Mode activation is signalled in the SPI register DEV_STAT with the bits FAILURE and
DEV_STAT
Data Sheet
29
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
Table 8
Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode
Prev. SBC Failure Event
Mode
DEV_
STAT
TSD2
WD_
FAIL
VCC1_
UV
VCC1_
UV_FS
VCC1_
OV
VCC1_
SC
Normal
1 x Watchdog Failure
01
x
01
x
x
x
x
Normal
2 x Watchdog Failure
01
x
10
x
x
x
x
Normal
TSD2
01
1
xx
x
x
x
x
Normal
VCC1 short to GND
01
x
xx
1
x
x
1
Normal
4x VCC1 UV
01
x
xx
1
1
x
x
Normal
VCC1 over voltage
01
x
xx
x
x
1
x
Stop
1 x Watchdog Failure
01
x
01
x
x
x
x
Stop
2 x Watchdog Failure
01
x
10
x
x
x
x
Stop
TSD2
01
1
xx
x
x
x
x
Stop
VCC1 short to GND
01
x
xx
1
x
x
1
Stop
4x VCC1 UV
01
x
xx
1
1
x
x
Stop
VCC1 over voltage
01
x
xx
x
x
1
x
Note: An over voltage event on VCC1 will only lead to SBC Fail-Safe Mode if the bit VCC1_OV_RST is set and if
CFGP = ‘0’ (Config 2/4).
Note: The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.
Note: See Chapter 13.6.1 for detailed description of the 4x VCC1 under voltage behavior.
5.1.7
SBC Development Mode
The SBC Development Mode is used during the development phase of the module. It is especially useful for
software development.
Compared to the default SBC user mode operation, this mode is a super set of the state machine. The device will
start also in SBC Init Mode and it is possible to use all the SBC Modes and functions with following differences:
•
Watchdog is stopped and does not need to be triggered. Therefore no reset is triggered due to watchdog failure
•
SBC Fail-Safe and SBC Restart Mode are not reached due to watchdog failure but the other reasons to enter
these modes are still valid
•
CAN and VCC2 default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON
instead of OFF
The SBC Software Development Mode is reached automatically if the FO3/TEST pin is set and kept LOW during
SBC Init Mode. The voltage level monitoring is started as soon as VS > VPOR,f. The Software Development Mode
is configured and maintained if SBC Init Mode is left by sending any SPI command while FO3/TEST is LOW. In
case the FO3/TEST level will be HIGH for longer than tTEST during the monitoring period then the SBC
Development Mode is not reached .
The SBC will remain in this mode for all conditions and can only be left by powering down the device
(VS < VPOR,f).
Data Sheet
30
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.2
Wake Features
Following wake sources are implemented in the device:
•
Static Sense: WK inputs are permanently active (see Chapter 10)
•
Cyclic Sense: WK inputs only active during on-time of cyclic sense period (see below)
•
Cyclic Wake: internal wake source controlled via internal timer (see below)
•
CAN wake: Wake-up via CAN message (see Chapter 9)
5.2.1
Cyclic Sense
The cyclic sense feature is intended to reduce the quiescent current of the device and the application.
In the cyclic sense configuration, one or more high-side drivers are switched on periodically controlled by
TIMER1_CTRL and TIMER2_CTRL. The respective high-side drivers supply external circuitries e.g. switches
and/or resistor arrays, which are connected to one or more wake inputs (see Figure 5). Any edge change of the
WKx input signal during the on-time of the cyclic sense period causes a wake. Depending on the SBC mode, either
the INT is pulled low (SBC Normal Mode and Stop Mode) or the SBC is woken enabling the VCC1 (after SBC
Sleep and SBC Fail-Safe Mode).
HS x
High Side
1-4
HS_CTRL
Signals
GND
Switching
Circuitry
TIMER_CTRL
Period / On-Time
INT
SBC
STATE
MACHINE
to uC
WK x
Figure 5
Data Sheet
WK
1-3
WK_FLT_CTRL
Cyclic Sense Working Principle
31
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.2.1.1
Configuration and Operation of Cyclic Sense
The correct sequence to configure the cyclic sense is shown in Figure 6. All the configurations have to be
performed before the on-time is set in the TIMERx_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH”
define the voltage level of the respective HS driver before the start of the cyclic sense. The intention of this
selection is to avoid an unintentional wake due to a voltage level change at the start of the cyclic sense.
Cyclic Sense (=TimerX) will start as soon as the respective on-time has been selected independently from the
assignment of the HS and filter configuration. The selection of the respective timer (Config C/D see
Chapter 10.2.1) must therefore be done before starting the timer. The correct configuration sequence is as
follows:
•
Configure the initial level
•
Mapping of a Timer to the respective HSx outputs
•
Configuring the respective filter timing and WK pins
•
Configuring the timer period and on-time
Cyclic Sense Configuration
Assign TIMERx_ON to OFF/Low or
OFF/High in TIMERx_CTRL
Timer1, Timer2
Assign Timer to selected HS switch
in HS_CTRL_X
Timer1, Timer2
Enable WKx as wake source with
configured Timer in WK_FLT_CTRL
WK1, WK2, WK3 with
above selected timer
Select WKx pull-up / pull-down
configuration in WK_PUPD_CTRL
No pull-up/-down, pull-down or pull-up
selected, automatic switching
Select Timer Period and desired
On-Time in TIMERx_CTRL
Period : 10, 20, 50, 100, 200ms, 1s, 2s
On-Time: 0.1, 0.3, 1.0, 10, 20ms
Changing the settings can be done on the
fly, changes become effective at the next
on-time or period
Cyclic Sense starts / ends by
setting / clearing On-time
Figure 6
Cyclic Sense: Configuration and Sequence
Note: All configurations of period and on-time can be selected. However, recommended on-times for cyclic sense
are 0.1ms, 0.3ms and 1ms. The SPI_FAIL will be set if the on-time is longer than the period.
Data Sheet
32
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
The first sample of the WK input value (HIGH or LOW) is taken as the reference for the next cycle. A change of
the WK input value between the first and second cycle recognized during the on-time of the second cycle will
cause a wake from SBC Sleep Mode or an interrupt during SBC Normal or SBC Stop Mode.
A filter time of 16µs is implemented to avoid a parasitic wake-up due to transients or EMC disturbances. The filter
time tFWK1 is triggered right at the end of the selected on-time and a wake signal is recognized if:
•
the input level will not cross the switching threshold level of typ. 3V during the selected filter time (i.e. if the
signal will keep the HIGH or LOW level) and
•
there was an input level change between the current and previous cycle
Data Sheet
33
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
A wake event due to cyclic sense in SBC Mode will set the respective bit WK1_WU, WK2_WU, or WK3_WU.
During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pins in SBC
Normal or SBC Stop Mode.
The functionality of the sampling and different scenarios are depicted in Figure 7 to Figure 9. The behavior in SBC
Stop and SBC Sleep Mode is identical except that in Stop Mode INT will be triggered to signal a change of WK
input levels and in SBC Sleep Mode, VCC1 will power-up instead.
HS on
Cyclic Sense
Periode
HS switch
Filter time
tFWK1
Filter time
tFWK1
On Time
t
1st sample taken
as reference
Figure 7
Wake detection possible
on 2nd sample
Wake Input Timing
HS
Filter time
High
Low
Switch
open
closed
WK
High
Low
INT
n-1
n
Learning
Cycle
WKn-1= High
WKn= Low
WKn ≠WKn-1
wake event
n+1
WKn+1 = Low
WKn = WKn+1
no wake
n+2
WKn+2 = High
WKn+2 ≠WK n+1
wake event
High
Low
Figure 8
Data Sheet
INT &
WK Bit Set
Cyclic Sense Example in SBC Stop Mode, HSx starts “OFF”/LOW, GND based WKx input
34
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
HS
Filter time
High
Low
Switch
Spike
open
closed
WK
High
Low
n-1
VCC1
n
Learning
Cycle
WKn-1 = Low
High
n+1
WKn= Low
WKn = WK n-1
no wake event
WKn = WKn+1 = Low
(but ignored because
change during filter time )
WKn = WKn+1
no wake event
Transition to:
SBC Normal Mode
SBC Sleep Mode
Low
INT &
WK Bit Set
Start of
Cyclic Sense
Figure 9
n+2
WKn+2= High
WKn+2 ≠WK n+1
wake event
Cyclic Sense Example in SBC Sleep Mode, HSx starts “OFF”/HIGH,
GND based WKx input
The cyclic sense function will not work properly anymore in case of following conditions:
•
in case SBC Fail-Safe Mode is entered: The respective HS Switch will be disabled and the respective wake
pin will be changed to static sensing
•
In SBC Normal, Stop, or Sleep Mode in case of an overcurrent, overtemperature, under- or overvoltage (in
case function is selected) event: the respective HS switch will be disabled
Note: The internal timers for cyclic sense are not disabled automatically in case the HS switch is turned off due to
above mentioned failures.This must be considered to avoid loss of wake events.
5.2.1.2
Cyclic Sense in Low Power Mode
If cyclic sense is intended for SBC Stop or SBC Sleep Mode mode, it is necessary to activate the cyclic sense in
SBC Normal Mode before going to the low power mode. A wake event due to cyclic sense will set the respective
bit WK1_WU, WK2_WU or WK3_WU. In Stop Mode the wake event will trigger an interrupt, in Sleep Mode the
wake event will send the device via Restart Mode to Normal Mode. Before returning to SBC Sleep Mode, the wake
status register WK_STAT_1 and WK_STAT_2 needs to be cleared. Trying to go to SBC Sleep mode with
uncleared wake flags, such as WKx_WU the SBC will directly wake-up from Sleep Mode by going via Restart
Mode to Normal Mode, a reset is issued. The WKx_WU bit is seen as source for the wake. This is implemented
in order not to loose an wake event during the transition.
Data Sheet
35
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.2.2
Cyclic Wake
The cyclic wake feature is intended to reduce the quiescent current of the device and application.
For the cyclic wake feature one or both timers are configured as internal wake-up source and will periodically
trigger an interrupt in SBC Normal and SBC Stop Mode.
The correct sequence to configure the cyclic wake is shown in Figure 10. The sequence is as follows:
•
First, disable the timers to ensure that there is not unintentional interrupt when activating cyclic wake,
•
Enable Timer1 and/or Timer2 as a wake-up source in the register WK_CTRL_1,
•
Configure the respective period Timer1 and/or Timer2. Also an on-time (any value) must be selected to start
the cyclic wake even if the value is ignored.
Cyclic Wake Configuration
Disable Timer1 and/or Timer2 as a
wake source in WK_CTRL_1
To avoid unintentional interrupts
Select Timer Period and any
On-Time in TIMERX_CTRL
Periods : 10, 20, 50, 100, 200 ms, 1s, 2s
On-times: any
(OFF/LOW & OFF/HIGH are not allowed )
Select Timer1 and/or Timer2 as a
wake source in WK_CTRL_1
No interrupt will be generated ,
if the timer is not enabled as a wake source
Cyclic Wake starts / ends by
setting / clearing On-time
INT is pulled low at every rising edge
of On-time except first one
Figure 10
Cyclic Wake: Configuration and Sequence
As in cyclic sense, the cyclic wake function will start as soon as the on-time is configured. An interrupt is generated
for every start of the on time except for the very first time when the timer is started
Data Sheet
36
Rev. 1.1, 2014-09-26
TLE9260QX
System Features
5.2.3
Internal Timer
The integrated Timer1 and Timer2 are typically used to wake up the microcontroller periodically (cyclic wake) or
to perform cyclic sense on the wake inputs. Therefore, the timers can be mapped to the dedicated HS switches
by SPI (via HS_CTRL1...2).
Following periods and on-times can be selected via the register TIMER1_CTRL and TIMER2_CTRL respectively:
•
Period: 10ms / 20ms / 50ms / 100ms / 200ms / 1s / 2s
•
On time: 0.1ms / 0.3ms / 1.0ms / 10ms / 20ms / OFF at HIGH or LOW
5.3
Supervision Features
The device offers various supervision features to support functional safety requirements. Please see Chapter 13
for more information.
Data Sheet
37
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 1
6
Voltage Regulator 1
6.1
Block Description
VS
V CC1
Vref
1
Overtemperature
Shutdown
Bandgap
Reference
State
Machine
INH
GND
Figure 11
Module Block Diagram
Functional Features
•
5V low-drop voltage regulator
•
Under voltage monitoring with adjustable reset level, VCC1 prewarning and VCC1 short circuit detection
(VRT1/2/3/4, VPW,f ). Please refer to Chapter 13.6 and Chapter 13.7 for more information.
•
Short circuit detection and switch off with under voltage fail threshold, device enters SBC Fail-Safe Mode
•
≥470nF ceramic capacitor at voltage output for stability, with ESR < 1Ω @ f = 10 kHz, to achieve the voltage
regulator control loop stability based on the safe phase margin (bode diagram).
•
Output current capability up to IVCC1,lim.
Data Sheet
38
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 1
6.2
Functional Description
The Voltage Regulator 1 (=VCC1) is “ON” in SBC Normal and SBC Stop Mode and is disabled in SBC Sleep and
in SBC Fail-Safe Mode. The regulator can provide an output current up to IVCC1,lim.
For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only a
low-power mode regulator with a lower accuracy (VCC1,out41) will be active for small loads. If the load current on
VCC1 exceeds the selected threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) then the high-power mode regulator will be also
activated to support an optimum dynamic load behavior. The current consumption will then increase by typ. 2.9mA.
If the load current on VCC1 falls below the selected threshold (IVCC1,Ipeak1,f or IVCC1,Ipeak2,f), then the low-quiescent
current mode is resumed again by disabling the high-power mode regulator.
Both regulators (low-power mode and high-power mode) are active in SBC Normal Mode.
Two different active peak thresholds can be selected via SPI:
•
I_PEAK_TH = ‘0’(default): the lower VCC1 active peak threshold 1 is selected with lowest quiescent current
consumption in SBC Stop Mode (IStop_1,25, IStop_1,85);
•
I_PEAK_TH = ‘1’: the higher VCC1 active peak threshold 2 is selected with an increased quiescent current
consumption in SBC Stop Mode (IStop_2,25, IStop_2,85);
Data Sheet
39
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 1
6.3
Electrical Characteristics
Table 9
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Number
Output Voltage including line
and Load regulation
VCC1,out1
4.9
5.0
5.1
V
1)
SBC Normal Mode;
10µA < IVCC1 < 250mA
6V < VS < 28V
P_6.3.1
Output Voltage including line
and Load regulation
VCC1,out2
4.9
5.0
5.1
V
1)
P_6.3.7
Output Voltage including line
and Load regulation
VCC1,out3
4.97
–
5.07
V
1)2)
SBC Normal Mode; P_6.3.12
20mA < IVCC1 < 90mA
8V < VS < 18V
25°C < Tj < 125°C
Output Voltage including line
and Load regulation
VCC1,out41
4.9
5.05
5.2
V
SBC Stop Mode;
P_6.3.2
1mA < IVCC1 < IVCC1,Ipeak
Output Voltage including line
and Load regulation
VCC1,out42
4.9
5.05
5.25
V
SBC Stop Mode;
10µA < IVCC1 < 1mA
P_6.3.20
Output Drop
VCC1,d1
–
–
500
mV
P_6.3.3
Output Drop
VCC1,d2
–
–
500
mV
VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,r –
(Transition threshold between
low-power and high-power
mode regulator)
1.9
3.5
mA
IVCC1 = 50mA
VS=3V
IVCC1 = 150mA
VS=5V
2)
ICC1 rising;
VS = 13.5V
-40°C < Tj < 150°C;
VCC1 Active Peak Threshold 1 IVCC1,Ipeak1,f 0.5
(Transition threshold between
high-power and low-power
mode regulator)
1.3
VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,r –
(Transition threshold between
low-power and high-power
mode regulator)
4.3
VCC1 Active Peak Threshold 2 IVCC1,Ipeak2,f 1.7
(Transition threshold between
high-power and low-power
mode regulator)
3.4
Over Current Limitation
IVCC1,lim
250
SBC Normal Mode;
10µA < IVCC1 < 150mA
P_6.3.4
P_6.3.13
I_PEAK_TH = ‘0’
–
mA
2)
ICC1 falling;
VS = 13.5V
-40°C < Tj < 150°C;
P_6.3.17
I_PEAK_TH = ‘0’
7.0
mA
2)
ICC1 rising;
VS = 13.5V
-40°C < Tj < 150°C;
P_6.3.18
I_PEAK_TH = ‘1’
–
mA
2)
ICC1 falling;
VS = 13.5V
-40°C < Tj < 150°C;
P_6.3.19
I_PEAK_TH = ‘1’
–
1200
2)
mA
current flowing out of
pin, VCC1 = 0V
P_6.3.6
1) In SBC Stop Mode, the specified output voltage tolerance applies when IVCC1 has exceeded the selected active peak
threshold (IVCC1,Ipeak1,r or IVCC1,Ipeak2,r) but with increased current consumption.
2) Not subject to production test, specified by design.
Data Sheet
40
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 1
Figure 12
Data Sheet
Typical on-resistance of VCC1 pass device during low drop operation for ICC1 = 100mA
41
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 1
Figure 13
Data Sheet
On-resistance range of VCC1 pass device during low drop operation for ICC1 = 150mA
42
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 2
7
Voltage Regulator 2
7.1
Block Description
VS
V CC2
Vref
1
Overtemperature
Shutdown
Bandgap
Reference
State
Machine
INH
GND
Figure 14
Module Block Diagram
Functional Features
•
5 V low-drop voltage regulator
•
Protected against short to battery voltage, e.g. for off-board sensor supply
•
Can also be used for CAN supply
•
VCC2 under voltage monitoring. Please refer to Chapter 13.8 for more information
•
Can be active in SBC Normal, SBC Stop, and SBC Sleep Mode (not SBC Fail-Safe Mode)
•
VCC2 switch off after entering SBC Restart Mode. Switch off is latched, LDO must be enabled via SPI after
shutdown.
•
Over temperature protection
•
≥ 470nF ceramic capacitor at output voltage for stability, with ESR < 1Ω @ f = 10 kHz, to achieve the voltage
regulator control loop stability based on the safe phase margin (bode diagram).
•
Output current capability up to IVCC2,lim.
Data Sheet
43
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 2
7.2
Functional Description
In SBC Normal Mode VCC2 can be switched on or off via SPI.
For SBC Stop- or Sleep Mode, the VCC2 has to be switched on or off before entering the respective SBC mode.
The regulator can provide an output current up to IVCC2,lim.
For low-quiescent current reasons, the output voltage tolerance is decreased in SBC Stop Mode because only a
low-power mode regulator with a lower accuracy (VCC2,out5) will be active for small loads. If the load current on
VCC2 exceeds IVCC2 > IVCC2,Ipeak,r then the high-power mode regulator will also be enabled to support an optimum
dynamic load behavior. The current consumption will then increase by typ. 2.9mA.
If the load current on VCC2 falls below the threshold (IVCC2 < IVCC2,Ipeak,f), then the low-quiescent current mode is
resumed again by disabling the high-power mode regulator.
Both regulators are active in SBC Normal Mode.
Note: If the VCC2 output voltage is supplying external off-board loads, the application must consider the series
resonance circuit built by cable inductance and decoupling capacitor at the load. Sufficient damping must be
provided.
7.2.1
Short to Battery Protection
The output stage is protected for short to VBAT.
Data Sheet
44
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 2
7.3
Electrical Characteristics
Table 10
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
Number
Output Voltage including line
and Load regulation
(SBC Normal Mode)
VCC2,out1
4.9
5.0
5.1
V
1)
SBC Normal Mode;
10µA < IVCC2 < 100mA
6.5V < VS < 28V
P_7.3.1
Output Voltage including line
and Load regulation
(SBC Normal Mode)
VCC2,out2
4.9
5.0
5.1
V
1)
SBC Normal Mode;
10µA < IVCC2 < 80mA
6V < VS < 28V
P_7.3.16
Output Voltage including line
and Load regulation
(SBC Normal Mode)
VCC2,out3
4.9
5.0
5.1
V
1)
SBC Normal Mode;
10µA < IVCC2 < 40mA
P_7.3.2
Output Voltage including line
and Load regulation
(SBC Normal Mode)
VCC2,out4
4.97
–
5.07
V
2)
P_7.3.14
Output Voltage including line
and Load regulation
(SBC Stop/Sleep Mode)
VCC2,out5
4.9
5.05
5.2
V
Stop, Sleep Mode;
P_7.3.3
1mA < IVCC2 < IVCC2,Ipeak
Output Voltage including line
and Load regulation
(SBC Stop/Sleep Mode)
VCC2,out6
4.9
5.05
5.25
V
Stop, Sleep Mode;
10µA < IVCC2 < 1mA
P_7.3.18
Output Drop
VCC2,d1
–
–
500
mV
P_7.3.4
VCC2 Active Peak Threshold
(Transition threshold between
low-power and high-power
mode regulator)
IVCC2,Ipeak,r –
1.9
3.5
mA
IVCC2 = 30mA
VS = 5V
2)
ICC2 rising;
VS = 13.5V
-40°C < Tj < 150°C
P_7.3.15
VCC2 Active Peak Threshold
(Transition threshold between
high-power and low-power
mode regulator)
IVCC2,Ipeak,f 0.5
1.3
–
mA
2)
ICC2 falling;
VS = 13.5V
-40°C < Tj < 150°C
P_7.3.17
Over Current limitation
IVCC2,lim
–
7502)
mA
current flowing out of
pin, VCC2 = 0V
P_7.3.5
100
SBC Normal Mode;
10µA < IVCC2 < 5mA
8V < VS < 18V
25°C < Tj < 125°C
1) In SBC Stop Mode, the specified output voltage tolerance applies when IVCC2 has exceeded the selected active peak
threshold (IVCC2,Ipeak,r) but with increased current consumption.
2) Not subject to production test, specified by design.
Data Sheet
45
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 2
Figure 15
Data Sheet
Typical on-resistance of VCC2 pass device during low drop operation for ICC2 = 30mA
46
Rev. 1.1, 2014-09-26
TLE9260QX
Voltage Regulator 2
Figure 16
Data Sheet
On-resistance range of VCC2 pass device during low drop operation for ICC2 = 50mA
47
Rev. 1.1, 2014-09-26
TLE9260QX
High-Side Switch
8
High-Side Switch
8.1
Block Description
HSx
VSHS
HS Gate Control
Overcurrent Detection
Open Load (On)
Figure 17
High-Side Module Block Diagram
Features
•
Dedicated supply pin VSHS for high-side outputs
•
Over voltage and under voltage switch off - configurable via SPI
•
Overcurrent detection and switch off
•
Open load detection in ON-state
•
PWM capability with internal timer configurable via SPI
•
Switch recovery after removal of OV or UV condition configurable via SPI
8.2
Functional Description
The High-Side switches can be used for control of LEDs, as supply for the wake inputs and for other loads. The
High-Side outputs can be controlled either directly via SPI by (HS_CTRL1, HS_CTRL2), by the integrated timers
or by the integrated PWM generators.
The high-side outputs are supplied by a dedicated supply pin VSHS (different to VS). The topology supports
improved cranking condition behavior.
The configuration of the High-Side (Permanent On, PWM, cyclic sense, etc.) drivers must be done in SBC Normal
Mode. The configuration is taken over in SBC Stop- or SBC Sleep Mode and cannot be modified. When entering
SBC Restart Mode or SBC Fail-Safe Mode the HSx outputs are disabled.
Data Sheet
48
Rev. 1.1, 2014-09-26
TLE9260QX
High-Side Switch
8.2.1
Over and Under Voltage Switch Off
All HS drivers in on-state are switched off in case of over voltage on VSHS (VSHS,OVD). If the voltage drops below
the over voltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit
HS_OV_SD_EN.
The HS drivers are switched off in case of under voltage on VSHS (VSHS,UVD). If the voltage rises above the under
voltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit
HS_UV_SD_EN.
So after release of under voltage or over voltage condition the HS switch goes back to programmed state in which
it was configured via SPI. This behavior is only valid if the bit HS_OV_UV_REC is set to ‘1’. Otherwise the switches
will stay off and the respective SPI control bits are cleared are cleared.
The over voltage and under voltage is signaled in the bits VSHS_OV and VSHS_UV, no other error bits are set.
8.2.2
Over Current Detection and Switch Off
If the load current exceeds the over current shutdown threshold for a time longer then the over current shutdown
filter time the output is switched off.
The over current condition and the switch off is signaled with the respective HSx_OC_OT bit in the register
HS_OC_OT_STAT. The HSx configuration is then reset to 000 by the SBC. To activate the High-Side again the
HSx configuration has to be set to ON (001) or be programmed to a timer function. It is recommended to clear the
over current bit before activation the High-Side switch, as the bits are not cleared automatically by the SBC.
8.2.3
Open Load Detection
Open load detection on the High-Side outputs is done during on state of the output. If the current in the activated
output falls below then Open Load Detection current, the open load is detected and signaled via the respective bit
HS1_OL, HS2_OL, HS3_OL, or HS4_OL in the register HS_OL_STAT. The High-Side output stays activated. If
the open load condition disappears the Open Load bit in the SPI can be cleared. The bits are not cleared
automatically by the SBC.
8.2.4
HSx Operation in Different SBC Modes
•
During SBC Stop and SBC Sleep Mode the HSx outputs can be used for the cyclic sense feature. The openload detection, over current shut down as well as over voltage and under voltage shutdown are available. The
over current shutdown protection feature may influence the wake-up behavior1).
•
the HSx output can also be enabled for SBC Stop and SBC Sleep Mode as well as controlled by the PWMx
generator. The HSx outputs must be configured in SBC Normal Mode before entering a low-power mode.
•
The HSx outputs are switched off during SBC Restart or SBC Fail-Safe Mode. They can be enabled via SPI if
the failure condition is removed.
1) For the wake feature, the forced over current shut down case must be considered in the user software for all SBC Modes,
i.e. due to disabled HSx switches a level change might not be detected anymore at WKx pins.
Data Sheet
49
Rev. 1.1, 2014-09-26
TLE9260QX
High-Side Switch
8.2.5
PWM and Timer Function
Two 8-bit PWM generators are dedicated to generate a PWM signal on the HS outputs, e.g. for brightness
adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated HS
outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI (PWM1_CTRL,
PWM2_CTRL). Two different frequencies (200Hz, 400Hz) can be selected independently for every PWM
generator in the register PWM_FREQ_CTRL.
PWM Assignment and Configuration:
•
Configure duty cycle and frequency for respective PWM generator in PWM1_CTRL/PWM2_CTRL and
PWM_FREQ_CTRL
•
Assign PWM generator to respective HS switch(es) in HSx_CTRL
•
The PWM generation will start right after the HSx is assigned to the PWM generator (HS_CTRL1, HS_CTRL2)
Assignment options of HS1... HS4
•
Timer 1
•
Timer 2
•
PWM 1
•
PWM 2
Note: The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.
the PWM setting ‘0000 0001’ could not be realized.
In addition, the minimum PWM setting for reliable detection of over-current and open-load measurement is
4 digits for a period of 400Hz and 2 digits for a period of 200Hz
Data Sheet
50
Rev. 1.1, 2014-09-26
TLE9260QX
High-Side Switch
8.3
Electrical Characteristics
Table 11
Target Specifications
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
Ids = 60mA,
Tj < 25°C
Ids = 60mA,
Tj < 150°C
P_9.3.1
Output HS1, HS2, HS3, HS4
Static Drain-Source ON
Resistance HS1...HS4
RON,HS25
–
7
–
Ω
Static Drain-Source ON
Resistance HS1...HS4
RON,HS150
–
11.5
16
Ω
Leakage Current HSx / per
channel
Ileak,HS
–
–
2
µA
1)
0 V < VHSx
< VSHS;
Tj < 85°C
P_9.3.11
Output Slew Rate (rising)
SRraise,HS
0.8
–
2.5
V/µs
1)
P_9.3.3
SRfall,HS
-2.5
Switch-on time HSx
tON,HS
3
–
30
µs
CSN = HIGH to
0.8*VSHS;
RL = 220Ω;
VSHS = 6 to 18V
P_9.3.5
Switch-off time HSx
tOFF,HS
3
–
30
µs
CSN = HIGH to
0.2*VSHS;
RL = 220Ω;
VSHS = 6 to 18V
P_9.3.6
Short Circuit Shutdown
Current
ISD,HS
150
245
300
mA
VSHS = 6 to 20V,
hysteresis
included
P_9.3.7
µs
2) 3)
P_9.3.8
Output Slew Rate (falling)
20 to 80%
VSHS = 6 to 18V
RL = 220Ω
–
-0.8
V/µs
1)
80 to 20%
P_9.3.4
VSHS = 6 to 18V
RL = 220Ω
Short Circuit Shutdown Filter tSD,HS
Time
Open Load Detection Current IOL,HS
P_9.3.2
16
,
0.4
–
3
mA
hysteresis
included
P_9.3.9
Open Load Detection
hysteresis
IOL,HS,hys
–
0.45
–
mA
1)
P_9.3.14
Open Load Detection Filter
Time
tOL,HS
–
64
–
µs
2) 3)
P_9.3.10
,
1) Not subject to production test, specified by design.
2) Not subject to production test, tolerance defined by internal oscillator tolerance.
3) The minimum PWM setting for reliable detection of over current and open load measurement is 5 digits for a period of
200Hz and 3 digits for a period of 150Hz.
Data Sheet
51
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
9
High Speed CAN Transceiver
9.1
Block Description
VCAN
SPI Mode
Control
CANH
CANL
VCC1
RTXD
Driver
Output
Stage
Temp.Protection
TXDCAN
+
timeout
To SPI diagnostic
VCAN
VBIAS = 2.5V
VCC 1
MUX
RXDCAN
Receiver
Vs
Wake
Receiver
Figure 18
Functional Block Diagram
9.2
Functional Description
The Controller Area Network (CAN) transceiver part of the SBC provides high-speed (HS) differential mode data
transmission (up to 2 Mbaud) and reception in automotive and industrial applications. It works as an interface
between the CAN protocol controller and the physical bus lines compatible to ISO/DIS 11898-2, 11898-5 and SAE
J2284.
The CAN transceiver offers low power modes to reduce current consumption. This supports networks with partially
powered down nodes. To support software diagnostic functions, a CAN Receive-only Mode is implemented.
It is designed to provide excellent passive behavior when the transceiver is switched off (mixed networks,
clamp15/30 applications).
A wake-up from the CAN wake capable mode is possible via a message on the bus. Thus, the microcontroller can
be powered down or idled and will be woken up by the CAN bus activities.
The CAN transceiver is designed to withstand the severe conditions of automotive applications and to support
12 V applications.
The different transceiver modes can be controlled via the SPI CAN bits.
Data Sheet
52
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Figure 19 shows the possible transceiver mode transitions when changing the SBC mode.
SBC Mode
CAN Transceiver Mode
SBC Stop Mode
Receive Only
Wake Capable
Normal Mode
OFF
SBC Normal Mode
Receive Only
Wake Capable
Normal Mode
OFF
SBC Sleep Mode
Wake Capable
OFF
SBC Restart Mode
Woken1
OFF
SBC Fail-Safe Mode
Wake Capable
1
after a wake event on CAN Bus
Behavior after SBC Restart Mode - not coming from SBC Sleep Mode due to a wake up of the respective transceiver:
If the transceivers had been configured to Normal Mode, or Receive Only Mode, then the mode will be changed to Wake
Capable. If it was Wake Capable, then it will remain Wake Capable. If it had been OFF before SBC Restart Mode, then it
will remain OFF.
Behavior in SBC Development Mode:
CAN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF.
Figure 19
CAN Mode Control Diagram
CAN FD Support
CAN FD stands for ‘CAN with Flexible Data Rate’. It is based on the well established CAN protocol as specified in
ISO 11898-1. CAN FD still uses the CAN bus arbitration method. The benefit is that the bit rate can be increased
by switching to a shorter bit time at the end of the arbitration process and then to return to the longer bit time at
the CRC delimiter, before the receivers transmit their acknowledge bits. See also Figure 20.
In addition, the effective data rate is increased by allowing longer data fields. CAN FD allows the transmission of
up to 64 data bytes compared to the 8 data bytes from the standard CAN.
Figure 20
Standard CAN
message
CAN Header
CAN FD with
reduced bit time
CAN Header
Data phase
(Byte 0 – Byte 7)
Data phase
(Byte 0 – Byte 7)
CAN Footer
CAN Footer
Example:
- 11bit identifier + 8Byte data
- Arbitration Phase
500kbps
- Data Phase
2Mbps
average bit rate
1.14Mbps
Bite Rate Increase with CAN FD vs. Standard CAN
Not only the physical layer must support CAN FD but also the CAN controller. In case the CAN controller is not
able to support CAN FD then the respective CAN node must at least tolerate CAN FD communication. This CAN
FD tolerant mode is realized in the physical layer in combination with CAN Partial Networking. The TLE926x-3QX
variants of this family also support the CAN FD tolerant mode.
Data Sheet
53
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
9.2.1
CAN OFF Mode
The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is intended
to completely stop CAN activities or when CAN communication is not needed. The CANH/L bus interface acts as
a high impedance input with a very small leakage current. In CAN OFF Mode, a wake-up event on the bus will be
ignored.
9.2.2
CAN Normal Mode
The CAN Transceiver is enabled via SPI in SBC Normal Mode. CAN Normal Mode is designed for normal data
transmission/reception within the HS-CAN network. The Mode is available in SBC Normal Mode and in SBC Stop
Mode. The bus biasing is set to VCAN/2.
Transmission
The signal from the microcontroller is applied to the TXDCAN input of the SBC. The bus driver switches the
CANH/L output stages to transfer this input signal to the CAN bus lines.
Enabling sequence
The CAN transceiver requires an enabling time tCAN,EN before a message can be sent on the bus. This means that
the TXDCAN signal can only be pulled LOW after the enabling time. If this is not ensured, then the TXDCAN needs
to be set back to HIGH (=recessive) until the enabling time is completed.
Only the next dominant bit will be transmitted on the bus.
Figure 21 shows different scenarios and explanations for CAN enabling.
VTXDCAN
CAN
Mode
t CAN,EN
t CAN ,EN
t
t CAN,EN
CAN
NORMAL
CAN
OFF
t
VCANDIFF
Dominant
Recessive
Correct sequence ,
Bus is enabled after tCAN, EN
Figure 21
tCAN, EN not ensured , no
transmission on bus
recessive TXD level
required bevor start of
transmission
t
tCAN, EN not ensured ,
no transmission on bus
recessive TXD
level required
CAN Transceiver Enabling Sequence
Reduced Electromagnetic Emission
To reduce electromagnetic emissions (EME), the bus driver controls CANH/L slopes symmetrically.
Reception
Analog CAN bus signals are converted into digital signals at RXD via the differential input receiver.
Data Sheet
54
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
9.2.3
CAN Receive Only Mode
In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This mode
is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.
9.2.4
CAN Wake Capable Mode
This mode can be used in SBC Stop, Sleep, Restart and Normal Mode and it is used to monitor bus activities.
It is automatically accessed in SBC Fail-Safe Mode. Both bus pins CANH/L are connected to GND via the input
resistors.
A wake-up signal on the bus results in a change of behavior of the SBC, as described in Table 12. The pins
CANH/L are terminated to typ. 2.5V through the input resistors. As a wake-up signalization to the microcontroller,
the RXD_CAN pin is set LOW and will stay LOW until the CAN transceiver is changed to any other mode. After a
wake-up event, the transceiver can be switched to CAN Normal Mode for communication via SPI.
As shown in Figure 22, a wake-up pattern is signaled on the bus by two consecutive dominant bus levels for at
least tWake1 (filter time t > tWake1), each separated by a recessive bus level of less than tWake2.
Entering low -power mode ,
when selective wake-up
function is disabled
or not supported
Ini
Bus recessive > t WAKE1
Bias off
Wait
Bias off
Bus dominant > tWAKE1
optional:
tWAKE2 expired
1
Bias off
Bus recessive > tWAKE1
optional:
tWAKE2 expired
2
Bias off
Bus dominant > tWAKE1
Entering CAN Normal
or CAN Recive Only
3
tSilence expired AND
Device in low-power mode
Bias on
Bus dominant > t WAKE1
Bus recessive > t WAKE1
4
tSilence expired AND
device in low-power mode
Bias on
Figure 22
Data Sheet
WUP detection following the definition in ISO 11898-5
55
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Rearming the Transceiver for Wake Capability
After a BUS wake-up event, the transceiver is woken. However, the CAN transceiver mode bits will still show wake
capable (=‘01’) so that the RXD signal will be pulled low. There are two possibilities how the CAN transceiver’s
wake capable mode is enabled again after a wake event:
•
The CAN transceiver mode must be toggled, i.e. switched from Wake Capable Mode to CAN Normal Mode,
CAN Receive Only Mode or CAN Off, before switching to CAN Wake Capable Mode again.
•
Rearming is done automatically when the SBC is changed to SBC Stop, SBC Sleep, or SBC Fail-Safe Mode
to ensure wake-up capability.
Note: It is not necessary to clear the CAN wake-up bit CAN_WU to become wake capable again. It is sufficient to
toggle the CAN mode.
Note: The CAN module is supplied by an internal voltage when in CAN Wake Capable Mode, i.e. the module must
not be supplied through the VCAN pin during this time. Before changing the CAN Mode to Normal Mode, the
supply of VCAN has to be activated first.
Wake-Up in SBC Stop and Normal Mode
In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 SPI
register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The
microcontroller should set the device from SBC Stop Mode to SBC Normal Mode, there is no automatic transition
to Normal Mode.
For functional safety reasons, the watchdog will be automatically enabled in SBC Stop Mode after a Bus wake
event in case it was disabled before (if bit WD_EN_ WK_BUS was configured to HIGH before).
Wake-Up in SBC Sleep Mode
Wake-up is possible via a CAN message (filter time t > tWake1). The wake-up automatically transfers the SBC into
the SBC Restart Mode and from there to Normal Mode the corresponding RXD pin in set to LOW. The
microcontroller is able to detect the low signal on RXD and to read the wake source out of the WK_STAT_1
register via SPI. No interrupt is generated when coming out of Sleep Mode. The microcontroller can now for
example switch the CAN transceiver into CAN Normal Mode via SPI to start communication.
Table 12
Action due to CAN Bus Wake-Up
SBC Mode
SBC Mode after Wake
VCC1
INT
RXD
Normal Mode
Normal Mode
ON
LOW
LOW
Stop Mode
Stop Mode
ON
LOW
LOW
Sleep Mode
Restart Mode
Ramping Up
HIGH
LOW
Restart Mode
Restart Mode
ON
HIGH
LOW
Fail-Safe Mode
Restart Mode
Ramping up
HIGH
LOW
Data Sheet
56
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
9.2.5
TXD Time-out Feature
If the TXD signal is dominant for a time t > tTXD_CAN_TO, in CAN Normal Mode, the TXD time-out function deactivates
the transmission of the signal at the bus. This is implemented to prevent the bus from being blocked permanently
due to an error. The transmitter is disabled and the transceiver is switched to Receive Only Mode. The failure is
stored in the SPI flag CAN_FAIL. The CAN transmitter stage is activated again after the dominant time-out
condition is removed and the transceiver is automatically switched back to CAN Normal Mode.The transceiver
configuration stays unchanged.
9.2.6
Bus Dominant Clamping
If the HS CAN bus signal is dominant for a time t > tBUS_CAN_TO, regardless of the CAN transceiver mode a bus
dominant clamping is detected and the SPI bit CAN_FAIL is set. The transceiver configuration stays unchanged.
9.2.7
Under Voltage Detection
The voltage at the CAN supply pin is monitored in CAN Normal Mode only. In case of VCAN under voltage a
signalization via SPI bit VCAN_UV is triggered and the SBC disables the transmitter stage. If the CAN supply
reaches a higher level than the under voltage detection threshold (VCAN > VCAN_UV), the transceiver is
automatically switched back to CAN Normal Mode. The transceiver configuration stays unchanged.
Data Sheet
57
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
9.3
Electrical Characteristics
Table 13
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
–
0.80
0.90
Unit
Note /
Test Condition
Number
V
P_10.3.2
Vdiff = VCANH VCANL ;
-12V ≤ VCM(CAN)
CAN Bus Receiver
Differential Receiver
Threshold Voltage,
recessive to dominant edge
Vdiff,rd_N
≤ +12 V;
CAN Normal
Mode
Differential Receiver
Threshold Voltage,
dominant to recessive edge
Vdiff,dr_N
0.50
0.60
–
V
P_10.3.3
Vdiff = VCANH VCANL;
-12V ≤ VCM(CAN)
≤ +12 V;
CAN Normal
Mode
Common Mode Range
CMR
-12
–
12
V
1)
P_10.3.4
CANH, CANL Input
Resistance
Rin
20
40
50
kΩ
CAN Normal /
Wake capable
Mode;
Recessive state
P_10.3.6
Differential Input Resistance
Rdiff
40
80
100
kΩ
CAN Normal /
Wake capable
Mode;
Recessive state
P_10.3.7
Input Resistance Deviation
between CANH and CANL
∆R i
-3
–
3
%
1)
Input Capacitance CANH,
CANL versus GND
Cin
–
20
40
pF
1)
P_10.3.39
–
10
20
pF
1)
P_10.3.40
Differential Input Capacitance Cdiff
Recessive state P_10.3.38
VTXD = 5V
VTXD = 5V
Wake-up Receiver
Threshold Voltage,
recessive to dominant edge
Vdiff, rd_W
–
0.8
1.15
V
-12V ≤ VCM(CAN) P_10.3.8
≤ +12 V;
CAN Wake
Capable Mode
Wake-up Receiver
Threshold Voltage,
dominant to recessive edge
Vdiff, dr_W
0.4
0.7
–
V
-12V ≤ VCM(CAN) P_10.3.9
≤ +12 V;
CAN Wake
Capable Mode
Data Sheet
58
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Table 13
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
CAN Bus Transmitter
CANH/CANL Recessive
Output Voltage
(CAN Normal Mode)
VCANL/H_NM
2.0
–
3.0
V
CAN Normal
Mode;
VTXD = VCC1;
no load
P_10.3.11
CANH/CANL Recessive
Output Voltage
(CAN Wake Capable Mode)
VCANL/H_LP
-0.1
–
0.1
V
CAN Wake
Capable Mode;
VTXD = VCC1;
no load
P_10.3.43
CANH, CANL Recessive
Output Voltage Difference
Vdiff_r_N
-500
–
50
mV
CAN Normal
Mode
VTXD = VCC1;
no load
P_10.3.12
Vdiff_r_W
-500
–
50
mV
CAN Wake
Capable Mode;
VTXD = VCC1;
no load
P_10.3.41
CANL Dominant Output
Voltage
VCANL
0.5
–
2.25
V
CAN Normal
Mode;
VTXD = 0 V;
VCAN = 5 V;
50Ω ≤ RL ≤ 65Ω
P_10.3.13
CANH Dominant Output
Voltage
VCANH
2.75
–
4.5
V
CAN Normal
Mode;
VTXD = 0 V;
VCAN = 5 V;
50Ω ≤ RL ≤ 65Ω
P_10.3.14
CANH, CANL Dominant
Output Voltage Difference
Vdiff = VCANH - VCANL
Vdiff_d_N
1.5
–
3.0
V
CAN Normal
Mode;
VTXD = 0 V;
VCAN = 5 V;
50Ω ≤ RL ≤ 65Ω
P_10.3.16
Driver Symmetry
VSYM = VCANH + VCANL
VSYM
4.5
–
5.5
V
2)
CAN Normal
Mode;
VTXD = 0 V / 5 V;
VCAN = 5 V;
CSPLIT = 4.7nF;
50Ω ≤ RL ≤ 60Ω
P_10.3.42
CANH Short Circuit Current
ICANHsc
-100
-80
-50
mA
CAN Normal
Mode;
VCANHshort = 0 V
P_10.3.17
Vdiff = VCANH - VCANL
(CAN Normal Mode)
CANH, CANL Recessive
Output Voltage Difference
Vdiff = VCANH - VCANL
(CAN Wake Capable Mode)
Data Sheet
59
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Table 13
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
CANL Short Circuit Current
ICANLsc
50
80
100
mA
CAN Normal
Mode
VCANLshort = 18 V
P_10.3.18
Leakage Current
(unpowered device)
ICANH,lk
ICANL,lk
–
5
7.5
µA
VS = VCAN = 0V; P_10.3.19
0V < VCANH,L ≤ 5V;
3)
Rtest = 0 / 47 kΩ
VRXD,H
0.8 ×
–
–
V
CAN Normal
P_10.3.21
Mode
IRXD(CAN) = -2 mA;
VRXD,L
–
–
0.2 ×
V
CAN Normal
Mode
IRXD(CAN) = 2 mA;
P_10.3.22
HIGH Level Input Voltage
Threshold
VTXD,H
–
V
CAN Normal
Mode
recessive state
P_10.3.23
LOW Level Input Voltage
Threshold
VTXD,L
0.3 ×
TXD Input Hysteresis
VTXD,hys
–
RTXD
tCAN,EN
20
–
Receiver Output RXD
HIGH level Output Voltage
LOW Level Output Voltage
VCC1
VCC1
Transmission Input TXD
TXD Pull-up Resistance
CAN Transceiver Enabling
Time
–
0.7 ×
VCC1
–
–
V
CAN Normal
Mode
dominant state
P_10.3.24
0.12 ×
–
mV
1)
P_10.3.25
40
80
kΩ
–
P_10.3.26
10
–
µs
4)
VCC1
VCC1
CSN = HIGH to P_10.3.27
first valid
transmitted TXD
dominant
Dynamic CAN-Transceiver Characteristics
Min. Dominant Time for Bus
Wake-up
tWake1
0.50
–
3
µs
-12V ≤ VCM(CAN) P_10.3.28
≤ +12 V;
CAN Wake
capable Mode
Wake-up Time-out,
Recessive Bus
tWake2
0.5
–
10
ms
4)
WUP Wake-up
Reaction Time
tWU_WUP
–
–
100
µs
4)5)6)
Data Sheet
60
CAN Wake
capable Mode
P_10.3.29
P_10.3.44
Wake-up
reaction time after
a valid WUP on
CAN bus;
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Table 13
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
Propagation Delay
TXD-to-RXD LOW
(recessive to dominant)
td(L),TR
–
150
255
ns
2)
CAN Normal
Mode
CL = 100 pF;
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF
P_10.3.30
Propagation Delay
TXD-to-RXD HIGH
(dominant to recessive)
td(H),TR
–
150
255
ns
2)
CAN Normal
Mode
CL = 100 pF;
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF
P_10.3.31
Propagation Delay
TXD LOW to bus dominant
td(L),T
–
50
–
ns
CAN Normal
Mode
CL = 100pF;
RL = 60 Ω;
VCAN = 5 V;
P_10.3.32
Propagation Delay
TXD HIGH to bus recessive
td(H),T
–
50
–
ns
CAN Normal
Mode
CL = 100 pF;
RL = 60 Ω;
VCAN = 5 V;
P_10.3.33
Propagation Delay
bus dominant to RXD LOW
td(L),R
–
100
–
ns
CAN Normal
Mode
CL = 100pF;
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF
P_10.3.34
Propagation Delay
bus recessive to RXD HIGH
td(H),R
–
100
–
ns
CAN Normal
Mode
CL = 100pF;
RL = 60 Ω
VCAN = 5 V;
CRXD = 15 pF
P_10.3.35
400
–
550
ns
CAN Normal
Mode
CL = 100pF;
RL = 60 Ω;
VCAN = 5 V;
CRXD = 15 pF;
tbit(TXD) = 500ns;
Refer to
Figure 24
P_10.3.46
Recessive Bit Width on RXD tbit(RXD)
(CAN FD up to 2Mbps)
Data Sheet
Values
61
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Table 13
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with
respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max.
TXD Permanent Dominant
Time-out
tTxD_CAN_TO
–
2
BUS Permanent Dominant
Time-out
tBUS_CAN_TO
–
2
1)
2)
3)
4)
5)
6)
Values
Unit
Note /
Test Condition
Number
–
ms
4)
CAN Normal
Mode
P_10.3.36
–
ms
4)
P_10.3.37
CAN Normal
Mode
Not subject to production test, specified by design.
fTXD = 250 kHz rectangular signal, duty cycle = 50%;
Rtest between supply (VS / VCAN) and 0V (GND);
Not subject to production test, tolerance defined by internal oscillator tolerance;
Wake-up is signalized via INT pin activation in SBC Stop Mode and via VCC1 ramping up with wake from SBC Sleep Mode;
Time starts with end of last dominant phase of WUP;
V TXD
V CC 1
GND
V DIFF
t d(L ),T
V diff, rd_N
V diff, dr_N
t d(L),R
V RXD
V CC 1
t
t d(H),T
t
t d(H),R
t d(L),TR
td (H),TR
0.8 x VCC 1
GND
0.2 x V CC1
t
CA N dynamic characteristics.vsd
Figure 23
Data Sheet
Timing Diagrams for Dynamic Characteristics
62
Rev. 1.1, 2014-09-26
TLE9260QX
High Speed CAN Transceiver
Figure 24
Data Sheet
Timing Diagrams for RXD recessive bit width definition tbit(RXD)
63
Rev. 1.1, 2014-09-26
TLE9260QX
Wake and Voltage Monitoring Inputs
10
Wake and Voltage Monitoring Inputs
10.1
Block Description
Internal Supply
I PU_WK
+
WKx
I PD_WK
t WK
VRef
Logic
MONx_Input_Circuit_ext.vsd
Figure 25
Wake Input Block Diagram
Features
•
Three High-Voltage inputs with a 3V (typ.) threshold voltage
•
Alternate Measurement function for high-voltage sensing via WK1 and WK2
•
Wake-up capability for power saving modes
•
Edge sensitive wake feature LOW to HIGH and HIGH to LOW
•
Pull-up and Pull-down current sources, configurable via SPI
•
Selectable configuration for static sense or cyclic sense working with TIMER1, TIMER2
•
In SBC Normal and SBC Stop Mode the level of the WK pin can be read via SPI even if the respective WK is
not enabled as a wake source.
Data Sheet
64
Rev. 1.1, 2014-09-26
TLE9260QX
Wake and Voltage Monitoring Inputs
10.2
Functional Description
The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both
transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either
in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep
and SBC Fail-Safe Mode.
Two different wake detection modes can be selected via SPI:
•
Static sense: WK inputs are always active
•
Cyclic sense: WK inputs are only active for a certain time period (see Chapter 5.2.1)
Two different filter times of 16µs or 64µs can be selected to avoid a parasitic wake-up due to transients or EMC
disturbances in static sense configuration.
The filter time (tFWK1, tFWK2) is triggered by a level change crossing the switching threshold and a wake signal is
recognized if the input level will not cross again the threshold during the selected filter time.
Figure 26 shows a typical wake-up timing and parasitic filter.
VWK
VWK,th
VWK,th
t
VINT
tWK,f
tWK,f
t INT
t
No Wake Event
Figure 26
Wake Event
Wake-up Filter Timing for Static Sense
The wake-up capability for each WK pin can be enabled or disabled via SPI command in the WK_CTRL_2
register.
The wake source for a wake via a WKx pin can always be read in the register WK_STAT_1 at the bits WK1_WU,
WK2_WU, and WK3_WU.
The actual voltage level of the WK pin (LOW or HIGH) can always be read in SBC Normal and SBC Stop Mode
in the register WK_LVL_STAT. During Cyclic Sense, the register show the sampled levels of the respective WK
pin.
If FO2...3 are configured as WK inputs in its alternative function (16µs static filter time), then the wake events will
be signalled in the register WK_STAT_2.
Data Sheet
65
Rev. 1.1, 2014-09-26
TLE9260QX
Wake and Voltage Monitoring Inputs
10.2.1
Wake Input Configuration
To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure integrated
current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes (including the filter
time) can be configured via the SPI register WK_FLT_CTRL. An example illustration for the automatic switching
configuration is shown in Figure 27.
Table 14
WKx_PUPD
_1
Pull-Up / Pull-Down Resistor
WKx_PUPD
_0
Current Sources Note
0
0
no current source WKx input is floating if left open (default setting)
0
1
pull-down
WKx input internally pulled to GND
1
0
pull-up
WKx input internally pulled to internal 5V supply
1
1
Automatic
switching
If a high level is detected at the WKx input the pull-up source is
activated, if low level is detected the pull down is activated.
Note: If there is no pull-up or pull-down configured on the WK input, then the respective input should be tied to
GND or VS on board to avoid unintended floating of the pin and subsequent wake events.
IWKth_min
I WK
I WKth_max
VWKth
Figure 27
Illustration for Pull-Up / Down Current Sources with Automatic Switching Configuration
Table 15
Wake Detection Configuration and Filter Time
WKx_FLT_1 WKx_FLT_0 Filter Time
Description
0
0
Config A
static sense, 16µs filter time
0
1
Config B
static sense, 64µs filter time
1
0
Config C
Cyclic sense, Timer 1, 16µs filter time. Period, On-time
configurable in register TIMER1_CTRL
1
1
Config D
Cyclic sense, Timer 2, 16µs filter time. Period, On-time
configurable in register TIMER2_CTRL
Config A and B are intended for static sense with two different filter times.
Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to be
assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1
controlled by Timer 2 (HS1 = 010) and connected to WK3 via an switch circuitry - see also Chapter 5.2.
Data Sheet
66
Rev. 1.1, 2014-09-26
TLE9260QX
Wake and Voltage Monitoring Inputs
10.2.2
Alternate Measurement Function with WK1 and WK2
10.2.2.1
Block Description
This function provides the possibility to measure a voltage, e.g. the unbuffered battery voltage, with the protected
WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage compensation for LED
lighting by changing the duty cycle of the High-Side outputs. A simple voltage divider needs to be placed externally
to provide the correct voltage level to the microcontroller A/D converter input.
The function is available in SBC Normal Mode and it is disabled in all other modes to allow a low-quiescent current
operation.The measurement function can be used instead of the WK1 and WK2 wake and level signalling
capability.
The benefits of the function is that the signal is measured by a HV-input pin and that there is no current flowing
through the resistor divider during low-power modes.
The functionality is shown in a simplified application diagram in Figure 48.
10.2.2.2
Functional Description
This measurement function is by default disabled. In this case, WK1 and WK2 have the regular wake and voltage
level signalization functionality. The switch S1 is open for this configuration (see Figure 48).
The measurement function can be enabled via the SPI bit WK_MEAS.
If WK_MEAS is set to ‘1’, then the measurement function is enabled and switch S1 is closed in SBC Normal Mode.
S1 is open in all other SBC modes. If this function the pull-up and down currents of WK1 and WK2 are disabled,
and the internal WK1 and WK2 signals are gated. In addition, the settings for WK1 and WK2 in the registers
WK_PUPD_CTRL, WK_FLT_CTRL and WK_CTRL_2 are ignored but changing these setting is not prevented.
The registers WK_STAT_1 and WK_LVL_STAT are not updated with respect to the inputs WK1 and WK2.
However, if only WK1 or WK2 are set as wake sources and a SBC Sleep Mode command is set, then the SPI_FAIL
flag will be set and the SBC will be changed into SBC Restart Mode (see Chapter 5.1 also for wake capability of
WK1 and WK2).
Table 16
Differences between Normal WK Function and Measurement Function
Affected Settings/Modules
for WK1 and WK2 Inputs
WK_MEAS = 0
WK_MEAS = 1
S1 configuration
‘open’
‘closed’ in SBC Normal Mode,
‘open’ in all other SBC Modes
Internal WK1 & WK2 signal
processing
Default wake and level signaling
function, WK_STAT_1, WK_STAT_2
are updated accordingly
‘WK1...2 inputs are gated internally,
WK_STAT_1, WK_STAT_2 are not
updated
WK1_EN, WK2_EN
Wake-up via WK1 and WK2 possible if setting the bits is ignored and not
bits are set
prevented. If only WK1_EN, WK2_EN
are set while trying to go to SBC Sleep
Mode, then the SPI_FAIL flag will be
set and the SBC will be changed into
SBC Restart Mode.
WK_PUPD_CTRL
normal configuration is possible
no pull-up or pull-down enabled
WK_FLT_CTRL
normal configuration is possible
setting the bits is ignored and not
prevented
Note: There is a diode in series to the switch S1 (not shown in the Figure 48), which will influence the temperature
behavior of the switch.
Data Sheet
67
Rev. 1.1, 2014-09-26
TLE9260QX
Wake and Voltage Monitoring Inputs
10.3
Electrical Characteristics
Table 17
Electrical Characteristics
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Min.
Unit
Note / Test Condition Number
Typ.
Max.
3
4
V
without external serial
resistor RS (with RS:
∆V = IPD/PU * RS);
hysteresis included
P_12.3.1
-
0.7
V
without external serial
resistor RS (with RS:
∆V = IPD/PU * RS);
P_12.3.2
VWK_IN = 4V
VWK_IN = 2V
P_12.3.3
P_12.3.5
WK1...WK3 Input Pin Characteristics
Wake-up/monitoring
threshold voltage
VWKth
Threshold hysteresis
VWKNth,hys 0.1
WK pin Pull-up Current IPU_WK
2
-20
-10
-3
µA
WK pin Pull-down
Current
IPD_WK
3
10
20
µA
Input leakage current
ILK,l
-2
2
µA
0 V < VWK_IN < 40V
–
1000
–
mV
1)
Drop Voltage
P_12.3.13
between WK1 and
WK2 when enabled for
voltage measurement;
IWK1 = 500µA;
Tj = 25°C
Refer to Figure 28
-
16
-
µs
2)
P_12.3.6
µs
2)
P_12.3.7
Drop Voltage across S1 VDrop,S1
switch
P_12.3.4
Timing
Wake-up filter time 1
Wake-up filter time 2
tFWK1
tFWK2
-
64
-
SPI Setting
SPI Setting
1) Not subject to production test; specified by design
2) Not subject to production test, tolerance defined by internal oscillator tolerance
Data Sheet
68
Rev. 1.1, 2014-09-26
TLE9260QX
Wake and Voltage Monitoring Inputs
1100
VS = 13.5V
VS1,VOLTA
AGEDROPOFSWITCHS1(mV)
1000
500 μA
900
800
250 μA
700
100 μA
600
50 μA
500
50
0
50
100
150
Tj JUNCTIONTEMPERATURE(°C)
Figure 28
Data Sheet
Typical Drop Voltage Characteristics of S1 (between WK1 & WK2)
69
Rev. 1.1, 2014-09-26
TLE9260QX
Interrupt Function
11
Interrupt Function
11.1
Block and Functional Description
Vcc1
Time
out
Interrupt logic
Figure 29
INT
Interrupt Block Diagram
The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed
as a push/pull output stage as shown in Figure 29. An interrupt is triggered and the INT pin is pulled low (active
low) for tINT in SBC Normal and Stop Mode and it is released again once tINT is expired. The minimum HIGH-time
of INT between two consecutive interrupts is tINTD. An interrupt does not cause a SBC mode change.
Two different interrupt classes could be selected via the SPI bit INT_ GLOBAL:
•
Class 1 (wake interrupt - INT_ GLOBAL=0): all wake-up events stored in the wake status SPI register
(WK_STAT_1 and WK_STAT_2) cause an interrupt (default setting). An interrupt is only triggered if the
respective function is also enabled as a wake source (including GPIOx if configured as a wake input).
•
Class 2 (global interrupt - INT_ GLOBAL=1): in addition to the wake-up events, all signalled failures stored in
the other status registers cause an interrupt (the register WK_LVL_STAT is not generating interrupts)
Note: The errors which will cause SBC Restart or SBC Fail-Safe Mode (Vcc1_UV, WD_FAIL, VCC1_SC, TSD2,
FAILURE) are the exceptions of an INT generation on status bits. Also POR and DEV_STAT_x and will not
generate interrupts.
In addition to this behavior, an INT will be triggered when the SBC is sent to SBC Stop Mode and not all bits were
cleared in the WK_STAT_1 and WK_STAT_2register.
The SPI status registers are updated at every falling edge of the INT pulse. All interrupt events are stored in the
respective register (except the register WK_LVL_STAT) until the register is read and cleared via SPI command.
A second SPI read after reading out the respective status register is optional but recommended to verify that the
interrupt event is not present anymore. The interrupt behavior is shown in Figure 30 for class 1 interrupts. The
behavior for class 2 is identical.
The INT pin is also used during SBC Init Mode to select the hardware configuration of the device. See
Chapter 5.1.1 for further information.
Data Sheet
70
Rev. 1.1, 2014-09-26
TLE9260QX
Interrupt Function
WK1
WK2
INT
tINTD
tINT
Scenario 2
Scenario 1
Update of
WK_STAT register
Update of
WK_STAT register
optional
SPI
Read & Clear
WK_STAT
contents
SPI
Read & Clear
WK1
no WK
WK2
no WK
WK1 + WK2
no WK
No SPI Read & Clear
Command sent
WK_STAT
contents
Interrupt_Behavior .vsd
Figure 30
Data Sheet
Interrupt Signalization Behavior
71
Rev. 1.1, 2014-09-26
TLE9260QX
Interrupt Function
11.2
Electrical Characteristics
Table 18
Interrupt Output
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
VINT,H
0.8 ×
–
–
V
1)
IINT = -1 mA;
INT = OFF
P_13.2.1
VINT,L
–
–
0.2 ×
V
1)
IINT = 1 mA;
INT = ON
P_13.2.2
µs
2)
P_13.2.3
Interrupt Output; Pin INT
INT High Output Voltage
INT Low Output Voltage
tINT
INT Pulse Minimum Delay tINTD
INT Pulse Width
VCC1
VCC1
–
100
–
–
100
–
µs
2)
between
consecutive pulses
P_13.2.4
Time
Configuration Select; Pin INT
Config Pull-down
Resistance
RCFG
–
250
–
kΩ
VINT = 5 V
P_13.2.5
Config Select Filter Time
tCFG_F
–
7
–
µs
2)
P_13.2.6
1) Output Voltage Value also determines device configuration during SBC Init Mode
2) Not subject to production test, tolerance defined by internal oscillator tolerance.
Data Sheet
72
Rev. 1.1, 2014-09-26
TLE9260QX
Fail Outputs
12
Fail Outputs
12.1
Block and Functional Description
5V_int
SBC Init
Mode
T test
R TEST
FO1/2
Failure logic
FO3/TEST
T FO_PL
Failure Logic
Figure 31
Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST
The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low
signalization.
The fail outputs are activated due to following failure conditions:
•
Watchdog trigger failure (For config 3&4 only after the 2nd watchdog trigger failure and for config 1&2 after 1st
watchdog trigger failure)
•
Thermal shutdown TSD2
•
VCC1 short to GND
•
VCC1 over voltage (only if the SPI bit VCC1_OV_RST is set)
•
After 4 consecutive VCC1 under voltage event (see Chapter 13.6 for details)
At the same time SBC Fail-Safe Mode is entered (exceptions are watchdog trigger failures depending on selected
configurations - see Chapter 5.1.1).
The fail output activation is signalled in the SPI bit FAILURE of the register DEV_STAT.
For testing purposes only the Fail Outputs can also be activated via SPI by setting the bit FO_ON. This bit is
independent of the FO failure bits. In case that there is no failure condition, the FO outputs can also be turned off
again via SPI, i.e. no successful watchdog trigger is needed.
The entry of SBC Fail-Safe Mode due to a watchdog failure can be configured as described in Chapter 5.1.1.
In order to deactivate the fail outputs in SBC Normal Mode the failure conditions must not be present anymore
(e.g. TSD2, VCC1 short circuit, etc) and the bit FAILURE needs to be cleared via SPI command. In case of a
FAILURE bit setting due to a watchdog fail, a successful WD trigger is needed in addition, i.e. WD_FAIL must be
cleared. WD_FAIL will also be cleared when going to SBC Sleep or SBC Fail-Safe Mode due to another failure
(not a WD failure) or if the watchdog is disabled in SBC Stop Mode.
Note: The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the 1st
watchdog failure if selected for Config2.
The three fail outputs are activated simultaneously with following output functionalities:
•
FO1: Static fail output
•
FO2: 1.25Hz, 50% (typ.) duty cycle, e.g. to generate an indicator signal
Data Sheet
73
Rev. 1.1, 2014-09-26
TLE9260QX
Fail Outputs
•
FO3: 100Hz PWM, 20% (typ.) duty cycle, e.g. to generate a dimmed rear light from a break light.
Note: The duty cycle for FO3 can be configured via SPI option to 20%, 10%, 5% or 2.5%. Default value is 20%.
See the register FO_DC for configuration.
12.1.1
General Purpose I/O Functionality of FO2 and FO3 as Alternate Function
In case that FO2 and FO3 are not used in the application, those pins can also be configured with an alternate
function as high-voltage (VSHS related) General Purpose I/O pins.
VSHS
Config &
Control Logic
Figure 32
FOx/
GPIOx
Simplified General Purpose I/O block diagram for FO2 and FO3/TEST
The pins are by default configured as FO pins. The configuration is done via the SPI register GPIO_CTRL. The
alternate function can be:
•
Wake Inputs: The detection threshold VGPIOI,th is similar as for the WK inputs. The wake-up detection behavior
is the same as for WKx pins. Wake events are stored and reported in WK_STAT_2.
•
Low-Side Switches: The switch is able to drive currents of up to 10mA (see also VGPIOL,L1). It is self-protected
with regards to current limitation. No other diagnosis is implemented.
•
High-Side Switches: The switch is able to drive currents up to 10mA (see also VGPIOH,H1). It is self-protected
with regards to current limitation. No other diagnosis is implemented.
•
If configured as GPIO then the respective level at the pin will be shown in WK_LVL_STAT in SBC Normal and
Stop Mode. This is also the case if configured as LS/HS and can serve as a feedback about the respective
state. GPIO2 is shared with the TEST level bit.
Figure 33 describes the behavior of the FO/GPIO pins in their different configurations and SBC modes.
Function
FOx
WK
HS
LS
Figure 33
Normal Mode
configurable
Stop Mode
keeps the state
wake capable
as configured in Normal Mode
as configured in Normal Mode
Sleep Mode
keeps the state
wake capable
OFF
OFF
Fail-Safe Mode
active
OFF
OFF
OFF
FO / GPIO behavior for the respective SBC modes
Note: In order to avoid unintentional entry of SBC Development Mode care must be taken that the level of
FO3/TEST is HIGH during device power up and SBC Init Mode.
Note: The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by
VSHS
Data Sheet
74
Rev. 1.1, 2014-09-26
TLE9260QX
Fail Outputs
12.2
Electrical Characteristics
Table 19
Interrupt Output
VSHS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.1)
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
Pin FO1
FO1 low output voltage
(active)
VFO,L1
–
–
1.0
V
IFO = 4mA
P_14.2.1
FO1 high output current
(inactive)
IFO,H
0
–
2
µA
VFO = 28V
P_14.2.2
FO2 side indicator
frequency
fFO2SI
1.00
1.25
1.50
Hz
3)
P_14.2.3
FO2 side indicator duty
cycle
dFO2SI
–
50
–
%
3)
P_14.2.4
Pull-up Resistance at pin
FO3/TEST
RTEST
2.5
5
10
kΩ
VTEST =0V;
SBC Init Mode
P_14.2.5
TEST Input Filter Time
tTEST
fFO3PL
–
64
–
µs
3)
P_14.2.6
80
100
120
Hz
3)
P_14.2.7
dFO3PL
–
20
–
%
3)4)
Pin FO2
Pin FO3/TEST2)
FO3 pulsed
light frequency
FO3 pulsed
light duty cycle
default setting
P_14.2.8
Alternate FO2...3
Electrical Characteristics: GPIO
GPIO low-side output
voltage (active)
VGPIOL,L1
–
–
1
V
IGPIO = 10mA
P_14.2.9
GPIO low-side output
voltage (active)
VGPIOL,L2
–
–
5
mV
5)
IGPIO = 50µA
P_14.2.17
GPIO high-side output
voltage (active)
VGPIOH,H1 VSHS-1 –
–
V
IGPO = -10mA
P_14.2.10
GPIO high-side output
voltage (active)
VGPIOH,H2 VSHS-5 –
–
mV
5)
P_14.2.18
GPIO input threshold
voltage
VGPIOI,th
1.5
2.5
3.5
V
6)
hysteresis included P_14.2.11
GPIO input threshold
hysteresis
VGPIOI,hys 100
400
700
mV
5)
P_14.2.12
GPIO low-side current
limitation
IGPIOL,max 10
–
30
mA
VGPIO = 28V
P_14.2.13
GPIO high-side current
limitation
IGPIOH,max -45
–
-10
mA
VGPIO = 0V
P_14.2.14
IGPO = -50µA
1) The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS
Data Sheet
75
Rev. 1.1, 2014-09-26
TLE9260QX
Fail Outputs
2) The external capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC Development
Mode and SBC User Mode operation.
3) Not subject to production test, tolerance defined by internal oscillator tolerance.
4) The duty cyclic is adjustable via the SPI bits FO_DC.
5) Not subject to production test, specified by design.
6) Applies also for TEST voltage input level
Data Sheet
76
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13
Supervision Functions
13.1
Reset Function
VCC1
RO
Reset logic
Incl. filter & delay
Figure 34
Reset Block Diagram
13.1.1
Reset Output Description
The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the
output voltage has fallen below the under voltage threshold VRT1/2/3/4. In case of a reset event, the reset output RO
is pulled to low after the filter time tRF and stays low as long as the reset event is present plus a reset delay time
tRD1. When connecting the SBC to battery voltage, the reset signal remains LOW initially. When the output voltage
Vcc1 has reached the reset default threshold VRT1,r, the reset output RO is released to HIGH after the reset delay
time tRD1. A reset can also occur due to a watchdog trigger failure. The reset threshold can be adjusted via SPI,
the default reset threshold is VRT1,f. The RO pin has an integrated pull-up resistor. In case reset is triggered, it will
be pulled low for Vcc1 ≥ 1V and for VS ≥ VPOR,f (see also Chapter 13.3).
The timings for the RO triggering regarding VCC1 under voltage and watchdog trigger is shown in Figure 35.
Data Sheet
77
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
VCC
VRT1
t < tRF
The reset threshold can be
configured via SPI in SBC
Normal Mode , default is VRT1
undervoltage
t RD1
t CW
tLW
tCW
SPI
SPI
Init
tOW
t
tLW
tOW
WD
Trigger
t CW
t RD1
WD
Trigger
SPI
Init
t
tRF
RO
tLW = long open window
tCW = closed window
tOW= open window
t
SBC Init
Figure 35
Reset Timing Diagram
13.1.2
Soft Reset Description
SBC Normal
SBC Restart
SBC Normal
In SBC Normal and SBC Stop Mode, it is also possible to trigger a device internal reset via a SPI command in
order to bring the SBC into a defined state in case of failures. In this case the microcontroller must send a SPI
command and set the MODE bits to ‘11’ in the M_S_CTRL register. As soon as this command becomes valid, the
SBC is set back to SBC INIT Mode and all SPI registers are set to their default values (see SPI Chapter 14.5 and
Chapter 14.6).
Two different soft reset configurations are possible via the SPI bit SOFT_ RESET_RO:
•
The reset output (RO) is triggered when the soft reset is executed (default setting, the same reset delay time
tRD1 applies)
•
The reset output (RO) is not triggered when the soft reset is executed
Note: The device must be in SBC Normal Mode or SBC Stop Mode when sending this command.
Otherwise, the command will be ignored.
Data Sheet
78
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.2
Watchdog Function
The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the
microcontroller stops serving the watchdog due to a lock up in the software.
Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN:
•
Time-Out Watchdog (default value)
•
Window Watchdog
The respective watchdog functions can be selected and programmed in SBC Normal Mode. The configuration
stays unchanged in SBC Stop Mode.
Please refer to Table 20 to match the SBC Modes with the respective watchdog modes.
Table 20
Watchdog Functionality by SBC Modes
SBC Mode
Watchdog Mode
Remarks
INIT Mode
Starts with Long Open Window Watchdog starts with Long Open Window after RO is
released
Normal Mode
WD Programmable
Stop Mode
Watchdog is fixed or OFF
Sleep Mode
OFF
SBC will start with Long Open Window when entering
SBC Normal Mode.
Restart Mode
OFF
SBC will start with Long Open Window when entering
SBC Normal Mode.
Window Watchdog, Time-Out watchdog or switched
OFF for SBC Stop Mode
The watchdog timing is programmed via SPI command. As soon as the watchdog is programmed, the timer starts
with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid SPI-write
command to the watchdog configuration register. The trigger SPI command is executed when the Chip Select
input (CSN) becomes HIGH.
When coming from SBC Init, SBC Restart Mode or in certain cases from SBC Stop Mode, the watchdog timer is
always started with a long open window. The long open window (tLW = 200ms) allows the microcontroller to run its
initialization sequences and then to trigger the watchdog via SPI.
The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER) and is in the range of
10 ms to 1000 ms. This setting is valid for both watchdog types.
The following watchdog timer periods are available:
•
WD Setting 1: 10ms
•
WD Setting 2: 20ms
•
WD Setting 3: 50ms
•
WD Setting 4: 100ms
•
WD Setting 5: 200ms
•
WD Setting 6: 500ms
•
WD Setting 7: 1000ms
In case of a watchdog reset, SBC Restart or SBC Fail-Safe Mode is entered according to the configuration and
the SPI bits WD_FAIL are set. Once the RO goes HIGH again the watchdog immediately starts with a long open
window the SBC enters automatically SBC Normal Mode.
In SBC Software Development Mode the watchdog is OFF and therefore no reset and interrupt are generated due
to a watchdog failure.
Data Sheet
79
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows:
•
In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the watchdog
counter expires without a valid trigger) then the WD_FAIL bits will be increased (showing the number of
incorrect WD triggers)
•
For config 2: the bits can have the maximum value of ‘01’
•
For config 1, 3 and 4: the bits can have the maximum value of ‘10’
The WD_FAIL bits are cleared automatically when following conditions apply:
•
After a successful watchdog trigger
•
When the watchdog is OFF: in SBC Stop Mode after successfully disabling it, in SBC Sleep Mode, or in SBC
Fail-Safe Mode (except for a watchdog failure)
13.2.1
Time-Out Watchdog
The time-out watchdog is an easier and less secure watchdog than a window watchdog as the watchdog trigger
can be done at any time within the configured watchdog timer period.
A correct watchdog service immediately results in starting a new watchdog timer period. Taking the tolerances of
the internal oscillator into account leads to the safe trigger area as defined in Figure 36.
If the time-out watchdog period elapses, a watchdog reset is created by setting the reset output RO low and the
SBC switches to SBC Restart or SBC Fail-Safe Mode.
Typical timout watchdog trigger period
t WD x 1.50
open window
uncertainty
Watchdog Timer Period (WD_TIMER)
tWD x 1.20
t WD x 1.80
t / [tWD_TIMER]
safe trigger area
Wd1_TimeOut_per.vsd
Figure 36
Data Sheet
Time-out Watchdog Definitions
80
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.2.2
Window Watchdog
Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer period
is divided between an closed and an open window. The watchdog must be triggered within the open window.
A correct watchdog trigger results in starting the window watchdog period by a closed window followed by an open
window.
The watchdog timer period is at the same time the typical trigger time and defines the middle of the open window.
Taking the oscillator tolerances into account leads to a safe trigger area of:
tWD x 0.72 < safe trigger area < tWD x 1.20.
The typical closed window is defined to a width of 60% of the selected window watchdog timer period. Taking the
tolerances of the internal oscillator into account leads to the timings as defined in Figure 37.
A correct watchdog service immediately results in starting the next closed window.
Should the trigger signal meet the closed window or should the watchdog timer period elapse, then a watchdog
reset is created by setting the reset output RO low and the SBC switches to SBC Restart or SBC Fail-Safe Mode.
tWD x 0.6
tWD x 0.9
Typ. closed window
Typ. open window
tWD x 0.48
closed window
tWD x 0.72
uncertainty
tWD x 1.0
tWD x 1.20
open window
tWD x 1.80
uncertainty
Watchdog Timer Period (WD_TIMER)
t / [tWD _TIMER ]
safe trigger area
Figure 37
Window Watchdog Definitions
13.2.3
Watchdog Setting Check Sum
A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting.
The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (1)). This is
realized by either setting the bit CHECKSUM to 0 or 1. If the check sum is wrong, then the SPI command is
ignored, i.e. the watchdog is not triggered or the settings are not changed and the bit SPI_FAIL is set.
The checksum is calculated by taking all 8 data bits into account. The written value of the reserved bit 3 of the
WWD_CTRL register is considered (even if read as ‘0’ in the SPI output) for checksum calculation, i.e. if a 1 is
written on the reserved bit position, then a 1 will be used in the checksum calculation.
(1)
CHKSUM = Bit15 ⊕ … ⊕ Bit8
Data Sheet
81
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.2.4
Watchdog during SBC Stop Mode
The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special
sequence to be followed in order to disable the watchdog as described in Figure 38. Two different SPI bits
(WD_STM_ EN_0, WD_STM_ EN_1) in the registers WK_CTRL_1 and WD_CTRL need to be set.
Correct WD disabling
sequence
Sequence Errors
•
Missing to set bit
WD_STM_EN_0 with the
next watchdog trigger after
having set WD_STM_EN_1
•
Staying in Normal Mode
instead of going to Stop
Mode with the next trigger
Set bit
WD_STM_EN_1 = 1
with next WD Trigger
Set bit
WD_STM_EN_0 = 1
Before subsequent WD Trigger
Will enable the WD :
Change to
SBC Stop Mode
•
Switching back to SBC
Normal Mode
•
Triggering the watchdog
WD is switched off
Figure 38
Watchdog disabling sequence in SBC Stop Mode
If a sequence error occurs, then the bit WD_STM_ EN_1 will be cleared and the sequence has to be started again.
The watchdog can be enabled by triggering the watchdog in SBC Stop Mode or by switching back to SBC Normal
Mode via SPI command. In both cases the watchdog will start with a long open window and the bits
WD_STM_EN_1 and WD_STM_ EN_0 are cleared. After the long open window the watchdog has to be served
as configured in the WD_CTRL register.
Note: The bit WD_STM_ EN_0 will be cleared automatically when the sequence is started and it was 1 before.
13.2.5
Watchdog Start in SBC Stop Mode due to Bus Wake
In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog
with any BUS wake (CAN) during SBC Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS = 1
(= default value after POR). The bit can only be changed in SBC Normal Mode and needs to be programmed
before starting the watchdog disable sequence.
A wake on CAN will generate an interrupt and the RXD pin for CAN is pulled to low. By these signals the
microcontroller is informed that the watchdog is startedwith a long open window. After the long open window the
watchdog has to be served as configured in the WD_CTRL register.
To disable the watchdog again, the SBC needs to be switched to Normal Mode and the sequence needs to be
sent again.
Data Sheet
82
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.3
VS Power On Reset
At power up of the device, the VS Power on Reset is detected when VS > VPOR,r and the SPI bit POR is set to
indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be kept
LOW and will only be released once VCC1 has crossed VRT1,r and after tRD1 has elapsed.
In case VS < VPOR,f, an device internal reset will be generated and the SBC is switched OFF and will restart in INIT
mode at the next VS rising. This is shown in Figure 39.
VS
VPOR,r
VPOR,f
t
VCC1
VRT1,r
The reset threshold can be
configured via SPI in SBC
Normal Mode , default is VRT1
VRTx,f
t
RO
SBC Restart Mode is
entered whenever the
Reset is triggered
t
SBC Mode
SBC OFF
tRD1
SBC INIT MODE
Any SBC MODE
Restart
SBC OFF
t
SPI
Command
Figure 39
Data Sheet
Ramp up / down example of Supply Voltage
83
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.4
Under Voltage VS and VSHS
If the supply voltage VS reaches the under voltage threshold VS,UV then the SBC does the following measures:
•
SPI bit VS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present
anymore,
•
The VCC1 short circuit protection becomes inactive (see Chapter 13.7). However, the thermal protection of
the device remains active.
If the under voltage threshold is exceeded (VS rising) then functions will be automatically enabled again.
If the supply voltage VSHS passes below the under voltage threshold (VSHS,UVD) the SBC does the following
measures:
•
HS1...4 are acting accordingly to the SPI setting (see Chapter 8)
•
SPI bit VSHS_UV is set. No other error bits are set. The bit can be cleared once the condition is not present
anymore,
•
VCC1, VCC2, WKx and CAN are not affected by VSHS under voltage
13.5
Over Voltage VSHS
If the supply voltage VSHS reaches the over voltage threshold (VSHS,OVD) the SBC triggers the following measures:
•
HS1...4 are acting accordingly to the SPI setting (see Chapter 8)
•
SPI bit VSHS_OV is set. No other error bits are set. The bit can be cleared once the condition is not present
anymore,
•
VCC1, VCC2, WKx and CAN are not affected by VS over voltage
13.6
VCC1 Over-/ Under Voltage and Under Voltage Prewarning
13.6.1
VCC1 Under Voltage and Under Voltage Prewarning
A first-level voltage detection threshold is implemented as a prewarning for the microcontroller. The prewarning
event is signaled with the bit VCC1_ WARN. No other actions are taken.
As described in Chapter 13.1 and Figure 40, a reset will be triggered (RO pulled ‘low’) when the VCC1 output
voltage falls below the selected under voltage threshold (VRTx). The bit VCC1_UV is set and the SBC will enter
SBC Restart Mode.
Note: The VCC1_ WARN or VCC1_UV bits are not set in Sleep Mode as VCC1 = 0V in this case
Data Sheet
84
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
VCC1
VRTx
tRF
t
tRD1
RO
t
SBC Normal
Figure 40
SBC Restart
SBC Normal
VCC1 Under Voltage Timing Diagram
An additional safety mechanism is implemented to avoid repetitive VCC1 under voltage resets due to high dynamic
loads on VCC1:
•
A counter is increased for every consecutive VCC1 under voltage event (regardless on the selected reset
threshold),
•
The counter is active in SBC Init-, Normal-, and Stop Mode,
•
For VS < VS,UV the counter will be stopped in SBC Normal Mode (i.e. the VS UV comparator is always enabled
in SBC Normal Mode),
•
A 4th consecutive VCC1 under voltage event will lead to SBC Fail-Safe Mode entry and to setting the bit
VCC1_UV _FS
•
This counter is cleared:
–
when SBC Fail-Safe Mode is entered,
–
when the bit VCC1_UV is cleared,
–
when a Soft Reset is triggered.
Note: It is recommended to clear the VCC1_UV bit once it was set and detected.
13.6.2
VCC1 Over Voltage
For fail-safe reasons a configurable VCC1 over voltage detection feature is implemented. It is active in SBC Init-,
Normal-, and Stop Mode.
In case the VCC1,OV,r threshold is crossed, the SBC triggers following measures depending on the configuration:
•
The bit VCC1_ OV is always set;
•
If the bit VCC1_OV_RST is set and CFGP = ‘1’, then SBC Restart Mode is entered. The FOx outputs are
activated. After the reset delay time (tRD1), the SBC Restart Mode is left and SBC Normal Mode is resumed
even if the VCC1 over voltage event is still present (see also Figure 41). The VCC1_OV_RST bit is cleared
automatically;
•
If the bit VCC1_OV_RST is set and CFGP = ‘0’, then SBC Fail-Safe Mode is entered and FOx outputs are
activated.
Note: In case the VCC1 output current in SBC STOP Mode is below the active peak threshold (IVCC1,Ipeak) it should
be considered to clear the bit VCC1_OV_RST before entering SBC Stop Mode to avoid unintentional SBC
Restart or Fail-Safe Mode entry and to ignore the VCC1_ OV bit due to external noise.
Data Sheet
85
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
VCC1
VCC1,OV
t
tOV_filt
RO
tRD1
t
SBC Normal
SBC Restart
Figure 41
VCC1 Over Voltage Timing Diagram
13.7
VCC1 Short Circuit Diagnostics
SBC Normal
The short circuit protection feature for VCC1 is implemented as follows (VS needs to be higher than VS,UV):
•
If VCC1 is not above the VRTx within tVCC1,SC after device power up or after waking from SBC Sleep Mode then
the SPI bit VCC1_SC bit is set, VCC1 is turned OFF, the FOx pins are enabled, FAILURE is set and SBC FailSafe Mode is entered. The SBC can be activated again via wake on CAN, WKx.
•
The same behavior applies, if VCC1 falls below VRTx for more than tVCC1,SC.
Note: The VCC1_SC flag is not set during power up of VCC1.
13.8
VCC2 Undervoltage and VCAN Undervoltage
An undervoltage warning is implemented for VCC2 and VCAN as follows:
•
VCC2 undervoltage Detection: In case VCC2 will drop below the VCC2,UV,f threshold, then the SPI bit VCC2_UV
is set and can be only cleared via SPI.
•
VCAN undvervoltage Detection: In case the voltage on VCAN will drop below the VCAN_UV threshold, then the SPI
bit VCAN_UV is set and can be only cleared via SPI.
Note: The VCC2_UV flag is not set during turn-on or turn-off of VCC2.
Data Sheet
86
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.9
Thermal Protection
Three independent and different thermal protection features are implemented in the SBC according to the system
impact:
•
Individual thermal shutdown of specific blocks
•
Temperature prewarning of main microcontroller supply VCC1
•
SBC thermal shutdown due to VCC1 over temperature
13.9.1
Individual Thermal Shutdown
As a first-level protection measure the output stages VCC2, CAN, and HSx are independently switched OFF if the
respective block reaches the temperature threshold TjTSD1. Then the TSD1 bit is set. This bit can only be cleared
via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the thermal shutdown
protection is only active if the respective block is ON.
The respective modules behave as follows:
•
VCC2: Is switched to OFF and the control bits VCC2_ON are cleared. The status bit VCC2_OT is set. Once
the over temperature condition is not present anymore, then VCC2 has to be configured again by SPI.
•
CAN: The transmitter is disabled and stays in CAN Normal Mode acting like CAN Receive only mode. The
status bits CAN_FAIL = ‘01’ are set. Once the over temperature condition is not present anymore, then the
CAN transmitter is automatically switched on.
•
HSx: If one or more HSx switches reach the TSD1 threshold, then all HSx switches are turned OFF and the
control bits for HSx are cleared (see registers HS_CTRL1 and HS_CTRL2). The status bits HSx_OC_OT are
set (see register HS_OC_OT_STAT). Once the over temperature condition is not present anymore, then HSx
has to be configured again by SPI.
Note: The diagnosis bits are not cleared automatically and have to be cleared via SPI once the overtemperature
condition is not present anymore.
Data Sheet
87
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.9.2
Temperature Prewarning
As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches
the thermal prewarning temperature threshold TjPW. Then the status bit TPW is set. This bit can only be cleared
via SPI once the overtemperature is not present anymore. Independent of the SBC Mode the thermal prewarning
is only active if the VCC1 is ON.
13.9.3
SBC Thermal Shutdown
As a highest level of thermal protection a temperature shutdown of the SBC is implemented if the main supply
VCC1 reaches the thermal shutdown temperature threshold TjTSD2. Once a TSD2 event is detected SBC Fail-Safe
Mode is entered for tTSD2 to allow the device to cool down. After this time has expired, the SBC will automatically
change via SBC Restart Mode to SBC Normal Mode (see also Chapter 5.1.6).
When a TSD2 event is detected, then the status bit TSD2 is set. This bit can only be cleared via SPI in SBC Normal
Mode once the overtemperature is not present anymore. Independent of the SBC Mode the thermal shutdown is
only active if VCC1 is ON.
Data Sheet
88
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
13.10
Electrical Characteristics
Table 21
Electrical Specification
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Min.
Typ.
Max.
Unit
Note /
Test Condition
Number
VCC1 Monitoring; VCC1 = 5.0V Version
Undervoltage Prewarning
Threshold Voltage PW,f
VPW,f
4.6
4.7
4.85
V
VCC1 falling,
SPI bit is set
P_15.10.1
Reset Threshold
Voltage RT1,f
VRT1,f
4.5
4.6
4.75
V
default setting;
VCC1 falling
P_15.10.3
Reset Threshold
Voltage RT1,r
VRT1,r
4.6
4.7
4.85
V
default setting;
VCC1 rising
P_15.10.4
Reset Threshold
Voltage RT2,f
VRT2,f
3.75
3.9
4.05
V
VCC1 falling
P_15.10.5
Reset Threshold
Voltage RT2,r
VRT2,r
3.85
4.0
4.15
V
VCC1 rising
P_15.10.6
Reset Threshold
Voltage RT3,f
VRT3,f
3.15
3.3
3.45
V
VS ≥ 4V;
VCC1 falling
P_15.10.7
Reset Threshold
Voltage RT3,r
VRT3,r
3.25
3.4
3.55
V
VS ≥ 4V;
VCC1 rising
P_15.10.8
Reset Threshold
Voltage RT4,f
VRT4,f
2.4
2.65
2.8
V
VS ≥ 4V;
VCC1 falling
P_15.10.9
Reset Threshold
Voltage RT4,r
VRT4,r
2.5
2.75
2.9
V
VS ≥ 4V;
VCC1 rising
P_15.10.10
Reset Threshold Hysteresis
VRT,hys
VCC1,OV,r
50
100
200
mV
–
P_15.10.11
5.2
–
5.5
V
1)5)
tVCC1,SC
–
4
–
ms
3)
P_15.10.12
Reset Low Output Voltage
VRO,L
–
0.2
0.4
V
P_15.10.14
Reset High Output Voltage
VRO,H
0.8 x
–
VCC1 + V
IRO = 1 mA for
VCC1 ≥ 1 V &
VS ≥ VPOR,f
IRO = -20 µA
VCC1 Over Voltage
Detection Threshold Voltage
VCC1 Short to GND Filter
Time
rising VCC1
P_15.10.50
Reset Generator; Pin RO
Reset Pull-up Resistor
Reset Filter Time
RRO
tRF
VCC1
P_15.10.15
0.3 V
10
20
40
kΩ
4
10
26
µs
VRO = 0 V
3)
VCC1 < VRT1x
P_15.10.16
P_15.10.17
to RO = L see also
Chapter 13.3
Reset Delay Time
Data Sheet
tRD1
1.5
2
2.5
89
ms
2) 3)
P_15.10.18
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
Table 21
Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
VCC2 Monitoring
VCC2 Undervoltage
Threshold Voltage (falling)
VCC2 Undervoltage
Threshold Voltage (rising)
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
VCC2,UV,f
4.5
–
4.75
V
VCC2 falling
P_15.10.19
VCC2,UV,r
4.6
–
4.9
V
VCC2 rising
P_15.10.77
20
100
250
mV
–
P_15.10.20
VCAN_UV
4.45
–
4.85
V
CAN Normal
Mode,
hysteresis
included;
P_15.10.23
tLW
fCLKSBC
–
200
–
ms
3)
P_15.10.24
0.8
1.0
1.2
MHz
–
P_15.10.25
–
ms
3)4)
P_15.10.75
VCC2 Undervoltage detection VCC2,UV, hys
hysteresis
VCAN Monitoring
CAN Supply under voltage
detection threshold
Watchdog Generator
Long Open Window
Internal Oscillator
Minimum Waiting time during SBC Fail-Safe Mode
Min. waiting time Fail-Safe
tFS,min
–
100
Power-on Reset, Over / Under Voltage Protection
VPOR,r
VPOR,f
VS,UV
–
4.5
V
VS increasing
P_15.10.26
–
3
V
VS decreasing
P_15.10.27
6.0
V
P_15.10.13
Supply UV
supervision for
VCC1 SC
detection;
hysteresis included
VSHS Over Voltage
Detection Threshold
VSHS,OVD
20
22
V
P_15.10.28
Supply OV
supervision for
HSx;
hysteresis included
VSHS Over Voltage
Detection hysteresis
VSHS,OVD,hys –
–
mV
5)
VSHS Under Voltage
Detection Threshold
VSHS,UVD
5.5
V
P_15.10.30
Supply UV
supervision for
HSx, and HS of
GPIOx;
hysteresis included
VSHS Under Voltage
Detection hysteresis
VSHS,UVD,hys –
–
mV
5)
VS Power on reset rising
VS Power on reset falling
VS Under Voltage Detection
Threshold
Data Sheet
5.3
–
500
4.8
200
90
P_15.10.29
P_15.10.31
Rev. 1.1, 2014-09-26
TLE9260QX
Supervision Functions
Table 21
Electrical Specification (cont’d)
VS = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current
defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Values
Unit
Min.
Typ.
Max.
Note /
Test Condition
Number
5)
Over Temperature Shutdown
Thermal Prewarning
Temperature
TjPW
125
145
165
°C
P_15.10.32
Thermal Shutdown TSD1
TjTSD1
TjTSD2
TjTSD,hys
165
185
200
°C
P_15.10.33
165
185
200
°C
P_15.10.34
–
25
–
°C
P_15.10.68
tTSD2
–
1
–
s
Thermal Shutdown TSD2
Thermal Shutdown
hysteresis
Deactivation time after
thermal shutdown TSD2
3)
P_15.10.35
1) It is ensured that the threshold VCC1,OV,r is always higher than the highest regulated VCC1 output voltage VCC1,out42.
2)
3)
4)
5)
The reset delay time will start when VCC1 crosses above the selected Vrtx threshold
Not subject to production test, tolerance defined by internal oscillator tolerance.
This time applies for all failure entries except a device thermal shutdown (TSD2 has a typ. 1s waiting time tTSD2)
Not subject to production test, specified by design.
Data Sheet
91
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14
Serial Peripheral Interface
14.1
SPI Block Description
The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK
provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 42).
The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After
the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.
The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for other
use.The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted
out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable.
CSN high to low: SDO is enabled. Status information transferred to output shift register
CSN
time
CSN low to high: data from shift register is transferred to output functions
CLK
time
Actual data
SDI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDI: will accept data on the falling edge of CLK signal
Actual status
SDO
ERR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-
New data
0 1
+ +
time
New status
ERR 0
+
1
+
time
SDO: will change state on the rising edge of CLK signal
Figure 42
Data Sheet
SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure
compared to the register description)
92
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.2
Failure Signalization in the SPI Data Output
When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI
commands are either invalid SBC mode commands or commands which are prohibited by the state machine to
avoid undesired device or system states (see below). In this case the diagnosis bit ‘SPI_FAIL’ is set and the SPI
Write command is ignored (mostly no partial interpretation). This bit can be only reset by actively clearing it via a
SPI command.
Invalid SPI Commands leading to SPI_FAIL are listed below:
•
Illegal state transitions: Going from SBC Stop to SBC Sleep Mode. In this case the SBC enters in addition the
SBC Restart Mode;
Trying to go to SBC Stop or SBC Sleep mode from SBC Init Mode. In this case SBC Normal Mode is entered;
•
Uneven parity in the data bit of the WD_CTRL register. In this case the watchdog trigger is ignored or the new
watchdog settings are ignored respectively;
•
In SBC Stop Mode: attempting to change any SPI settings, e.g. changing the watchdog configuration, PWM
settings and HS configuration settings during SBC Stop Mode, etc.;
the SPI command is ignored in this case;
only WD trigger, returning to Normal Mode, triggering a SBC Soft Reset, and Read & Clear status registers
commands are valid SPI commands in SBC Stop Mode;
•
When entering SBC Stop Mode and WK_STAT_1 and WK_STAT_2 are not cleared; SPI_FAIL will not be set
but the INT pin will be triggered;
•
Changing from SBC Stop to Normal Mode and changing the other bits of the M_S_CTRL register. The other
modifications will be ignored;
•
SBC Sleep Mode: attempt to go to Sleep Mode when all bits in the BUS_CTRL_1 and WK_CTRL_2 registers
are cleared. In this case the SPI_FAIL bit is set and the SBC enters Restart Mode.
Even though the Sleep Mode command is not entered in this case, the rest of the command (e.g modifying
VCC2 ) is executed and the values stay unchanged during SBC Restart Mode;
Note: At least one wake source must be activated in order to avoid a deadlock situation in SBC Sleep Mode,
i.e. the SBC would not be able to wake up anymore.
If the only wake source is a timer and the timer is OFF then the SBC will wake immediately from Sleep Mode
and enter Restart Mode;
No failure handling is done for the attempt to go to SBC STOP Mode when all bits in the registers
BUS_CTRL_1 and WK_CTRL_2 are cleared because the microcontroller can leave this mode via SPI;
•
Attempt to enter SBC Sleep Mode if WK_MEAS is set to ‘1’ and only WK1_EN or WK2_EN are set as wake
sources. Also in this case the SPI_FAIL bit is set and the SBC enters Restart Mode;
•
Setting a longer or equal on-time than the timer period of the respective timer;
•
SDI stuck at HIGH or LOW, e.g. SDI received all ‘0’ or all ‘1’;
Note: There is no SPI fail information for unused addresses.
Signalization of the ERR Flag (high active) in the SPI Data Output (see Figure 42):
The ERR flag presents an additional diagnosis possibility for the SPI communication. The ERR flag is being set
for following conditions:
•
in case the number of received SPI clocks is not 0 or 16,
•
in case RO is LOW and SPI frames are being sent at the same time.
Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not
valid if the CLK is high on a falling edge of CSN
Data Sheet
93
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
The number of received SPI clocks is not 0 or 16:
The number of received input clocks is supervised to be 0- or 16 clock cycles and the input word is discarded in
case of a mismatch (0 clock cycle to enable ERR signalization). The error logic also recognizes if CLK was high
during CSN edges. Both errors - 0 bit and 16 bit CLK mismatch or CLK high during CSN edges - are flagged in
the following SPI output by a “HIGH” at the data output (SDO pin, bit ERR) before the first rising edge of the clock
is received. The complete SPI command is ignored in this case.
RO is LOW and SPI frames are being sent at the same time:
The ERR flag will be set when the RO pin is triggered (during SBC Restart) and SPI frames are being sent to the
SBC at the same time. The behavior of the ERR flag will be signalized at the next SPI command for below
conditions:
•
if the command begins when RO is HIGH and it ends when RO is LOW,
•
if a SPI command will be sent while RO is LOW,
•
If a SPI command begins when RO is LOW and it ends when RO is HIGH.
and the SDO output will behave as follows:
•
always when RO is LOW then SDO will be HIGH,
•
when a SPI command begins with RO is LOW and ends when RO is HIGH, then the SDO should be ignored
because wrong data will be sent.
Note: It is possible to quickly check for the ERR flag without sending any data bits. i.e. only the CSN is pulled low
and SDO is observed - no SPI Clocks are sent in this case
Note: The ERR flag could also be set after the SBC has entered SBC Fail-Safe Mode because the SPI
communication is stopped immediately.
Data Sheet
94
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.3
SPI Programming
For the TLE9260QX, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read
Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual
configuration and status information, 8 data bits (BIT15...8) are used.
Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be
cleared by the microcontroller, e.g. if the TSD2 was set due to over temperature. The configuration bits will be
partially automatically cleared by the SBC - please refer to the individual registers description for detailed
information. During SBC Restart Mode the SPI communication is ignored by the SBC, i.e. it is not interpreted.
There are two types of SPI registers:
•
Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc
•
Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake events, warnings,
failures, etc.
For the status registers, the requested information is given in the same SPI command in DO.
For the control registers, also the status of the respective byte is shown in the same SPI command. However, if
the setting is changed this is only shown with the next SPI command (it is only valid after CSN high) of the same
register.
The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI
response on SDO in the so called Status Information Field register (see also Figure 43). The purpose of this
register is to quickly signal the information to the microcontroller if there was a change in one of the SPI status
registers. In this way, the microcontroller does not need to read constantly all the SPI status registers but only
those registers, which were changed.
Each bit in the Status Information Field represents a SPI status register (see Table 22). As soon as one bit is set
in one of the status registers, then the respective bit in the Status Information Field register will be set. The register
WK_LVL_STAT is not included in the status Information field. This is listed in Table 22.
For Example if bit 0 in the Status Information Field is set to 1, one or more bits of the register 100 0001
(SUP_STAT_1) is set to 1. Then this register needs to be read in a second SPI command. The bit in the Status
Information Field will be set to 0 when all bits in the register 100 0001 are set back to 0.
Table 22
Status Information Field
Bit in Status
Information Field
Corresponding
Address Bit
Status Register Description
0
100 0001
SUP_STAT_1: Supply Status -VSHS fail, VCCx fail, POR
1
100 0010
THERM_STAT: Thermal Protection Status
2
100 0011
DEV_STAT: Device Status - Mode before Wake, WD Fail,
SPI Fail, Failure
3
100 0100
BUS_STAT: Bus Failure Status: CAN;
4
100 0110
WK_STAT_1, WK_STAT_2: Wake Source Status;
Status bit is set as combinational OR of both registers
5
100 0000
SUP_STAT_2:VCC1_WARN/OV
6
101 0100
HS_OC_OT_STAT: High-Side Over Load Status
7
101 0101
HS_OL_STAT: High-Side Open Load Status
Data Sheet
95
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
LSB
DI
0
MSB
1
2
3
4
5
6
Address Bits
7
8
9
10 11 12 13 14 15
Data Bits
R/W
x
x
x
x
x
x
x
x
Register content of
selected address
DO
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Status Information Field
Data Bits
x
x
x
x
x
x
x
x
time
LSB is sent first in SPI message
Figure 43
Data Sheet
SPI Operation Mode
96
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.4
SPI Bit Mapping
The following figures show the mapping of the registers and the SPI bits of the respective registers.
The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only read
(setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’). The new setting of the bit after write can be seen with a new
read / write command.
The registers ‘100 0000’ to ‘111 1110’ are Status Registers and can be read or read with clearing the bit (if
possible) depending on bit 7. To clear a Data Byte of one of the Status Registers bit 7 must be set to 1. The
registers WK_LVL_STAT, and FAM_PROD_STAT are an exception as they show the actual voltage level at the
respective WK pin (LOW/HIGH), or a fixed family/ product ID respectively and can thus not be cleared. It is
recommended for proper diagnosis to clear respective status bits for wake events or failure. However, in general
it is possible to enable drivers without clearing the respective failure flags.
When changing to a different SBC Mode, certain configurations bits will be cleared automatically or modified:
•
The SBC Mode bits are updated to the actual status, e.g. when returning to Normal Mode
•
When changing to a low-power mode (Stop/Sleep), the diagnosis bits of the switches and transceivers are not
cleared. FOx will stay activated if it was triggered before.
•
When changing to SBC Stop Mode, the CAN control bits will not be modified.
•
When changing to SBC Sleep Mode, the CAN control bits will be modified if they were not OFF or wake
capable before.
•
HSx, VCC2 will stay on when going to Sleep-/Stop Mode (configuration can only be done in Normal Mode).
Diagnosis is active (OC, OL, OT). In case of a failure the switch is turned off and no wake-up is issued
•
The configuration bits for HSx and VCC2 in stand-alone configuration are cleared in SBC Restart Mode. FOx
will stay activated if it was triggered before. Depending on the respective configuration, CAN transceivers will
be either OFF, woken or still wake capable.
Note: The detailed behavior of the respective SPI bits and control functions is described in Chapter 14.5,
Chapter 14.6.and in the respective module chapter. The bit type be marked as ‘rwh’ in case the SBC will
modify respective control bits.
Data Sheet
97
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
MSB
LSB
9
Status Registers
Control Registers
8 Data Bits [bits 8... 15]
Figure 44
Data Sheet
for Configuration & Status Information
M_S_CTRL
HW_CTRL
WD_CTRL
BUS_CTRL_1
BUS_CTRL_2
WK_CTRL_1
WK_CTRL_2
WK_PUPD_CTRL
WK_FLT_CTRL
TIMER1_CTRL
TIMER2_CTRL
SW_SD_CTRL
HS_CTRL_1
HS_CTRL_2
GPIO_CTRL
PWM1_CTRL
PWM2_CTRL
PWM_FREQ_CTRL
SYS_STAT_CTRL
SUP_STAT_2
SUP_STAT_1
THERM_STAT
DEV_STAT
BUS_STAT_1
WK_STAT_1
WK_STAT_2
WK_LVL_STAT
HS_OC_OT_STAT
HS_OL_STAT
FAM_PROD_STAT
8
7
Reg.
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rc
rc
rc
rc
rc
rc
rc
r
rc
rc
r
6
5
4
3
2
1
0
7 Address Bits [bits 0...6]
for Register Selection
0 0 0 0 0 0 1
0 0 0 0 0 1 0
0 0 0 0 0 1 1
0 0 0 0 1 0 0
0 0 0 0 1 0 1
0 0 0 0 1 1 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 0 0 1 0 0 1
0 0 0 1 1 0 0
0 0 0 1 1 0 1
0 0 1 0 0 0 0
0 0 1 0 1 0 0
0 0 1 0 1 0 1
0 0 1 0 1 1 1
0 0 1 1 0 0 0
0 0 1 1 0 0 1
0 0 1 1 1 0 0
0 0 1 1 1 1 0
1 0 0 0 0 0 0
1 0 0 0 0 0 1
1 0 0 0 0 1 0
1 0 0 0 0 1 1
1 0 0 0 1 0 0
1 0 0 0 1 1 0
1 0 0 0 1 1 1
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 0 1 0 1 0 1
1 1 1 1 1 1 0
5
0
1
2
3
4
4
6
7
Status Information
Field Bit
15 14 13 12 11 10
SPI Register Mapping
98
Rev. 1.1, 2014-09-26
Figure 45
Data Sheet
99
D6
14
D5
13
reserved
POR
reserved
DEV_STAT_1
reserved
reserved
reserved
SBC_DEV_LVL
reserved
reserved
FAM_3
FAM_PROD_STAT
FAM_2
VS_UV
VSHS_UV
reserved
DEV_STAT_0
reserved
reserved
reserved
CFGP
reserved
reserved
reserved
VCC2_OT
reserved
reserved
reserved
TIMER_WU
GPIO1_WU
GPIO1_LVL
reserved
reserved
VCC2_UV
reserved
WD_FAIL_1
reserved
reserved
reserved
reserved
HS4_OC_OT
HS4_OL
STATUS REGISTERS
VCC2_ON_0
reserved
reserved
reserved
reserved
reserved
reserved
WK2_PUPD_1
WK2_FLT_1
reserved
reserved
reserved
reserved
reserved
GPIO2_0
PWM1_DC_3
PWM2_DC_3
reserved
SYS_STAT_3
reserved
VCC1_SC
TSD2
WD_FAIL_0
CAN_FAIL_1
WK3_WU
reserved
WK3_LVL
HS3_OC_OT
HS3_OL
VCC1_OV_RST
reserved
WD_TIMER_2
reserved
reserved
WD_STM_EN_1
WK3_EN
WK2_PUPD_0
WK2_FLT_0
TIMER1_PER_2
TIMER2_PER_2
reserved
HS1_2
HS3_2
GPIO1_2
PWM1_DC_2
PWM2_DC_2
PWM2_FREQ_0
SYS_STAT_2
D2
10
F A M I LY A N D P R O D U C T R E G I S T E R S
FAM_1
FAM_0
PROD_3
PROD_2
reserved
VSHS_OV
reserved
reserved
reserved
CAN_WU
GPIO2_WU
GPIO2_LVL
reserved
D3
11
CONTROL REGISTERS
12
Data Bit 15…8
D4
MODE_1
MODE_0
reserved
VCC2_ON_1
reserved
SOFT_RESET_RO
FO_ON
reserved
CHECKSUM
WD_STM_EN_0
WD_WIN
WD_EN_WK_BUS
reserved
reserved
reserved
reserved
reserved
reserved
I_PEAK_TH
reserved
TIMER2_WK_EN TIMER1_WK_EN
reserved
reserved
INT_GLOBAL
reserved
WK_MEAS
reserved
reserved
reserved
WK3_PUPD_1
WK3_PUPD_0
reserved
reserved
WK3_FLT_1
WK3_FLT_0
reserved
TIMER1_ON_2
TIMER1_ON_1
TIMER1_ON_0
reserved
TIMER2_ON_2
TIMER2_ON_1
TIMER2_ON_0
reserved
HS_OV_SD_EN
HS_UV_SD_EN HS_OV_UV_REC
reserved
HS2_2
HS2_1
HS2_0
reserved
HS4_2
HS4_1
HS4_0
FO_DC_1
FO_DC_0
GPIO2_2
GPIO2_1
PWM1_DC_7
PWM1_DC_6
PWM1_DC_5
PWM1_DC_4
PWM2_DC_7
PWM2_DC_6
PWM2_DC_5
PWM2_DC_4
reserved
reserved
reserved
reserved
SYS_STAT_7
SYS_STAT_6
SYS_STAT_5
SYS_STAT_4
D7
15
SUP_STAT_2
SUP_STAT_1
THERM_STAT
DEV_STAT
BUS_STAT_1
WK_STAT_1
WK_STAT_2
WK_LVL_STAT
HS_OC_OT_STAT
HS_OL_STAT
M_S_CTRL
HW_CTRL
WD_CTRL
BUS_CTRL_1
BUS_CTRL_2
WK_CTRL_1
WK_CTRL_2
WK_PUPD_CTRL
WK_FLT_CTRL
TIMER1_CTRL
TIMER2_CTRL
SW_SD_CTRL
HS_CTRL_1
HS_CTRL_2
GPIO_CTRL
PWM1_CTRL
PWM2_CTRL
PWM_FREQ_CTRL
SYS_STAT_CTRL
Register Short Name
PROD_1
VCC1_OV
VCC1_UV_FS
TSD1
SPI_FAIL
CAN_FAIL_0
WK2_WU
reserved
WK2_LVL
HS2_OC_OT
HS2_OL
VCC1_RT_1
reserved
WD_TIMER_1
CAN_1
reserved
reserved
WK2_EN
WK1_PUPD_1
WK1_FLT_1
TIMER1_PER_1
TIMER2_PER_1
reserved
HS1_1
HS3_1
GPIO1_1
PWM1_DC_1
PWM2_DC_1
reserved
SYS_STAT_1
D1
9
PROD_0
VCC1_WARN
VCC1_UV
TPW
FAILURE
VCAN_UV
WK1_WU
reserved
WK1_LVL
HS1_OC_OT
HS1_OL
VCC1_RT_0
CFG
WD_TIMER_0
CAN_0
reserved
reserved
WK1_EN
WK1_PUPD_0
WK1_FLT_0
TIMER1_PER_0
TIMER2_PER_0
reserved
HS1_0
HS3_0
GPIO1_0
PWM1_DC_0
PWM2_DC_0
PWM1_FREQ_0
SYS_STAT_0
D0
8
read
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read/clear
read
read/clear
read/clear
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
7
Access
Mode
1111110
1000000
1000001
1000010
1000011
1000100
1000110
1000111
1001000
1010100
1010101
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001100
0001101
0010000
0010100
0010101
0010111
0011000
0011001
0011100
0011110
6...0
Address
A6…A0
TLE9260QX
Serial Peripheral Interface
TLE9260QX SPI Bit Mapping
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.5
SPI Control Registers
READ/WRITE Operation (see also Chapter 14.3):
•
The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset.
•
The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.
•
One 16-bit SPI command consist of two bytes:
- the 7-bit address and one additional bit for the register access mode and
- following the data byte
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the
SPI bits 8...15 (see also figure before).
•
There are three different bit types:
- ‘r’ = READ: read only bits (or reserved bits)
- ‘rw’ = READ/WRITE: readable and writable bits
- ‘rwh’ = READ/WRITE/Hardware: readable/writable bits, which can also be modified by the SBC hardware
•
Reserved bits are marked as “Reserved” and always read as “0”. The respective bits shall also be programmed
as “0”.
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only).
•
Writing to a register is done byte wise by setting the SPI bit 7 to “1”.
•
SPI control bits are in general not cleared or changed automatically. This must be done by the microcontroller
via SPI programming. Exceptions to this behavior are stated at the respective register description and the
respective bit type is marked with a ‘h’ meaning that the SBC is able to change the register content.
The registers are addressed wordwise.
Data Sheet
100
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.5.1
General Control Registers
M_S_CTRL
Mode- and Supply Control (Address 000 0001B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 00xxB
7
6
5
4
3
MODE_1
MODE_0
Reserved
VCC2_ON_1
VCC2_ON_0
rwh
rwh
rwh
rwh
rwh
2
1
VCC1_OV_RS
VCC1_RT_1
T
rwh
r
rw
0
VCC1_RT_0
rw
Field
Bits
Type
Description
MODE
7:6
rwh
SBC Mode Control
00B , SBC Normal Mode
01B , SBC Sleep Mode
10B , SBC Stop Mode
11B , SBC Reset: Soft Reset is executed (configuration of RO
triggering in bit SOFT_ RESET_RO)
Reserved
5
r
Reserved, always reads as 0
VCC2_ON
4:3
rwh
VCC2 Mode Control
00B , VCC2 off
01B , VCC2 on in Normal Mode
10B , VCC2 on in Normal and Stop Mode
11B , VCC2 always on (except in SBC Fail-Safe Mode)
VCC1_OV_R 2
ST
rwh
VCC1 Over Voltage leading to Restart / Fail-Safe Mode enable
0B
, VCC1_ OV is set in case of VCC1_OV; no SBC Restart or FailSafe is entered for VCC1_OV
1B
, VCC1_ OV is set in case of VCC1_OV; depending on the
device configuration SBC Restart or SBC Fail-Safe Mode is
entered (see Chapter 5.1.1);
VCC1_RT
rw
VCC1 Reset Threshold Control
00B , Vrt1 selected (highest threshold)
01B , Vrt2 selected
10B , Vrt3 selected
11B , Vrt4 selected
1:0
Notes
1. It is not possible to change from Stop to Sleep Mode via SPI Command. See also the State Machine Chapter
2. After entering SBC Restart Mode, the MODE bits will be automatically set to SBC Normal Mode. The
VCC2_ON bits will be automatically set to OFF after entering SBC Restart Mode and after OT.
3. The SPI output will always show the previously written state with a Write Command (what has been
programmed before)
Data Sheet
101
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
HW_CTRL
Mode- and Supply Control (Address 000 0010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0x00 000xB
7
6
5
4
3
2
1
0
Reserved
SOFT_RESET
_RO
FO_ON
Reserved
Reserved
Reserved
Reserved
CFG
r
rw
rwh
r
r
r
r
rw
r
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
SOFT_
RESET_RO
6
rw
Soft Reset Configuration
0B
, RO will be triggered (pulled low) during a Soft Reset
1B
, No RO triggering during a Soft Reset
FO_ON
5
rwh
Failure Output Activation (FO1..3)
0B
, FOx not activated by software, FO can be activated by defined
failures (see Chapter 12)
1B
, FOx activated by software (via SPI)
Reserved
4
r
Reserved, always reads as 0
Reserved
3
r
Reserved, always reads as 0
Reserved
2
r
Reserved, always reads as 0
Reserved
1
r
Reserved, always reads as 0
CFG
0
rw
Configuration Select (see also Table 5)
0B
, Depending on hardware configuration, SBC Restart or FailSafe Mode is reached after the 2. watchdog trigger failure
(=default) - Config 3/4
1B
, Depending on hardware configuration, SBC Restart or FailSafe Mode is reached after the 1. watchdog trigger failure Config 1/2
Notes
1. Clearing the FO_ON bit will not disable the FOx outputs for the case a failure occurred which triggered the FOx
outputs. In this case the FOx outputs have to be disabled by clearing the FAILURE bit.
If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered
and the FOx outputs will be disabled. See also Chapter 12 for FOx activation and deactivation.
Data Sheet
102
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WD_CTRL
Watchdog Control (Address 000 0011B)
POR / Soft Reset Value: 0001 0100B;
Restart Value: x0xx 0100B
7
6
5
4
3
CHECKSUM
WD_STM_
EN_0
WD_WIN
WD_EN_
WK_BUS
Reserved
rw
rwh
rw
rw
r
Field
Bits
CHECKSUM 7
2
1
0
WD_TIMER_2 WD_TIMER_1 WD_TIMER_0
rwh
r
rwh
rwh
Type
Description
rw
Watchdog Setting Check Sum Bit
The sum of bits 7:0 needs to have even parity (see Chapter 13.2.3)
0B
, Counts as 0 for checksum calculation
1B
, Counts as 1 for checksum calculation
WD_STM_
EN_0
6
rwh
Watchdog Deactivation during Stop Mode, bit 0 (Chapter 13.2.4)
0B
, Watchdog is active in Stop Mode
1B
, Watchdog is deactivated in Stop Mode
WD_WIN
5
rw
Watchdog Type Selection
0B
, Watchdog works as a Time-Out watchdog
1B
, Watchdog works as a Window watchdog
WD_EN_
WK_BUS
4
rwh
Watchdog Enable after Bus (CAN) Wake in SBC Stop Mode
0B
, Watchdog will not start after a CAN wake
1B
, Watchdog starts with a long open window after CAN Wake
Reserved
3
r
Reserved, always reads as 0
WD_TIMER
2:0
rwh
Watchdog Timer Period
000B , 10ms
001B , 20ms
010B , 50ms
011B , 100ms
100B , 200ms
101B , 500ms
110B , 1000ms
111B , reserved
Notes
1. See also Chapter 13.2.4 for more information on disabling the watchdog in SBC Stop Mode.
2. See Chapter 13.2.5 for more information on the effect of the bit WD_EN_WK_BUS.
3. See Chapter 13.2.3 for calculation of checksum.
Data Sheet
103
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
BUS_CTRL_1
Bus Control (Address 000 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 00yyB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CAN_1
CAN_0
r
r
r
r
r
r
rwh
rwh
Field
Bits
Type
Description
Reserved
7:3
r
Reserved, always reads as 0
Reserved
2
r
Reserved, always reads as 0
CAN
1:0
rwh
HS-CAN Module Modes
00B , CAN OFF
01B , CAN is wake capable
10B , CAN Receive Only Mode
11B , CAN Normal Mode
r
Notes
1. The reset values for the CAN transceivers are marked with ‘y’ because they will vary depending on the cause
of change - see below.
2. see Figure 19 for detailed state changes of CAN Transceiver for different SBC modes.
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1, and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0
1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.
Data Sheet
104
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
BUS_CTRL_2
Bus Control (Address 000 0101B)
POR / Soft Reset Value: 0000 0000B; Restart Value: 00x0 0000B
7
6
5
4
3
2
1
0
Reserved
Reserved
I_PEAK_TH
Reserved
Reserved
Reserved
Reserved
Reserved
r
r
rw
r
r
r
r
r
r
Field
Bits
Type
Description
Reserved
7:6
r
Reserved, always reads as 0
I_PEAK_TH
5
rw
VCC1 Active Peak Threshold Selection
0B
, low VCC1 active peak threshold selected (ICC1,peak_1)
1B
, higher VCC1 active peak threshold selected (ICC1,peak_2)
Reserved
4:0
r
Reserved, always reads as 0
Notes
1. The bit I_PEAK_TH can be modified in SBC Init and Normal Mode. In SBC Stop Mode this bit is Read only but
SPI_FAIL will not be set when trying to modify the bit in SBC STOP Mode and no INT is triggered in case INT_
GLOBAL is set.
2. see Figure 19 for detailed state changes of CAN Transceiver for different SBC modes
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1, BUS_CTRL_2 and WK_CTRL_2 are reset to following values (=wake
sources) ‘xxx0 1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.
Data Sheet
105
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_CTRL_1
Internal Wake Input Control (Address 000 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xx00 0000B
7
6
TIMER2_WK_ TIMER1_WK_
EN
EN
rw
Field
5
4
3
2
1
0
Reserved
Reserved
Reserved
WD_STM_
EN_1
Reserved
Reserved
r
r
r
rwh
r
r
rw
Type
Description
TIMER2_WK 7
_EN
rw
Timer2 Wake Source Control (for cyclic wake)
0B
, Timer2 wake disabled
1B
, Timer2 is enabled as a wake source
TIMER1_WK 6
_EN
rw
Timer1 Wake Source Control (for cyclic wake)
0B
, Timer1 wake disabled
1B
, Timer1 is enabled as a wake source
Reserved
5:3
r
Reserved, always reads as 0
WD_STM_
EN_1
2
rwh
Watchdog Deactivation during Stop Mode, bit 1 (Chapter 13.2.4)
0B
, Watchdog is active in Stop Mode
1B
, Watchdog is deactivated in Stop Mode
Reserved
1:0
r
Reserved, always reads as 0
Data Sheet
Bits
r
106
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_CTRL_2
External Wake Source Control (Address 000 0111B)
POR / Soft Reset Value: 0000 0111B;
Restart Value: x0x0 0xxxB
7
6
5
4
3
2
1
0
INT_GLOBAL
Reserved
WK_MEAS
Reserved
Reserved
WK3_EN
WK2_EN
WK1_EN
r
rw
r
r
rw
rw
rw
w
rw
r
Field
Bits
Type
Description
INT_
GLOBAL
7
rw
Global Interrupt Configuration (see also Chapter 11.1)
0B
, Only wake sources trigger INT (default)
1B
, All status information register bits will trigger INT (including all
wake sources)
Reserved
6
r
Reserved, always reads as 0
WK_MEAS
5
rw
WK / Measurement selection (see also Chapter 10.2.2)
0B
, WK functionality enabled for WK1 and WK2
1B
, Measurement functionality enabled; WK1 & WK2 are disabled
as wake sources, i.e. bits WK1/2_EN bits are ignored
Reserved
4:3
r
Reserved, always reads as 0
WK3_EN
2
rw
WK3 Wake Source Control
0B
, WK3 wake disabled
1B
, WK3 is enabled as a wake source
WK2_EN
1
rw
WK2 Wake Source Control
0B
, WK2 wake disabled
1B
, WK2 is enabled as a wake source
WK1_EN
0
rw
WK1 Wake Source Control
0B
, WK1 wake disabled
1B
, WK1 is enabled as a wake source
Notes
1. WK_MEAS is by default configured for standard WK functionality (WK1 and WK2). The bits WK1_EN and
WK2_EN are ignored in case WK_MEAS is activated. If the bit is set to ‘1’ then the measurement function is
enabled during Normal Mode & the bits WK1_EN and WK2_EN are ignored. The bits WK1/”_LVL bits need to
be ignored as well.
2. The wake sources CAN are selected in the register BUS_CTRL_1 by setting the respective bits to ‘wake
capable’
3. Failure Handling Mechanism: When the device enters Fail-Safe Mode due to a failure (TSD2, WD-Failure,...),
then the wake registers BUS_CTRL_1 and WK_CTRL_2 are reset to following values (=wake sources) ‘xxx0
1001’, ‘0000 0001’ and ‘x0xx 0111’ in order to ensure that the device can be woken again.
Data Sheet
107
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_PUPD_CTRL
Wake Input Level Control (Address 000 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx xxxxB
7
6
Reserved
Reserved
r
r
5
4
3
2
1
WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0
rw
rw
rw
rw
r
rw
Field
Bits
Type
Description
Reserved
7:6
r
Reserved, always reads as 0
WK3_PUPD
5:4
rw
WK3 Pull-Up / Pull-Down Configuration
00B , No pull-up / pull-down selected
01B , Pull-down resistor selected
10B , Pull-up resistor selected
11B , Automatic switching to pull-up or pull-down
WK2_PUPD
3:2
rw
WK2 Pull-Up / Pull-Down Configuration
00B , No pull-up / pull-down selected
01B , Pull-down resistor selected
10B , Pull-up resistor selected
11B , Automatic switching to pull-up or pull-down
WK1_PUPD
1:0
rw
WK1 Pull-Up / Pull-Down Configuration
00B , No pull-up / pull-down selected
01B , Pull-down resistor selected
10B , Pull-up resistor selected
11B , Automatic switching to pull-up or pull-down
Data Sheet
0
108
rw
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_FLT_CTRL
Wake Input Filter Time Control (Address 000 1001B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx xxxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
WK3_FLT_1
WK3_FLT_0
WK2_FLT_1
WK2_FLT_0
WK1_FLT_1
WK1_FLT_0
r
r
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
Reserved
7:6
r
Reserved, always reads as 0
WK3_FLT
5:4
rw
WK3 Filter Time Configuration
00B , Configuration A: Filter with 16µs filter time (static sensing)
01B , Configuration B: Filter with 64µs filter time (static sensing)
10B , Configuration C: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer1
11B , Configuration D: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer2
WK2_FLT
3:2
rw
WK2 Filter Time Configuration
00B , Configuration A: Filter with 16µs filter time (static sensing)
01B , Configuration B: Filter with 64µs filter time (static sensing)
10B , Configuration C: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer1
11B , Configuration D: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer2
WK1_FLT
1:0
rw
WK1 Filter Time Configuration
00B , Configuration A: Filter with 16µs filter time (static sensing)
01B , Configuration B: Filter with 64µs filter time (static sensing)
10B , Configuration C: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer1
11B , Configuration D: Filtering at the end of the on-time;
a filter time of 16µs (cyclic sensing) is selected, Timer2
Note: When selecting a filter time configuration, the user must make sure to also assign the respective timer to at
least one HS switch during cyclic sense operation
Data Sheet
109
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
TIMER1_CTRL
Timer1 Control and Selection (Address 000 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
TIMER1_
ON_2
TIMER1_
ON_1
TIMER1_
ON_0
Reserved
TIMER1_
PER_2
TIMER1_
PER_1
TIMER1_
PER_0
r
rwh
rwh
rwh
r
rwh
rwh
rwh
r
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
TIMER1_
ON
6:4
rwh
Timer1 On-Time Configuration
000B , OFF / Low (timer not running, HSx output is low)
001B , 0.1ms on-time
010B , 0.3ms on-time
011B , 1.0ms on-time
100B , 10ms on-time
101B , 20ms on-time
110B , OFF / HIGH (timer not running, HSx output is high)
111B , reserved
Reserved
3
r
Reserved, always reads as 0
TIMER1_
PER
2:0
rwh
Timer1 Period Configuration
000B , 10ms
001B , 20ms
010B , 50ms
011B , 100ms
100B , 200ms
101B , 1s
110B , 2s
111B , reserved
Notes
1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.
2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer
settings (period and on-time) are cleared to avoid incorrect switch detection.
3. in case the timer are set as wake sources and cyclic sense is running, then both cyclic sense and cyclic wake
will be active at the same time.
Data Sheet
110
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
TIMER2_CTRL
Timer2 Control and selection (Address 000 1101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
TIMER2_
ON_2
TIMER2_
ON_1
TIMER2_
ON_0
Reserved
TIMER2_
PER_2
TIMER2_
PER_1
TIMER2_
PER_0
r
rwh
rwh
rwh
r
rwh
rwh
rwh
r
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
TIMER2_
ON
6:4
rwh
Timer2 On-Time Configuration
000B , OFF / Low (timer not running, HSx output is low)
001B , 0.1ms on-time
010B , 0.3ms on-time
011B , 1.0ms on-time
100B , 10ms on-time
101B , 20ms on-time
110B , OFF / HIGH (timer not running, HSx output is high)
111B , reserved
Reserved
3
r
Reserved, always reads as 0
TIMER2_
PER
2:0
rwh
Timer2 Period Configuration
000B , 10ms
001B , 20ms
010B , 50ms
011B , 100ms
100B , 200ms
101B , 1s
110B , 2s
111B , reserved
Notes
1. A timer must be first assigned and is then automatically activated as soon as the on-time is configured.
2. If cyclic sense is selected and the HS switches are cleared during SBC Restart Mode, then also the timer
settings (period and on-time) are cleared to avoid incorrect switch detection.
Data Sheet
111
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
SW_SD_CTRL
Switch Shutdown Control (Address 001 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0xxx 0000B
7
Reserved
6
5
4
HS_OV_SD_E HS_UV_SD_E HS_OV_UV_R
N
N
EC
r
rw
rw
rw
3
2
1
0
Reserved
Reserved
Reserved
Reserved
r
r
r
r
r
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
HS_OV_SD_ 6
EN
rw
Shutdown Disabling of HS1...4 in case of VSHS OV
0B
, shutdown enabled in case of VSHS OV
1B
, shutdown disabled in case of VSHS OV
HS_UV_SD_ 5
EN
rw
Shutdown Disabling of HS1...4 in case of VSHS UV
0B
, shutdown enabled in case of VSHS UV
1B
, shutdown disabled in case of VSHS UV
HS_OV_UV_ 4
REC
rw
Switch Recovery after Removal of VSHS OV/UV for HS1...4
0B
, Switch recovery is disabled
1B
, Previous state before VSHS OV/UV is enabled after OV/UV
condition is removed
Reserved
r
Reserved, always reads as 0
Data Sheet
3:0
112
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
HS_CTRL1
High-Side Switch Control 1 (Address 001 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
HS2_2
HS2_1
HS2_0
Reserved
HS1_2
HS1_1
HS1_0
rw
rwh
rwh
rwh
r
rwh
rwh
rwh
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
HS2
6:4
rwh
HS2 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
Reserved
3
r
Reserved, always reads as 0
HS1
2:0
rwh
HS1 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
r
Note: The bits for the switches are also reset in case of overcurrent and overtemperature.
Data Sheet
113
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
HS_CTRL2
High-Side Switch Control 2 (Address 001 0101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0000B
7
6
5
4
3
2
1
0
Reserved
HS4_2
HS4_1
HS4_0
Reserved
HS3_2
HS3_1
HS3_0
r
rwh
rwh
rwh
r
rwh
rwh
rwh
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
HS4
6:4
rwh
HS4 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
Reserved
3
r
Reserved, always reads as 0
HS3
2:0
rwh
HS3 Configuration
000B , Off
001B , On
010B , Controlled by Timer1
011B , Controlled by Timer2
100B , Controlled by PWM1
101B , Controlled by PWM2
110B , Reserved
111B , Reserved
r
Note: The bits for the switches are also reset in case of overcurrent and overtemperature.
Data Sheet
114
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
GPIO_CTRL
GPIO Configuration Control (Address 001 0111B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
FO_DC_1
FO_DC_0
GPIO2_2
GPIO2_1
GPIO2_0
GPIO1_2
GPIO1_1
GPIO1_0
rw
rw
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
FO_DC
7:6
rw
Duty Cycle Configuration of FO3 (if selected)
00B , 20%
01B , 10%
10B , 5%
11B , 2.5%
GPIO2
5:3
rw
GPIO2 Configuration
000B , FO3 selected
001B , FO3 selected
010B , FO3 selected
011B , FO3 selected
100B , OFF
101B , Wake input enabled (16µs static filter)
110B , Low-Side Switch ON
111B , High-Side Switch ON
GPIO1
2:0
rw
GPIO1 Configuration
000B , FO2 selected
001B , FO2 selected
010B , FO2 selected
011B , FO2 selected
100B , OFF
101B , Wake input enabled (16µs static filter)
110B , Low-Side Switch ON
111B , High-Side Switch ON
Note: When selecting a filter time configuration, the user must make sure to also assign the respective timer to at
least one HS switch during cyclic sense operation
Data Sheet
115
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
PWM1_CTRL
PWM1 Configuration Control (Address 001 1000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
PWM1_DC
7:0
rw
PWM1 Duty Cycle (bit0=LSB; bit7=MSB)
0000 0000B, 100% OFF
xxxx xxxx B, ON with DC fraction of 255
1111 1111B, 100% ON
rw
rw
Note: The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.
the PWM setting ‘000 0001’ could not be realized.
PWM2_CTRL
PWM2 Configuration Control (Address 001 1001B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xxxx xxxxB
7
6
5
4
3
2
1
0
PWM2_DC_7 PWM2_DC_6 PWM2_DC_5 PWM2_DC_4 PWM2_DC_3 PWM2_DC_2 PWM2_DC_1 PWM2_DC_0
rw
rw
rw
rw
rw
rw
r
Field
Bits
Type
Description
PWM2_DC
7:0
rw
PWM2 Duty Cycle (bit0=LSB; bit7=MSB)
0000 0000B, 100% OFF
xxxx xxxxB, ON with DC fraction of 255
1111 1111B, 100% ON
rw
rw
Note: The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.
the PWM setting ‘000 0001’ could not be realized.
Data Sheet
116
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
PWM_FREQ_CTRL
PWM Frequency Configuration Control (Address 001 1100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0x0xB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
PWM2_FREQ
Reserved
PWM1_FREQ
r
r
r
r
r
rw
r
rw
Field
Bits
Type
Description
Reserved
7:3
r
Reserved, always reads as 0
PWM2_
FREQ
2
rw
PWM2 Frequency Selection
0B
, 200Hz configuration
1B
, 400Hz configuration
Reserved
1
r
Reserved, always reads as 0
PWM1_
FREQ
0
rw
PWM1 Frequency Selection
0B
, 200Hz configuration
1B
, 400Hz configuration
r
Note: The min. On-time during PWM is limited by the actual Ton and Toff time of the respective HS switch, e.g.
the PWM setting ‘000 0001’ could not be realized.
SYS_STATUS_CTRL
System Status Control (Address 001 1110B)
POR Value: 0000 0000B;
Restart Value/Soft Reset Value: xxxx xxxxB
7
6
5
4
3
2
1
0
SYS_STAT_7 SYS_STAT_6 SYS_STAT_5 SYS_STAT_4 SYS_STAT_3 SYS_STAT_2 SYS_STAT_1 SYS_STAT_0
rw
rw
rw
rw
rw
rw
r
rw
Field
Bits
Type
Description
SYS_STAT
7:0
rw
System Status Control Byte (bit0=LSB; bit7=MSB)
Dedicated byte for system configuration, access only by
microcontroller. Cleared after power up and Soft Reset
rw
Notes
1. The SYS_STATUS_CTRL register is an exception for the default values, i.e. it will keep its configured value
also after a Soft Reset.
2. This byte is intended for storing system configurations of the ECU by the microcontroller and is only accessible
in SBC Normal Mode. The byte is not accessible by the SBC and is also not cleared after Fail-Safe or SBC
Restart Mode. It allows the microcontroller to quickly store system configuration without loosing the data.
Data Sheet
117
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.6
SPI Status Information Registers
READ/CLEAR Operation (see also Chapter 14.3):
•
One 16-bit SPI command consist of two bytes:
- the 7-bit address and one additional bit for the register access mode and
- following the data byte
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the
SPI bits 8...15 (see also figure).
•
There are two different bit types:
- ‘r’ = READ: read only bits (or reserved bits)
- ‘rc’ = READ/CLEAR: readable and clearable bits
•
Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)
•
Clearing a register is done byte wise by setting the SPI bit 7 to “1”
•
SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL bits).
This must be done by the microcontroller via SPI command
The registers are addressed wordwise.
Data Sheet
118
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.6.1
General Status Registers
SUP_STAT_2
Supply Voltage Fail Status (Address 100 0000B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0x00 00xxB
7
6
5
4
3
2
1
0
Reserved
VS_UV
Reserved
Reserved
Reserved
Reserved
VCC1_OV
VCC1_WARN
r
rc
r
r
r
r
rc
rc
r
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
VS_UV
6
rc
VS Under-Voltage Detection (VS,UV)
0B
, No VS under voltage detected
1B
, VS under voltage detected
Reserved
5
r
Reserved, always reads as 0
Reserved
4:2
r
Reserved, always reads as 0
VCC1_
OV
1
rc
VCC1 Over Voltage Detection (VCC1,OV,r)
0B
, No VCC1 over voltage warning
1B
, VCC1 over voltage detected
VCC1_
WARN
0
rc
VCC1 Undervoltage Prewarning (VPW,f)
0B
, No VCC1 undervoltage prewarning
1B
, VCC1 undervoltage prewarning detected
Notes
1. The VCC1 undervoltage prewarning threshold VPW,f / VPW,r is a fixed threshold and independent of the VCC1
undervoltage reset thresholds.
Data Sheet
119
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
SUP_STAT_1
Supply Voltage Fail Status (Address 100 0001B)
POR / Soft Reset Value: y000 0000B;
Restart Value: xxxx xx0xB
7
6
5
4
3
2
1
0
POR
VSHS_UV
VSHS_OV
VCC2_OT
VCC2_UV
VCC1_SC
VCC1_UV_FS
VCC1_UV
rc
rc
rc
rc
rc
rc
rc
rc
r
Field
Bits
Type
Description
POR
7
rc
Power-On Reset Detection
0B
, No POR
1B
, POR occurred
VSHS_UV
6
rc
VSHS Under-Voltage Detection (VSHS,UVD)
0B
, No VSHS-UV
1B
, VSHS-UV detected
VSHS_OV
5
rc
VSHS Over-Voltage Detection (VSHS,OVD)
0B
, No VSHS-OV
1B
, VSHS-OV detected
VCC2_OT
4
rc
VCC2 Over Temperature Detection
0B
, No over temperature
1B
, VCC2 over temperature detected
VCC2_UV
3
rc
VCC2 Under Voltage Detection (VCC2,UV,f)
0B
, No VCC2 Under voltage
1B
, VCC2 under voltage detected
VCC1_SC
2
rc
VCC1 Short to GND Detection (<Vrtx for t>4ms after switch on)
0B
, No short
1B
, VCC1 short to GND detected
VCC1_UV
_FS
1
rc
VCC1 UV-Detection (due to Vrtx reset)
0B
, No Fail-Safe Mode entry due to 4th consecutive VCC1_UV
1B
, Fail-Safe Mode entry due to 4th consecutive VCC1_UV
VCC1_UV
0
rc
VCC1 UV-Detection (due to Vrtx reset)
0B
, No VCC1_UV detection
1B
, VCC1 UV-Fail detected
Notes
1. The MSB of the POR/Soft Reset value is marked as ‘y’: the default value of the POR bit is set after Power-on
reset (POR value = 1000 0000). However it will be cleared after a SBC Soft Reset command (Soft Reset value
= 0000 0000).
2. During Sleep Mode, the bits VCC1_SC,VCC1_OV and VCC1_UV will not be set when VCC1 is off
3. The VCC1_UV bit is never updated in SBC Restart Mode, in SBC Init Mode it is only updated after RO was
released for the first time, it is always updated in SBC Normal and Stop Mode, and it is always updated in any
SBC modes in a VCC1_SC condition (after VCC1_UV = 1 for >4ms).
Data Sheet
120
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
THERM_STAT
Thermal Protection Status (Address 100 0010B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0xxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
TSD2
TSD1
TPW
r
r
r
r
r
rc
rc
rc
r
Field
Bits
Type
Description
Reserved
7:3
r
Reserved, always reads as 0
TSD2
2
rc
TSD2 Thermal Shut-Down Detection
0B
, No TSD2 event
1B
, TSD2 OT detected - leading to SBC Fail-Safe Mode
TSD1
1
rc
TSD1 Thermal Shut-Down Detection
0B
, No TSD1 fail
1B
, TSD1 OT detected
TPW
0
rc
Thermal Pre Warning
0B
, No Thermal Pre warning
1B
, Thermal Pre warning detected
Note: TSD1 and TSD2 are not reset automatically, even if the temperature pre warning or TSD1 OT condition is
not present anymore. Also TSD2 is not reset.
Data Sheet
121
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
DEV_STAT
Device Information Status (Address 100 0011B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: xx00 xxxxB
7
6
DEV_STAT_1 DEV_STAT_0
rc
5
4
3
2
1
0
Reserved
Reserved
WD_FAIL_1
WD_FAIL_0
SPI_FAIL
FAILURE
r
r
rh
rh
rc
rc
rc
r
Field
Bits
Type
Description
DEV_STAT
7:6
rc
Device Status before Restart Mode
00B , Cleared (Register must be actively cleared)
01B , Restart due to failure (WD fail, TSD2, VCC1_UV); also after a
wake from Fail-Safe Mode
10B , Sleep Mode
11B , Reserved
Reserved
5:4
r
Reserved, always reads as 0
WD_FAIL
3:2
rh
Number of WD-Failure Events (1/2 WD failures depending on
CFG)
00B , No WD Fail
01B , 1x WD Fail, FOx activation - Config 2 selected
10B , 2x WD Fail, FOx activation - Config 1 / 3 / 4 selected
11B , Reserved (never reached)
SPI_FAIL
1
rc
SPI Fail Information
0B
, No SPI fail
1B
, Invalid SPI command detected
FAILURE
0
rc
Activation of Fail Output FO
0B
, No Failure
1B
, Failure occurred
Notes
1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from
regular Sleep Mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe Mode: WD fail, TSD2 fail, VCC_UV
fail or VCC1_OV if bit VCC1_OV_RST is set) occurred. Failure is also an illegal command from SBC Stop to
SBC Sleep Mode or going to SBC Sleep Mode without activation of any wake source. Coming from SBC Sleep
Mode (‘10’) will also be shown if there was a trial to enter SBC Sleep Mode without having cleared all wake
flags before.
2. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically
by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in
SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 12.1.
3. The SPI_FAIL bit is cleared only by SPI command
4. In case of Config 2/4 the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger.
5. If CFG = ‘0’ then a 1st watchdog failure will not trigger the FO outputs or the FAILURE bit but only force the
SBC into SBC Restart Mode.
Data Sheet
122
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
BUS_STAT_1
Bus Communication Status (Address 100 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 0xxxB
7
6
5
4
3
Reserved
Reserved
Reserved
Reserved
Reserved
r
r
r
r
r
2
1
CAN_FAIL_1 CAN_FAIL_0
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
rc
r
rc
0
VCAN_UV
rc
Reserved
6:5
r
Reserved, always reads as 0
Reserved
4:3
r
Reserved, always reads as 0
CAN_FAIL
2:1
rc
CAN Failure Status
00B , No error
01B , CAN TSD
10B , CAN_TXD_DOM: TXD dominant time out for more than 4ms
11B , CAN_BUS_DOM: BUS dominant time out for more than 4ms
VCAN_UV
0
rc
Under Voltage CAN Bus Supply
0B
, Normal operation
1B
, CAN Supply under voltage detected. Transmitter disabled
Notes
1. The VCAN_UV comparator is enabled if the mode bit CAN_1 = ‘1’, i.e. in CAN Normal or CAN Receive Only
Mode.
Data Sheet
123
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_STAT_1
Wake-up Source and Information Status (Address 100 0110B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx 0xxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
CAN_WU
TIMER_WU
Reserved
WK3_WU
WK2_WU
WK1_WU
r
r
rc
rc
r
rc
rc
rc
Field
Bits
Type
Description
Reserved
7
r
Reserved, always reads as 0
Reserved
6
r
Reserved, always reads as 0
CAN_WU
5
rc
Wake up via CAN Bus
0B
, No Wake up
1B
, Wake up
TIMER_WU
4
rc
Wake up via TimerX
0B
, No Wake up
1B
, Wake up
Reserved
3
r
Reserved, always reads as 0
WK3_WU
2
rc
Wake up via WK3
0B
, No Wake up
1B
, Wake up
WK2_WU
1
rc
Wake up via WK2
0B
, No Wake up
1B
, Wake up
WK1_WU
0
rc
Wake up via WK1
0B
, No Wake up
1B
, Wake up
r
Note: The respective wake source bit will also be set when the device is woken from SBC Fail-Safe Mode
Data Sheet
124
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_STAT_2
Wake-up Source and Information Status (Address 100 0111B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 00xx 0000B
7
6
5
4
3
2
1
0
Reserved
Reserved
GPIO2_WU
GPIO1_WU
Reserved
Reserved
Reserved
Reserved
r
r
rc
rc
r
r
r
r
Field
Bits
Type
Description
Reserved
7:6
r
Reserved, always reads as 0
GPIO2_WU
5
rc
Wake up via GPIO2
0B
, No Wake up
1B
, Wake up
GPIO1_WU
4
rc
Wake up via GPIO1
0B
, No Wake up
1B
, Wake up
Reserved
3:0
r
Reserved, always reads as 0
Data Sheet
125
r
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
WK_LVL_STAT
WK Input Level (Address 100 1000B)
POR / Soft Reset Value: xx00 0xxxB;
Restart Value: xxxx 0xxxB
7
6
5
4
3
2
1
0
SBC_DEV
_LVL
CFGP
GPIO2_LVL
GPIO1_LVL
Reserved
WK3_LVL
WK2_LVL
WK1_LVL
r
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
SBC_DEV
_LVL
7
r
Status of SBC Operating Mode at FO3/TEST Pin
0B
, User Mode activated
1B
, SBC Software Development Mode activated
CFGP
6
r
Device Configuration Status
0B
, No external pull-up resistor connected on INT (Config 2/4)
1B
, External pull-up resistor connected on INT (Config 1/3)
GPIO2_LVL
5
r
Status of GPIO2 (if selected as GPIO)
0B
, Low Level (=0)
1B
, High Level (=1)
GPIO1_LVL
4
r
Status of GPIO1 (if selected as GPIO)
0B
, Low Level (=0)
1B
, High Level (=1)
Reserved
3
r
Reserved, always reads as 0
WK3_LVL
2
r
Status of WK3
0B
, Low Level (=0)
1B
, High Level (=1)
WK2_LVL
1
r
Status of WK2
0B
, Low Level (=0)
1B
, High Level (=1)
WK1_LVL
0
r
Status of WK1
0B
, Low Level (=0)
1B
, High Level (=1)
Note: GPIOx_LVL is updated in SBC Normal and Stop Mode if configured as wake input, low-side switch or highside switch.
In cyclic sense or wake mode, the registers contain the sampled level, i.e. the registers are updated after
every sampling. The GPIOs are not capable of cyclic sensing.
If selected as GPIO then the respective level is shown even if configured as low-side or high-side.
Data Sheet
126
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
HS_OC_OT_STAT
High-Side Switch Overload Status (Address 101 0100B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 xxxxB
7
6
5
4
Reserved
Reserved
Reserved
Reserved
r
r
r
r
3
2
1
0
HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT
rc
rc
r
rc
Field
Bits
Type
Description
Reserved
7:4
r
Reserved, always reads as 0
HS4_OC_OT 3
rc
Over-Current & Over-Temperature Detection HS4
0B
, No OC or OT
1B
, OC or OT detected
HS3_OC_OT 2
rc
Over-Current & Over-Temperature Detection HS3
0B
, No OC or OT
1B
, OC or OT detected
HS2_OC_OT 1
rc
Over-Current & Over-Temperature Detection HS2
0B
, No OC or OT
1B
, OC or OT detected
HS1_OC_OT 0
rc
Over-Current & Over-Temperature Detection HS1
0B
, No OC or OT
1B
, OC or OT detected
rc
Note: The OC/OT bit might be set for VPOR,f < VS < 5.5V (see also Chapter 4.2)
Data Sheet
127
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
HS_OL_STAT
High-Side Switch Open-Load Status (Address 101 0101B)
POR / Soft Reset Value: 0000 0000B;
Restart Value: 0000 xxxxB
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
HS4_OL
HS3_OL
HS2_OL
HS1_OL
r
r
r
r
rc
rc
rc
rc
Field
Bits
Type
Description
Reserved
7:4
r
Reserved, always reads as 0
HS4_OL
3
rc
Open-Load Detection HS4
0B
, No OL
1B
, OL detected
HS3_OL
2
rc
Open-Load Detection HS3
0B
, No OL
1B
, OL detected
HS2_OL
1
rc
Open-Load Detection HS2
0B
, No OL
1B
, OL detected
HS1_OL
0
rc
Open-Load Detection HS1
0B
, No OL
1B
, OL detected
Data Sheet
128
r
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.6.2
Family and Product Information Register
FAM_PROD_STAT
Family and Product Identification Register (Address 111 1110B)
POR / Soft Reset Value: 0011 yyyy B; Restart Value: 0011 yyyyB
7
6
5
4
3
2
1
0
FAM_3
FAM_2
FAM_1
FAM_0
PROD_3
PROD_2
PROD_1
PROD_0
r
r
r
r
r
r
r
r
r
Field
Bits
Type
Description
FAM
7:4
r
SBC Family Identifier (bit4=LSB; bit7=MSB)
0 0 01B, Driver SBC Family
0 0 10B, DC/DC-SBC Family
0 0 11B, Mid-Range SBC Family
x x x xB, reserved for future products
PROD
3:0
r
SBC Product Identifier (bit0=LSB; bit3=MSB)
0 0 0 0B, TLE9260QX (5V, no LIN, no VCC3, no SWK)
0 1 0 0B, TLE9261QX (5V, no LIN, VCC3, no SWK)
1 0 0 0B, TLE9262QX (5V, 1 LIN, VCC3, no SWK)
1 1 0 0B, TLE9263QX (5V, 2 LIN, VCC3, no SWK)
Notes
1. The actual default register value after POR, Soft Reset or Restart of PROD will depend on the respective
product. Therefore the value ‘y’ is specified.
2. SWK = Selective Wake feature in CAN Partial Networking standard
Data Sheet
129
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
14.7
Electrical Characteristics
Table 23
Electrical Characteristics
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
–
–
4.0
MHz
1)
P_16.7.1
V
–
P_16.7.2
SPI frequency
Maximum SPI frequency
fSPI,max
SPI Interface; Logic Inputs SDI, CLK and CSN
H-input Voltage Threshold
VIH
–
–
0.7*
L-input Voltage Threshold
VIL
0.3*
–
–
V
–
P_16.7.3
VIHY
–
0.12*
–
V
1)
P_16.7.4
P_16.7.5
Hysteresis of input Voltage
Pull-up Resistance at pin CSN RICSN
VCC1
VCC1
VCC1
20
40
80
kΩ
20
40
80
kΩ
VCSN = 0.7 x VCC1
VSDI/CLK =
0.2 x VCC1
–
10
–
pF
1)
P_16.7.7
VCC1 -
VCC1 -
–
V
IDOH = -1.6 mA
P_16.7.8
0.4
0.2
–
0.2
0.4
V
-10
–
10
µA
IDOL = 1.6 mA
VCSN = VCC1;
0 V < VDO < VCC1
P_16.7.9
Tristate Leakage Current
VSDOL
ISDOLK
P_16.7.10
Tristate Input Capacitance
CSDO
–
10
15
pF
1)
P_16.7.11
tpCLK
tCLKH
tCLKL
tbef
tlead
tlag
tbeh
tDISU
tDIHO
trIN
250
–
–
ns
–
P_16.7.12
125
–
–
ns
–
P_16.7.13
125
–
–
ns
–
P_16.7.14
125
–
–
ns
–
P_16.7.15
250
–
–
ns
–
P_16.7.16
250
–
–
ns
–
P_16.7.17
125
–
–
ns
–
P_16.7.18
100
–
–
ns
–
P_16.7.19
50
–
–
ns
–
P_16.7.20
–
–
50
ns
–
P_16.7.21
Input Signal Fall Time at pin
SDI, CLK and CSN
tfIN
–
–
50
ns
–
P_16.7.22
Delay Time for Mode
Changes2)
tDel,Mode
–
–
6
µs
includes internal
P_16.7.23
oscillator tolerance
Pull-down Resistance at pin
SDI and CLK
RICLK/SDI
Input Capacitance at pin CSN, CI
SDI or CLK
P_16.7.6
Logic Output SDO
H-output Voltage Level
L-output Voltage Level
VSDOH
1)
Data Input Timing
Clock Period
Clock High Time
Clock Low Time
Clock Low before CSN Low
CSN Setup Time
CLK Setup Time
Clock Low after CSN High
SDI Set-up Time
SDI Hold Time
Input Signal Rise Time at pin
SDI, CLK and CSN
Data Sheet
130
Rev. 1.1, 2014-09-26
TLE9260QX
Serial Peripheral Interface
Table 23
Electrical Characteristics (cont’d)
VS = 5.5 V to 28 V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Parameter
Symbol
CSN High Time
Values
Unit
Note /
Test Condition
Number
Min.
Typ.
Max.
tCSN(high)
3
–
–
µs
–
P_16.7.24
trSDO
tfSDO
tENSDO
tDISSDO
tVASDO
–
30
80
ns
P_16.7.25
–
30
80
ns
CL = 100 pF
CL = 100 pF
–
–
50
ns
low impedance
P_16.7.27
–
–
50
ns
high impedance
P_16.7.28
–
–
50
ns
CL = 100 pF
P_16.7.29
1)
Data Output Timing
SDO Rise Time
SDO Fall Time
SDO Enable Time
SDO Disable Time
SDO Valid Time
P_16.7.26
1) Not subject to production test; specified by design
2) Applies to all mode changes triggered via SPI commands
24
CSN
15
16
13
17
14
18
CLK
19
SDI
not defined
27
SDO
Figure 46
20
LSB
MSB
28
29
Flag
LSB
MSB
SPI Timing Diagram
Note: Numbers in drawing correlate to the last 2 digits of the Number field in the Electrical Characteristics table.
Data Sheet
131
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
15
Application Information
15.1
Application Diagram
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBAT
VBAT
VS
D1
C1
D2
C2
C3
R8
VS
VSHS
VSHS
D3
V CC1
VS
VCC1
VCC2
C7
HS1
VCC2
VS
C5
C4
C6
R9
VSHS
C 17
CSN
R7
VSHS
D4
C8
CSN
CLK
SDI
SDO
CLK
SDI
SDO
HS2
C 18
VDD
µC
HS3
Other loads , e.g.
sensor , opamp, ...
VSHS
LOGIC
State
Machine
TxD CAN
RxD CAN
INT
TxD CAN
RxD CAN
INT
RO
Reset
HS4
R5
R3
S3
R6
C9
Hall1
Q2
Hall2
V SS
TLE9260
R4
VBAT
S2
WK1
Q1
WK2
C 10
S1
V CC2
R1
C 11
R2
WK3
VCAN
CANH
CANH
R10
CAN cell
C 12
R11
CANL
GND
CANL
VS
FOx
T1
LH
Note: The external capacitance on FO3/TEST must be
<=10nF in oder to ensure proper detection of SBC
Development Mode und SBC user mode operation
Application _information _TLE9260. vsd
Figure 47
Data Sheet
Simplified Application Diagram
132
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
Note: Unused outputs are recommended to be left unconnected on the application board. If unused output pins
are routed to an external connector which leaves the ECU, then these pins should have provision for a zero
ohm jumper (depopulated if unused) or ESD protection.
Table 24
Ref.
Bill of Material for Simplified Application Diagram
Typical Value
Purpose / Comment
Capacitances
C1
68µF
Buffering capacitor to cut off battery spikes, depending on application
C2
100nF
EMC, blocking capacitor
C3
22µF
Buffering capacitor to cut off battery spikes from VSHS as separate supply
input; Depending on application, only needed if VSHS is not connected to
VS;
C4
2.2µF low ESR
As required by application, min. 470nF for stability
C5
100nF ceramic
Spike filtering, improve stability of supply for microcontroller;
not needed for SBC
C6
2.2µF low ESR
Blocking capacitor, min. 470nF for stability;
if used for CAN supply place a 100nF ceramic capacitor in addition very
close to VCAN pin for optimum EMC behavior
C7
33nF
As required by application, mandatory protection for off-board connections
C8
33nF
As required by application, mandatory protection for off-board connections
C17
47pF
Only required in case of off-board connection to optimize EMC behavior,
place close to pin
C18
47pF
Only required in case of off-board connection to optimize EMC behavior,
place close to pin
C9
10nF
Spike filtering, as required by application, mandatory protection for off-board
connections (see also Simplified Application Diagram with the Alternate
Measurement Function)
C10
10nF
Spike filtering, as required by application, mandatory protection for off-board
connections
C11
10nF
Spike filtering, as required by application, mandatory protection for off-board
connections
C12
4.7nF / OEM dependent
Split termination stability
Data Sheet
133
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
Table 24
Ref.
Bill of Material for Simplified Application Diagram (cont’d)
Typical Value
Purpose / Comment
Resistances
R1
10kΩ
Wetting current of the switch, as required by application
R2
10kΩ
Limit the WK pin current, e.g. for ISO pulses
R3
10kΩ
Wetting current of the switch, as required by application
R4
10kΩ
Limit the WK pin current, e.g. for ISO pulses
R5
10kΩ
Wetting current of the switch, as required by application
R6
10kΩ
Limit the WK pin current, e.g. for ISO pulses
R7
depending on LED config. LED current limitation, as required by application
R8
depending on LED config. LED current limitation, as required by application
R9
47kΩ
Selection of hardware configuration 1/3, i.e. in case of WD failure SBC
Restart Mode is entered.
If not connected, then hardware configuration 2/4 is selected
R10
60Ω / OEM dependent
CAN bus termination
R11
60Ω / OEM dependent
CAN bus termination
R15
10kΩ
WK1 pin current limitation, e.g. for ISO pulses, for alternate measurement
function (see also Simplified Application Diagram with the Alternate
Measurement Function)
R16
depending on application
and microcontroller
Voltage Divider resistor to adjust measurement voltage to microcontroller
ADC input range (see also Simplified Application Diagram with the Alternate
Measurement Function)
R17
depending on application
and microcontroller
Voltage Divider resistor to adjust measurement voltage to microcontroller
ADC input range (see also Simplified Application Diagram with the Alternate
Measurement Function)
Active Components
D1
e.g. BAS 3010A, Infineon Reverse polarity protection for VS supply pins
D2
e.g. BAS 3010A, Infineon Reverse polarity protection for VSHS supply pin; if separate supplies are not
needed, then connect VSHS to VS pins
D3
LED
As required by application, configure series resistor accordingly
D4
LED
As required by application, configure series resistor accordingly
T1
e.g. BCR191W
High active FO control
µC
e.g. TC2xxx
Microcontroller
Note: This is a simplified example of an application circuit. The function must be verified in the real application.
Data Sheet
134
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
VBAT
D2
VS
D1
VBAT
C1
e.g.
470uF
C2
VS
VCC1
VCC1
C5
C4
VS
CSN
CSN VDD
CLK
SDI
SDO
CLK
SDI
SDO
LOGIC
State
Machine
µC
TxD CAN
RxD CAN
TxD CAN
RxD CAN
INT
max.
500uA
R 17
Figure 48
R6
WK1
≥10k
C9
≥10n
ISO Pulse
protection
Vbat_uC
TLE9260
INT
RO
Reset
Vbat_uC
ADC_x
VSS
S1
WK2
Note:
Max. WK1 input current limited to
500µA to ensure accuracy and
proper operation ;
R 16
GND
Simplified Application Diagram with the Alternate Measurement Function via WK1 and WK2
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.WK1 must be connected to signal to be measured and WK2 is the output to the microcontroller
supervision function. The maximum current into WK1 must be <500uA. The minimum current into WK1
should be >5uA to ensure proper operation.
Data Sheet
135
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
15.2
ESD Tests
Note: Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) will been performed. The
results and test condition will be available in a test report. The target values for the test are listed in Table 25
below.
Table 25
ESD “Gun Test”
Performed Test
Result
Unit
Remarks
ESD at pin CANH, CANL,
VS, WK1..3, HSx, VCC2
versus GND
>6
kV
1)2)
positive pulse
1)2)
ESD at pin CANH, CANL, < -6
kV
negative pulse
VS, WK1..3, HSx, VCC2
versus GND
1)ESD Test “Gun Test” is specified with external components for pins VS, WK1..3, HSx and VCC2. See the
application diagram in Chapter 15.1 for more information.
2) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3 (IEC 61000-4-2). Tested by external
test house (IBEE Zwickau, EMC Test report Nr. 07-10-13)
EMC and ESD susceptibility tests according to SAE J2962-2 (2010) have been performed. Tested by external test
house (UL LLC, Test report Nr. 2013-474A)
Data Sheet
136
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
15.3
Thermal Behavior of Package
Below figure shows the thermal resistance (Rth_JA) of the device vs. the cooling area on the bottom of the PCB for
Ta = 85°C. Every line reflects a different PCB and thermal via design.
Figure 49
Data Sheet
Thermal Resistance (Rth_JA) vs. Cooling Area
137
Rev. 1.1, 2014-09-26
TLE9260QX
Application Information
Cross Section (JEDEC 2s2p) with Cooling Area
Cross Section (JEDEC 1s0p) with Cooling Area
1,5 mm
1,5 mm
70µm modelled (traces)
35µm, 90% metalization*
35µm, 90% metalization*
70µm / 5% metalization + cooling area
*: means percentual Cu metalization on each layer
PCB (top view)
Figure 50
PCB (bottom view)
Detail SolderArea
Board Setup
Board setup is defined according to JESD 51-2,-5,-7.
Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (35µm thick), with thermal via array under the exposed pad
contacting the first inner copper layer and 300mm2 cooling area on the bottom layer (70µm).
Data Sheet
138
Rev. 1.1, 2014-09-26
TLE9260QX
Package Outlines
Package Outlines
6.8
11 x 0.5 = 5.5
0.5
0.1±0.03
+0.03
1)
0.1 ±0.05
B
0.4 x 45°
Index Marking
0.15 ±0.05
48
13
5)
0.05 MAX.
1) Vertical burr 0.03 max., all sides
2) This four metal areas have exposed diepad potential
Figure 51
1
12
(0.2)
2)
37
.3
C
24
(0
SEATING PLANE
7 ±0.1
6.8
48x
0.08
36
25
0.5 ±0.07
A
(6)
7 ±0.1
0.9 MAX.
(0.65)
(5.2)
16
0.23 ±0.05
(5.2)
Index Marking
48x
0.1 M A B C
(6)
PG-VQFN-48-29, -31-PO V03
PG-VQFN-48-31
Note: For assembly recommendations please also refer to the documents "Recommendations for Board Assembly
(VQFN and IQFN)" and "VQFN48 Layout Hints" on the Infineon website (www.infineon.com).
The PG-VQFN-48-31 package is a leadless exposed pad power package featuring Lead Tip Inspection (LTI) to
support Automatic Optical Inspection (AOI).
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
139
Dimensions in mm
Rev. 1.1, 2014-09-26
TLE9260QX
Revision History
17
Revision History
Table 26
Revision History
Revision
Date
Changes
Rev 1.1
2014-09-26
Initial Release
Data Sheet
140
Rev. 1.1, 2014-09-26
Edition 2014-09-26
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.