PAGE 1 OF 10 ATMEL CORPORATION Tel: (408) 441-0311 Fax: (408) 436-4200 AT-22V10 CMOS PROGRAMMABLE LOGIC ARRAYS RELIABILITY DATA* - 125°C DYNAMIC OPERATING LIFE TEST - 200°C RETENTION BAKE - 125°C DYNAMIC OPERATING LIFE TEST (PLASTIC) - 125°C RETENTION BAKE (PLASTIC) - 15 PSIG PRESSURE POT * This report was generated from AT-22V10 reliability testing. This data is applicable to the following device types due to same technology grouping as defined in MIL-M-38535 Appendix A: AT-V750 AT-V2500 AT-V5000 JANUARY 2001 2325 Orchard Parkway San Jose CA. 95131 PAGE 2 OF 10 AT-22V10 125°C DYNAMIC OPERATING LIFE TEST LOT NUMBER 680 2891 80650-1 81196 83993 88437 03024 03012 22118 132633-23 132448-8 134265-4 232290 232289-3 232534 234585 3D0836 DATE CODE 8739 8804 8829 8B8840 8D8905 9B8949 0C9037 0C9041 0C9039 1C9139 1C9135 2A9207 2C9231 2C9232 2C9240 3B9320 3D9404 SAMPLE SIZE TOTAL CKT-HRS(K) 77 77 77 77 45 77 77 77 79 77 80 77 80 78 227 45 80 NUMBER OF FAILURES 77.0 77.0 77.0 77.0 45.0 77.0 77.0 77.0 79.0 77.0 80.0 77.0 80.0 78.0 227.0 45.0 80.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILURE RATE TOTAL DEVICE HOURS 1,323,000 DEVICE HOURS BEST ESTIMATE λ = 0.05% PER 1,000 HOURS 50°C AMBIENT EXTRAPOLATION TO 50°C VIA ARRHENNIUS EQUATION AND ACTIVATION ENERGY OF 0.5eV λ = 0.002% PER 1,000 HOUR (18 FITS) CONFIDENCE ESTIMATE λ 60 = 0.002% PER 1,000 HOURS 60% CONFIDENCE (23 FITS) λ 90 = 0.006% PER 1,000 HOURS 90% CONFIDENCE (60 FITS) PAGE 3 OF 10 AT-22V10 200°C RETENTION BAKE 200°C BAKE. LOT NUMBER 81198-2 88846-1 20050-2 132633-23 134265-4 232534 231649A-2 DATE CODE 8B8831 9B8920 9024 1C9139 2A9207 2C9240 2C9244 DEVICES WITH ALL ZEROS OR WITH ALL ONES SAMPLE SIZE 80 45 80 27 42 231 43 24 0 0 0 0 0 0 0 NUMBER OF FAILURES 162 500 1,000 HRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAILURE RATE TOTAL DEVICE HOURS 548,000 DEVICE HOURS BEST ESTIMATE λ = 0.013% PER 1,000 HOURS 50°C AMBIENT EXTRAPOLATION TO 50°C VIA ARRHENNIUS EQUATION AND ACTIVATION ENERGY OF 0.5eV λ = 0.0004% PER 1,000 HOURS (4 FITS) CONFIDENCE ESTIMATE λ = 60 = 0.0006% PER 1,000 HOURS 60% CONFIDENCE (6 FITS) λ 90 = 0.0014% PER 1,000 HOURS 90% CONFIDENCE (14 FITS) PAGE 4 OF 10 AT-22V10 PLASTIC PACKAGE 125°C DYNAMIC OPERATING LIFE TEST LOT NUMBER 80956 DATE CODE SAMPLE SIZE TOTAL CKT-HRS(K) NUMBER OF OF FAILS 8C8947 77 77.0 0 9B8925 79 79.0 0 04250 1A9116 78 78.0 1 (Marginal VCC) 131081 2C9235 77 77.0 0 232534 2C9236 78 78.0 0 3B066A 3B9333 78 78.0 0 5A2541 5A9525 116 116.0 0 FAILURE RATE TOTAL DEVICE HOURS 583,000 DEVICE HOURS BEST ESTIMATE λ = 0.3% PER 1,000 HOURS 50°C AMBIENT EXTRAPOLATION TO 50°C VIA ARRHENNIUS EQUATION AND ACTIVATION ENERGY OF 0.5eV λ = 0.010% PER 1,000 HOURS (99 FITS) CONFIDENCE ESTIMATE λ 60 = 0.012% PER 1,000 HOURS 60% CONFIDENCE (120 FITS) λ 90 = 0.023% PER 1,000 HOURS 90% CONFIDENCE (228 FITS) PAGE 5 OF 10 AT-22V10 PLASTIC PACKAGE 125°C RETENTION BAKE LOT NUMBER 03033 23120-2 04250 231097 133469 131081 232534 3B0066A DATE CODE 0D9045 0D9106 1A9116 2B9224 2B9225 2C9235 2C9236 3B9333 PKG TYPE 24 24 24 24 24 28 28 24 P-DIP P-DIP P-DIP SOIC SOIC PLCC PLCC PDIP SAMPLE SIZE 78 77 84 79 77 78 78 77 NUMBER OF FAILURES AT INDICATED HOURS (250) (500) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (1000) 0 0 0 0 0 0 0 0 FAILURE RATE TOTAL DEVICE HOURS 628,000 DEVICE HOURS BEST ESTIMATE λ = 0.11% PER 1,000 HOURS 50°C AMBIENT EXTRAPOLATION TO 50°C VIA ARRHENNIUS EQUATION AND ACTIVATION ENERGY OF 0.5eV λ = 0.004% PER 1,000 HOURS (37 FITS) CONFIDENCE ESTIMATE λ 60 = 0.005% PER 1,000 HOURS 60% CONFIDENCE (48 FITS) λ 90 = 0.012% PER 1,000 HOURS 90% CONFIDENCE (124 FITS) PAGE 6 OF 10 AT-22V10 PLASTIC PACKAGE PRESSURE POT TEST DATE CODE PACKAGE TYPE SAMPLE SIZE NUMBER OF FAILURES AT INDICATED HOURS (24) (48) (72) (96) 8C8947 24 P-DIP 45 0 0 0 0 0C9034 28 PLCC 45 0 0 0 0 0D9045 24 P-DIP 45 0 0 0 0 3B9333 24 P-DIP 90 0 0 0 0 PAGE 7 OF 10 AT-22V10 PLASTIC PACKAGE 85°C/85% RELATIVE HUMIDITY OPERATING LIFE TEST LOT NUMBER DATE CODE PACKAGE TYPE SAMPLE SIZE NUMBER OF FAILURES AT INDICATED HOURS (168) (500) (1000) 03033-5 0D9045 24 P-DIP 45 0 0 0 23120-2 0D9106 24 P-DIP 45 0 0 0 PAGE 8 OF 10 MEMORANDUM Date: Subject: From: February 8, 1990 AT22V10 Bake Experiment Keith Gudger A 200 degree C bake experiment was performed on 34 units from AT22V10 lot 680-1. Margining was accomplished by measuring VCC Max for the standard class test pattern. This pattern has more than 85% of all bits programmed, and checks every product term and output to all known possible conditions. Product programmed on the Data I/O 29B LogicPak has VCC Max above 6V. The product specification is operation to VCC = 5.5V. Therefor, a 0.5V margin is available for charge loss over the life of the device. The following table lists the change in worst case VCC Max versus time at 200°C for the 34 devices. The far right column equates time at 200 C to lifetime at 55°C using the Arrhennius equation and an activation energy of 0.5 eV, which is considered very conservative for this type of charge loss mechanism. Time 0 168 250 514 1016 delta VCC Max hours hours hours hours hours 0 0.20V 0.25V 0.25V 0.25V Equivalent time at 55°C 0 4.3 6.5 13.3 26.3 years years years years As can be seen, there is very little charge loss at bake times corresponding to more than 25 years. The charge lost is well within the margin provided by all commercially available programming equipment. (The specification for certification of programming equipment for ATMEL EPLD'S is a VCC Max of a minimum of 5.9V.) PAGE 9 OF 10 MEMORANDUM Date Subject From : Dec. 14, 1989 : New AT22V10 Latchup Characterization : Jinglun Tam Packaged units of AT22V10 from the first lot in Colorado site were tested for latchup under normal coditions: Rome Temp Vcc=5v. 15 150ohmn - 1/4W in parallel were connected across the Vcc power supply and group to allow current to be forced out of the Vcc pin during testing. The ammeter in the power supply was monitored to verify when latchup occurred. A curve tracer was used to force current into each pin and latchup trigger current and voltage were observed and recorded. Collector series resistance specified in curve tracer was 1.9ohmn. No more than 600mA or 26V (-10V for negative power supply) would be applied to pins from curve tracer before latchup occurred. A lessinteference sequence of testing made it possible to test on a single unit and get all the data for latchup characterization: 1) Negative voltage applied to I/O pins 2) Positive voltage applied to I/O pins 3) Negative voltage applied to input pins 4) Positive voltage applied to input pins. *input pin #1 and #13 were the last input pins tested in each step. One or two among the above four types of characterization were performed to three units and junction breakdowns made impossible other characterizations on the same unit. Data taken before the voltage breakdown destructions from these units were consistent with the corresponding data taken on a single unit with the above test sequence. The latchup trigger current and voltage for that single unit were listed as following: PAGE 10 OF 10 Pin # Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Vpp/In In In In In In In In In In In Gnd Pgm/In I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Vcc +I (mA) 35 35 35 35 35 35 35 35 35 35 35 35 400 400 400 400 400 400 420 400 450 490 +I (V) -I (mA) -V (V) 26 26 26 26 26 26 26 26 26 26 26 >600 >500 >550 >500 >500 >550 >500 >550 >500 >550 >600 10 10 10 10 10 10 10 10 10 10 4.8 26 8.4 8.5 8.5 8.3 8.1 8.1 8.1 7.9 6.8 7.0 >600 >600 >600 >600 >600 >600 >600 >600 >600 >600 >600 3.1 2.0 2.1 2.2 2.2 2.1 2.2 2.3 2.5 2.3 2.5