High Temperature, 16-Bit, 600 kSPS PulSAR® ADC AD7981-KGD Known Good Die FEATURES METAL MASK DIE IMAGE REF VIO REF VDD VDD VIO IN+ SDI IN– SCK GND SDO GND CNV 12479-004 Extreme high temperature operation Specified temperature range: −55°C to +175°C High performance 16-bit resolution with no missing codes 600 kSPS throughput with no latency/pipeline delay SNR: 91 dB typical at 1 kHz input frequency THD: −102 dB typical at 1 kHz input frequency INL: ±2.0 LSB maximum, DNL: ±0.9 LSB maximum Low power dissipation 2.25 mW typical at 600 kSPS (VDD only) 4.65 mW typical at 600 kSPS (total) 70 μW typical at 10 kSPS Pseudo differential analog input range 0 V to VREF with VREF between 2.4 V and 5.1 V Easy to use Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface SPI-/QSPI-/MICROWIRE-/DSP-compatible digital interface Daisy-chain multiple ADCs and busy indicator Known good die (KGD): these die are fully guaranteed to data sheet specifications Figure 1. APPLICATIONS Downhole drilling and instrumentation Avionics Heavy industrial High temperature environments GENERAL DESCRIPTION The AD7981-KGD1 is a 16-bit, successive approximation, analog-to-digital converter (ADC) designed for high temperature operation. The AD7981-KGD is capable of sample rates up to 600 kSPS while maintaining low power consumption from a single power supply, VDD. It is a fast throughput, high accuracy, high temperature, successive approximation register (SAR) ADC and packaged in a small form factor with a versatile serial port interface (SPI). On the CNV rising edge, the AD7981-KGD samples an analog input, IN+, between 0 V and REF with respect to a ground sense, IN−. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. The device power scales linearly with throughput. 1 The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. The AD7981-KGD is a member of a growing series of high temperature qualified products offered by Analog Devices, Inc. For a complete selection of available high temperature products, see the high temperature product list and qualification data available at www.analog.com/hightemp. Additional application and technical information can be found in the AD7981 data sheet. Protected by U.S. Patent 6,703,961. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7981-KGD Known Good Die TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Metal Mask Die Image ..................................................................... 1 Terminology .......................................................................................8 General Description ......................................................................... 1 Outline Dimensions ..........................................................................9 Revision History ............................................................................... 2 Die Specifications and Assembly Recommendations ..............9 Specifications..................................................................................... 3 Ordering Guide .............................................................................9 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY 4/15—Revision 0: Initial Version Rev. 0 | Page 2 of 9 Known Good Die AD7981-KGD SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −55°C to +175°C, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input Common-Mode Rejection Ratio (CMRR) Leakage Current at 25°C ACCURACY No Missing Codes Differential Nonlinearity Integral Nonlinearity Transition Noise Gain Error 2 Gain Error Temperature Drift Zero Error2 Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY 3 Dynamic Range Oversampled Dynamic Range 4 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion (SINAD) Test Conditions/Comments Min 16 IN+ − IN− IN+ IN− fIN = 100 kHz Acquisition phase 0 −0.1 −0.1 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V TMIN to TMAX TMIN to TMAX Typ Unit Bits VREF VREF + 0.1 +0.1 V V V dB nA 60 1 16 −0.9 −2.0 −1 VDD = 2.5 V ± 5% ±0.4 ±0.5 ±0.7 ±0.6 0.75 1.2 ±2 ±0.35 ±0.08 0.45 ±0.1 0 89 +0.9 +2.0 +1 600 290 Full-scale step VREF = 5 V VREF = 2.5 V OSR = 256 fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz, VREF = 5 V fIN = 1 kHz, VREF = 2.5 V Max 92 87 110 91 86 104 −102 90.5 85.5 Bits LSB 1 LSB1 LSB1 LSB1 LSB1 LSB1 LSB1 ppm/°C mV ppm/°C LSB1 kSPS ns dB dB dB dB dB dB dB dB dB LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV. See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference. All ac accuracy specifications in dB are referred to an input full-scale range (FSR). Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 The oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in the ADC output FFT from dc up to fS/(2 × OSR), where fS is the ADC sample rate and OSR is the oversampling ratio. 1 2 3 Rev. 0 | Page 3 of 9 AD7981-KGD Known Good Die VDD = 2.5 V, VIO = 2.3 V to 5.5 V, VREF = 5 V, TA = −55°C to +175°C, unless otherwise noted. Table 2. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH Test Conditions/Comments Min 2.4 VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance 3 Max Unit 5.1 600 kSPS, VREF = 5 V 330 V µA VDD = 2.5 V 10 2.0 MHz ns VIO > 3 V VIO ≤ 3 V VIO > 3 V VIO ≤ 3 V –0.3 –0.3 0.7 × VIO 0.9 × VIO −1 −1 IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation Total Typ 0.3 × VIO 0.1 × VIO VIO + 0.3 VIO + 0.3 +1 +1 Serial 16 bits straight binary Conversion results available immediately after completed conversion 0.4 VIO − 0.3 ISINK = 500 µA ISOURCE = −500 µA 2.375 2.3 1.8 Specified performance VDD and VIO = 2.5 V VDD = 2.625 V, VREF = 5 V, VIO = 3 V 10 kSPS 600 kSPS 600 kSPS 600 kSPS 600 kSPS TMIN to TMAX 2.5 2.625 5.5 5.5 0.35 70 4.65 2.25 1.5 0.9 7.75 −55 With all digital inputs forced to VIO or GND as required. During the acquisition phase. 3 Qualified for up to 1000 hours of operation at the maximum temperature rating. 1 2 Rev. 0 | Page 4 of 9 7.0 +175 V V V µA µA µA V V V V V µA µW mW mW mW mW nJ/sample °C Known Good Die AD7981-KGD TIMING SPECIFICATIONS TA = −55°C to +175°C, VDD = 2.375 V to 2.625 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions. Table 3. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) tSCKL tSCKH tHSDO tDSDO Unit ns ns ns ns 10.5 12 13 15 ns ns ns ns 11.5 13 14 16 4.5 4.5 3 ns ns ns ns ns ns ns 9.5 11 12 14 ns ns ns ns 10 15 20 ns ns ns ns ns ns ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 5 2 0 5 5 2 3 15 X% VIO1 tDELAY VIH2 VIL2 1.4V CL 20pF VIH2 VIL2 1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30. VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 2. 12589-002 IOH Max 1377 tSCK tDELAY 500µA Typ Y% VIO1 IOL TO SDO Min 625 290 1667 10 2MINIMUM Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. 0 | Page 5 of 9 12589-003 500µA Symbol tCONV tACQ tCYC tCNVH tSCK AD7981-KGD Known Good Die ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Inputs IN+, IN− to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6 V −0.3 V to +3 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 176.4°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. 0 | Page 6 of 9 Known Good Die AD7981-KGD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 REF VDD 1 2 VDD 2 3 IN– 4 GND 5 GND 5 VIO 10 VIO 9 SDI 8 SCK 7 SDO 6 CNV 12479-005 IN+ 10 Figure 4. Pad Configuration Table 5. Pad Function Descriptions Pad No. 1 1 2 2 3 Mnemonic REF REF VDD VDD IN+ X-Axis (μm) −602 −602 −602 −602 −616 Y-Axis (μm) +1014 +811 +719 +517 −198 Pad Type1 AI AI P P AI 4 IN− −616 −372 AI 5 5 6 GND GND CNV −616 −610 +624 −558 −730 −850 P P DI 7 8 SDO SCK +624 +624 −675 −470 DO DI 9 SDI +624 −288 DI 10 10 VIO VIO +619 +622 +123 +993 P P Description Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND pin. Decouple REF with a 10 μF capacitor as close as possible to the pin. Power Supply. Analog Input. This pin is referred to IN+. The voltage range, for example, the difference between IN+ and IN−, is 0 V to VREF. Analog Input Ground Sense. Connect this pin to the analog ground plane or to a remote sense ground. Power Supply Ground. Conversion Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: chain mode or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, read the data when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the device is selected, this clock shifts out the conversion result. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally it is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1 AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. 0 | Page 7 of 9 AD7981-KGD Known Good Die TERMINOLOGY Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error The first transition occurs at a level ½ LSB above analog ground (38.1 µV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111 … 10 to 111 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the following formula: Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. It is measured with a signal at −60 dBFS to include all noise sources and DNL artifacts. The value for dynamic range is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Rev. 0 | Page 8 of 9 Known Good Die AD7981-KGD OUTLINE DIMENSIONS 1.520 1 0.750 10 1 2 2 10 3 2.285 9 4 8 5 7 5 TOP VIEW (CIRCUIT SIDE) SIDE VIEW 0.07 × 0.07 12-01-2014- A 6 Figure 5. 10-Pad Bare Die [CHIP] (C-10-5) Dimensions shown in millimeters DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS Table 6. Die Specifications Parameter Chip Size Scribe Line Width Die Size Thickness Bond Pad Bond Pad Composition Backside Passivation Value 1440 × 2205 80 × 80 1520 × 2285 750 70 × 70 0.5 AlCu Standard assembly die attach Oxynitride Unit μm μm μm μm μm % Not applicable Not applicable Table 7. Assembly Recommendations Assembly Component Die Attach Bonding Method Bonding Sequence 1 Recommendation Epoxy adhesive Gold ball1 or aluminum wedge Bond pin five first Evaluate the gold wire for suitability before use at elevated temperatures for extended durations. ORDERING GUIDE Model AD7981-KGD-WP Temperature Range −55°C to +175°C Package Description 10-Pad Bare Die [CHIP] ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12589-0-4/15(0) Rev. 0 | Page 9 of 9 Package Option C-10-5