AD7980-DSCC: Military Data Sheet

REVISIONS
LTR
DESCRIPTION
DATE
Prepared in accordance with ASME Y14.24
APPROVED
Vendor item drawing
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PMIC N/A
PREPARED BY
Phu H. Nguyen
Original date of drawing
YY MM DD
CHECKED BY
12-11-20
Phu H. Nguyen
APPROVED BY
Thomas M. Hess
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AMSC N/A
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CODE IDENT. NO.
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DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
TITLE
MICROCIRCUIT, DIGITAL-LINEAR, 16-BIT,
1 MSPS PulSAR ADC, MONOLITHIC SILICON
DWG NO.
V62/12640
16236
PAGE
1
OF
10
5962-V026-13
1. SCOPE
1.1 Scope. This drawing documents the general requirements of a high performance 16-bit, 1 MSPS PulSAR ADC microcircuit, with
an operating temperature range of -55°C to +125°C.
1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item
drawing establishes an administrative control number for identifying the item on the engineering documentation:
V62/12640
-
Drawing
number
01
X
E
Device type
(See 1.2.1)
Case outline
(See 1.2.2)
Lead finish
(See 1.2.3)
1.2.1 Device type(s).
Device type
Generic
Circuit function
01
AD7980-EP
16-bit, 1 MSPS PulSAR ADC
1.2.2 Case outline(s). The case outlines are as specified herein.
Outline letter
Number of pins
JEDEC PUB 95
10
JEDEC MO-187-BA
X
Package style
Mini Small Outline Package
1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer:
Finish designator
A
B
C
D
E
Z
DLA LAND AND MARITIME
COLUMBUS, OHIO
Material
Hot solder dip
Tin-lead plate
Gold plate
Palladium
Gold flash palladium
Other
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
2
1.3 Absolute maximum ratings.
1/
Analog inputs: IN+, IN- to GND .............................................................
Supply voltage:
REF, VIO to GND ..............................................................................
VDD to GND ......................................................................................
VDD to VIO .........................................................................................
Digital inputs to GND ...............................................................................
Digital outputs to GND ............................................................................
Storage temperature range .....................................................................
Junction temperature ..............................................................................
θJA Thermal impedance (Case outline X) ................................................
θJC Thermal impedance (Case outline X) ................................................
Lead temperature:
Vapor phase (60 sec) .......................................................................
Infrared (15 sec) ...............................................................................
-0.3 V to VREF + 0.3 V or ±130 mA
-0.3 V to +6 V
-0.3 V to +3 V
+3 V to -6 V
-0.3 V to VIO + 0.3 V
-0.3 V to VIO + 0.3 V
-65°C to 150°C
150°C
200°C/W
44°C/W
215°C
220°C
2. APPLICABLE DOCUMENTS
JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC)
JEP95
–
Registered and Standard Outlines for Semiconductor Devices
(Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103
North 10th Street, Suite 240–S, Arlington, VA 22201.)
3. REQUIREMENTS
3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as
follows:
A.
B.
C.
Manufacturer’s name, CAGE code, or logo
Pin 1 identifier
ESDS identification (optional)
3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable)
above.
1/
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
3
3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as
specified in 1.3, 1.4, and table I herein.
3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein.
3.5 Diagrams.
3.5.1
Case outline. The case outline shall be as shown in 1.2.2 and figure 1.
3.5.2
Terminal connections. The terminal connections shall be as shown in figure 2.
3.5.3
Load circuit for digital interface timing. The load circuit for digital interface timing shall be as shown in figure 3.
3.5.4
Voltage levels for timing. The voltage levels for timing shall be as shown in figure 4.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
4
TABLE I. Electrical performance characteristics. 1/
Test
Symbol
Resolution
Analog input
Voltage range
Limits
Test conditions
VDD = 2.5 V, VREF = 5.0 V
2.3 V ≤ VIO ≤ 5.5 V
-55°C ≤ TA ≤ +125°C
unless otherwise noted
Min
Typ
Unit
Max
16
IN+ - ININ+
INfIN = 100 kHz
Acquisition phase
Absolute input voltage
Analog input CMRR
Leakage current @ 25°C
Accuracy
No missing codes
0
-0.1
-0.1
Integral linearity error
Transition noise
16
-0.9
-1.5
Gain error, TMIN to TMAX 3/
Gain error temperature drift
Zero error, TMIN to TMAX
Zero temperature drift
Power supply sensitivity
Throughput
3/
-0.62
VDD = 2.5 V ± 5%
VIO ≥ 2.3 V up to 85°C,
VIO ≥ 3.3 V above 85°C up to 125°C
Full scale step
Conversion rate
Transient response
AC accuracy
Dynamic range
Oversampled dynamic range
Signal to Noise Ratio,
SNR
Spurious Free Dynamic Range,
Total Harmonic Distortion,
SFDR
THD
Signal to (Noise +Distortion),
SINAD
VREF
VREF + 0.1
+0.1
60
1
REF = 5 V
REF = 2.5 V
REF = 5 V
REF = 2.5 V
REF = 5 V
REF = 2.5 V
Differential linearity error
Bits
VREF = 5V
VREF = 2.5V
fo = 10 kSPS
fIN = 10 kHz, VREF = 5 V
fIN = 10 kHz, VREF = 2.5 V
fIN = 10 kHz
fIN = 10 kHz
fIN = 10 kHz, VREF = 5 V
fIN = 10 kHz, VREF = 2.5 V
dB
nA
±0.4
±0.55
±0.6
±0.65
0.6
1.0
±2
±0.35
+0.9
±0.08
0.54
±0.1
+0.62
0
V
V
Bits
LSB 2/
+1.5
ppm/°C
mV
ppm/°C
LSB 2/
1
MSPS
290
ns
92
87
111
91
86.5
-110
-114
91.5
87.0
dB 4/
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
5
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Reference
Voltage range
Load current
Sampling dynamics
-3 dB input bandwidth
Aperture delay
Digital inputs
Digital outputs
Data format
Pipeline delay
VOL
VOH
Power supply
VDD
VIO
VIO range
Standby current 5/ 6/
Power dissipation
Energy per conversion
Temperature range
Specified performance
Limits
Min
Typ
2.4
VIL
VIH
VIL
VIH
IIL
IIH
Logic level
Test conditions
VDD = 2.5 V, VREF = 5.0 V
2.3 V ≤ VIO ≤ 5.5 V
-55°C ≤ TA ≤ +125°C
unless otherwise noted
Unit
Max
1 MSPS, REF = 5 V
330
V
µA
VDD = 2.5 V
10
2.0
MHz
ns
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
5.1
-0.3
0.7 x VIO
-0.3
0.9 x VIO
-1
-1
Serial 16 bits straight binary
Conversion results available
immediately after completed
conversion
ISINK = 500 µA
ISOURCE = -500 µA
V
µA
0.4
V
2.625
5.5
5.5
V
VIO – 0.3
2.375
2.3
1.8
Specified performance
0.3 x VIO
VIO + 0.3
0.1 x VIO
VIO + 0.3
+1
+1
VDD and VIO = 2.5 V, TA = 25°C
10 kSPS throughput
1 MSPS throughput
TMIN to TMAX
2.5
0.35
nA
70
7.0
7.0
10
µW
mW
nJ/sample
+125
°C
-55
See footnote at end of table.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
6
TABLE I. Electrical performance characteristics - Continued. 1/
Test
Symbol
Timing specifications (see FIGURE 2 and 3 for load condition)
Conversion time: CNV rising edge to data available
tCONV
Acquisition time
tACQ
Time between conversions
tCYC
��� Mode)
tCNVH
CNV pulse width (CS
��� Mode)
SCK period (CS
tSCK
SCK period (chain mode)
tSCK
SCK low time
SCK high time
SCK falling edge to data remains valid
tSCKL
tSCKH
tHSDO
SCK falling edge to data valid delay
tDSDO
��� Mode)
CNV or SDI low to SDO D15 MSB valid (CS
CNV or SDI high or last SCK falling edge to SDO high
��� Mode)
impedance (CS
SDI valid setup time from CNV rising edge
��� Mode)
SDI valid hold time from CNV rising edge (CS
SDI valid hold time from CNV rising edge ( Chain Mode)
SCK valid setup time from CNV rising edge (Chain mode)
SCK valid hold time from CNV rising edge ( Chain Mode)
SDI valid setup time from SCK falling edge (Chain mode)
SDI valid hold time from SCK falling edge ( Chain Mode)
SDI high to SDO high (Chain mode with Busy Indicator)
1/
2/
3/
4/
5/
6/
tEN
Test conditions
2.37 V ≤ VDD ≤ 2.63 V
3.3 V ≤ VIO ≤ 5.5 V
-55°C ≤ TA ≤ +125°C
unless otherwise noted
VIO above 4.5 V
VIO above 3 V
VIO above 2.7 V
VIO above 2.3 V
VIO above 4.5 V
VIO above 3 V
VIO above 2.7 V
VIO above 2.3 V
Limits
Min
Typ
Unit
Max
500
290
1000
10
10.5
12
13
15
11.5
13
14
16
4.5
4.5
3
710
VIO above 4.5 V
VIO above 3 V
VIO above 2.7 V
VIO above 2.3 V
VIO above 3 V
VIO above 2.7 V
9.5
11
12
14
10
15
20
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
ns
5
2
0
5
5
2
3
15
Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the
specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not
necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or
design.
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
These specifications include full temperature range variation, but not the error contribution from the external reference.
All specifications in dB are referred to a full scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless
otherwise specified.
With all digital inputs forced to VIO or GND as required.
During the acquisition phase.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
7
Case X
e
b
10 PLS
10
0°-6°
6
E
1
E1
L
5
PIN 1
IDENTIFIER
DETAIL A
D
SEE DETAIL A
A2
A
c
A1
Symbol
A
A1
A2
b
c
Dimensions
Millimeters
Symbol
Min
Max
0.05
0.75
0.15
0.13
1.10
0.15
0.95
0.30
0.23
D/E
E1
e
L
Millimeters
Min
Max
2.90
3.10
4.65
5.15
0.50 BSC
0.40
0.70
NOTES:
1. All linear dimensions are in millimeters.
2. Falls within JEDEC MO-187-BA.
FIGURE 1. Case outline.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
8
Case outline X
Terminal
Terminal
symbol
number
10
REF
Terminal
number
1
Terminal
symbol
VIO
2
3
VDD
IN+
9
8
SCK
4
5
INGND
7
6
CNV
SDI
SDO
FIGURE 2. Terminal connections.
500
I OL
A
1.4 V
TO SDO
CL
20 pF
500
I OH
A
IGURE 3. Load circuit for digital interface timing.
Y% VIO (SEE NOTE 1)
X% VIO (SEE NOTE 1)
t
t
DELAY
DELAY
VIH (SEE NOTE 2)
VIL (SEE NOTE 2)
NOTES:
1. For VIO ≤ 3.0 V, X = 90 and Y = 10; For VIO > 3.0 V X = 70 and Y = 30.
2. Minimum VIH and maximum VIL used. See Digital Inputs specifications in table I.
FIGURE 4. Voltage levels for timing.
DLA LAND AND MARITIME
COLUMBUS, OHIO
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
9
4. VERIFICATION
4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as
indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices,
classification, packaging, and labeling of moisture sensitive devices, as applicable.
5. PREPARATION FOR DELIVERY
5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial
practices for electrostatic discharge sensitive devices.
6. NOTES
6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum.
6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book.
The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided.
6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of
present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current
sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Vendor item drawing
administrative control
number 1/
Device
manufacturer
CAGE code
Vendor part number
V62/12640-01XE
24355
AD7980SRMZ-EP-RL7 2/
1/ The vendor item drawing establishes an administrative control number for
identifying the item on the engineering documentation.
2/ Z = RoHS compliant part
CAGE code
24355
DLA LAND AND MARITIME
COLUMBUS, OHIO
Source of supply
Analog Devices
1 Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
SIZE
A
CODE IDENT NO.
16236
REV
DWG NO.
V62/12640
PAGE
10