4-Channel, 16-Bit, Continuous Time Data Acquisition ADC ADAR7251 Data Sheet FEATURES GENERAL DESCRIPTION Low noise: 2.4 nV/√Hz input referred voltage noise at maximum gain setting Wide input signal bandwidth: 500 kHz at 1.2 MSPS sample rate, 16-bit resolution Additional sample rates supported: 300 kSPS, 450 kSPS, 600 kSPS, 900 kSPS, and 1.8 MSPS 4 differential simultaneous sampling channels No active antialiasing filter required LNA and PGA with 45 dB gain range in 6 dB steps Selectable equalizer Flexible data port supports serial or parallel mode Supports FSK mode for FMCW radar systems On-chip 1.5 V reference Internal oscillator/PLL input: 16 MHz to 54 MHz High speed serial data interface SPI control 2 general-purpose inputs/outputs 48-lead LFCSP_SS package Temperature range: −40°C to +125°C Single supply operation of 3.3 V Qualified for automotive applications The ADAR7251 is a 16-bit, 4-channel, simultaneous sampling analog-to-digital converter (ADC) designed especially for applications such as automotive LSR-FMCW or FSK-FMCW radar systems. Each of the four channels contains a low noise amplifier (LNA), a programmable gain amplifier (PGA), an equalizer, a multibit Σ-Δ ADC, and a decimation filter. APPLICATIONS The front-end circuitry is designed to allow direct connection to an MMIC output with few external passive components. The ADAR7251 eliminates the need for a high order antialiasing filter, driver op amps, and external bipolar supplies. The ADAR7251 also offers precise channel-to-channel drift matching. The ADAR7251 features an on-chip phase-locked loop (PLL) that allows a range of clock frequencies for flexibility in the system. The CONV_START input and DATA_READY output signals synchronize the ADC with an external ramp for applications such as FSK-FMCW radar. The ADAR7251 supports serial and parallel interfaces at programmable sample rates from 300 kSPS to 1.8 MSPS, as well as easy connections to digital signal processors (DSPs) and microcontroller units (MCUs) in the system. Automotive LSR systems Data acquisition systems Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAR7251 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 PLL Control Register ................................................................. 38 Applications ....................................................................................... 1 PLL Status Register..................................................................... 38 General Description ......................................................................... 1 Master Enable Switch Register ................................................. 39 Revision History ............................................................................... 3 ADC Enable Register ................................................................. 39 Functional Block Diagram .............................................................. 4 Power Enable Register ............................................................... 40 Specifications..................................................................................... 5 Clear the ASIL errors Register .................................................. 41 Analog Channel ............................................................................ 5 Selects Which Errors to Mask Register ................................... 42 Digital Input/Output .................................................................... 6 ASIL Error Flag Register ........................................................... 43 Power Supply ................................................................................. 7 ASIL Error Code Register ......................................................... 43 Digital Filter .................................................................................. 8 CRC Value, Bits[7:0] Register ................................................... 44 SPI Port Timing ............................................................................ 8 CRC Value Register .................................................................... 44 Serial/Peripheral Parallel Interface (PPI) Port Timing............ 8 Absolute Maximum Ratings.......................................................... 11 Start Calculating the CRC Value of the Register Map Content Register ........................................................................................ 45 Thermal Resistance .................................................................... 11 Register Map CRC Calculation Done Register ...................... 45 ESD Caution ................................................................................ 11 Register Map CRC Value, Bits[7:0] Register ........................... 45 Pin Configuration and Function Descriptions ........................... 12 Register Map CRC Value, Bits[15:8] Register......................... 46 Typical Performance Characteristics ........................................... 14 Low Noise Amplifier Gain Control Register .......................... 46 Terminology .................................................................................... 17 Programmable Gain Amplifier Gain Control Register ......... 47 Theory of Operation ...................................................................... 18 Signal Path for ADC 1 Through ADC 4 Register .................. 48 Low Speed Ramp Radar Analog Front End ............................ 18 Decimator Rate Control Register ............................................. 49 Main Channel Overview ........................................................... 18 High Pass Filter Control Register ............................................. 50 Σ-Δ Modulation and Digital Filtering ..................................... 18 DAQ Mode Control Register .................................................... 51 Differential Input Configuration .............................................. 19 Decimator Truncate Control Register ..................................... 52 Equalizer (EQ) ............................................................................ 19 Serial Output Port Control Register ........................................ 52 Using LNA/PGA, EQ, or the Input Capacitor ........................ 20 Parallel Port Control Register ................................................... 53 Reference ..................................................................................... 20 ADC Digital Output Mode Register ........................................ 54 Auxiliary ADC ............................................................................ 20 Auxiliary ADC Read Value Registers ...................................... 54 Power Supply ............................................................................... 21 Auxiliary ADC Sample Rate Selection Register ..................... 55 LDO .............................................................................................. 21 Auxiliary ADC Mode Register ................................................. 56 Clock Requirements ................................................................... 21 MPx Pin Modes Registers ......................................................... 56 Crystal Oscillator ........................................................................ 21 MP Write Value Registers.......................................................... 58 PLL ............................................................................................... 21 MP Read Value Registers........................................................... 58 GPIO ............................................................................................ 23 SPI_CLK Pin Drive Strength and Slew Rate Register ........... 59 ADC Data Port ........................................................................... 23 SPI_MISO Pin Drive Strength and Slew Rate Register ......... 60 PCB Layout Guidelines .................................................................. 33 SPI_SS Pin Drive Strength and Slew Rate Register ............... 60 Register Summary .......................................................................... 34 SPI_MOSI Pin Drive Strength and Slew Rate Register ......... 61 Register Details ............................................................................... 37 ADDR15 Pin Drive Strength and Slew Rate Register ........... 62 Clock Control Register .............................................................. 37 FAULT Pin Drive Strength and Slew Rate Register ............... 62 PLL Denominator Register ....................................................... 37 FS_ADC Pin Drive Strength and Slew Rate Register ............ 63 PLL Numerator Register ............................................................ 37 CONV_START Pin Drive Strength and Slew Rate Register ..... 64 Rev. 0 | Page 2 of 72 Data Sheet ADAR7251 SCLK_ADC Pin Drive Strength and Slew Rate Register .......64 CRC Enable/Disable Register .................................................... 70 ADC_DOUTx Pins Drive Strength and Slew Rate Registers ....65 Typical Application Circuit ............................................................ 71 DATA_READY Pin Drive Strength and Slew Rate Register ......68 Outline Dimensions ........................................................................ 72 XTAL Enable and Drive Register ..............................................68 Ordering Guide ........................................................................... 72 ADC Test Register .......................................................................69 Automotive Products .................................................................. 72 Digital Filter Sync Enable Register ...........................................70 REVISION HISTORY 11/14—Revision 0: Initial Version Rev. 0 | Page 3 of 72 ADAR7251 Data Sheet IOVDD1, IOVDD2 DVDD1, DVDD2 REGOUT_DIGITAL AVDD1, AVDD2, AVDD3 PLLVDD FUNCTIONAL BLOCK DIAGRAM AVDD CM AIN1P AIN1N BIAS GENERATOR PLLVDD AVDD DVDD AVDD REFERENCE LNA AIN2P AIN2N LNA AIN3P AIN3N LNA AIN4P AIN4N LNA EQ PGA EQ PGA EQ PGA ADC_DOUT0 VOLTAGE REGULATOR CH1 DIGITAL FILTER Σ-∆ ADC CH2 CH3 ADC_DOUT1 Σ-∆ ADC DIGITAL FILTER Σ-∆ ADC DIGITAL FILTER Σ-∆ ADC DIGITAL FILTER ADC_DOUT2/GPIO1 DECIMATORS ADC BIASP BIASN ADC_DOUT3/GPIO2 ADC_DOUT4 ADC_DOUT5 DIGITAL INTERFACE ADDR15/ADC_DOUT6 FS_ADC/ADC_DOUT7 SCLK_ADC CONV_START DATA_READY FAULT EQ PGA CH4 AUX ADC SPI_MISO SPI_MOSI SPI_CLK SPI_SS AVDD DVDD PLLVDD RESET OSCILLATOR POR RESET, PWDN PLL 12357-001 AGND1, AGND2 DGND1, DGND2, DGND3 PLLFILT PLLGND XOUT ADAR7251 XIN/MCLKIN AUXIN1 AUXIN2 MUX SPI CONTROL Figure 1. Rev. 0 | Page 4 of 72 Data Sheet ADAR7251 SPECIFICATIONS ANALOG CHANNEL AVDDx = 3.3 V, DVDDx = 1.8 V, IOVDDx = 3.3 V, VREF = 1.5 V internal/external reference, fSAMPLE = 1.2 MSPS, TAMB = −40°C to +125°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Input Referred Noise Spectral Density Frequency = 100 Hz Test Conditions/Comments Min Typ Max Unit Gain = 9 dB Gain = 15 dB Gain = 21 dB Gain = 27 dB Gain = 33 dB Gain = 39 dB Gain = 45 dB 44.7 23.6 15 12 11.3 10.9 10.8 nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz Gain = 9 dB Gain = 15 dB Gain = 21 dB Gain = 27 dB Gain = 33 dB Gain = 39 dB Gain = 45 dB 16 8.7 5.4 4.3 4 3.86 3.83 nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz Gain = 9 dB Gain = 15 dB Gain = 21 dB Gain = 27 dB Gain = 33 dB Gain = 39 dB Gain = 45 dB Setting 1 EQ00 Setting 2 EQ01 Setting 3 EQ10 Setting 4 EQ11 No input signal and reference to 0 dBFS At −3 dBFS input, 100 kHz At −3 dBFS input, 100 kHz At −1 dBFS input, 100 kHz At 50 kHz, −3 dBFS input 9.7 5.2 3.3 2.67 2.5 2.44 2.4 54 45 37 32 94 82 −80 −77 −94 0 0.04 −72 65 nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz nV/√Hz kHz kHz kHz kHz dB dB dB dB dB dB Degrees dBFS dB Frequency = 1 kHz Frequency = 100 kHz Equalizer Corner Frequency Signal to Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion Plus Noise (THD + N) Channel to Channel Crosstalk Interchannel Gain Mismatch Interchannel Phase Mismatch DC Offset Power Supply Rejection 88 68 −0.5 Ripple = 100 mV rms on AVDDx at 1 kHz Rev. 0 | Page 5 of 72 −66 −62 −89 +0.5 ADAR7251 Data Sheet Parameter ANALOG INPUT Full-Scale Differential Voltage Test Conditions/Comments Gain = 0 dB (LNA and PGA bypass) Gain = 9 dB Gain = 15 dB Gain = 21 dB Gain = 27 dB Gain = 33 dB Gain = 39 dB Gain = 45 dB At 1 kHz Common-Mode Rejection Ratio (CMRR) Gain Error Input Resistance Typ Max 5.6 1.987 0.995 0.498 249 124 62 31 68 −0.8 Single-ended Differential At the CM pin VOLTAGE REFERENCE IN/OUT (VREF) CONVERSION SAMPLE RATE Sample Rate Input Signal Bandwidth PLL Input Frequency Output Frequency (Internal) Lock Time LDO REGOUT_DIGITAL Output Voltage Line Regulation Load Regulation AUXILIARY ADC Full-Scale Input Sample Rate Resolution INL DNL Input Resistance1 1 Min +0.8 2860 5720 1.5 0.3 150 1.2 600 16 2.97 1.8 3.3 1 MSPS kHz 54 MHz MHz ms 3.63 3.3 112.5 Switched capacitor input at a switching frequency of 112.5 kHz V p-p V p-p V p-p V p-p mV p-p mV p-p mV p-p mV p-p dB dB Ω Ω V 1.8 900 115.2 1 Used for internal digital core only AVDDx as an input Used for internal digital core only Unit 450 8 0.5 1 1.2 V V % V p-p kHz bits LSB LSB MΩ From simulation. DIGITAL INPUT/OUTPUT DVDDx = 1.8 V, IOVDDx = 3.3 V, CLOAD = 22 pF. Table 2. Parameter INPUT VOLTAGE High Level Low Level OUTPUT VOLTAGE High Level Low Level INPUT CAPACITANCE INPUT LEAKAGE CURRENT Symbol Test Conditions/Comments VIH VIL VOH VOL Min Typ Max Unit 0.3 × IOVDDx V V 0.4 5 ±10 V V pF μA 0.7 × IOVDDx IOH = 1 mA IOL = 1 mA IOVDDx − 0.60 Rev. 0 | Page 6 of 72 Data Sheet ADAR7251 POWER SUPPLY AVDDx = 3.3 V, DVDDx = 1.8 V, IOVDDx = 3.3 V, fS = 1.2 MHz (master mode), PLL enabled with 19.2 MHz master clock input, −3 dBFS, 100 kHz input on all channels, unless otherwise noted. Table 3. Parameter DVDD Current Normal Operation Power-Down AVDD Current Normal Operation Power-Down IOVDD Current Normal Operation Power-Down POWER DISSIPATION Normal Operation Power-Down, All Supplies Test Conditions/Comments On-chip LDO Min 1.62 Typ 1.8 2.97 32 80 3.3 2.97 115 87 1.1 1.1 3.3 DVDDx external at fS = 1.2 MHz Standby without master clock 4-channel ADC, DVDDx internal, fS = 1.2 MHz Power save mode RESET/PWDN pin held low without master clock RESET/PWDN pin held low with master clock Max 1.98 Unit V 3.6 mA μA V 3.6 mA mA mA mA V Input master clock = 19.2 MHz 4-channel ADC; serial mode, 2 channels per data line fS = 1.2 MHz fS = 900 kHz fS = 600 kHz fS = 300 kHz 4-channel ADC; parallel mode, byte wide format fS = 1.8 MHz fS = 1.2 MHz fS = 900 kHz fS = 600 kHz fS = 300 kHz RESET/PWDN pin held low without master clock RESET/PWDN pin held low with master clock 4 3.4 2.7 2 mA mA mA mA 2.8 2.3 2 1.7 1.3 335 360 mA mA mA mA mA μA μA Input master clock = 19.2 MHz DVDDx internal, 4-channel ADC at fS = 1.2 MHz DVDDx external, 4-channel ADC at fS = 1.2 MHz RESET/PWDN pin held low with master clock 400 294 5 mW mW mW Rev. 0 | Page 7 of 72 ADAR7251 Data Sheet DIGITAL FILTER Table 4. Parameter ADC DECIMATION FILTER At fS = 1.2 MHz, Decimation Ratio = 48 Pass Band Pass-Band Droop Stop Band Stop-Band Attenuation Group Delay High-Pass Filter Corner Frequency Attenuation Mode At fS =1.2 MHz, decimation ratio = 48 Factor Min −0.1 dB corner At 600 kHz 0.166 × fS Typ Unit 200 −1.4 800 70 95 0.666 × fS −3 dB, programmable in eight steps See Figure 24 in the Typical Performance Characteristics section Max kHz dB kHz dB μs 0.729 93.3 Hz SPI PORT TIMING DVDDx = 1.8 V, IOVDDx = 3.3 V, C LOAD = 22 pF, IOUT = ±1 mA. Table 5. Parameter SPI PORT tCCPH tCCPL fSPI_CLK tCDS tCDH tCLS tCLH tCLPH tCDH tCOD tCOTS Description See Figure 2 SPI_SCLK high SPI_SCLK low SPI_SCLK frequency SPI_MOSI setup to SPI_SCLK rising SPI_MOSI hold from SPI_SCLK rising SPI_SS setup to SPI_SCLK rising SPI_SS hold from SPI_SCLK rising SPI_SS high SPI_MISO hold from SPI_SCLK rising SPI_MISO delay from SPI_SCLK falling SPI_MISO tristate from SPI_SS rising Min Limit at Typ Max Unit 50 50 ns ns MHz ns ns ns ns ns ns ns ns 10 10 10 10 40 10 30 30 30 SERIAL/PERIPHERAL PARALLEL INTERFACE (PPI) PORT TIMING DVDDx = 1.8 V, IOVDDx = 3.3 V, C LOAD = 22 pF, IOUT = ±1 mA. Table 6. Parameter INPUT MASTER CLOCK (MCLKIN) Duty Cycle fMCLKIN RESET Reset Pulse, tRESET Description Min MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS MCLKIN frequency, PLL in MCLK mode 40 16 RESET/PWDN held low 15 PLL Lock Time Limit at Typ Max Unit 60 54 % MHz ns 1 Rev. 0 | Page 8 of 72 ms Data Sheet ADAR7251 Parameter ADC SERIAL PORT MASTER MODE tSCKH tSCKL tDS tDH tDD tFSH tFSS ADC SERIAL PORT SLAVE MODE tSCKH tSCKL tDS tDH tDD tFSH tFSS PARALLEL MODE, BYTE WIDE FORMAT tSCKH tSCKL tDS tDH tDD tCSDR DATA ACQUISITION (DAQ) MODE tDRH tCSDR Description See Figure 3 Min SCLK_ADC high, slave mode SCLK_ADC low, slave mode ADC_DOUTx setup to SCLK_ADC rising, slave mode ADC_DOUTx hold from SCLK_ADC rising, slave mode ADC_DOUTx delay from SCLK_ADC falling FS_ADC hold from SCLK_ADC rising FS_ADC setup from SCLK_ADC falling See Figure 4 SCLK_ADC high, slave mode SCLK_ADC low, slave mode ADC_DOUTx valid to SCLK_ADC rising, slave mode ADC_DOUTx hold from SCLK_ADC rising, slave mode ADC_DOUTx delay from SCLK_ADC falling FS_ADC hold from SCLK_ADC rising FS_ADC setup from SCLK_ADC falling See Figure 5; if usingCONV_START, see Figure 6 for the CONV_START to DATA_READY timing relation SCLK_ADC high, master mode SCLK_ADC low, master mode ADC_DOUTx setup to SCLK_ADC rising, master mode ADC_DOUTx hold from SCLK_ADC rising, master mode ADC_DOUTx delay from SCLK_ADC falling for left justified (LJ) mode For I2S mode, add one SCLK_ADC period to the tDD of LJ mode CONV_START falling to DATA_READY rising 10 10 10 5 Limit at Typ Max Unit 18 18 1 ns ns ns ns ns ns ns 2 1 1 ns ns ns ns ns ns ns 6 ns ns ns ns ns 1.215 μs 0.44 1.215 1.8 2.43 μs μs μs μs 7 7 11 11 28 28 7 5 CONV_START falling to DATA_READY rising, see Figure 6 CONV_START rising to DATA_READY falling DAQ16 mode (16 acquisition clock cycles) DAQ24 mode (24 acquisition clock cycles) DAQ32 mode (32 acquisition clock cycles) Timing Diagrams tCLH tCLS tCCPL tCCPH SPI_SS tCLPH SPI_SCLK SPI_MOSI tCDH SPI_MISO tCOD Figure 2. SPI Port Timing Rev. 0 | Page 9 of 72 tCOTS 12357-002 tCDH tCDS ADAR7251 Data Sheet tFSS FS_ADC tFSH tSCKH SCLK_ADC tSCKL tDS ADC_DOUTx LEFT JUSTIFIED MODE 16-BIT CLOCKS PER CHANNEL (16-BIT DATA) tDH tDD MSB MSB – 1 tDH tDS tDD ADC_DOUTx I2S MODE 12357-004 MSB Figure 3. Serial Port Timing Master Mode tFSS FS_ADC tFSH tSCKH SCLK_ADC tSCKL tDS ADC_DOUTx LEFT JUSTIFIED MODE 16-BIT CLOCKS PER CHANNEL (16-BIT DATA) tDH tDD MSB MSB – 1 tDH tDS ADC_DOUTx I2S MODE MSB 12357-003 tDD Figure 4. Serial Output Port Timing Slave Mode DATA_READY tDS tSCKH SCLK_ADC tSCKL tDH MSB LJ: ADC_DOUTx 12357-005 tDD MSB I2S: ADC_DOUTx tDD Figure 5. PPI Timing Master Mode tCSDR tDRH 12357-006 CONV_START DATA_READY Figure 6. CONV_START to DATA_READY Timing Rev. 0 | Page 10 of 72 Data Sheet ADAR7251 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter AVDDx to AGNDx, DGNDx DVDDx to AGNDx, DGNDx IOVDDx to AGNDx, DGNDx AGNDx to DGNDx Analog Input Voltage to AGNDx Digital Input Voltage to DGNDx Digital Output Voltage to DGNDx Input Current to Any Pin Except Supplies Operating Temperature Range (Ambient) Junction Temperature Range Storage Temperature Range RoHS-Compliant Temperature Soldering Reflow Rating −0.3 V to +3.63 V −0.3 V to +1.98 V −0.3 V to +3.63 V −0.3 V to +0.3 V −0.3 V to +3.63 V −0.3 V to +3.63 V −0.3 V to +3.63 V ±10 mA −40°C to +125°C −40°C to + 150°C −65°C to +150°C 260°C θJA represents junction-to-ambient thermal resistance, and θJC represents the junction-to-case thermal resistance. All characteristics are for a standard JEDEC board per JESD51. Table 8. Thermal Resistance Package Type 48-Lead LFCSP_SS 1 JEDEC 2S2P standard board. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 11 of 72 θJA1 25 θJC1 1 Unit °C/W ADAR7251 Data Sheet 48 47 46 45 44 43 42 41 40 39 38 37 AVDD3 AIN2N AIN2P AIN1N AIN1P RESET/PWDN FAULT SPI_SS SPI_CLK SPI_MOSI SPI_MISO IOVDD2 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADAR7251 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 DGND3 CONV_START SCLK_ADC FS_ADC/ADC_DOUT7 ADDR15/ADC_DOUT6 ADC_DOUT5 ADC_DOUT4 ADC_DOUT3/GPIO2 ADC_DOUT2/GPIO1 ADC_DOUT1 ADC_DOUT0 IOVDD1 NOTES 1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE SOLDERED TO THE GROUND PLANE ON THE BOARD FOR POWER DISSIPATION. 12357-007 PLLGND PLLFILT PLLVDD XIN/MCLKIN XOUT AVDD2 REGOUT_DIGITAL DGND1 DVDD1 DATA_READY DGND2 DVDD2 13 14 15 16 17 18 19 20 21 22 23 24 AGND1 1 AIN3P 2 AIN3N 3 AIN4P 4 AIN4N 5 AUXIN1 6 AUXIN2 7 CM 8 AGND2 9 BIASN 10 BIASP 11 AVDD1 12 Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic EPAD Type1 1 2 3 4 5 6 7 8 AGND12 AIN3P AIN3N AIN4P AIN4N AUXIN1 AUXIN2 CM PWR AIN AIN AIN AIN AIN AIN AIO 9 10 11 12 13 14 15 AGND22 BIASN BIASP AVDD1 PLLGND PLLFILT PLLVDD PWR AOUT AOUT PWR PWR AIN PWR 16 XIN/MCLKIN AIN 17 18 19 XOUT AVDD2 REGOUT_DIGITAL AOUT PWR PWR 20 DGND13 PWR Description Exposed Pad. The exposed pad on the bottom of the package must be soldered to the ground plane on the board for power dissipation. Analog Ground. This pin is the ground reference point for all analog blocks in the ADAR7251. Noninverting Input to Differential Analog Channel 3. Inverting Input to Differential Analog Channel 3. Noninverting Input to Differential Analog Channel 4. Inverting Input to Differential Analog Channel 4. Auxiliary ADC Analog Input 1. Single-ended analog input channel. Auxiliary ADC Analog Input 2. Single-ended analog input channel. ADC Reference Output. Connect a 10 μF capacitor in parallel with a 100 nF capacitor from this pin to AGNDx. Analog Ground. This pin is the ground reference point for all analog blocks in the ADAR7251. Internal Bias Generator. Decouple to AGNDx using a 0.47 μF capacitor. Internal Bias Generator. Decouple to AVDDx using a 0.47 μF capacitor. Analog Supply Voltage, 3.3 V. Decouple this supply pin to AGNDx. See Figure 60. Analog Ground for PLL. Connect to a ground plane directly on the board. Filter Components Connection for PLL. See Figure 60. Analog Supply for Analog PLL, 3.3 V. Decouple to the PLLGND pin (Pin13) using a 0.1 μF multilayer ceramic capacitor (MLCC). Connect to AVDDx or an external 3.3 V source. It is recommended to add the filter for a clean 3.3 V source and for good PLL performance. Internal Oscillator Input/Clock Input. If using an external crystal, connect it between the XIN and XOUT pins. If not using a crystal, a single-ended clock must be provided at the MCLKIN pin. The ADAR7251 accepts a clock frequency range of 16 MHz to 54 MHz. Internal Oscillator Output Connection for External Crystal. Analog Supply Voltage, 3.3 V. Decouple this supply pin to AGNDx. See Figure 60. LDO Regulator Output for Internal Digital Core (1.8 V, Typical). Decouple to DGNDx. See Figure 60. Connect REGOUT_DIGITAL to the DVDDx pins if using the internal regulator to supplythe 1.8 V to the digital core. Digital Ground. This pin is the ground reference point for the digital circuitry on the ADAR7251. Rev. 0 | Page 12 of 72 Data Sheet ADAR7251 Pin No. 21 Mnemonic DVDD1 Type1 PWR 22 DATA_READY DOUT 23 24 DGND23 DVDD2 PWR PWR 25 IOVDD1 PWR 26 ADC_DOUT0 DOUT 27 ADC_DOUT1 DOUT 28 ADC_DOUT2/GPIO1 DOUT 29 ADC_DOUT3/GPIO2 DOUT 30 ADC_DOUT4 DIO 31 ADC_DOUT5 DIO 32 ADDR15/ ADC_DOUT6 DIO 33 DIO 34 FS_ADC/ ADC_DOUT7 SCLK_ADC DIO 35 CONV_START DIN 36 37 DGND33 IOVDD2 PWR PWR 38 39 40 41 SPI_MISO SPI_MOSI SPI_CLK SPI_SS DOUT DIN DIN DIN 42 FAULT DOUT 43 RESET/PWDN DIN 44 45 46 47 48 AIN1P AIN1N AIN2P AIN2N AVDD3 AIN AIN AIN AIN PWR Description Digital Core Power Supply Input. Connect decoupling capacitors between the DVDDx and DGNDx pins. See Figure 60. The voltage on this pin is 1.8 V. This pin can be connected to REGOUT_DIGITAL (Pin 19), or to the external 1.8 V source if the internal LDO is not used. ADC Conversion Data Ready Output. Connect to the DSP general-purpose input/output (GPIO) in the system. Digital Ground. This pin is the ground reference point for digital circuitry on the ADAR7251. Digital Core Power Supply Input. Connect decoupling capacitors between the DVDDx and DGNDx pins. See Figure 60. The voltage on this pin is 1.8 V. This pin can be connected to REGOUT_DIGITAL (Pin 19), or to the external 1.8 V source if the internal LDO is not used. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Connect decoupling capacitors between the IOVDDx and DGNDx pins. See Figure 60. ADC Data Output (Serial Mode) or ADC Data Output Bit 0 and Bit 8 (PPI Mode). Refer to the ADC Serial Mode and ADC PPI (Byte Wide Mode) sections for function information. ADC Data Output (Serial Mode) or ADC Data Output Bit 1/9 (PPI Mode). Refer to the ADC Serial Mode and ADC PPI (Byte Wide Mode) sections for function information. ADC Data Output Bit 2 and Bit 10 (PPI Mode)/General-Purpose Input/Output 1. Refer to the ADC Serial Mode section for function information. ADC Data Output Bit 3 and Bit 11 (PPI Mode)/General-Purpose Input/Output 2. Refer to the ADC PPI (Byte Wide Mode) section for function information. ADC Data Output Bit 4 and Bit 12 (PPI Mode). Refer to the ADC PPI (Byte Wide Mode) section for function information. ADC Data Output Bit 5 and Bit 13 (PPI Mode). Refer to the ADC PPI (Byte Wide Mode) section for function information. Device Address Setting for the SPI Control Interface/ADC Data Output Bit 6 and Bit 14 in PPI mode. This pin sets Bit 1 of the SPI device address. Connect to either DGNDx or IOVDDx as desired using a 10 kΩ pull-down or pull-up resistor. Refer to the ADC PPI (Byte Wide Mode) section for function information. Active Low Frame Synchronization Signal for Default ADC Data (Serial Mode)/ADC Data Output Bit 7 and Bit 15 (PPI Mode). Refer to the ADC PPI (Byte Wide Mode) section for function information. Serial Bit Clock for the ADC Data Output (Serial Mode and PPI Mode). This pin is an input in slave mode or is an output in master mode. ADC Conversion Start in DAQ/PPI/Serial Mode (Active Low). An active low signal initiates an ADC conversion. See the Theory of Operation section for further details. Digital Ground. This pin is the ground reference point for digital circuitry on the ADAR7251. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. Connect decoupling capacitors between the IOVDDx and DGNDx pins. See Figure 60. SPI Control Interface Slave Data Output. SPI Control Interface Slave Data Input. SPI Control Interface Serial clock Input. SPI Control Interface Slave Select (Active Low Input). Connect an external 10 kΩ pull-up resistor to IOVDDx. Digital Output. This pin becomes active under fault condition. Connect an external 10 kΩ pull-up resistor to IOVDDx. This pin can be used as an interrupt input to the microcontroller or DSP in case of faults. Active Low Reset Input/Power-Down. The ADAR7251 requires an external reset signal to hold the RESET input low until AVDDx is within the specified operating range. When held low, this pin places the ADAR7251 into power-down mode. Noninverting Input to Differential Analog Channel 1. Inverting Input to Differential Analog Channel 1. Noninverting Input to Differential Analog Channel 2. Inverting Input to Differential Analog Channel 2. Analog Supply Voltage. Decouple this supply pin to AGNDx. 1 PWR is power supply or ground pin, AIN is analog input, AIO is analog input/output, AOUT is analog output, DIN is digital input, DOUT is digital output, and DIO is digital input/output. 2 All the AGNDx pins (AGND1 and AGND2) are shorted internally and recommended to be connected to a single ground plane on the board. Refer to the PCB Layout Guidelines section for details. 3 All the DGNDx pins (DGND1, DGND2, and DGND3) are shorted internally and recommended to be connected to a single ground plane on the board. Refer to the PCB Layout Guidelines section for details. Rev. 0 | Page 13 of 72 ADAR7251 Data Sheet 0 –20 –20 –40 –40 –60 –80 –100 –100 –120 –140 –140 90 60 FREQUENCY (kHz) 120 –160 150 –20 –20 –40 –40 AMPLITUDEF (dBFS) 0 –60 –80 –100 12357-101 –140 180 –160 225 Figure 9. FFT with −60 dBFS, 100 kHz Input at fS = 450 kHz –20 –20 –40 –40 AMPLITUDEF (dBFS) 0 –60 –80 –100 12357-102 –140 240 480 600 –100 –140 180 120 FREQUENCY (kHz) 360 240 FREQUENCY (kHz) –80 –120 60 120 –60 –120 0 0 Figure 12. FFT with −60 dBFS, 100 kHz Input at fS = 1.2 MHz 0 –160 450 –100 –140 135 90 FREQUENCY (kHz) 360 –80 –120 45 270 180 FREQUENCY (kHz) –60 –120 0 90 Figure 11. FFT with −60 dBFS, 100 kHz Input at fS = 900 kHz 0 –160 0 12357-104 30 300 Figure 10. FFT with −60 dBFS, 100 kHz Input at fS = 600 kHz –160 12357-105 0 Figure 8. FFT with −60 dBFS, 100 kHz Input at fS = 300 kHz AMPLITUDEF (dBFS) –80 –120 –160 AMPLITUDEF (dBFS) –60 12357-103 AMPLITUDEF (dBFS) 0 12357-100 AMPLITUDEF (dBFS) TYPICAL PERFORMANCE CHARACTERISTICS 0 180 540 360 FREQUENCY (kHz) 720 Figure 13. FFT with −60 dBFS, 100 kHz Input at fS = 1.8 MHz Rev. 0 | Page 14 of 72 900 ADAR7251 0 –20 –20 –40 –40 –60 –80 –100 –100 –120 –140 –140 228 152 FREQUENCY (kHz) 304 –160 380 –20 –20 –40 –40 AMPLITUDEF (dBFS) 0 –60 –80 –100 12357-111 –140 152 –160 190 Figure 15. FFT with −60 dBFS, 100 kHz Input, DAQ24, at fS = 380 kHz –20 –20 –40 –40 AMPLITUDEF (dBFS) 0 –60 –80 –100 12357-109 –140 80 80 100 –100 –140 60 40 FREQUENCY (kHz) 60 40 FREQUENCY (kHz) –80 –120 20 20 –60 –120 0 0 Figure 18. FFT with −1 dBFS, 10 kHz Input, DAQ16, at fS = 200 kHz 0 –160 100 –100 –140 114 76 FREQUENCY (kHz) 80 –80 –120 38 60 40 FREQUENCY (kHz) –60 –120 0 20 Figure 17. FFT with −60 dBFS, 10 kHz Input, DAQ16, at fS = 200 kHz 0 –160 0 12357-108 76 100 –160 12357-106 0 Figure 14. FFT with −60 dBFS, 100 kHz Input, DAQ16, at fS = 758 kHz AMPLITUDEF (dBFS) –80 –120 –160 AMPLITUDEF (dBFS) –60 12357-107 AMPLITUDEF (dBFS) 0 12357-110 AMPLITUDEF (dBFS) Data Sheet 0 120 360 240 FREQUENCY (kHz) 480 Figure 19. FFT with −1 dBFS, 100 kHz Input, at fS = 1.2 MHz Figure 16. FFT with −60 dBFS, 10 kHz Input, DAQ32, at fS = 200 kHz Rev. 0 | Page 15 of 72 600 ADAR7251 Data Sheet –10 0 –0.5 –15 MAGNITUDE (dB) NO EQ_CAP_CTRL EQ_CAP_CTRL = 00 EQ_CAP_CTRL = 01 EQ_CAP_CTRL = 10 EQ_CAP_CTRL = 11 –25 –30 –1.5 –2.0 –2.5 –3.0 –3.5 –4.5 12357-014 –40 1 10 FREQUENCY (kHz) 10k 100 Figure 23. ADC Digital Filter Pass Band at fS = 1.2 MHz 50 LNA + PGA GAIN = 39dB 35 LNA + PGA GAIN = 33dB 30 LNA + PGA GAIN = 27dB 25 LNA + PGA GAIN = 21dB 20 LNA + PGA GAIN = 15dB 15 –10 –15 –20 LNA + PGA GAIN = 9dB 10 –25 12357-015 5 0 1 10 10 100 Figure 21. LNA + PGA Gain 0 –40 –60 –80 –100 –120 –140 –160 12357-115 –180 –200 100k 1M 1k 10k 100k Figure 24. ADC High-Pass Filter Frequency Response –20 10k 100 FREQUENCY (Hz) FREQUENCY (kHz) MAGNITUDE (dB) 93.300Hz 46.600Hz 23.300Hz 11.700Hz 5.830Hz 2.910Hz 1.460Hz 0.729Hz –5 MAGNITUDE (dB) AMPLITUDE (dB) 0 LNA + PGA GAIN = 45dB 40 100k FREQUENCY (Hz) Figure 20. EQ 45 12357-116 –4.0 –35 12357-117 AMPLITUDE (dB) –1.0 –20 10M FREQUENCY (Hz) Figure 22. Frequency Response, ADC Digital Filter at fS = 1.2 MHz Rev. 0 | Page 16 of 72 Data Sheet ADAR7251 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the ADAR7251, the endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the ADAR7251, THD is defined as Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error Offset error is the deviation of the first code transition (00…000) to (00…001) from the ideal (such as ground + 0.5 LSB). Gain Error For the ADAR7251, gain error is the deviation of the last code transition (111…110) to (111…111) from the ideal (such as VREF – 1.5 LSB) after the offset error is adjusted out. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels (dB). THD dB 20 log V2 2 V3 2 V 4 2 V5 2 V6 2 V1 Dynamic Range (DNR) THD + N is measured in dB with an input level of −60 dBFS (−60 dB relative to the full-scale input). Then, 60 dB is added to the measured THD + N value and is expressed in decibels. For example, when measuring 36 dB THD + N with a −60 dBFS input, DNR is 60 + 36 = 96 dB. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Rev. 0 | Page 17 of 72 ADAR7251 Data Sheet THEORY OF OPERATION The total channel noise of the ADAR7251 depends on the bandwidth specification and the selected analog input range. The data rate at the output of the ADAR7251 can be reduced further to meet specific application requirements. The continuous time modulator removes the need for a high order antialias filter at the input to the ADAR7251. The continuous time Σ-Δ modulator used within the ADAR7251 has inherent antialiasing due to oversampling. The device uses 48× oversampling. This relaxes the requirement of filtering required at the input of the ADC. Typically, a single pole passive resistor capacitor (RC) filter is sufficient. LOW SPEED RAMP RADAR ANALOG FRONT END The most common application for the ADAR7251 is low speed ramp, frequency modulated, continuous wave, or frequency shift keying radar (LSR-FMCW or FSK-FMCW). Figure 28 shows a typical block diagram of an LSR/FSK radar system for a 4-channel application. The signal chain may require up to eight channels, each including an LNA, a PGA, and a ∑-Δ ADC. All input channels on the ADAR7251 sample the input signals simultaneously. The ADAR7251 also delivers secondary features required by an LSR radar system: a 2-channel, auxiliary 8-bit ADC and two GPIOs. MAIN CHANNEL OVERVIEW The ADAR7251 features an on-chip, fully differential LNA and PGA to feed the Σ-Δ input pins, as well as a digital filter block to perform the required filtering on the Σ-Δ modulator output. Using this Σ-Δ conversion technique with added digital filtering, the analog input converts to an equivalent digital word. The ADAR7251 uses an internal 1.5 V reference voltage. fICLK/2 BAND OF INTEREST 12357-017 QUANTIZATION NOISE Figure 25. Σ-Δ ADC, Quantization Noise Σ-∆ MODULATION AND DIGITAL FILTERING fICLK/2 BAND OF INTEREST Figure 26. Σ-Δ ADC, Noise Shaping fICLK/2 BAND OF INTEREST Figure 27. Σ-Δ ADC, Digital Filter Cutoff Frequency RAMP GENERATOR MMIC PSU ×M VCO PA ADC PGA LNA LPF HPF ADC PGA LNA LPF HPF ADC PGA LNA LPF HPF ADC PGA LNA LPF HPF DATA PORT ANTENNA Figure 28. Radar System Overview Rev. 0 | Page 18 of 72 12357-016 CAN/ FLEXRAY ADAR7251 DSP 12357-019 DIGITAL FILTER CUTOFF FREQUENCY The digital filtering that follows the modulator removes the large out-of-band quantization noise (see Figure 27) while also reducing the data rate at the input of the filter to 1.2 MHz or less at the output of the filter, depending on the decimation rate used. MCU 12357-018 NOISE SHAPING The input waveform applied to the modulator is sampled, and an equivalent digital word is output to the digital filter at a rate equal to the modulator clock. The modulator is clocked by 48 × fS (57.6 MHz clock signal, fICLK, for fS =1.2 MHz). By employing oversampling, the quantization noise spreads across a wide bandwidth (see Figure 25). This means that the noise energy contained in the bandwidth of interest is reduced. To further reduce the quantization noise, a third-order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the signal band (see Figure 26). Data Sheet ADAR7251 DIFFERENTIAL INPUT CONFIGURATION Low-Pass Filter (LPF) The ADAR7251 main ADC input channel consists of an LNA, a PGA, a continuous time Σ-Δ ADC, and internal bias resistors that set the common-mode voltage on the input of the LNA. The PGA includes an equalizer (EQ) function that gains up low amplitude, high frequency signals. Typically, in an automotive radar application, the analog inputs of the ADAR7251 connect directly to the mixer output (See Figure 29). If additional external filtering is required, the external C1, C2, and C3 capacitors can be used. These capacitors, together with the R1, R2, and the mixer output impedance, create an external filter that removes dc components and high frequency noise from the ADC inputs. The low-pass filter is formed by adding the capacitor across the differential input pins. The value of the source resistance driving the ADC dictates the corner frequency of the filter. Use the following equation to set the corner frequency to the desired frequency: TYPICAL ONE INPUT CHANNEL MIXER RM AVDDx RM R1 C1 AINxP C3 GAIN + MUX Σ-∆ ADC AINxN 12357-020 C2 R2 Figure 29. Typical Differential Input Channel Configuration A monolithic microwave integrated circuit (MMIC) mixer output impedance, RM, with Capacitor C3, forms a single-pole, low-pass filter that reduces high frequency spurs from the ADAR7251 inputs. Two capacitors, C1 and C2, with the ADAR7251 internal resistance of R1 and R2, produce a high-pass filter that removes dc components from the input signal. Each Σ-Δ ADC input is preceded by its own LNA and PGA gain stage. The variable gain settings ensure that the device is able to amplify signals from a variety of sources. The ADAR7251 offers the flexibility to choose the most appropriate gain setting to utilize the wide dynamic range of the device. The LNA stage gain can be set using Register 0x100 in 6 dB steps. The default gain is 6 dB. The PGA gain can be set independently using Register 0x101and has a default gain of 2.92 dB. The total LNA + PGA gain range is 36 dB. The gain settings, along with the ADAR7251 analog input range and channel noise specifications, are shown in the Specifications section (see Table 1). The default gain with LNA + PGA is 9 dB (2.8×), so that the full-scale differential input signal is 0.7 V rms. However, if a direct path is chosen and LNA + PGA is bypassed, the full-scale input signal to the ADC is 2 V rms differential. where RM (typical) is the source resistance of the MMIC output. Input Routing Figure 30 shows the typical 2-channel input block with multiplexers and input signal routing inside the ADAR7251. For simplicity, the connections in Figure 30 are shown as singleended, although they are differential. The input signal can be routed through LNA + PGA, LNA + PGA + EQ, or direct to the ADC. Register 0x102 is used to select the multiplexer at the input of the ADC. The inputs to the ADC can be swapped between adjacent channels, for example, Channel 1 can be sent to ADC2 and the Channel 2 input can be sent to ADC1. In addition, the auxiliary Input 1 and Input 2 can be sent directly to the ADC. In this case, AUXIN1 becomes a noninverting input, and AUXIN2 becomes an inverting input to form a differential pair. The default path is LNA + PGA + ADC. INPUT 1 INPUT MUX 1 LNA + PGA 1 CT ADC 1 EQ TEST INPUT (COMMON FOR ALL ADCs) MUX SELECT 1 MUX SELECT 2 INPUT 2 INPUT MUX 2 LNA + PGA 2 CT ADC 2 EQ 12357-021 ADAR7251 MMIC OUTPUT f3dB =1/(4 × π × RM × C3) Figure 30. Typical 2-Channel Input Block High-Pass Filter (HPF) EQUALIZER (EQ) The external input coupling capacitors form the passive first order, high-pass filter with the input impedance of the ADAR7251. This filter can also be used as a passive equalizer to boost the high frequency if desired. The corner frequency can be set to the desired frequency using the equation The output of LNA + PGA can be routed to an equalizer block. In LSR-FMCW radar systems, the distance between the radar and the object affects signal amplitude and frequency. Distant objects have a higher frequency and smaller amplitude. The EQ provides frequency dependent gain to boost these signals. This provides easier detection of distant objects in a system. Excellent noise performance relies on an ultralow noise LNA at the beginning of the signal chain and a high precision ADC architecture. Enable the EQ path in Register 0x102. The EQ is a first order, high-pass f3dB = 1/(2 × π × R1 × C1) where R1 = R2 (typical) is 2.86 kΩ and C2 = C1 (see Figure 29). Rev. 0 | Page 19 of 72 ADAR7251 Data Sheet USING LNA/PGA, EQ, OR THE INPUT CAPACITOR The input passive filter, along with LNA + PGA and EQ, can be used to achieve the desired frequency response in the system. See Figure 31, Figure 32, and Figure 33 for typical examples. Figure 31 shows the frequency response plot by varying the input coupling capacitor value, with the LNA + PGA gain and EQ fixed. 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 0.1 10µF 1µF 1nF 100pF 10 100 1k 10k 100k 1M FREQUENCY (Hz) 45dB GAIN 33dB GAIN 27dB GAIN 21dB GAIN 9dB GAIN 12357-113 AMPLITUDE (dB) Figure 31. Frequency Response, Coupling Capacitor Change 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 0.1 1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 33. Frequency Response, Coupling EQ Change REFERENCE AUXILIARY ADC 10nF 1 45dB GAIN 33dB GAIN 27dB GAIN 21dB GAIN The internal reference of the ADAR7251 is set to 1.5 V. This 1.5 V reference is available at the CM pin. Decouple the CM pin to the AGNDx pin using a 10 μF MLCC in parallel with a 100 nF MLCC. The 1.5 V reference is current-limited and not designed to drive an external load. Employ an external buffer circuit if this reference is required for use with external circuits. The internal reference voltage can be overdriven externally if required. 12357-112 AMPLITUDE (dB) Figure 32 shows the frequency response plot by varying the LNA + PGA gain, with the input coupling capacitor and EQ fixed. Figure 33 shows the frequency response plot by varying the EQ setting, with the input coupling capacitor and LNA + PGA gain fixed. 65 60 55 50 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 0.1 12357-114 AMPLITUDE (dB) type. The cutoff frequency can be either 32 kHz (default), 37 kHz, 45 kHz, or 54 kHz. Select the EQ cutoff frequency in EQ_CAP_CTRL, Bits[1:0] in Register 0x301 (see Figure 20 in the Typical Performance Characteristics section). 10 100 1k 10k 100k FREQUENCY (Hz) Figure 32. Frequency Response, Coupling Gain Change 1M The ADAR7251 includes a 2-channel, auxiliary successive approximation register (SAR) ADC for low frequency housekeeping functions in the system. These functions include dc voltage monitoring and temperature monitoring. The auxiliary ADC uses AVDDx as the power supply; therefore, the input range is limited from 0 V to AVDDx. The ADC uses a time multiplexing technique to sample the two auxiliary inputs. The multiplexer in the front of the ADC selects the input for the conversion. The sample rate of the ADC is selectable between 112.5 kHz and 450 kHz. The default sample rate is 112.5 kHz. When 2-channel operation is selected, the set sample rate is the effective sample rate. If only one channel is selected, the effective sample rate is double the set value. The resolution of the ADC is eight bits, and the ADC output is straight binary. The ADC output is stored in the internal registers, which are read via the SPI port. Register 0x200 stores the current conversion value for Input 1 and Input 2. In addition, Register 0x201 stores the last sample value. The ADC sample rate can be selected using Register 0x210, and Register 0x211 is used for selecting the input to the ADC. By default, the AUXINx pins are sampled. If the AUX_ADC_MODE bit (Bit 0 of Register 0x211) is set to 1, only one input is sampled at twice the sample rate. Because the auxiliary ADC is not continuous, care must be taken to ensure that the input signals are band limited and time multiplexed to prevent aliases. The auxiliary ADC inputs are switched capacitor type; therefore, the input impedance is capacitive during the sampling phase. The typical source impedance must be less than 1 kΩ to ensure that the input settles before the sample value is held internally. The Rev. 0 | Page 20 of 72 Data Sheet ADAR7251 source driving the ADC inputs must be able to drive at least 20 pF, excluding the parasitic capacitance on the board. ADAR7251 AUXIN1 R1 Y1 12357-022 C1 Figure 34. Auxiliary ADC C2 Figure 35. Crystal Oscillator The ADAR7251 uses three supplies: 3.3 V for AVDDx, 1.8 V for DVDDx, and 3.3 V for IOVDDx. AVDDx and IOVDDx must be supplied to the device, but the supply to the DVDDx pins can be either generated by an internal LDO, or provided externally by turning off the LDO. The AVDDx pins supply the analog core of the ADC, and the DVDDx pins supply the digital core of the ADC. The IOVDDx pins supply the digital input/output pins of the ADAR7251. Decouple all power supplies to ground with a 0.1 μF and a 10 μF X7R MLCC for best ADC performance. The device provides the exposed pad underneath, which must be connected to the ground plane with thermal vias. All the ground pins must be connected to the single ground plane on the PCB with the shortest possible path close to the respective pins. PLL The PLL provides the stable clock for the internal blocks. It uses the clock input at the XIN/MCLKIN pin as a reference to generate the core clock. Set the PLL for either integer or fractional mode. The PLL multipliers and dividers (X, R, M, and N) are programmed using Register 0x000 to Register 0x003. The PLL can accept input frequencies in the range of 16 MHz to 54 MHz, either directly from an external source, or using the crystal connected at the XIN/MCLKIN and XOUT pins. The PLL output frequency is fixed at 115.2 MHz. PLL XIN ÷X x (R + N ÷ M) INTERNAL PLL OUTPUT 115.2MHz ADC CLOCK ÷2 LDO 12357-024 POWER SUPPLY Figure 36. PLL Block Diagram The internal LDO generates the DVDDx voltage (1.8 V) required for the digital core. The LDO takes the AVDDx (3.3 V) supply and regulates down to 1.8 V. External decoupling capacitors are required to ensure clean power to the digital core. If using the internal 1.8 V supply for the digital core, the REGOUT_DIGITAL pin must be externally connected to the DVDDx pins. The 1 nF MLCC, in parallel with 0.1 μF and 10 μF capacitors, are recommended at the DVDDx pins to decouple the high frequency noise. The PLL requires an external loop filter, which is fixed (see Figure 37). For temperature sensitive applications, the loop filter components must be appropriate. The PLL loop filter capacitors must be NPO type for best temperature performance. PLLFILT 5.6nF 390pF 1kΩ CLOCK REQUIREMENTS To achieve the specified dynamic performance, use an external crystal at the XIN/MCLKIN and XOUT pins. Alternatively, provide the single-ended clock at the MCLKIN input via an MCU/DSP controller. The ADAR7251 features an internal PLL block that accepts the clock frequency in a range of 16 MHz to 54 MHz, via either the clock available in the system, or an external crystal. An external clock must be connected to the XIN/ MCLKIN pin and must be within the 0 V to 3.3 V p-p. PLLGND 12357-025 AUXIN2 XOUT 12357-023 XIN AUX ADC Figure 37. PLL Loop Filter Place the PLL loop filter close to the PLLFILT pin to prevent crosstalk from other sources on the board. In addition, take care to decouple the PLLVDD supply to the PLL. It is recommended that X7R MLCC or better dielectric MLCCs of 1 nF be added in parallel with 0.1 μF and 10 μF capacitors close to the PLLVDD pin. See the PCB Layout Guidelines section for details. CRYSTAL OSCILLATOR The external quartz crystal can be connected across the XIN and XOUT pins. When using the crystal, use Register 0x292 to enable the crystal oscillator block. The output of the crystal oscillator is an input to the PLL. The typical supported frequency range is 16 MHz to 54 MHz. Select load capacitors C1 and C2 for the crystal based on the recommendation of the crystal manufacturer. Determine the value of R1 based on the crystal current rating. Rev. 0 | Page 21 of 72 ADAR7251 Data Sheet Table 10 describes the registers used to set the PLL. Table 11. Required Writes for Register 0x0003, Integer Mode Table 10. Registers Used to Set the PLL Bits [15:11] [7:4] 1 Name PLL_INTEGER_DIV PLL_INPUT_PRESCALE PLL_TYPE 0 PLL_EN Register 0x000 Name CLK_CTRL 0x001 PLL_DEN 0x002 PLL_NUM 0x003 PLL_CTRL 0x005 PLL_LOCK Description Uses the PLL output for the internal master clock, or bypasses the PLL Sets the 16-bit denominator of the fractional part (M) Sets the 16-bit numerator of the fractional part (N) Sets the PLL mode, PLL enable, 4-bit integer multiplier (R), and 4-bit integer divider (X) Checks the PLL lock status The PLL can be used in either integer mode or fractional mode. Integer Mode Use integer mode when the input clock frequency is an integer multiple of the PLL output frequency, governed by the following equation: fPLL = (R/X) × fIN Function Sets the R value Sets the X value Sets the integer mode for the PLL Enables the PLL Required Setting 00110 0001 0 1 Set Register 0x003 to 0011000000000001, that is, 0x3011. To check the status of the PLL, read Register 0x0005. Fractional Mode Fractional mode is used when the available clock input at XIN/MCLKIN is a fractional multiple of the desired PLL output; it is governed by the following equation: fPLL = fIN × (R + (N/M))/X For example, if XIN/MCLKIN = 16 MHz, the PLL output is 115.2 MHz. To find the values of R, N, and M, use the following equation: where fPLL = 115.2 MHz. fPLL = fIN × (R + (N/M))/X For example, if fIN = 19.2 MHz, then (R/X) = fPLL (PLL Required Output)/fIN = 6 Therefore, R and X are set as follows: R = 6, and X = 1 (default). where: fPLL = 115.2 MHz. fIN = 16 MHz. To find the values of R, N, M, and X, use the following equation: To route the clock through the PLL, first set Register 0x000 to 0x0001. (R + (N/M))/X = 115.2 MHz/16 MHz = 7.2 = 7 + (2/10) In integer mode, the values set for N and M are ignored; leave Register 0x001 and Register 0x002 at default. Therefore, R, X, N and M can be set as follows: R = 7, X = 1 (default), N = 2, and M =10. Table 11 shows the name, function, and required settings for the bits in Register 0x003. To route the clock through the PLL, first set Register 0x000 to 0x0001. See Table 12 for the required register settings while in fractional mode. Set Register 0x003 to 0011100000000001, that is, 0x3813. To check the status of the PLL, read Register 0x005. PLL Lock Acquisition Register 0x005 is a read only register that indicates the PLL status. After writing the PLL settings, it is recommended to read the PLL lock status bit to ensure that the PLL is locked. A PLL_LOCK bit value of 1 indicates that the PLL is locked. Table 12. Required Register Writes for Fractional Mode Register 0x0001 0x0002 0x0003 Bits [15:0] [15:0] [15:11] [7:4] 1 Name PLL_DEN PLL_NUM PLL_INTEGER_DIV PLL_INPUT_PRESCALE PLL_TYPE 0 PLL_EN Function Sets the M value Sets the N value Sets the R value Sets the X value Sets the fractional mode for the PLL Enables the PLL Rev. 0 | Page 22 of 72 Required Setting 0000000000001010 (that is, 0x000A) 0000000000000010 (that is, 0x0002) 00111 0001 1 1 Data Sheet ADAR7251 GPIO The ADAR7251 contains two GPIOs: Pin 28 and Pin 29. These pins are dual function. They serve as ADC data output pins in PPI mode, or as GPIOs in serial mode. These pins can be configured as inputs or outputs, and are read back or programmed via the SPI control interface. Register 0x250 and Register 0x251 are used for setting GPIO1 and GPIO2, respectively. Typical applications for these pins include monitoring the status of logic signals or controlling external devices. Use the GPIO pins for low speed serial communication. Configure the GPIO pins by writing to the GPIO configuration registers, Register 0x250 and Register 0x251. Note that, in these registers, the GPIO pins are referred to as the multipurpose (MPx) pins, Each GPIO pin has associated bits in the GPIO configuration register that define a status of the pin and whether the GPIO is used as an input or an output, as well as the debounce period. Register 0x260 and Register 0x261 can be used to output 1 or 0 to GPIO1 and GPIO2, respectively. Register 0x270 and Register 0x271 provide the read value from GPIO1 and GPIO2, respectively. ADC DATA PORT The ADAR7251 digital interface port provides multiple options for accessing the ADC data and connecting to DSP or microcontrollers in the system. The digital interface port can be set as serial mode or parallel mode. Note that, throughout the remainder of the data sheet, multifunction pins are referred to by the relevant function in text and figures, where applicable. ADC Serial Mode The ADC serial port uses the conversion start pin (CONV_START), the frame sync pin (FS_ADC/ADC_DOUT7), the bit clock pin (SCLK_ADC), and two data output pins (ADC_DOUT0 and ADC_DOUT1). CONV_START can be disabled if it is not required in the system. The serial port can be set to either master or slave mode. The ADC output data is twos complement, 16-bit binary. Depending on the mode setup, the frame sync and bit clock pin directions change. In master mode, the ADAR7251 generates these signals, whereas in slave mode, these signals are provided by the external DSP. The ADC_DOUT0 and ADC_DOUT1 pins are always set as outputs, independent of the master or slave mode. The data format is fixed to MSB first. The serial port is powered using the IOVDDx supply. Take proper care to ensure decoupling of the high frequency noise on this pin to prevent jitter on the clock and data outputs. Connect a 100 nF MLCC is recommended to be connected to the IOVDDx pins as close as possible with direct connection to the DGNDx pins and a ground plane on the board. drive strength for the digital output pins using Register 0x0280 through Register 0x292. The ADAR7251 consists of four ADCs. Data is available in two pairs on the ADC_DOUT0 and ADC_DOUT1 pins: Channel 1 and Channel 2 on ADC_DOUT0, and Channel3 and Channel 4 on ADC_DOUT1 in 2-channel mode. Each channel uses 16 bits; for two channels, 32-bit clocks are required. The frame sync signal (FS_ADC) sets the sample rate for the ADC. Therefore, the typical bit clock rate for a sample rate of 1.2 MHz is 32 × 1.2 MHz = 38.4 MHz ADC Serial Master Mode In master mode, the ADC generates the bit clock (SCLK_ADC) and frame sync (FS_ADC) signals. The sample rate is restricted to a maximum of 1.2 MHz in serial mode. Two pins are provided for the serial data: ADC_DOUT0 and ADC_DOUT1. By default, each pin provides the two channel output. In addition, all four channels can be output from one data pin, ADC_DOUT0. The bit clock rate depends on the sample rate and the number of channels per data pin used. See Table 13 for available options. Figure 38 shows the typical connections diagram for ADC serial master mode Table 13. Bit Clock Rate Options for ADC Serial Mode Number of Channels per ADC_DOUT0/ADC_DOUT1 Pin 2 4 2 4 2 4 2 4 2 4 2 4 1 Supported in master mode only. Because the bit clock rate is in the 40 MHz range, traces on the board require proper attention. The bit clock and data pin (ADC_DOUTx) must be traced out with transmission line considerations. If the clock is connected to multiple devices, the stubs must be properly terminated to reduce reflections. Microstrip or stripline traces are recommended for these pins. Increase the Rev. 0 | Page 23 of 72 FS_ADC (MHz) 0.3 0.3 0.45 0.45 0.6 0.6 0.9 0.9 1.2 1.2 1.8 1.8 SCLK_ADC (MHz) 9.6 19.2 14.4 28.8 19.2 38.4 28.8 57.6 38.4 Not applicable 57.61 Not applicable ADAR7251 Data Sheet MASTER XOUT XIN/MCLKIN SCLK_ADC/ADC_DOUT7 FS_ADC ADC_DOUT0 ADC_DOUT1 attempts to synchronize to the serial port clocks. In serial master mode, this bit must be disabled by writing 0x0000 to Register 0x30E. This is an important step because the digital filter is already synchronized to the internal serial port clocks and does not need to be resynchronized based on the external asynchronous demand of the CONV_START signal. See Figure 39 for waveforms. SLAVE DSP SPORT1 ADAR7251 OSCILLATOR RAMP PROFILE MCLKIN ADAR7251 MASTER FREQUENCY (GHz) SPORT2 ON TIME OFF TIME SEE NOTE 1 CONV_START 1 FRAME CLOCK PERIOD SEE NOTE 1 FS_ADC Figure 38. Typical Connection Diagram for ADC Serial Master Mode 32 BIT CLOCKS Figure 41 and Figure 42 show the waveforms for the serial modes without the CONV_START signal. 12357-133 SCLK_ADC ADC Serial Master Mode with CONV_START The following precautions must be taken into account while using ADC serial master mode with CONV_START: NOTES 1. IGNORE FIRST AND LAST SAMPLES BECAUSE CONV_START IS NOT SYNCHRONOUS TO INTERNAL ADC CLOCK. Figure 39. Typical Timing Waveforms for ADC Serial Master Mode with CONV_START MASTER SLAVE DSP ADAR7251 SCLK_ADC FS_ADC/DOUT7 ADC_DOUT0 ADC_DOUT1 CONV_START GPIO1 DATA_READY GPIO2 XIN/MCLKIN OSCILLATOR The very first sample data may not be complete and may need to be ignored. This is because the CONV_START signal is asynchronous to the internal ADC clocks, and may request the data anywhere in the middle of the internal frame sync signal. The digital filter sync enable bit in Register 0x30E is used to synchronize the internal digital filter to the serial port clocks. This bit is enabled by default, therefore, the digital filter Rev. 0 | Page 24 of 72 SPORT1 The ADC provides the CONV_START signal to synchronize the ADC conversion data with an external ramp signal used in a FMCW system. Use the CS_OVERRIDE bit (Register 0x1C2, Bit 1) to enable or disable the CONV_START signal. This bit is disabled by default. When the CS_OVERRIDE bit is enabled with ADC serial master mode, the serial port waits for the CONV_START signal from the external DSP or MCU in the system. The CONV_START signal is used to indicate the start of the ramp signal in the system. The CONV_START signal is active low and needs an external pull-up resistor to IOVDDx. When the CONV_START signal is high, the ADC remains running internally, but the data and clocks are not output from the serial port. Therefore, there is no data output to the external DSP while this signal is logic high. When the CONV_START signal goes low, indicating the start of the ramp signal, the serial port starts outputting the clocks and data. The external DSP can grab the data on the ADC serial port based on the frame sync and serial clock. The data is synchronous to the external ramp signal. XOUT MCLKIN Figure 40. ADC Serial Master Mode with CONV_START 12357-132 OPTIONAL FOR > 4 CHANNELS 12357-026 XOUT XI/MCLKINN SCLK_ADC/ADC_DOUT7 FS_ADC ADC_DOUT0 ADC_DOUT1 Data Sheet ADAR7251 SCLK_ADC 0 15 31 ADC_DOUT0 CHANNEL 1 CHANNEL 2 ADC_DOUT1 CHANNEL 3 CHANNEL 4 12357-027 FS_ADC Figure 41. Serial Mode, Two Channels per the ADC_DOUTx Pins SCLK_ADC 0 15 63 31 ADC_DOUT0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 12357-028 FS_ADC Figure 42. Serial Mode, 4 Channels per the ADC_DOUTx Pins ADAR7251 SLAVE SPORT1 MASTER SPI ADAR7251 SLAVE SPI_MISO SCLK_ADC FS_ADC/ADC_DOUT7 ADC_DOUT0 ADC_DOUT1 SPI_MOSI SPI_SCLK SPI_SS1 SPI_SS2 SPI_SS SPI_SCLK SPI_MOSI SPI_MISO MCLKOUT 12357-029 XIN/MCLKIN MASTER DSP SPI_SS SPI_SCLK SPI_MOSI SPI_MISO XIN/MCLKIN SCLK_ADC FS_ADC/ADC_DOUT7 ADC_DOUT0 ADC_DOUT1 OPTIONAL FOR > 4 CHANNELS FCLK = 16MHz TO 54MHz Figure 43. Typical Connection Diagram for ADC Serial Slave Mode ADC Serial Slave Figure 43 shows the typical connection diagram for ADC serial slave mode. In this mode, the directions of the frame sync and bit clock pins change. Both pins are inputs and must be provided with bit clock and frame sync signals via an external DSP. The ADC_DOUT0 and ADC_DOUT1 pins are always used as outputs. The data format is fixed as MSB first. The ADC must be provided with master clock from the DSP to synchronize the ports. ADC PPI (Byte Wide Mode) ADC PPI mode is parallel byte wide mode and, in this mode, the device is always master. In this mode, the ADC outputs the bit clock and data. Provide the ADC port with a conversion start signal (CONV_START) if selected. This initiates the conversion process. When the ADC is ready with conversion data, it pulls the DATA_READY pin high to indicate the data ready status to the DSP. The ADC then provides the bit clock, SCLK_ADC. The data is available on the rising edge of the bit clock. The maximum sample rate supported is 3.6 MHz in this mode. The data is available on the ADC_DOUT0 through ADC_DOUT7 pins, one byte at a time. The ADC data is twos complement, 16-bit binary, but the 16-bit data is split into two bytes: a higher byte and a lower byte (each is 8 bits wide). The higher byte is output first, and is followed by the lower byte. The bit clock (SCLK_ADC) rate depends on the sample rate setting. See Table 14 for available options. Note that in the PPI mode, the FS_ADC output is not Rev. 0 | Page 25 of 72 ADAR7251 Data Sheet The other sample rates supported are 300 kHz, 600 kHz, 900 kHz, 2.4 MHz, and 3.6 MHz. The highest serial clock supported is 57.6 MHz. However, as the sample rate increases beyond 1.2 MHz, the ADC resolution decreases. At the highest sample rate of 3.6 MHz, the ADC resolution is limited to 11 bits. available. This mode may be useful if the DSP port cannot support the 38.4 MHz data rate. The data rate is less than that of the serial port; however, it uses more pins for data. Table 14. Bit Clock Rate Options for ADC PPI Byte Wide Mode Number of Channels 2 FS_ADC (MHz) 1.2 SCLK_ADC (MHz) 4.8 4 1.2 9.6 2 1.8 7.2 4 1.8 14.4 Figure 44 shows the typical connections diagram for ADC PPI master mode. Data Output Pins ADC_DOUT0 through ADC_DOUT7 ADC_DOUT0 through ADC_DOUT7 ADC_DOUT0 through ADC_DOUT7 ADC_DOUT0 through ADC_DOUT7 Figure 45 and Figure 46 show waveforms for PPI 2-channel and PPI 4-channel mode. MASTER SLAVE DSP ADAR7251 SCLK SCLK_ADC ADC_DOUT0 TO ADC_DOUT7 CONV_START GPIO1 DATA_READY GPIO2 XOUT MCLKOUT 12357-030 XIN ADC_DOUT0 TO ADC_DOUT7 Figure 44. Typical Connection Diagram for ADC PPI Master Mode CONV_START DATA_READY 0 1 3 2 CHANNEL 1 CHANNEL 2 CHANNEL 1 CHANNEL 2 CHANNEL 1 ADC_DOUT7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 ADC_DOUT6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 ADC_DOUT5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 ADC_DOUT4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 ADC_DOUT3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 ADC_DOUT2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 ADC_DOUT1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 ADC_DOUT0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 Figure 45. PPI, 2-Channel Rev. 0 | Page 26 of 72 CHANNEL 2 CHANNEL 1 CHANNEL 2 12357-031 SCLK_ADC Data Sheet ADAR7251 CONV_START DATA_READY 0 1 3 2 CHANNEL 3 CHANNEL 4 CHANNEL 1 ADC_DOUT7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 B15 B7 ADC_DOUT6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 B14 B6 ADC_DOUT5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 B13 B5 ADC_DOUT4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 B12 B4 ADC_DOUT3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 B11 B3 ADC_DOUT2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 B10 B2 ADC_DOUT1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 B9 B1 ADC_DOUT0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 B8 B0 CHANNEL 1 CHANNEL 2 CHANNEL 2 CHANNEL 3 CHANNEL 4 12357-032 SCLK_ADC Figure 46. PPI, 4-Channel Table 15. Bit Clock Rate Options for ADC PPI Nibble Wide Mode FS_ADC (MHz) 1.2 1.2 1.8 1.8 SCLK_ADC (MHz) 9.6 19.2 14.4 28.8 ADC PPI Nibble Wide Mode ADC PPI nibble wide mode differs from byte wide mode in that the data is transferred in nibble form (four bits at a time) instead of in byte wide mode (eight bits at a time). In master mode, the ADC outputs the bit clock and data. Provide the ADC port with a conversion start (CONV_START); this initiates the conversion process. When the ADC is ready with the conversion data, it pulls the DATA_READY pin high to the DSP. The ADC then provides the bit clock, SCLK_ADC. The data is available on the rising edge of the bit clock. The maximum sample rate supported is 3.6 MHz in this mode. The data is available on the ADC_DOUT0 through ADC_DOUT3 pins, one nibble at a time. The 16-bit data is split into four nibbles each, 4 bits wide. The higher nibble is output first, followed by the lower nibble. The bit clock (SCLK) rate depends on the sample rate setting. See Table 15 for available options. This mode may be useful if the DSP cannot support the 8-bit wide data port. The data rate is twice that of the PPI byte wide mode; however, it saves four pins. Data Output Pins ADC_DOUT0 through ADC_DOUT3 and PPI modes are supported, but are limited to master mode. The typical connections for the ADC serial master mode (see Figure 48) and PPI master mode(see Figure 44) are valid. In DAQ serial mode, the SCLK_ADC is fixed at 38.4 MHz, whereas the clock rate is adjustable in PPI mode. Figure 50 shows the typical operation sequence for the DAQ serial mode with two channels per data line. MASTER SCLK_ADC ADC_DOUT0 TO ADC_DOUT3 XIN DAQ Mode DAQ mode is designed specifically for FSK radar applications. In this mode, the ADC synchronizes with the FSK clock. Both serial Rev. 0 | Page 27 of 72 SLAVE DSP ADAR7251 SCLK ADC_DOUT0 TO ADC_DOUT3 CONV_START GPIO1 DATA_READY GPIO2 XOUT 12357-033 Number of Channels 2 4 2 4 Figure 47. Typical Connection Diagram for PPI Nibble Wide Mode ADAR7251 Data Sheet MASTER SLAVE DSP ADAR7251 SPORT1 SCLK_ADC FS_ADC ADC_DOUT0 ADC_DOUT1 GPIO1 DATA_READY GPIO2 XOUT 12357-034 XIN CONV_START MCLKIN OSCILLATOR Figure 48. Typical Connection Diagram for DAQ Serial Master Mode DATA_READY 0 1 3 2 15 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 1 ADC_DOUT0 B15 B11 B7 B3 B15 B11 B7 B3 B15 B11 B7 B3 B15 B11 B7 B3 ADC_DOUT1 B14 B10 B6 B2 B14 B10 B6 B6 B14 B10 B6 B2 B14 B10 B6 B2 ADC_DOUT2 B13 B9 B5 B1 B13 B9 B5 B5 B13 B9 B5 B1 B13 B9 B5 B1 ADC_DOUT3 B12 B8 B4 B0 B12 B8 B4 B0 B12 B8 B4 B0 B12 B8 B4 B0 CHANNEL 2 CHANNEL 3 CHANNEL 4 12357-035 SCLK_ADC Figure 49. PPI, 4-Channel Nibble Wide Mode tCONV tWAIT (MIN) = 1SCLK + (tDATA – tCONV) IF tCONV < tDATA tWAIT (MIN) = 1SCLK IF tCONV > tDATA CS DATA_READY tDATA = [(2 × 16)] SCLK CYCLES ADC_DOUT0 ADC_DOUT1 CHANNEL 1 B15 B14 B13 B12 CHANNEL 2 B1 B0 B15 CHANNEL 3 B15 B14 B13 B12 CHANNEL 3 B1 B0 Figure 50. DAQ Serial Master, Two Channels Per Pin Rev. 0 | Page 28 of 72 12357-036 SCLK_ADC Data Sheet ADAR7251 tWAIT (MIN) = 1SCLK + (tDATA – tCONV) IF tCONV < tDATA tWAIT (MIN) = 1SCLK IF tCONV > tDATA tCONV tWAIT = 1 SCLK CYCLE CS DATA_READY tDATA = [(2 × # OF CHANNELS)] SCLK CYCLES SCLK_ADC CHANNEL 1 B7 B15 CHANNEL 2 B15 B7 ADC_DOUT6 B14 B6 B14 ADC_DOUT5 B13 B5 ADC_DOUT4 B12 ADC_DOUT3 CHANNEL 4 B15 B7 B6 B14 B6 B13 B5 B13 B5 B4 B12 B4 B12 B4 B11 B3 B11 B3 B11 B3 ADC_DOUT2 B10 B2 B10 B2 B10 B2 ADC_DOUT1 B9 B1 B9 B1 B9 B1 ADC_DOUT0 B8 B0 B8 B0 B8 B0 12357-037 ADC_DOUT7 Figure 51. DAQ PPI Master Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels The ADAR7251 offers flexible serial port for multichannel applications requiring more than four channels. The typical connection diagram is shown in Figure 52. MASTER fS DAQ_MODE = 1/(tCONV + tWAIT) OSCILLATOR ADAR7251 MASTER Table 16 shows the supported modes and typical acquisition times in DAQ mode. Table 16. Acquisition Times in DAQ Mode tCONV (μs) 1.2 1.8 2.4 SS SPI_SCLK SPI_MOSI SPI_MISO XIN SCLK_ADC FS_ADC ADC_DOUT0 ADC_DOUT1 OPTIONAL FOR > 4 CHANNELS MASTER SPI SPI_MISO SPI_MOSI SPI_SCLK SPI_SS1 SPI_SS2 12357-038 where: tDATA < tCONV. tCONV is the time required for the conversion. tWAIT is the time required to wait before another conversion start can be initiated. tDATA is the time the data is available on the ADC_DOUTx pins. Acquisition Cycles 16 24 32 SS SPI_SCLK SPI_MOSI SPI_MISO SCLK_ADC FS_ADC ADC_DOUT0 ADC_DOUT1 SLAVE DSP SPORT1 ADAR7251 XIN The high to low transition on the CONV_START signal starts the conversion process. The ADC signals set the DATA_READY signal high. Data is available at the next clock cycle. Two channels per pin are supported in serial mode, whereas two or four channels are supported in PPI mode. The SCLK frequency determines the total time required for the data (tDATA). This value is typically 32-bit clock cycles for serial mode and (2× the number of channels) of bit clock cycles in PPI mode. The fastest data rate available is 57.6 MHz in 2-channel, PPI, 16-cycle acquisition mode. The maximum data rate in DAQ serial mode is 38.4 MHz and is fixed. The frequency of the CONV_START signal dictates the sample rate of the ADC in DAQ mode. Calculate the sampling frequency in DAQ mode as Figure 52. Connecting Multiple ADAR7251 Devices for an 8-Channel System Multiple ADAR7251 devices can be configured using a single SPI master and clock oscillator to synchronize the PLLs of both devices. For the system to function, it is recommended to have both the ADCs on the same board and within a few inches of each other. Both the devices act as master, but only one ADAR7251 supplies the bit clock and frame sync signal to the DSP port, which is slave. This connection option may save the Rev. 0 | Page 29 of 72 ADAR7251 Data Sheet extra serial port (SPORT) on the DSP. This works because both PLLs are synchronized to one master clock and are enabled at the same time using a single SPI master. SPI writes must be written to both devices simultaneously. For this to work, the SPI_SS pin of both devices must be selected at the same time. The SPI reads, however, can be performed independently for both devices. SPI CONTROL PORT The ADAR7251 control port uses a 4-wire SPI. The SPI port sets the internal registers of the device. The SPI allows read and write capability of the registers. All the registers are 16 bits wide. The SPI control port supports Mode 11 (clock polarity = 1 and clock phase = 1), slave only and, therefore, requires the master in the system to operate. The registers cannot be accessed without the master clock to the device. It is recommended to configure the PLL first to achieve full speed on the control port. The port is powered by IOVDDx, and control signals must be within the IOVDDx limits. The serial control interface also allows the user to control auxiliary functions of the device such as the GPIOs and the auxiliary ADC. peripheral SPI_MISO ports for sharing the same system controller port. All SPI transactions have the same basic format shown in Table 19. Figure 2 shows an SPI port timing diagram. All data must be written MSB first. Device Address R/W The LSB of the first byte of an SPI transaction is a R/W bit. This bit determines whether the communication is a read (Logic level 1) or a write (Logic Level 0). This format is shown in Table 18. Table 18. SPI Address and R/W Byte Format Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 ADDR15 Bit 0 R/W Table 17 shows the functions of the control port pins in SPI mode. The ADDR15 pin (Pin 32) determines the address of the device. The device reads the status of this pin on power-up and uses the device address. A 47 kΩ typical resistor must be used to set the device address by using a pull-down resistor to ground or a pull-up resistor to the IOVDDx pins. Pin 32 is multifunctional and is also used as a data output in PPI mode. The R/W bit setting determines if the device is used for an SPI write or SPI read operation. When the R/W bit is set to 0, it is used for an SPI write operation; when it is set to 1, it is used for an SPI read operation. Table 17. Control Port Pin Functions Register Address Pin No. 32 38 Mnemonic ADDR15 SPI_MISO 39 SPI_MOSI 40 41 SPI_CLK SPI_SS Pin Function Sets the device address for the SPI SPI port outputs data from the ADAR7251 SPI port inputs data to the ADAR7251 SPI clock to the ADAR7251 SPI slave select to the ADAR7251 Pin Type Input Output The registers address field is 16 bits wide. The registers start at Register 0x000. Data Bytes The register data field is 16 bits wide. Input CRC Input Input The ADAR7251 provides the user with a 16-bit cyclic redundancy check (CRC) for SPI read and writes to the device, and for data communication error detection. The CRC is enabled by default and can be disabled if not required. The SPI port uses a 4-wire interface, consisting of the SPI_SS, SPI_CLK, SPI_ MOSI, and SPI_MISO signals. The SPI port is always a slave port. The SPI_SS (slave select) selects the device. The SPI_CLK is the serial clock input for the device, and all data transfers (either SPI_MOSI or SPI_MISO) take place with respect to this clock signal. The SPI_MOSI pin addresses the on-chip registers and transfers data to these registers. The SPI_MISO pin outputs data from the on-chip registers. The SPI_SS goes low at the beginning of a transaction and high at the end of a transaction. The SPI_CLK signal samples SPI_MOSI on a low to high SPI_CLK transition; therefore, the data to be written to the device must be stable during this edge. The data shifts out of the SPI_MISO on the falling edge of the SPI_CLK and must be clocked into a receiving device, such as a microcontroller, on the SPI_CLK rising edge. The SPI_MOSI signal carries the serial input data to the ADAR7251, and the SPI_MISO signal carries the serial output data from the device. The SPI_MISO signal remains tristated until a read operation is requested. This allows direct connection to other SPI-compatible Disable the CRC by writing 0x0001 to Register 0xFD00. This SPI write disables the CRC function. With the CRC disabled, the SPI read and write sequence is conventional. Table 19 shows the typical single read/write byte sequence without the CRC; this sequence typically requires 40 clock cycles or 5 bytes. The typical 5-byte sequence consists of Byte 0 for the device address with the R/W bit. The next two bytes, Byte 1 and Byte 2, contain the register address followed by Byte 3 and Byte 4, which carry the data to or from the register. A sample timing diagram for a single-word SPI write operation to a register is shown in Figure 53. Figure 54 show a single-word SPI read. During the read operation, the SPI_MISO pin goes from being high impedance (high-Z) to output at the beginning of Byte 3. Figure 55 and Figure 56 shows the typical sequence for the multiple byte SPI read and writes. Rev. 0 | Page 30 of 72 Data Sheet –1 ADAR7251 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 SPI_CLK SPI_SS REGISTER ADDRESS BYTE1 REGISTER ADDRESS BYTE2 DATA BYTE1 DATA BYTE2 12357-039 DEVICE ADDRESS (7 BITS) SPI_MOSI R/W Figure 53. SPI Write to the ADAR7251 Clocking (Single-Word Write Mode), No CRC –1 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 SPI_CLK SPI_SS DEVICE ADDRESS (7 BITS) SPI_MOSI REGISTER ADDRESS BYTE1 DATA BYTE1 REGISTER ADDRESS BYTE2 DATA BYTE2 DATA BYTE FROM ADAR7251 SPI_MISO DATA BYTE FROM ADAR7251 12357-040 R/W Figure 54. SPI Read from the ADAR7251 Clocking (Single-Word Read Mode), No CRC SPI_SS TOTAL CLOCK CYCLES = 24 + 16 (n); n = NUMBER OF REGISTERS SPI_CLK DEVICE ADDRESS BYTE DATA1 16 BITS REGISTER ADDRESS 16 BITS DATA2 16 BITS DATA BYTE n – 1 DATA BYTE n 12357-041 SPI_MOSI Figure 55. SPI Write to the ADAR7251 (Multiple Bytes), No CRC SPI_SS TOTAL CLOCK CYCLES = 24 + 16 (n); n = NUMBER OF REGISTERS SPI_CLK SPI_MOSI REGISTER ADDRESS BYTE SPI_MISO DATA1 16 BITS DATA2 16 BITS DATA BYTE n – 1 DATA BYTE n 12357-042 DEVICE ADDRESS BYTE Figure 56. SPI Read from the ADAR7251 (Multiple Bytes), No CRC Table 19. Single SPI Write or Read Format Operation Write Read Byte 0 Device Address[6:0], R/W = 0 Device Address[6:0], R/W = 1 Byte 1 Register Address[15:8] Register Address[15:8] Byte 2 Register Address[7:0] Register Address[7:0] Byte 3 Data[15:8] Data[15:8] Table 20. Single Register Write with CRC Device Address 1 byte 00 1 Register Address 2 bytes XXXX1 Register Data 2 bytes XXXX1 X means don’t care. Rev. 0 | Page 31 of 72 CRC 2 bytes XXXX1 Byte 4 Data[7:0] Data[7:0] ADAR7251 Data Sheet If the CRC is enabled, the 16-bit CRC must be included in the SPI write following the register and data bytes. Any SPI write that does not include valid CRC bits is ignored. The SPI write with CRC included is as follows for single or multiple registers: Register 0x084 and Register 0x085. Register 0x084 stores the lower byte, and Register 0x085 stores the higher byte. The lower and upper bytes combined form the 16-bit CRC value expected in the SPI write sequence. 1. Register 0x086 enables the CRC calculation for the whole register map. It is enabled by default. Register 0x087 stores the flag that indicates the CRC calculation status. A value of 1 indicates that the CRC calculation is ready. 2. 3. The CRC is calculated based on the data, excluding the device address byte. The CRC polynomial used is (x16 + x15 + x12 + x7 + x6 + x4 + x3 + 1), that is, xC86Ch. The two calculated, 16-bit CRC bytes must be appended to the SPI writes along with the register address and data bytes for valid transaction. In addition, the CRC value for the whole register map is stored in Register 0x088 and Register 0x089. Register 0x088 stores the lower byte, whereas Register 0x089 stores the higher byte. Register 0x084, Register 0x085, Register 0x087, Register 0x088, and Register 0x089 are read only. The SPI read is limited to 8 bytes (see Table 22). Three registers must be read one at a time to achieve the CRC. The device address is excluded from the eight bytes. The last two bytes represent the CRC bytes after the eight bytes (two bytes of the register address + six bytes of the register data). Figure 57 and Figure 58 show the SPI read and write operations with the CRC. If during the SPI write the invalid CRC is included, the expected CRC value of the last SPI transaction is stored in Table 21. Multiple Register Write with CRC Device Address 1 byte 00 1 Register Address 2 bytes XXXX1 Register Data 2 bytes XXXX1 Register Data 2 bytes XXXX1 Register Data 2 bytes XXXX1 CRC 2 bytes XXXX1 Register Data 2 bytes XXXX1 Register Data 2 bytes XXXX1 Register Data 2 bytes XXXX1 CRC 2 bytes XXXX1 X means don’t care. Table 22. Register Read with CRC Device Address 1 byte 01 X means don’t care. –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 SPI_CLK SPI_SS REGISTER ADDRESS BYTE1 REGISTER ADDRESS BYTE2 DATA BYTE1 DATA BYTE2 CRC LOWER BYTE CRC UPPPER BYTE 8 CLOCK CYCLES 8 CLOCK CYCLES CRC LOWER BYTE CRC UPPPER BYTE 12357-043 DEVICE ADDRESS (7 BITS) R/W SPI_MOSI Figure 57. SPI Single Write with CRC SPI_CLK SPI_SS DEVICE ADDRESS (7 BITS) SPI_MOSI COPY OF SPI_MOSI REGISTER ADDRESS BYTE1 (8 CLOCK CYCLES) REGISTER ADDRESS BYTE2 (8 CLOCK CYCLES) 48 CLOCK CYCLES R/W DATA BYTE1 DATA BYTE6 Figure 58. SPI Read with CRC Rev. 0 | Page 32 of 72 12357-044 1 Register Address 2 bytes XXXX1 Data Sheet ADAR7251 PCB LAYOUT GUIDELINES 10µF GND IOVDDx footprint for the thermal pad is available at http://www.analog.com/en/content/packageinformation/fca.html. The typical recommended board stackup is four layers with the top and bottom layers used for signaling, the second layer as the ground plane, and the third layer as the power plane. Ensure that the ground plane is contiguous without breaks for the best EMI and thermal performance. During the board layout, use the SCLK_ADC and ADC_DOUTx signals as a transmission line to maintain the signal integrity. AVDDx GROUND The printed circuit board (PCB) layout is an important consideration, as is the component placement of the decoupling capacitors. Figure 59 shows the component placement for some of the decoupling capacitors. The decoupling components for AVDDx, DVDDx, IOVDDx, CM, BIASP, BIASN, REGOUT_ DIGITAL, and PLLFILT must be placed close to the device. The 1 nF and 100 nF MLCCs must be placed close to their respective pins and on the same layer as the device. The bulk 10 μF capacitor can be placed further from the pins. The exposed pad underneath the device must be soldered to the ground plane on the PCB with thermal vias. The recommended 10µF 100nF 100nF 1nF CM 100nF 1nF 1nF CM 10µF BIASN 470nF IOVDDx BIASP 470nF 1nF AVDDx 100nF IOVDDx 10µF 100nF 1nF PLLVDD PLL LOOP FILTER Figure 59. Recommended PCB Layout Rev. 0 | Page 33 of 72 AVDDx 100nF 12357-046 DVDDx 10µF XTAL AVDDx 10µF DVDDx 100nF REGOUT_DIGITAL 100nF ADAR7251 Data Sheet REGISTER SUMMARY Table 23. Register Summary Reg Name 0x000 CLK_CTRL Bits Bit 7 [15:8] [7:0] Bit 6 Bit 5 Bit 4 Bit 3 RESERVED[15:8] RESERVED[7:0] Bit 2 Bit 1 Bit 0 Reset 0x0001 RW RW PLL_BYPASS 0x001 PLL_DEN [15:8] [7:0] PLL_DEN[15:8] PLL_DEN[7:0] 0x0000 RW 0x002 PLL_NUM [15:8] [7:0] PLL_NUM[15:8] PLL_NUM[7:0] 0x0000 RW 0x003 PLL_CTRL [15:8] [7:0] 0x0000 RW 0x0000 R 0x0000 RW 0x00FF RW 0x03FF RW 0x0000 RW 0x0000 RW 0x0000 R 0x0000 R 0x005 PLL_LOCK 0x040 MASTER_ ENABLE PLL_INTEGER_DIV PLL_INPUT_PRESCALE 0x042 POWER_ ENABLE RESERVED[15:8] RESERVED[7:0] [15:8] RESERVED[14:7] 0x081 ASIL_MASK LN_PG1_EN [15:8] RESERVED 0x082 ASIL_FLAG 0x083 ASIL_ERROR 0x084 CRC_VALUE_L FLASH_ LDO_EN LDO_EN DIN_EN ADC3_EN ADC2_EN ADC1_EN RESERVED POUT_EN CLOCK_ LOSS_EN SOUT_EN CLKGEN_EN RESERVED[14:7] RESERVED[6:0] RESERVED[1:0] CLK_LOSS_ MASK RESERVED[9:2] BRP_GOOD_ MASK RESERVED[14:7] RESERVED[6:0] BRN_GOOD_ MASK [15:8] [7:0] [15:8] [7:0] PLL_LOCK MASTER_EN RESERVED ADC4_EN AUXADC_EN MP_EN [15:8] [7:0] [15:8] [7:0] RESERVED[2:0] PLL_TYPE PLL_EN RESERVED[6:0] [15:8] [7:0] LN_PG4_EN LN_PG3_EN LN_PG2_EN [7:0] 0x080 ASIL_CLEAR RESERVED [15:8] [7:0] [7:0] 0x041 ADC_ENABLE RESERVED RESERVED[1:0] CLK_LOSS_ ERROR BRN_ERROR RESERVED[9:2] BRP_ERROR ASIL_CLEAR VR_GOOD_MASK OVERTEMP_ MASK CRC_MASK ASIL_FLAG VR_GOOD_ ERROR OVERTEMP_ ERROR CRC_ERROR [15:8] [7:0] RESERVED[7:0] CRC_VALUE_L 0x0000 R 0x085 CRC_VALUE_H [15:8] [7:0] RESERVED[7:0] CRC_VALUE_H 0x0000 R 0x086 RM_CRC_ ENABLE RESERVED[14:7] 0x0000 RW 0x0000 R 0x0000 R 0x0000 R 0x0000 RW 0x0000 RW 0x2222 RW 0x0003 RW 0x0018 RW [15:8] [7:0] RESERVED[6:0] 0x087 RM_CRC_DONE [15:8] [7:0] 0x088 RM_CRC_ VALUE_L 0x089 RM_CRC_ VALUE_H 0x100 LNA_GAIN 0x101 PGA_GAIN 0x102 ADC_ ROUTING1_4 0x140 DECIM_RATE 0x141 HIGH_PASS RM_CRC_ ENABLE RESERVED[14:7] RESERVED[6:0] [15:8] RESERVED[7:0] [7:0] RM_CRC_VALUE_L [15:8] RESERVED[7:0] [7:0] RM_CRC_VALUE_H [15:8] [7:0] LNA4_GAIN LNA3_GAIN [15:8] [7:0] PGA4_GAIN PGA3_GAIN RM_CRC_DONE RESERVED LNA2_GAIN LNA1_GAIN PGA2_GAIN PGA1_GAIN RESERVED [15:8] RESERVED ADC4_SRC [7:0] ADC2_SRC RESERVED [15:8] [7:0] [15:8] [7:0] RESERVED [0] RESERVED ADC3_SRC RESERVED ADC1_SRC RESERVED[12:5] RESERVED[4:0] PHASE_EQ DECIM_RATE RESERVED[8:1] HP_SHIFT Rev. 0 | Page 34 of 72 ENABLE_HP Data Sheet ADAR7251 Reg Name 0x143 ACK_MODE Bits Bit 7 Bit 6 [15:8] [7:0] RESERVED[1:0] 0x144 TRUNCATE_ MODE [15:8] Bit 5 0x1C1 PARALLEL_ MODE Bit 3 RESERVED[9:2] ACK_CYCLES CLK_SRC LRCLK_ MODE LRCLK_POL [15:8] RESERVED[5:0] [15:8] [7:0] RESERVED[5:0] 0x260 MP0_WRITE 0x261 MP1_WRITE 0x270 MP0_READ 0x271 MP1_READ 0x280 SPI_CLK_PIN [15:8] [7:0] [15:8] [7:0] ADC_VALUE[9:8] 0x0000 R ADC_VALUE[9:8] 0x0000 R 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 R 0x0000 R 0x0000 RW 0x0000 RW 0x0004 RW 0x0000 RW 0x0000 RW 0x0004 RW 0x0000 RW 0x0004 RW 0x0000 RW 0x0000 RW ADC_SPEED AUX_INPUT_SEL AUX_ADC_ MODE [15:8] [7:0] RESERVED[0] RESERVED[8:1] DEBOUNCE_VALUE MP_MODE [15:8] [7:0] RESERVED[0] RESERVED[8:1] DEBOUNCE_VALUE MP_MODE [15:8] [7:0] RESERVED[14:7] RESERVED[6:0] MP_REG_WRITE [15:8] [7:0] RESERVED[14:7] RESERVED[6:0] MP_REG_WRITE [15:8] [7:0] RESERVED[14:7] RESERVED[6:0] MP_REG_READ [15:8] [7:0] RESERVED[14:7] RESERVED[6:0] MP_REG_READ RESERVED[4:0] [15:8] [7:0] RESERVED[4:0] [15:8] [7:0] RESERVED[4:0] [15:8] [7:0] RESERVED[4:0] [15:8] [7:0] RESERVED[4:0] 0x288 SCLK_ADC_PIN [15:8] [7:0] RESERVED[4:0] 0x289 ADC_DOUT0_ PIN RW RESERVED[12:5] [15:8] [7:0] 0x287 CS_PIN 0x0000 PAR_ CHANNELS CS_OVERRIDE OUTPUT_MODE RESERVED[4:0] RESERVED[4:0] 0x286 FS_ADC_PIN RW RESERVED[13:6] [15:8] [7:0] 0x285 FAULT_PIN 0x0000 PAR_ENDIAN RESERVED[5:0] RESERVED[4:0] 0x284 ADDR15_PIN RW ADC_VALUE[7:0] [15:8] [7:0] 0x283 MOSI_PIN 0x0000 TDM_MODE ADC_VALUE[7:0] RESERVED[4:0] 0x282 SS_PIN RW RESERVED[13:6] [15:8] [7:0] 0x281 MISO_PIN 0x0002 ACK_MODE DATA_FMT PAR_NIBBLE [15:8] [7:0] 0x251 MP1_MODE RW RW TRUNC_MODE RESERVED BCLK_POL RESERVED[4:0] 0x200 ADC_READ0 0x250 MP0_MODE Reset 0x0000 RESERVED[12:5] RESERVED[5:0] 0x211 ADC_MODE Bit 0 ACK_OUT_RATE 0x1C2 OUTPUT_MODE [15:8] [7:0] 0x210 ADC_SPEED Bit 1 RESERVED[5:0] [15:8] [7:0] RESERVED [7:0] 0x201 ADC_READ1 Bit 2 RESERVED[13:6] [7:0] 0x1C0 SERIAL_MODE Bit 4 RESERVED[12:5] SPI_CLK_DRIVE RESERVED[12:5] MISO_PULL MISO_DRIVE RESERVED[12:5] SS_PULL SS_DRIVE RESERVED[12:5] MOSI_PULL MOSI_DRIVE RESERVED[12:5] ADDR15_PULL ADDR15_DRIVE RESERVED[12:5] FAULT_PULL FAULT_DRIVE RESERVED[12:5] FS_ADC_PULL FS_ADC_DRIVE RESERVED[12:5] CS_PULL CS_DRIVE RESERVED[12:5] [15:8] [7:0] SPI_CLK_PULL SCLK_ADC_PULL SCLK_ADC_DRIVE RESERVED[12:5] RESERVED[4:0] Rev. 0 | Page 35 of 72 ADC_DOUT_ PULL ADC_DOUT_DRIVE ADAR7251 Reg Name 0x28A ADC_DOUT1_ PIN Data Sheet Bits Bit 7 [15:8] Bit 6 Bit 5 [7:0] 0x28B ADC_DOUT2_ PIN RESERVED[4:0] RESERVED[4:0] ADC_DOUT_ PULL ADC_DOUT_ PULL [15:8] 0x291 DATA_READY_ [15:8] PIN [7:0] [15:8] 0xFD00 CRC_EN [15:8] [7:0] [7:0] XTAL_DRV RESERVED[15:10] RESERVED[7:3] PDETECT_EN RESERVED[3:0] RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0000 RW 0x0304 RW 0x0000 RW 0x0009 RW 0x0003 RW 0x0000 RW XTAL_ENB EQ_CAP_CTRL PERFOM_ RESERVED IMPROVE1 RESERVED[8:1] RESERVED[0] 0x0000 DATA_READY_DRIVE RESERVED[13:6] 0x301 ADC_SETTING1 [15:8] [7:0] 0x30E DEJITTER_ WINDOW DATA_READY_ PULL RESERVED[5:0] RW ADC_DOUT_DRIVE RESERVED[12:5] [15:8] [7:0] 0x30A ADC_SETTING3 [15:8] [7:0] ADC_DOUT_ PULL RESERVED[4:0] 0x0000 ADC_DOUT_DRIVE RESERVED[12:5] RESERVED[4:0] RW RW ADC_DOUT_DRIVE RESERVED[12:5] RESERVED[4:0] Reset 0x0000 ADC_DOUT_DRIVE RESERVED[12:5] [15:8] 0x308 ADC_SETTING2 [15:8] [7:0] Bit 0 ADC_DOUT_DRIVE ADC_DOUT_ PULL [15:8] [7:0] 0x292 XTAL_CTRL Bit 1 RESERVED[12:5] [7:0] 0x28E ADC_DOUT5_ PIN Bit 2 ADC_DOUT_ PULL [15:8] [7:0] 0x28D ADC_DOUT4_ PIN Bit 3 RESERVED[12:5] RESERVED[4:0] [7:0] 0x28C ADC_DOUT3_ PIN Bit 4 PERFORM_IMPROVE2 RESERVED[11:4] PERFORM_IMPROVE5 RESERVED PERFORM_ IMPROVE4 RESERVED[15:8] RESERVED[7:4] DEJITTER RESERVED[14:7] RESERVED[6:0] Rev. 0 | Page 36 of 72 CRC_EN Data Sheet ADAR7251 REGISTER DETAILS CLOCK CONTROL REGISTER Address: 0x000, Reset: 0x0001, Name: CLK_CTRL Table 24. Bit Descriptions for CLK_CTRL Bits 0 Bit Name PLL_BYPASS Settings 1 0 Description Use PLL or External Pin Clock. Bypass PLL. Use PLL Clock. Reset 0x1 Access RW Reset 0x0 Access RW Reset 0x0 Access RW PLL DENOMINATOR REGISTER Address: 0x001, Reset: 0x0000, Name: PLL_DEN Table 25. Bit Descriptions for PLL_DEN Bits [15:0] Bit Name PLL_DEN Settings 0x0001 to 0xFFFF Description 16-Bit Denominator for the PLL Fractional Part Range from 0x0001 Through 0xFFFF. Denominator Value 1 to 65,535. PLL NUMERATOR REGISTER Address: 0x002, Reset: 0x0000, Name: PLL_NUM Table 26. Bit Descriptions for PLL_NUM Bits [15:0] Bit Name PLL_NUM Settings 0x0001 to 0xFFFF Description 16-Bit Numerator for the PLL Fractional Part Range from 0x0001 Through 0xFFFF. Numerator Value 1 to 65,535. Rev. 0 | Page 37 of 72 ADAR7251 Data Sheet PLL CONTROL REGISTER Address: 0x003, Reset: 0x0000, Name: PLL_CTRL Table 27. Bit Descriptions for PLL_CTRL Bits [15:11] Bit Name PLL_INTEGER_DIV Settings [7:4] PLL_INPUT_PRESCALE 0x1 to 0x1F 0x0 to 0xF 1 PLL_TYPE 0 1 0 PLL_EN 0 1 Description Integer Part of the PLL Multiplier. Multiplier 1 to 31. PLL Input Prescaler. Prescale Value from 1 Through 16. Type of PLL. PLL is in Integer Mode. PLL is in Fractional Mode. PLL Enable. PLL is Disabled. PLL is Enabled. Reset 0x00 Access RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access R PLL STATUS REGISTER Address: 0x005, Reset: 0x0000, Name: PLL_LOCK Table 28. Bit Descriptions for PLL_LOCK Bits 0 Bit Name PLL_LOCK Settings 0 1 Description PLL Lock Bit. PLL is Unlocked. PLL is Locked. Rev. 0 | Page 38 of 72 Data Sheet ADAR7251 MASTER ENABLE SWITCH REGISTER Address: 0x040, Reset: 0x0000, Name: MASTER_ENABLE Table 29. Bit Descriptions for MASTER_ENABLE Bits 0 Bit Name MASTER_EN Settings 0 1 Description Master Enable Switch. Disables the Entire Chip. Enables the Entire Chip. Reset 0x0 Access RW Reset 0x1 Access RW 0x1 RW ADC ENABLE REGISTER Address: 0x041, Reset: 0x00FF, Name: ADC_ENABLE Table 30. Bit Descriptions for ADC_ENABLE Bits 7 Bit Name LN_PG4_EN Settings 0 1 6 LN_PG3_EN 0 1 Description LNA and PGA Enable Channel 4. Disable the LNA/PGA Channel 4. Enable the LNA/PGA Channel 4. LNA and PGA Enable Channel 3. Disable the LNA/PGA Channel 3. Enable the LNA/PGA Channel 3. Rev. 0 | Page 39 of 72 ADAR7251 Bits 5 Bit Name LN_PG2_EN Data Sheet Settings 0 1 4 LN_PG1_EN 0 1 3 ADC4_EN 0 1 2 ADC3_EN 0 1 1 ADC2_EN 0 1 0 ADC1_EN 0 1 Description LNA and PGA Enable Channel 2. Disable the LNA/PGA Channel 2. Enable the LNA/PGA Channel 2. LNA and PGA Enable Channel 1. Disable the LNA/PGA Channel 1. Enable the LNA/PGA Channel 1. ADC 4 Enable. Disable ADC 4. Enable ADC 4. ADC 3 Enable. Disable ADC 3. Enable ADC 3. ADC 2 Enable. Disable ADC 2. Enable ADC 2. ADC 1 Enable. Disable ADC 1. Enable ADC 1. Reset 0x1 Access RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW Reset 0x1 Access RW 0x1 RW POWER ENABLE REGISTER Address: 0x042, Reset: 0x03FF, Name: POWER_ENABLE Table 31. Bit Descriptions for POWER_ENABLE Bits 9 Bit Name CLOCK_LOSS_EN Settings 0 1 7 FLASH_LDO_EN Description Enables Clock Loss. Disables Clock Loss Detect. Enables Clock Loss Detect. Flash LDO Block Enable. Rev. 0 | Page 40 of 72 Data Sheet Bits 6 Bit Name LDO_EN ADAR7251 Settings 0 1 5 AUXADC_EN 0 1 4 MP_EN 0 1 3 DIN_EN 0 1 2 POUT_EN 0 1 1 SOUT_EN 0 1 0 CLKGEN_EN 0 1 Description LDO Block Enable. LDO Disable. LDO Enable. AUX ADC Block Enable. Disable ADC Power. Enable ADC Power. Multipurpose Pin Enable. GPIO Pin Disable. GPIO Pin Enable. Serial Input Block Enable. Disable Serial Input Port. Enable Serial Input Port. Parallel Output Block Enable. Disable Parallel Output Port. Enable Parallel Output Port. Serial Output Block Enable. Disable Serial Output Port. Enable Serial Output Port. Clock Generator Block Enable. Disable Clock Generator. Enable Clock Generator. Reset 0x1 Access RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW 0x1 RW Reset 0x0 Access RW CLEAR THE ASIL ERRORS REGISTER Address: 0x080, Reset: 0x0000, Name: ASIL_CLEAR Table 32. Bit Descriptions for ASIL_CLEAR Bits 0 Bit Name ASIL_CLEAR Settings 0 1 Description Clear the Automotive Safety Integrity Level (ASIL) Errors. ASIL Errors are Reported. Clears the ASIL Error. Set back to 0 after reading the ASIL register. If left at 1, no ASIL errors are reported. Rev. 0 | Page 41 of 72 ADAR7251 Data Sheet SELECTS WHICH ERRORS TO MASK REGISTER Address: 0x081, Reset: 0x0000, Name: ASIL_MASK Table 33. Bit Descriptions for ASIL_MASK Bits 5 Bit Name CLK_LOSS_MASK Settings 0 1 4 BRN_GOOD_MASK 0 1 3 BRP_GOOD_MASK 0 1 2 VR_GOOD_MASK 0 1 1 OVERTEMP_MASK 0 1 0 CRC_MASK 0 1 Description Clock Loss Error Mask. Clock Loss Error Not Masked. Clock Loss Error Masked. BIASN Voltage Error Mask. BIASN Voltage Error Not Masked. BIASN Voltage Error Masked. BIASP Voltage Error Mask. BIASP Voltage Error Not Masked. BIASP Voltage Error Masked. Reference Voltage Error Mask. Reference Voltage Error Not Masked. Reference Voltage Error Masked. Overtemperature Error Mask. Overtemperature Flag Not Masked. Overtemperature Flag Masked. CRC Error Mask. CRC Error Not Masked. CRC Error Masked. Rev. 0 | Page 42 of 72 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Data Sheet ADAR7251 ASIL ERROR FLAG REGISTER Address: 0x082, Reset: 0x0000, Name: ASIL_FLAG Table 34. Bit Descriptions for ASIL_FLAG Bits 0 Bit Name ASIL_FLAG Settings 0 1 Description Indicates an ASIL Error. No Error. ASIL Error. Reset 0x0 Access R Reset 0x0 Access R 0x0 R 0x0 R 0x0 R ASIL ERROR CODE REGISTER Address: 0x083, Reset: 0x0000, Name: ASIL_ERROR Table 35. Bit Descriptions for ASIL_ERROR Bits 5 Bit Name CLK_LOSS_ERROR Settings 0 1 4 BRN_ERROR 0 1 3 BRP_ERROR 0 1 2 VR_GOOD_ERROR 0 1 Description Clock Loss Error. Clock Available. Clock Loss Error. BIASN Error. BIASN OK. BIASN Error. BIASP Error. BIASP OK. BIASP Error. Voltage Reference Error. Voltage Reference OK. Voltage Reference Error. Rev. 0 | Page 43 of 72 ADAR7251 Bits 1 Bit Name OVERTEMP_ERROR Data Sheet Settings 0 1 0 CRC_ERROR 0 1 Description Overtemperature Error. Normal. Overtemperature Error. CRC Error. No CRC Error. CRC Error. Reset 0x0 Access R 0x0 R Reset 0x0 Access R Reset 0x0 Access R CRC VALUE, BITS[7:0] REGISTER Address: 0x084, Reset: 0x0000, Name: CRC_VALUE_L Table 36. Bit Descriptions for CRC_VALUE_L Bits [7:0] Bit Name CRC_VALUE_L Settings 0x00 to 0xFF Description CRC Value Lower Byte. CRC Value Lower Byte. CRC VALUE REGISTER Address: 0x085, Reset: 0x0000, Name: CRC_VALUE_H Table 37. Bit Descriptions for CRC_VALUE_H Bits [7:0] Bit Name CRC_VALUE_H Settings 0x00 to 0xFF Description CRC Value Upper Byte. CRC Value Upper Byte. Rev. 0 | Page 44 of 72 Data Sheet ADAR7251 START CALCULATING THE CRC VALUE OF THE REGISTER MAP CONTENT REGISTER Address: 0x086, Reset: 0x0000, Name: RM_CRC_ENABLE Table 38. Bit Descriptions for RM_CRC_ENABLE Bits 0 Bit Name RM_CRC_ENABLE Settings 0 1 Description CRC Enable. CRC Enable. CRC Disable. Reset 0x0 Access RW Reset 0x0 Access R Reset 0x0 Access R REGISTER MAP CRC CALCULATION DONE REGISTER Address: 0x087, Reset: 0x0000, Name: RM_CRC_DONE Table 39. Bit Descriptions for RM_CRC_DONE Bits 0 Bit Name RM_CRC_DONE Settings 0 1 Description Register Map CRC Calculation Done. CRC Calculation Not Done. CRC Calculation Done. REGISTER MAP CRC VALUE, BITS[7:0] REGISTER Address: 0x088, Reset: 0x0000, Name: RM_CRC_VALUE_L Table 40. Bit Descriptions for RM_CRC_VALUE_L Bits [7:0] Bit Name RM_CRC_VALUE_L Settings 0x0000 to 0xFFFF Description Regmap CRC Lower Byte. Rev. 0 | Page 45 of 72 ADAR7251 Data Sheet REGISTER MAP CRC VALUE, BITS[15:8] REGISTER Address: 0x089, Reset: 0x0000, Name: RM_CRC_VALUE_H Table 41. Bit Descriptions for RM_CRC_VALUE_H Bits [7:0] Bit Name RM_CRC_VALUE_H Settings 0x0000 to 0xFFFF Description Regmap CRC Value Upper Byte. Regmap CRC Value Upper Byte. Reset 0x0 Access R Reset 0x0 Access RW 0x0 RW LOW NOISE AMPLIFIER GAIN CONTROL REGISTER Address: 0x100, Reset: 0x0000, Name: LNA_GAIN Table 42. Bit Descriptions for LNA_GAIN Bits [7:6] Bit Name LNA4_GAIN Settings 00 01 10 11 [5:4] LNA3_GAIN 00 01 10 11 Description LNA Gain for Channel 4. Gain of 2. Gain of 4. Gain of 8. Gain of 16. LNA Gain for Channel 3. Gain of 2. Gain of 4. Gain of 8. Gain of 16. Rev. 0 | Page 46 of 72 Data Sheet Bits [3:2] Bit Name LNA2_GAIN ADAR7251 Settings 00 01 10 11 [1:0] LNA1_GAIN 00 01 10 11 Description LNA Gain for Channel 2. Gain of 2. Gain of 4. Gain of 8. Gain of 16. LNA Gain for Channel 1. Gain of 2. Gain of 4. Gain of 8. Gain of 16. Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 RW PROGRAMMABLE GAIN AMPLIFIER GAIN CONTROL REGISTER Address: 0x101, Reset: 0x0000, Name: PGA_GAIN Table 43. Bit Descriptions for PGA_GAIN Bits [7:6] Bit Name PGA4_GAIN Settings 00 01 10 11 [5:4] PGA3_GAIN 00 01 10 11 [3:2] PGA2_GAIN 00 01 10 11 Description PGA Gain for Channel 4. Gain of 1.4. Gain of 2.8. Gain of 5.6. Gain of 11.2. PGA Gain for Channel 3. Gain of 1.4. Gain of 2.8. Gain of 5.6. Gain of 11.2. PGA Gain for Channel 2. Gain of 1.4. Gain of 2.8. Gain of 5.6. Gain of 11.2. Rev. 0 | Page 47 of 72 ADAR7251 Bits [1:0] Bit Name PGA1_GAIN Data Sheet Settings 00 01 10 11 Description PGA Gain for Channel 1. Gain of 1.4. Gain of 2.8. Gain of 5.6. Gain of 11.2. Reset 0x0 Access RW Reset 0x2 Access RW 0x2 RW SIGNAL PATH FOR ADC 1 THROUGH ADC 4 REGISTER Address: 0x102, Reset: 0x2222, Name: ADC_ROUTING1_4 Table 44. Bit Descriptions for ADC_ROUTING1_4 Bits [14:12] Bit Name ADC4_SRC Settings 000 001 010 011 100 101 [10:8] ADC3_SRC 000 001 010 011 100 101 Description Signal Source for ADC4. ADC Disabled. LNA PGA EQ Path. LNA PGA Path (Bypass EQ). Bypass LNA, PGA, and EQ. Swap Channels. Use Test Pin. Signal Source for ADC3. ADC Disabled. LNA PGA EQ Path. LNA PGA Path (Bypass EQ). Bypass LNA, PGA, and EQ. Swap Channels. Use Test Pin. Rev. 0 | Page 48 of 72 Data Sheet Bits [6:4] Bit Name ADC2_SRC ADAR7251 Settings 000 001 010 011 100 101 [2:0] ADC1_SRC 000 001 010 011 100 101 Description Signal Source for ADC2. ADC Disabled. LNA PGA EQ Path. LNA PGA Path (Bypass EQ). Bypass LNA, PGA, and EQ. Swap Channels. Use Test Pin. Signal Source for ADC1. ADC Disabled. LNA PGA EQ Path. LNA PGA Path (Bypass EQ). Bypass LNA, PGA, and EQ. Swap Channels. Use Test Pin. Reset 0x2 Access RW 0x2 RW Reset 0x3 Access RW DECIMATOR RATE CONTROL REGISTER Address: 0x140, Reset: 0x0003, Name: DECIM_RATE Table 45. Bit Descriptions for DECIM_RATE Bits [2:0] Bit Name DECIM_RATE Settings 000 001 010 011 100 101 110 111 Description Decimator Rate. Reserved. Reserved. 1.8 MSPS. 1.2 MSPS. 900 kSPS. 600 kSPS. 450 kSPS. 300 kSPS. Rev. 0 | Page 49 of 72 ADAR7251 Data Sheet HIGH PASS FILTER CONTROL REGISTER Address: 0x141, Reset: 0x0018, Name: HIGH_PASS Table 46. Bit Descriptions for HIGH_PASS Bits 6 Bit Name PHASE_EQ Settings 0 1 [5:1] HP_SHIFT 00000 01011 01100 01101 01110 01111 10000 10001 10010 0 ENABLE_HP 0 1 Description Enable the 4th-Order EQ. Phase EQ is Off. Phase EQ is On. Shift Value for High-Pass Filter. DC Cal Mode. HP Shift Value 11. HP Shift Value 12. HP Shift Value 13. HP Shift Value 14. HP Shift Value 15. HP Shift Value 16. HP Shift Value 17. HP Shift Value 18. Enables the High-Pass Filter. HP Filter is Off. HP Filter is On. Rev. 0 | Page 50 of 72 Reset 0x0 Access RW 0x0C RW 0x0 RW Data Sheet ADAR7251 DAQ MODE CONTROL REGISTER Address: 0x143, Reset: 0x0000, Name: ACK_MODE Table 47. Bit Descriptions for ACK_MODE Bits [5:4] Bit Name ACK_CYCLES Settings 00 01 10 11 [3:1] ACK_OUT_RATE 000 001 010 011 100 101 110 111 0 ACK_MODE 0 1 Description Selects the Number of Acquisition Cycles in DAQ Mode. 16-Cycle Acquisition. 24-Cycle Acquisition. 32-Cycle Acquisition. Reserved. Selects the Data Output Rate in DAQ Mode. 57.6 MHz. 38.4 MHz. 28.8 MHz. 19.2 MHz. 14.4 MHz. 9.6 MHz. 7.2 MHz. 4.8 MHz. Selects the Data Conversion Mode. Default Continuous Mode. DAQ Mode. Rev. 0 | Page 51 of 72 Reset 0x0 Access RW 0x0 RW 0x0 RW ADAR7251 Data Sheet DECIMATOR TRUNCATE CONTROL REGISTER Address: 0x144, Reset: 0x0002, Name: TRUNCATE_MODE Table 48. Bit Descriptions for TRUNCATE_MODE Bits [1:0] Bit Name TRUNC_MODE Settings 00 01 10 11 Description Decimator Word Truncation Method. Truncate LSBs. Round to Zero. Normal Rounding. Reserved. Reset 0x2 Access RW Reset 0x0 Access RW 0x0 RW SERIAL OUTPUT PORT CONTROL REGISTER Address: 0x1C0, Reset: 0x0000, Name: SERIAL_MODE Table 49. Bit Descriptions for SERIAL_MODE Bits 6 Bit Name CLK_SRC Settings 0 1 5 LRCLK_MODE 0 1 Description SCLK_ADC Source. Slave. Master. Frame Sync (FS_ADC) Mode. 50/50 Duty Cycle Clock. Pulse. Rev. 0 | Page 52 of 72 Data Sheet Bits 4 Bit Name LRCLK_POL ADAR7251 Settings 0 1 3 BCLK_POL 0 1 2 DATA_FMT 0 1 [1:0] TDM_MODE 00 01 10 11 Description Frame Sync (FS_ADC) Polarity. Negative Polarity. Positive Polarity. SCLK_ADC Polarity. Negative Polarity. Positive Polarity. Serial Data Format. Left Justified Format. I2S Format—Data Delayed by 1 SCLK Period. Channels per Frame and SCLK Cycles per Channel. 2 Channels, 16 Bits per Channel. 4 Channels, 16 Bits per Channel. Reserved. Reserved. Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 RW PARALLEL PORT CONTROL REGISTER Address: 0x1C1, Reset: 0x0000, Name: PARALLEL_MODE Table 50. Bit Descriptions for PARALLEL_MODE Bits 2 Bit Name PAR_NIBBLE Settings 1 0 1 PAR_ENDIAN 0 1 0 PAR_CHANNELS 1 0 Description Enable Nibble Mode. Byte Mode. Nibble Mode. High Byte/Low Byte Order. High Byte Goes Out First. Low Byte Goes Out First. Number of Channels to be Output. 2 Channels. 4 Channels. Rev. 0 | Page 53 of 72 ADAR7251 Data Sheet ADC DIGITAL OUTPUT MODE REGISTER Address: 0x1C2, Reset: 0x0000, Name: OUTPUT_MODE Table 51. Bit Descriptions for OUTPUT_MODE Bits 1 0 Bit Name CS_OVERRIDE Settings Reset 0x0 Access RW 0 1 Description CONV_START Enable or Disable. CONV_START Function is Enabled CONV_START Function is Disabled Serial or Parallel Mode. Serial Mode Parallel Mode 0x0 RW 0 1 OUTPUT_MODE AUXILIARY ADC READ VALUE REGISTERS Address: 0x200, Reset: 0x0000, Name: ADC_READ0 This register contains the output data of the auxiliary ADC for the given channel. Each of the two channels are updated once per sample frame. Table 52. Bit Descriptions for ADC_READ0 Bits [9:0] Bit Name ADC_VALUE Settings Description ADC Input Value. Instantaneous value of the sampled data on the ADC input. Rev. 0 | Page 54 of 72 Reset 0x000 Access RW Data Sheet ADAR7251 Address: 0x201, Reset: 0x0000, Name: ADC_READ1 This register contains the output data of the auxiliary ADC for the given channel. Each of the two channels are updated once per sample frame. Table 53. Bit Descriptions for ADC_READ1 Bits [9:0] Bit Name ADC_VALUE Settings Description ADC Input Value. Instantaneous value of the sampled data on the ADC input. Reset 0x000 Access RW Reset 0x0 Access RW AUXILIARY ADC SAMPLE RATE SELECTION REGISTER Address: 0x210, Reset: 0x0000, Name: ADC_SPEED This register sets the sample rate for the auxiliary ADCs. Table 54. Bit Descriptions for ADC_SPEED Bits [1:0] Bit Name ADC_SPEED Settings 00 01 10 11 Description ADC Speed. Test register allowing the auxiliary ADCs to be sampled at double rate or half rate. 112.5 kHz Sample Rate. 225 kHz Sample Rate. 450 kHz Sample Rate. Reserved. Rev. 0 | Page 55 of 72 ADAR7251 Data Sheet AUXILIARY ADC MODE REGISTER Address: 0x211, Reset: 0x0000, Name: ADC_MODE Table 55. Bit Descriptions for ADC_MODE Bits [2:1] Bit Name AUX_INPUT_SEL Settings 00 01 0 AUX_ADC_MODE 0 1 Description AUX Input Selection. AUXIN1 pin used for ADC AUXIN2 pin used for ADC AUX ADC Mode. Both pins are sampled once every sample period. Only one pin is sampled twice every sample period. The pin is selected based on AUX_INPUT_SEL Bits[2:1]. Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW MPX PIN MODES REGISTERS Address: 0x250, Reset: 0x0000, Name: MP0_MODE Table 56. Bit Descriptions for MP0_MODE Bits [5:2] Bit Name DEBOUNCE_VALUE Settings 0001 0010 0011 0100 0101 0110 Description Debounce Time Setting. 0.3 ms Debounce. 0.6 ms Debounce. 0.9 ms Debounce. 5.0 ms Debounce. 10.0 ms Debounce. 20.0 ms Debounce. Rev. 0 | Page 56 of 72 Data Sheet Bits Bit Name [1:0] MP_MODE ADAR7251 Settings 0111 0000 01 10 00 Description 40.0 ms Debounce. No Debounce. Mode Setting for MP. Pin Used as an Input. Pin Used as an Output. Primary Function of the Pin is Selected. Reset Access 0x0 RW Reset 0x0 Access RW 0x0 RW Address: 0x251, Reset: 0x0000, Name: MP1_MODE Table 57. Bit Descriptions for MP1_MODE Bits [5:2] Bit Name DEBOUNCE_VALUE Settings 0001 0010 0011 0100 0101 0110 0111 0000 [1:0] MP_MODE 01 10 00 Description Debounce Time Setting. 0.3 ms Debounce. 0.6 ms Debounce. 0.9 ms Debounce. 5.0 ms Debounce. 10.0 ms Debounce. 20.0 ms Debounce. 40.0 ms Debounce. No Debounce. Mode setting for MP. Pin Used as an Input. Pin Used as an Output. Primary Function of the Pin is Selected. Rev. 0 | Page 57 of 72 ADAR7251 Data Sheet MP WRITE VALUE REGISTERS Address: 0x260, Reset: 0x0000, Name: MP0_WRITE Table 58. Bit Descriptions for MP0_WRITE Bits 0 Bit Name MP_REG_WRITE Settings 0 1 Description Multipurpose Pin Write Value. MP Pin Output Off. MP Pin Output On. Reset 0x0 Access W Reset 0x0 Access W Reset 0x0 Access R Address: 0x261, Reset: 0x0000, Name: MP1_WRITE Table 59. Bit Descriptions for MP1_WRITE Bits 0 Bit Name MP_REG_WRITE Settings 0 1 Description Multipurpose Pin Write Value. MP Pin Output Off. MP Pin Output On. MP READ VALUE REGISTERS Address: 0x270, Reset: 0x0000, Name: MP0_READ Table 60. Bit Descriptions for MP0_READ Bits 0 Bit Name MP_REG_READ Settings 0 1 Description Multipurpose Pin Read Value. MP Pin Input Low. MP Pin Input High. Rev. 0 | Page 58 of 72 Data Sheet ADAR7251 Address: 0x271, Reset: 0x0000, Name: MP1_READ Table 61. Bit Descriptions for MP1_READ Bits 0 Bit Name MP_REG_READ Settings 0 1 Description Multipurpose Pin Read Value. MP Pin Input Low. MP Pin Input High. Reset 0x0 Access R Reset 0x0 Access RW 0x0 RW SPI_CLK PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x280, Reset: 0x0000, Name: SPI_CLK_PIN Table 62. Bit Descriptions for SPI_CLK_PIN Bits 2 Bit Name SPI_CLK_PULL Settings 0 1 [1:0] SPI_CLK_DRIVE 00 01 10 11 Description SPI_CLK Pull-Down. Pull-Down Disabled. Pull-Down Enabled. SPI_CLK Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 59 of 72 ADAR7251 Data Sheet SPI_MISO PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x281, Reset: 0x0000, Name: MISO_PIN Table 63. Bit Descriptions for MISO_PIN Bits 2 Bit Name MISO_PULL Settings 0 1 [1:0] MISO_DRIVE 00 01 10 11 Description SPI_MISO Pull-Down. Pull-Down Disabled. Pull-Down Enabled. SPI_MISO Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW 0x0 RW Reset 0x1 Access RW SPI_SS PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x282, Reset: 0x0004, Name: SS_PIN Table 64. Bit Descriptions for SS_PIN Bits 2 Bit Name SS_PULL Settings 0 1 Description SPI_SS Pull-Up. Pull-Up Disabled. Pull-Up Enabled. Rev. 0 | Page 60 of 72 Data Sheet Bits [1:0] Bit Name SS_DRIVE ADAR7251 Settings 00 01 10 11 Description SPI_SS Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW Reset 0x0 Access RW 0x0 RW SPI_MOSI PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x283, Reset: 0x0000, Name: MOSI_PIN Table 65. Bit Descriptions for MOSI_PIN Bits 2 Bit Name MOSI_PULL Settings 0 1 [1:0] MOSI_DRIVE 00 01 10 11 Description SPI_MOSI Pull-Down. Pull-Down Disabled. Pull-Down Enabled. SPI_MOSI Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 61 of 72 ADAR7251 Data Sheet ADDR15 PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x284, Reset: 0x0000, Name: ADDR15_PIN This register also controls the drive strength setting for ADC_DOUT6 in PPI mode. Table 66. Bit Descriptions for ADDR15_PIN Bits 2 Bit Name ADDR15_PULL Settings 0 1 [1:0] ADDR15_DRIVE 00 01 10 11 Description ADDR15 Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADDR15 Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW 0x0 RW Reset 0x1 Access RW FAULT PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x285, Reset: 0x0004, Name: FAULT_PIN Table 67. Bit Descriptions for FAULT_PIN Bits 2 Bit Name FAULT_PULL Settings 0 1 Description FAULT Pull-Up. Pull-Up Disabled. Pull-Up Enabled. Rev. 0 | Page 62 of 72 Data Sheet Bits [1:0] Bit Name FAULT_DRIVE ADAR7251 Settings 00 01 10 11 Description FAULT Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW Reset 0x0 Access RW 0x0 RW FS_ADC PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x286, Reset: 0x0000, Name: FS_ADC_PIN This register also controls the drive strength setting for ADC_DOUT7 in PPI mode. Table 68. Bit Descriptions for FS_ADC_PIN Bits 2 Bit Name FS_ADC_PULL Settings 0 1 [1:0] FS_ADC_DRIVE 00 01 10 11 Description FS_ADC Pull-Down. Pull-Down Disabled. Pull-Down Enabled. FS_ADC Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 63 of 72 ADAR7251 Data Sheet CONV_START PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x287, Reset: 0x0004, Name: CS_PIN Table 69. Bit Descriptions for CS_PIN Bits 2 Bit Name CS_PULL Settings 0 1 [1:0] CS_DRIVE 00 01 10 11 Description CONV_START Pull-Up. Pull-Up Disabled. Pull-Up Enabled. CONV_START Drive Strength. Lowest. Low. High. Highest. Reset 0x1 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW SCLK_ADC PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x288, Reset: 0x0000, Name: SCLK_ADC_PIN Table 70. Bit Descriptions for SCLK_ADC_PIN Bits 2 Bit Name SCLK_ADC_PULL Settings 0 1 [1:0] SCLK_ADC_DRIVE 00 01 10 11 Description SCLK_ADC Pull-Down. Pull-Down Disabled. Pull-Down Enabled. SCLK_ADC Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 64 of 72 Data Sheet ADAR7251 ADC_DOUTX PINS DRIVE STRENGTH AND SLEW RATE REGISTERS The following registers refer to the ADC_DOUTx pins. This range includes ADC_DOUT0 through ADC_DOUT5. For Bits[1:0] and Bit 2 in Table 71 through Table 76, ADC_DOUT refers to the ADC_DOUTx pin defined by the register name. Address: 0x289, Reset: 0x0000, Name: ADC_DOUT0_PIN Table 71. Bit Descriptions for ADC_DOUT0_PIN Bits 2 Bit Name ADC_DOUT_PULL Settings 0 1 [1:0] ADC_DOUT_DRIVE 00 01 10 11 Description ADC_DOUT Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADC_DOUT Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW Address: 0x28A, Reset: 0x0000, Name: ADC_DOUT1_PIN Table 72. Bit Descriptions for ADC_DOUT1_PIN Bits 2 Bit Name ADC_DOUT_PULL Settings 0 1 [1:0] ADC_DOUT_DRIVE 00 01 10 11 Description ADC_DOUT Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADC_DOUT Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 65 of 72 ADAR7251 Data Sheet Address: 0x28B, Reset: 0x0000, Name: ADC_DOUT2_PIN Table 73. Bit Descriptions for ADC_DOUT2_PIN Bits 2 Bit Name ADC_DOUT_PULL Settings 0 1 [1:0] ADC_DOUT_DRIVE 00 01 10 11 Description ADC_DOUT Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADC_DOUT Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW Address: 0x28C, Reset: 0x0000, Name: ADC_DOUT3_PIN Table 74. Bit Descriptions for ADC_DOUT3_PIN Bits 2 Bit Name ADC_DOUT_PULL Settings 0 1 [1:0] ADC_DOUT_DRIVE 00 01 10 11 Description ADC_DOUT Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADC_DOUT Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 66 of 72 Data Sheet ADAR7251 Address: 0x28D, Reset: 0x0000, Name: ADC_DOUT4_PIN Table 75. Bit Descriptions for ADC_DOUT4_PIN Bits 2 Bit Name ADC_DOUT_PULL Settings 0 1 [1:0] ADC_DOUT_DRIVE 00 01 10 11 Description ADC_DOUT Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADC_DOUT Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW Address: 0x28E, Reset: 0x0000, Name: ADC_DOUT5_PIN Table 76. Bit Descriptions for ADC_DOUT5_PIN Bits 2 Bit Name ADC_DOUT_PULL Settings 0 1 [1:0] ADC_DOUT_DRIVE 00 01 10 11 Description ADC_DOUT Pull-Down. Pull-Down Disabled. Pull-Down Enabled. ADC_DOUT Drive Strength. Lowest. Low. High. Highest. Rev. 0 | Page 67 of 72 ADAR7251 Data Sheet DATA_READY PIN DRIVE STRENGTH AND SLEW RATE REGISTER Address: 0x291, Reset: 0x0000, Name: DATA_READY_PIN Table 77. Bit Descriptions for DATA_READY_PIN Bits 2 Bit Name DATA_READY_PULL Settings 0 1 [1:0] DATA_READY_DRIVE 00 01 10 11 Description DATA_READY Pull-Down. Pull-Down Disabled. Pull-Down Enabled. DATA_READY Drive Strength. Lowest. Low. High. Highest. Reset 0x0 Access RW 0x0 RW Reset 0x0 Access RW 0x0 RW XTAL ENABLE AND DRIVE REGISTER Address: 0x292, Reset: 0x0000, Name: XTAL_CTRL Table 78. Bit Descriptions for XTAL_CTRL Bits 1 Bit Name XTAL_DRV Settings 0 1 0 XTAL_ENB 0 1 Description Drive Strength of XOUT Pin. Low. High. Crystal Oscillator Enable. XTAL Enable. XTAL Disable. Rev. 0 | Page 68 of 72 Data Sheet ADAR7251 ADC TEST REGISTER Address: 0x301, Reset: 0x0304, Name: ADC_SETTING1 Table 79. Bit Descriptions for ADC_SETTING1 Bits [9:8] Bit Name EQ_CAP_CTRL Settings 00 01 10 11 2 PDETECT_EN 0 1 1 PERFOM_IMPROVE1 0 1 Description HPF Corner Frequency Select. EQ HPF corner frequency 54 kHz EQ HPF corner frequency 45 kHz EQ HPF corner frequency 37 kHz EQ HPF corner frequency 32 kHz Peak Detect Enable. Peak Detect Disable Peak Detect Enable Performance Improvement Setting 1. Performance Improvement Setting 1 Enable Performance Improvement Setting 1 Disable (Use this value) Reset 0x3 Access RW 0x1 RW 0x0 RW Reset 0x00 Access RW Address: 0x308, Reset: 0x0000, Name: ADC_SETTING2 Table 80. Bit Descriptions for ADC_SETTING2 Bits [4:0] Bit Name PERFORM_IMPROVE2 Settings 0xxxx 1xxxx 10011 Description Performance Improvement Setting 2. Performance Improvement Setting 2a. Performance Improvement Setting 2b. Performance Improvement Setting 2c (Use This Value) Rev. 0 | Page 69 of 72 ADAR7251 Data Sheet Address: 0x30A, Reset: 0x0009, Name: ADC_SETTING3 Table 81. Bit Descriptions for ADC_SETTING3 Bits [3:2] Bit Name PERFORM_IMPROVE5 Settings 10 00 0 PERFORM_IMPROVE4 0 1 Description Performance Improvement Setting 5. Reserved. Performance Improvement Setting 5 (Use This Setting). Performance Improvement Setting 4. Performance Improvement Setting 4 Disable. Performance Improvement Setting 4 Enable (Use This Setting). Reset 0x2 Access RW 0x1 RW Reset 0x3 Access RW Reset 0x0 Access RW DIGITAL FILTER SYNC ENABLE REGISTER Address: 0x30E, Reset: 0x0003, Name: DEJITTER_WINDOW Table 82. Bit Descriptions for DEJITTER_WINDOW Bits [3:0] Bit Name DEJITTER Settings 0000 0011 Description Digital Filter Sync Enable. Digital Filter Sync Disable. Digital Filter Sync Enable. CRC ENABLE/DISABLE REGISTER Address: 0xFD00, Reset: 0x0000, Name: CRC_EN Table 83. Bit Descriptions for CRC_EN Bits 0 Bit Name CRC_EN Settings Description 0 1 CRC Enable CRC Disable Rev. 0 | Page 70 of 72 Data Sheet ADAR7251 TYPICAL APPLICATION CIRCUIT C21 10µF R5 SPI_CLK AIN2P MICROCONTROLLER SPI_MOSI AIN2N SPI_MISO FAULT ADAR7251 AIN3P IOVDD C9 AIN3N R3 ADDR15 AIN4P R4 C12 AIN4N AUXIN1 ADC_DOUT0 AUX INPUTS ADC_DOUT1 AUXIN2 FS_ADC CM DATA_READY C17 C18 DGND2 DGND1 PLLGND AGND3 R1 R2 C20 C19 C1, C2, C4, C5, C7, C8, C10, C11: SEE HIGH-PASS FILTER (HPF) SECTION C3, C6, C9, C12: SEE LOW-PASS FILTER (LPF) SECTION C17, C18: 12pF TO 18pF, SELECT BASED ON CRYSTAL R1: 100Ω TYPICAL. SELECT BASED ON CRYSTAL C19: 5.6nF C20: 390pF R2: 1kΩ R3, R4: 10kΩ; USE EITHER PULL-UP OR PULL-DOWN BASED ON DEVICE ADDRESS R5, R6: 10kΩ TYPICAL CONV_START AND DATA_READY SIGNALS MAY NOT BE NECESSARY, SEE ADC SERIAL MODE SECTION FS_ADC AND SCLK_ADC DIRECTION DEPENDS ON THE MASTER OR SLAVE MODE Y1: 19.2MHz TYPICAL. ACCEPTABLE RANGE IS 16MHz TO 54MHz. ALTERNATELY CLOCK AVAILABLE IN THE SYSTEM CAN BE CONNECTED TO XIN. Figure 60. Typical Application Circuit, 4-Channel, Serial Mode Rev. 0 | Page 71 of 72 12357-045 Y1 AGND2 BIASN XIN C16 470nF DSP CONV_START BIASP AGND1 AVDDx C15 470nF SCLK_ADC PLLFILT C14 100nF XOUT C13 10µF IOVDD2 IOVDD1 C23 100nF C24 10µF C25 100nF C26 100nF C27 10µF C29 10µF C28 100nF PLLVDD DVDD1 DVDD2 R6 SPI_SS C6 C10 C11 C30 100nF AIN1N C7 C8 AVDD3 C3 IOVDD DGND3 FROM MMIC C31 10µF C32 100nF AIN1P C4 C5 REGOUT_DIGITAL C2 AVDD2 C33 10µF C34 100nF AVDD1 C35 10µF C1 C22 100nF IOVDD AVDD ADAR7251 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 7.10 7.00 SQ 6.90 0.30 0.25 0.20 37 PIN 1 INDICATOR 48 1 36 0.50 BSC 5.70 5.60 SQ 5.50 EXPOSED PAD 0.30 MIN 12 25 TOP VIEW 0.80 0.75 0.70 0.075~0.150 (Step dimension) 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PKG-4277 01-28-2014-A SEATING PLANE 0.51 0.45 0.41 Figure 61. 48-Lead Lead Frame Chip Scale Package [LFCSP_SS] 7 mm × 7 mm Body, With Side Solderable Leads (CS-48-1) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 ADAR7251WBCSZ ADAR7251WBCSZ-RL EVAL-ADAR7251Z 1 2 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 48-Lead LFCSP_SS 48-Lead LFCSP_SS, 13” Tape and Reel Evaluation Board Package Option CS-48-1 CS-48-1 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADAR7251W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12357-0-11/14(0) Rev. 0 | Page 72 of 72