AS998/A PWM Controller Preliminary Specification SEMICONDUCTOR Description • Low start-up current 64 µA (Typ) • Low running current 2 mA (Typ) • Low power light load mode • Low power standby when OV is activated The AS998/AS998A is an IC intended for use as a PWM controller for switch mode power supplies. The device is particularly suited as a primary side controller for adapter, printer, peripheral, mobile chargers and desktop auxiliary power supplies. The AS998/AS998A is manufactured in BICMOS technology and exhibits very low start-up and operating power. This allows the device to be suitable in applications where stringent standby or Blue Angel criteria are required. • Extended commercial operating temperature range: 0 to 105°C • On-board fixed frequency oscillator 100 kHz (Typ) • Frequency randomizer to reduce EMC emissions • Dedicated OV shutdown pin • On-board voltage ramp compensation • On-board current sensing filtering • Optional primary side regulation R Many of the external functions associated with PWM controllers have been integrated into the AS998/AS998A allowing the external component count to be significantly reduced. Features such as fixed internal oscillator, internal ramp compensation and current filters all reduce the external support components. IN A The AS998/AS998A has a typical output rise and fall time of 250/210 ns. M Pin Configuration – Y Features Top View 1 Comp 2 E OV 8L SOIC (8D) LI 8L PDIP (8N) 8 VREG 7 VCC OV 1 8 VREG Comp 2 7 VCC 3 6 OUT VFB 3 6 OUT ISENSE 4 5 GND ISENSE 4 5 GND R VFB P Ordering Information AS998/A B 8D Circuit Type: PWM Controller (Models AS998 & AS998A) Packaging Option: T = Tubes N = Tape and Reel (13" Reel Dia.) Temperature Range: B = 0°C to 105°C www.ptcc.com.tw N Package Type: 8D = 8 Pin, Plastic SOIC 8N = 8 Pin, Plastic DIP 233 www.ptcc.com.tw 234 CSNS Comp FB OV Gnd Vdd Vdd > 10 (Turn On) Ref 1 Vcc Current Conveyor > 6.5 (Turn Off) + Vcc Ref 3 Comp 1 Attenuator + LPF RC=3E-7 Vcc Comp 2 Vcc IN OSC Dither I-bias Bias N Bias P Vcc on chip power M OSC Vramp 75% Duty Cycle Fout Vcc LI Ref 1 2 3 Internal Power & Reference PTAT Generator Bandgap E > 14 (OverVolt) R Temp Comp Current Source Vcc Power Management P A CLR Q R R S SET Q Y Output Driver Out Reg AS998/AS998A PWM Controller Functional Block Diagram PWM Controller AS998/AS998A Pin Function Description Pin Number Function OV Overvoltage pin. The OV input/output function is implemented by an on-chip latch. This pin is driven to the Reg voltage if the on-chip circuitry senses a VDD level greater than the OV threshold (VDDov). This error condition stops the part from generating any more output pulses until VDD has been reduced to the VDDul level and then raised as in a normal power-on sequence. Y Alternatively, the OV error condition can be cleared by forcing the OV pin to near ground. The output is immediately enabled following an OV clear function. The OV error condition can also be generated externally by temporarily forcing the OV pin to a voltage greater than the VOV threshold. This will force the part to latch an tion and not generate any more output pulses unless cleared as OV condidescribed. COMP 3 FB 4 CSNS Compensation pin. This pin is the output of the error amplifier and can also be used as an input for an optocoupled control signal to the PWM comparator. Generally this pin is connected to a feedback network to FB. If an optocoupler feedback is used, COMP connects to the collector of the common emitter optocoupler, generally with a pull-up resistor to VDD or Reg. A 2 R 1 Description IN Feedback pin. Inverting input to the error amplifier. This pin is tied to an internal default divider which will tend to regulate VDD at a nominal 11V. M Current sense input. The signal on this pin is fed via a low pass filter to the PWM com-parator. Superimposed on the input to the PWM is a slope compensation ramp derived from the main oscillator. GND 6 OUT 7 VDD R P 8 Circuit common ground. Gate drive output. The current source and sink capability of the output buffer is tailored to minimize EMI. When the IC is not running, this pin is held low so a pull down resistor on the FET gate is not required. E 5 LI In addition to the above, the current sense signal is connected directly to an overcurrent comparator that detects an overload condition and immediately terminates the gate drive pulse with a minimum propagation delay. REG www.ptcc.com.tw Positive supply voltage. An on-board shunt regulator allows this IC to be powered via a simple resistor from a widely varying bias supply. The ICs power management block keeps the part in startup current mode while VDD is ramping up until the part turns on at the UVLhigh threshold. The IC then draws the specified supply current while operating unless VDD drops below the UVLlow threshold. If VDD drops below UVLlow, then the part will return to startup current mode. Voltage regulator. Decoupling pin as required for internal low voltage supply. This pin may be used to source 1mA for the control optocoupler. 235 AS998/AS998A PWM Controller IC Block Diagram Description Power Management This block contains reference generators and comparators to determine the under-voltage shutdown point, the power-on point, the primary regulation operating point, and the overvoltage shutdown point. Internal Power / Reference This block includes a course regulator for on-chip power and cascade voltages for HV circuitry, a bandgap for comparator references, a bias current generator, PTAT, BiasP and BiasN. Y Temperature Compensated Current Source This block generates a constant current as a function of voltage and temperature with no off-chip components. R Oscillator A Mirrored currents from the reference block are used to charge a capacitor to the threshold voltage at which point the direction is switched to an opposing 3X mirror to drive the capacitor to a lower threshold value. This generates a 75% duty cycle digital clock to the output latch, and a 100kHz ramp voltage to be used in the feedback control. IN Feedback Control M This block senses one of the various feedback methods to control the output duty cycle. It includes a current sense, a low pass filter, current amplifier, summing amp, and comparators. This block sums the analog ramp from the OSC, sense, and compensation node voltages into a comparator which triggers the falling edge of the PWM clock signal. This provides supply voltage compensation and load regulation to the power converter system. Out_Drv LI A high speed, high current bipolar output stage capable of providing approximately 500 mA sink and 250 mA source current to charge and discharge the gate of a large power FET. It is understood that the total delay from the comp pin to the output pin should be about 100 ns. Absolute Maximum Ratings E Rating Supply Voltage (Low Impedance Source) Symbol Rating Unit VDD 13 V IDD 15 mA Output Peak Current IOUT 600 mA R Supply Current (High Impedance Source) Regulator Current P Continuous Power at 25°C 8L SOIC IREG 10 mA PD 750 mW 1000 mW Junction Temperature 8L PDIP TJ 150 °C Storage Temperature TSTG – 65 to 150 °C TL 300 °C Lead Temperature, Soldering 10 Seconds Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. www.ptcc.com.tw 236 PWM Controller AS998/AS998A Electrical Characteristics Electrical Characteristics are guaranteed over full junction temperature range (0 to 105°C). Ambient temperature must be derated based on power dissipation and package thermal characteristics. Unless otherwise specified, the conditions of test are VDD = 12 V; OV = 0V, CSNS = 0V. Cload = 1800pf, Creg = 100 nf (AVVD to GND). To start chip, Vdd must be raised above UVLhigh. Symbol Test Condition Min. Startup Current IDDO UVLHIGH Threshold Supply Current IDD No Load 1 Startup Threshold UVLHIGH AS998 UVL off Threshold UVLLOW Bias Current at POS VCLAMP IDD = 10mA No Load 13 Int Regulator Voltage VREG IREG = 1mA 5.5 AS998A Max. 64 100 µA 2 4 mA 9 10 11 V 9.5 10 10.5 8 8.4 V V 14 14.7 V 7.0 V Test Condition Typ. Max. Unit TOSC 8.4V < VDD < 13.3V; 15 cycle avg. - AS998 7.3 9.3 11.7 µs 8.4V < VDD < 13.3V; 15 cycle avg. - AS998A 8.1 9.3 10.7 Modulation Repetition Rate TREP DMAX IN TDEV Max. Duty Cycle A Symbol Mean Period Peak-to-Peak Modulation Peak-to-Peak change in period Error Amplifier Symbol Test Condition M Parameter Min. Unit 6.25 R 7.6 Oscillator Parameter Typ. Y Parameter 15 µs cycles 13.7 16.5 23 % 70 75 78 % Min. Typ. Max. Unit RFB VDD Regulation Point VDDREG FB Threshold VREF COMP = FB, VDD = 12V AVOL No load on COMP 85 dB GBP No load on COMP 10 MHz VCOMPH FB = 2V VCOMPL FB = 3V Gain (DC) Gain-Bandwidth Product E COMP Output High LI FB Divider R COMP Output Low R COMP Source Current COMP Sink Current 100 kΩ 11.4 12 12.6 V 2.37 2.5 2.62 V 4.5 V 100 250 mV ICOMPH COMP = 3V, FB = 2V 25 50 100 µA ICOMPL COMP = 1V, FB = 3V 25 300 500 µA Symbol Test Condition Min. Typ. Max. Unit Current Sense Comparator P Parameter Scaling of COMP to CSNS input 0.4 AC Input Impedance RCSAC Fin ≥ FCO 100 kΩ Input Filter FCS Time Constant 320 ns Prop. Delay to Output tpd1 700 ns www.ptcc.com.tw 237 AS998/AS998A PWM Controller Electrical Characteristics (cont.) Over Current Comparator Parameter Symbol Test Condition VCSTH tpd2 COMP = 1V, FB = 3V FB = 2, Vcs step to 1.65V, from 50% point on CSNS input to 90% point on output H to L transistion Symbol Test Condition Min. OV VDD Threshold VDDOV Forcing VDD pin 13 OV Threshold VOV Forcing OV pin OV Latch State Low OVRN OV = Reg - 1V, Equiv. R to Reg OV Latch State High OVRP OV = 1V, Equiv. R to Gnd OV Hi Impedance Pull-up OVHI OV = 1V, IDD = 10mA OV Unlatch Threshold VDDUL VDD dropped until latch fails Comparator Threshold Propagation Delay to Output Min. Typ. Max. Unit 1.25 100 150 V ns Typ. Max. Unit 14 14.7 R V V 4 8 16 kΩ 4 8 16 kΩ 0.3 1 µA 4.75 5 5.25 V Min. Typ. Max. Unit 1.7 V Test Condition VOFF IOUT = 100µA Output Rise Time tr T = 25°C, 10% - 90% 170 250 290 ns Output Fall Time tf T = 25°C, 10% - 90% 140 210 240 ns M Symbol Max. “Off State” Voltage P R E LI Parameter IN Output 3.5 A Parameter Y Over Voltage Input www.ptcc.com.tw 238