View detail for SAM9263

AT91SAM ARM-based Embedded MPU
SAM9263
Description
The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It
also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent
bottlenecks, thus guaranteeing maximum performance.
The AT91SAM9263 embeds an LCD Controller supported by a Two D Graphics Controller
and a 2-channel DMA Controller, and one Image Sensor Interface. It also integrates several
standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multimedia Card interface and one CAN Controller.
When coupled with an external GPS engine, the AT91SAM9263 provides the ideal solution
for navigation systems.
This is a summary document.
The complete document is
available on the Atmel website
at www.atmel.com.
6249IS–ATARM–28-Jan-13
1. Features
• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
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– DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 220 MIPS at 200 MHz
– Memory Management Unit
– EmbeddedICE™, Debug Communication Channel Support
– Mid-level Implementation Embedded Trace Macrocell™
Bus Matrix
– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
– Boot Mode Select Option, Remap Command
Embedded Memories
– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed
– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
Dual External Bus Interface (EBI0 and EBI1)
– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash®
– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control
Twenty Peripheral DMA Controller Channels (PDC)
LCD Controller
– Supports Passive or Active Displays
– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers
Two D Graphics Accelerator
– Line Draw, Block Transfer, Clipping, Commands Queuing
Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
Ethernet MAC 10/100 Base-T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
Reset Controller (RSTC)
– Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
Shutdown Controller (SHDWC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
Clock Generator (CKGR)
– 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
2
– 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs
• Power Management Controller (PMC)
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– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Four Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose Two-wire UART Serial Communication
Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
Two Real-time Timers (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE)
– 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
One Part 2.0A and Part 2.0B-compliant CAN Controller
– 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
Two Multimedia Card Interface (MCI)
– SDCard/SDIO and MultiMediaCard™ Compliant
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
– Two SDCard Slots Support on eAch Controller
Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Two Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
One Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
One Four-channel 16-bit PWM Controller (PWMC)
One Two-wire Interface (TWI)
– Master Mode Support, All Two-wire Atmel® EEPROMs Supported
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Required Power Supplies
– 1.08V to 1.32V for VDDCORE and VDDBU
– 3.0V to 3.6V for VDDOSC and VDDPLL
– 2.7V to 3.6V for VDDIOP0 (Peripheral I/Os)
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os)
Available in a 324-ball TFBGA Green Package
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
3
NRST
DDCORE
S DN
W UP
IN32
OUT32
DDBU
TWI
MCI0 , MCI 1
USART0
USART1
USART2
MCI0
MCI1
PIOE
PIOD
PIOC
PIOB
PIOA
PDC
RSTC
S DWC
RTT1
RTT0
DTCM
PDC
SPI0 , SPI1
SPI0
SPI1
I
D
ETM
PWMC
Peripheral
Bridge
DCache
16 bytes
Bus Interface
MMU
ROM
128 bytes
SRAM
16 bytes
CAN
Fast SRAM
80 bytes
ITCM
PDC
POR
POR
OSC
PIT
20GPREG
OSC
IN
OUT
PMC
ICache
16 bytes
ARM926EJ-S Processor
TCM Interface
In-Circuit
Emulator
JTAG Boundary Scan
N
T
TDRS
T
TDI
O
TM
TC S
TC0
TC1
TC2
FIFO
AC97C
PDC
20-channel
Peripheral
DMA
FIFO
PDC
SSC0
SSC1
APB
DMA
Transc.
DMA
DMA
USB
O CI
Transc. Transc.
Image
Sensor
Interface
2D
Graphics
Controller
DMA
FIFO
USB
Device
Port
DMA
10/100 Ethernet
MAC
2-channel
9-layer Bus Matrix
DMA
LUT
LCD
Controller
D
B0
-D
DA C B3
0- D B
D
A
C 3
DA
C
TW
C TW D
T
C
RTS0C
S C S 0- T S
R 2
R 0 -S T S
D C 2
T 0- 2
D RD
0- 2
T
D
2
C
A
C N
AN T
R
N
P
N CS
P 3
N CS
P 2
N C
P CS 1
SP S0
C
M
O
M SI
PW
IS
O
M
0PW
TC
M
L
3
T 0
I
O -T C
TI A 0 L 2
O -T
B 0 IO
T A2
AC IOB
2
AC97C
AC 97
F
AC97RS
9
T 7T
0
T F -T
TD 0-T1
R 0 -T F 1
D
D D
M
AR RF0-R 1
0 R 0 D1
D 0- -RF
M R 1
AR 1
3
DDCORE
PLLB
PLLRCB
WDT
PLLA
PLLRCA
DBGU
DR D
DT D
PC 0-PC 3
PDC
AIC
System
Controller
FI
IR 0-IR 1
TST
L
SE
RT
JT C
AG
SLA E
IS
I D IS
0- I P
IS ISI C
I D
IS S 11
I NC
S
IS NC
IM
C
MASTER
TC
TS L
T NC
P
TPS0
0 TP
BM -TP S2
S 15
LC
LCDD
0
LCD S -LC
LCD S NC DD
L D NC 23
D
C
O
LCDD TC
D EN
C
ET C
ET C E
EC EN R C
R -E
ER S- T E -ER
E
E
ER ER CO R FC
- L
ET 0-E ER
R D
EM 0-E 3
T
E DC 3
M
EF DIO
10
0
D
D
D P
D
M
D
P
D A
M
A
D
PB
D
M
B
ECC
Controller
Static
Memory
Controller
SDRAM
Controller
NAND Flash
EBI1
ECC
Controller
Static
Memory
Controller
SDRAM
Controller
CompactFlash
NAND Flash
EBI0
D0-D15
A0/NBS0
A1/NWR2
A2-A15/A18-A20
A16/BA0
A17/BA1
NCS0
NRD
NWR0/NWE
NWR1/NBS1
SDC
A21/NANDALE
A22/NANDCLE
NWAIT
NWR3/NBS3
NCS1/SDCS
NCS2/NANDCS
D16-D31
SDC E
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
EBI1
EBI0
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15, A18-A20
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD
NWR0/NWE
NWR1/NBS1
NWR3/NBS3
SDC , SDC E
RAS, CAS
SDWE, SDA10
NANDOE, NANDWE
A21/NANDALE
A22/NANDCLE
NWAIT
A23-A24
NCS4/CFCS0
NCS5/CFCS1
NCS3/NANDCS
A25/CFRNW
CFCE1-CFCE2
D16-D31
NCS2
2.
AT91SAM9263 Block Diagram
Figure 2-1. AT91SAM9263 Block Diagram
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
4
3.
Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1.
Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Power Supplies
VDDIOM0
EBI0 I/O Lines Power Supply
Power
1.65V to 3.6V
VDDIOM1
EBI1 I/O Lines Power Supply
Power
1.65V to 3.6V
VDDIOP0
Peripherals I/O Lines Power Supply
Power
2.7V to 3.6V
VDDIOP1
Peripherals I/O Lines Power Supply
Power
1.65V to 3.6V
VDDBU
Backup I/O Lines Power Supply
Power
1.08V to 1.32V
VDDPLL
PLL Power Supply
Power
3.0V to 3.6V
VDDOSC
Oscillator Power Supply
Power
3.0V to 3.6V
VDDCORE
Core Chip Power Supply
Power
1.08V to 1.32V
GND
Ground
Ground
GNDPLL
PLL Ground
Ground
GNDBU
Backup Ground
Ground
Clocks, Oscillators and PLLs
XIN
Main Oscillator Input
Input
XOUT
Main Oscillator Output
XIN32
Slow Clock Oscillator Input
XOUT32
Slow Clock Oscillator Output
PLLRCA
PLL A Filter
Input
PLLRCB
PLL B Filter
Input
PCK0 - PCK3
Programmable Clock Output
Output
Input
Output
Output
Shutdown, Wakeup Logic
SHDN
Shutdown Control
WKUP
Wake-up Input
Driven at 0V only. Do not tie
over VDDBU.
Output
Accepts between 0V and
VDDBU.
Input
ICE and JTAG
NTRST
Test Reset Signal
Input
Low
Pull-up resistor
TCK
Test Clock
Input
No pull-up resistor
TDI
Test Data In
Input
No pull-up resistor
TDO
Test Data Out
TMS
Test Mode Select
Input
No pull-up resistor
JTAGSEL
JTAG Selection
Input
Pull-down resistor. Accepts
between 0V and VDDBU.
RTCK
Return Test Clock
Output
Output
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
5
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Embedded Trace Module - ETM
TSYNC
Trace Synchronization Signal
Output
TCLK
Trace Clock
Output
TPS0 - TPS2
Trace ARM Pipeline Status
Output
TPK0 - TPK15
Trace Packet Port
Output
Reset/Test
NRST
Microcontroller Reset
I/O
TST
Test Mode Select
Input
BMS
Boot Mode Select
Input
Low
Pull-up resistor
Pull-down resistor
Debug Unit - DBGU
DRXD
Debug Receive Data
Input
DTXD
Debug Transmit Data
Output
Advanced Interrupt Controller - AIC
IRQ0 - IRQ1
External Interrupt Inputs
Input
FIQ
Fast Interrupt Input
Input
PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE
PA0 - PA31
Parallel IO Controller A
I/O
Pulled-up input at reset
PB0 - PB31
Parallel IO Controller B
I/O
Pulled-up input at reset
PC0 - PC31
Parallel IO Controller C
I/O
Pulled-up input at reset
PD0 - PD31
Parallel IO Controller D
I/O
Pulled-up input at reset
PE0 - PE31
Parallel IO Controller E
I/O
Pulled-up input at reset
Direct Memory Access Controller - DMA
DMARQ0-DMARQ3
DMA Requests
Input
External Bus Interface - EBI0 - EBI1
EBIx_D0 - EBIx_D31
Data Bus
I/O
EBIx_A0 - EBIx_A25
Address Bus
EBIx_NWAIT
External Wait Signal
Pulled-up input at reset
Output
Input
0 at reset
Low
Static Memory Controller - SMC
EBI0_NCS0 - EBI0_NCS5,
EBI1_NCS0 - EBI1_NCS2
Chip Select Lines
Output
Low
EBIx_NWR0 -EBIx_NWR3
Write Signal
Output
Low
EBIx_NRD
Read Signal
Output
Low
EBIx_NWE
Write Enable
Output
Low
EBIx_NBS0 - EBIx_NBS3
Byte Mask Signal
Output
Low
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
6
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
CompactFlash Support
EBI0_CFCE1 - EBI0_CFCE2
CompactFlash Chip Enable
Output
Low
EBI0_CFOE
CompactFlash Output Enable
Output
Low
EBI0_CFWE
CompactFlash Write Enable
Output
Low
EBI0_CFIOR
CompactFlash IO Read
Output
Low
EBI0_CFIOW
CompactFlash IO Write
Output
Low
EBI0_CFRNW
CompactFlash Read Not Write
Output
EBI0_CFCS0 - EBI0_CFCS1
CompactFlash Chip Select Lines
Output
Low
NAND Flash Support
EBIx_NANDCS
NAND Flash Chip Select
Output
Low
EBIx_NANDOE
NAND Flash Output Enable
Output
Low
EBIx_NANDWE
NAND Flash Write Enable
Output
Low
SDRAM Controller
EBIx_SDCK
SDRAM Clock
Output
EBIx_SDCKE
SDRAM Clock Enable
Output
High
EBIx_SDCS
SDRAM Controller Chip Select
Output
Low
EBIx_BA0 - EBIx_BA1
Bank Select
Output
EBIx_SDWE
SDRAM Write Enable
Output
Low
EBIx_RAS - EBIx_CAS
Row and Column Signal
Output
Low
EBIx_SDA10
SDRAM Address 10 Line
Output
Multimedia Card Interface
MCIx_CK
Multimedia Card Clock
Output
MCIx_CDA
Multimedia Card Slot A Command
I/O
MCIx_CDB
Multimedia Card Slot B Command
I/O
MCIx_DA0 - MCIx_DA3
Multimedia Card Slot A Data
I/O
MCIx_DB0 - MCIx_DB3
Multimedia Card Slot B Data
I/O
Universal Synchronous Asynchronous Receiver Transmitter USART
SCKx
USARTx Serial Clock
I/O
TXDx
USARTx Transmit Data
I/O
RXDx
USARTx Receive Data
Input
RTSx
USARTx Request To Send
CTSx
USARTx Clear To Send
Output
Input
Synchronous Serial Controller SSC
TDx
SSCx Transmit Data
Output
RDx
SSCx Receive Data
Input
TKx
SSCx Transmit Clock
I/O
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
7
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
RKx
SSCx Receive Clock
I/O
TFx
SSCx Transmit Frame Sync
I/O
RFx
SSCx Receive Frame Sync
I/O
Active
Level
Comments
AC97 Controller - AC97C
AC97RX
AC97 Receive Signal
Input
AC97TX
AC97 Transmit Signal
Output
AC97FS
AC97 Frame Synchronization Signal
Output
AC97CK
AC97 Clock signal
Input
Timer/Counter - TC
TCLKx
TC Channel x External Clock Input
Input
TIOAx
TC Channel x I/O Line A
I/O
TIOBx
TC Channel x I/O Line B
I/O
Pulse Width Modulation Controller- PWMC
PWMx
Pulse Width Modulation Output
Output
Serial Peripheral Interface - SPI
SPIx_MISO
Master In Slave Out
I/O
SPIx_MOSI
Master Out Slave In
I/O
SPIx_SPCK
SPI Serial Clock
I/O
SPIx_NPCS0
SPI Peripheral Chip Select 0
I/O
Low
SPIx_NPCS1 - SPIx_NPCS3
SPI Peripheral Chip Select
Output
Low
Two-Wire Interface
TWD
Two-wire Serial Data
I/O
TWCK
Two-wire Serial Clock
I/O
CAN Controllers
CANRX
CAN Input
CANTX
CAN Output
Input
Output
LCD Controller - LCDC
LCDD0 - LCDD23
LCD Data Bus
Output
LCDVSYNC
LCD Vertical Synchronization
Output
LCDHSYNC
LCD Horizontal Synchronization
Output
LCDDOTCK
LCD Dot Clock
Output
LCDDEN
LCD Data Enable
Output
LCDCC
LCD Contrast Control
Output
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
8
Table 3-1.
Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Comments
Ethernet 10/100
ETXCK
Transmit Clock or Reference Clock
Input
MII only, REFCK in RMII
ERXCK
Receive Clock
Input
MII only
ETXEN
Transmit Enable
Output
ETX0-ETX3
Transmit Data
Output
ETX0-ETX1 only in RMII
ETXER
Transmit Coding Error
Output
MII only
ERXDV
Receive Data Valid
Input
RXDV in MII, CRSDV in RMII
ERX0-ERX3
Receive Data
Input
ERX0-ERX1 only in RMII
ERXER
Receive Error
Input
ECRS
Carrier Sense and Data Valid
Input
MII only
ECOL
Collision Detect
Input
MII only
EMDC
Management Data Clock
EMDIO
Management Data Input/Output
EF100
Force 100Mbit/sec.
Output
I/O
Output
High
RMII only
USB Device Port
DDM
USB Device Port Data -
Analog
DDP
USB Device Port Data +
Analog
USB Host Port
HDPA
USB Host Port A Data +
Analog
HDMA
USB Host Port A Data -
Analog
HDPB
USB Host Port B Data +
Analog
HDMB
USB Host Port B Data -
Analog
Image Sensor Interface - ISI
ISI_D0-ISI_D11
Image Sensor Data
Input
ISI_MCK
Image Sensor Reference Clock
ISI_HSYNC
Image Sensor Horizontal Synchro
Input
ISI_VSYNC
Image Sensor Vertical Synchro
Input
ISI_PCK
Image Sensor Data Clock
Input
Output
Provided by PCK3
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
9
4.
Package and Pinout
The AT91SAM9263 is available in a 324-ball TFBGA Green package, 15 x 15 mm, 0.8mm ball pitch.
4.1
324-ball TFBGA Package Outline
Figure 4-1 shows the orientation of the 324-ball TFBGA package.
A detailed mechanical description is given in the section “AT91SAM9263 Mechanical Characteristics” in the product
datasheet.
Figure 4-1. 324-ball TFBGA Pinout (Top View)
TOP IEW
Pin A1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
A
B
C
D
E
F
G
J
L
M
N
P
R
T
U
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
10
4.2
324-ball TFBGA Package Pinout
Table 4-1.
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
AT91SAM9263 Pinout for 324-ball TFBGA Package
Signal Name
EBI0_D2
EBI0_SDCKE
EBI0_NWE_NWR0
EBI0_NCS1_SDCS
EBI0_A19
EBI0_A11
EBI0_A10
EBI0_A5
EBI0_A1_NBS2_NWR2
PD4
PC30
PC26
PC24
PC19
PC12
VDDCORE
VDDIOP0
DDP
EBI0_D4
EBI0_NANDOE
EBI0_CAS
EBI0_RAS
EBI0_NBS3_NWR3
EBI0_A22
EBI0_A15
EBI0_A7
EBI0_A4
PD0
PC28
PC21
PC17
PC9
PC7
PC5
PB16
DDM
EBI0_D6
EBI0_D0
EBI0_NANDWE
EBI0_SDWE
EBI0_SDCK
EBI0_A21
EBI0_A13
EBI0_A8
EBI0_A3
PD2
PC29
PC23
PC14
PC8
PC3
Pin
E10
E11
E12
E13
E14
E15
E16
E17
E18
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
H1
H2
H3
H4
H5
H6
Signal Name
PC31
PC22
PC15
PC11
PC4
PB30
PC0
PB31
HDPA
PD7
EBI0_D13
EBI0_D9
EBI0_D11
EBI0_D12
EBI0_NCS0
EBI0_A16_BA0
EBI0_A12
EBI0_A6
PD3
PC27
PC18
PC13
PB26
PB25
PB29
PB27
HDMA
PD17
PD12
PD6
EBI0_D14
PD5
PD8
PD10
GND
NC(1)
GND
GND
GND
PB21
PB20
PB23
PB28
PB22
PB18
PD24
PD13
PD15
PD9
PD11
PD14
Pin
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
Signal Name
PE6
PD28
PE0
PE1
PD27
PD31
PD29
PD25
GND
VDDIOM0
GND
VDDIOM0
PB3/BMS
PA14
PA15
PB1
PB0
PB2
PE10
PE4
PE9
PE7
PE5
PE2
PE3
VDDIOP1
VDDIOM1
VDDIOM0
VDDIOP0
GNDBU
PA13
PB4
PA9
PA12
PA10
PA11
PE18
PE14
PE15
PE11
PE13
PE12
PE8
VDDBU
EBI1_A21
VDDIOM1
GND
GND
VDDIOM1
PA6
PA4
Pin
P10
P11
P12
P13
P14
P15
P16
P17
P18
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
U2
U3
U4
U5
U6
Signal Name
EBI1_NCS0
EBI1_NWE_NWR0
EBI1_D4
EBI1_D10
PA3
PA2
PE28
TDI
PLLRCB
XOUT32
TST
PA18
PA25
PA30
EBI1_A2
EBI1_A14
EBI1_A13
EBI1_A17_BA1
EBI1_D1
EBI1_D8
EBI1_D12
EBI1_D15
PE26
EBI1_SDCK
PE30
TCK
XOUT
VDDOSC
VDDIOM1
PA19
PA21
PA26
PA31
EBI1_A7
EBI1_A12
EBI1_A18
EBI1_D0
EBI1_D7
EBI1_D14
PE23
PE25
PE29
PE31
GNDPLL
XIN
PA17
PA20
PA23
PA24
PA28
EBI1_A0_NBS0
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
11
Table 4-1.
Pin
C16
C17
C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
E1
E2
E3
E4
E5
E6
E7
E8
E9
Note:
AT91SAM9263 Pinout for 324-ball TFBGA Package (Continued)
Signal Name
GND
VDDIOP0
HDPB
EBI0_D10
EBI0_D3
NC(1)
EBI0_D1
EBI0_A20
EBI0_A17_BA1
EBI0_A18
EBI0_A9
EBI0_A2
PD1
PC25
PC20
PC6
PC16
PC10
PC2
PC1
HDMB
EBI0_D15
EBI0_D7
EBI0_D5
EBI0_D8
EBI0_NBS1_NWR1
EBI0_NRD
EBI0_A14
EBI0_SDA10
EBI0_A0_NBS0
Pin
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
Signal Name
PD16
VDDIOM0
GND
VDDCORE
GND
PB19
PB17
PB15
PB13
PB24
PB14
PB12
PD30
PD26
PD22
PD19
PD18
PD23
PD21
PD20
GND
GND
GND
PB11
PB9
PB10
PB5
PB6
PB7
PB8
Pin
M16
M17
M18
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
P1
P2
P3
P4
P5
P6
P7
P8
P9
Signal Name
PA7
PA5
PA8
NC
NC
PE19
NC(1)
PE17
PE16
EBI1_A6
EBI1_A11
EBI1_A22
EBI1_D2
EBI1_D6
EBI1_D9
GND
GNDPLL
PA1
PA0
TMS
TDO
XIN32
SHDN
PA16
WKUP
JTAGSEL
PE20
EBI1_A8
EBI1_A4
EBI1_A19
Pin
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
Signal Name
EBI1_A5
EBI1_A10
EBI1_A16_BA0
EBI1_NRD
EBI1_D3
EBI1_D13
PE22
PE27
RTCK
NTRST
VDDPLLA
PLLRCA
VDDCORE
PA22
PA27
PA29
EBI1_A1_NWR2
EBI1_A3
EBI1_A9
EBI1_A15
EBI1_A20
EBI1_NBS1_NWR1
EBI1_D5
EBI1_D11
PE21
PE24
NRST
GND
GND
VDDPLLB
1. NC pins must be left unconnected.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
12
5.
Power Considerations
5.1
Power Supplies
AT91SAM9263 has several types of power supply pins:
z
VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage
ranges from 1.08V to 1.32V, 1.2V nominal.
z
VDDIOM0 and VDDIOM1 pins: Power the External Bus Interface 0 I/O lines and the External Bus Interface 1 I/O
lines, respectively; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V
nominal).
z
VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V to 3.6V, 3.3V
nominal.
z
VDDIOP1 pins: Power the Peripheral I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V to
3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
z
VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V to
1.32V, 1.2V nominal.
z
VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
z
VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V to 3.6V, L3.3V nominal.
The power supplies VDDIOM0, VDDIOM1 and VDDIOP0, VDDIOP1 are identified in the pinout table and the multiplexing
tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing
with peripherals.
Ground pins GND are common to VDDOSC, VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0 and VDDIOP1 pins power
supplies. Separated ground pins are provided for VDDBU and VDDPLL. These ground pins are respectively GNDBU and
GNDPLL.
5.2
Power Consumption
The AT91SAM9263 consumes about 700 µA (worst case) of static current on VDDCORE at 25°C. This static current
rises at up to 7 mA if the temperature increases to 85°C.
On VDDBU, the current does not exceed 3 μA @25°C, but can rise at up to 20 μA @85°C. An automatic switch to
VDDCORE guarantees low power consumption on the battery when the system is on.
For dynamic power consumption, the AT91SAM9263 consumes a maximum of 70 mA on VDDCORE at maximum
conditions (1.2V, 25°C, processor running full-performance algorithm).
5.3
Programmable I/O Lines Power Supplies
The power supply pins VDDIOM0 and VDDIOM1 accept two voltage ranges. This allows the device to reach its
maximum speed, either out of 1.8V or 3.0V external memories.
The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF. The other signals (control,
address and data signals) do not go over 50 MHz, loaded with 30 pF for power supply at 1.8V and 50 pF for power
supply at 3.3V.
The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix
User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. However,
the device cannot reach its maximum speed if the voltage supplied to the pins is only 1.8V without reprogramming the
EBI0 voltage range. The user must be sure to program the EBI0 voltage range before getting the device out of its Slow
Clock Mode.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
13
6.
I/O Line Considerations
6.1
JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (VDDBU). It integrates a
permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.
The NTRST signal is described in Section 6.3.
All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0.
6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of
about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to
unpredictable results.
This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to
VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor.
As the product integrates power-on reset cells, which manage the processor and the JTAG reset, the NRST and NTRST
pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 kΩ minimum to VDDIOP0.
The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor of 100 kΩ typical.
Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the
External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column
“Reset State” of the PIO Controller multiplexing tables on page 33 and following.
6.5
Shutdown Logic Pins
The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An
external pull-up to VDDBU is needed and its value must be higher than 1 MΩ. The resistor value is calculated according
to the regulator enable implementation and the SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
14
7.
Processor and Architecture
7.1
ARM926EJ-S Processor
z
RISC Processor based on ARM v5TEJ Harvard Architecture with Jazelle technology for Java acceleration
z
Two Instruction Sets
ARM High-performance 32-bit Instruction Set
z
Thumb High Code Density 16-bit Instruction Set
z
DSP Instruction Extensions
z
5-stage Pipeline Architecture
z
z
z
z
7.2
z
z
Instruction Fetch (F)
z
Instruction Decode (D)
z
Execute (E)
z
Data Memory (M)
z
Register Write (W)
16 Kbyte Data Cache, 16 Kbyte Instruction Cache
z
Virtually-addressed 4-way Associative Cache
z
Eight words per line
z
Write-through and Write-back Operation
z
Pseudo-random or Round-robin Replacement
Write Buffer
z
Main Write Buffer with 16-word Data Buffer and 4-address Buffer
z
DCache Write-back Buffer with 8-word Entries and a Single Address Entry
z
Software Control Drain
Standard ARM v4 and v5 Memory Management Unit (MMU)
z
Access Permission for Sections
z
Access Permission for large pages and small pages can be specified separately for each quarter of the
page
z
16 embedded domains
Bus Interface Unit (BIU)
z
Arbitrates and Schedules AHB Requests
z
Separate Masters for both instruction and data access providing complete Matrix system flexibility
z
Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface
z
On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
Bus Matrix
z
9-layer Matrix, handling requests from 9 masters
z
Programmable Arbitration strategy
z
z
z
Fixed-priority Arbitration
z
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
Burst Management
z
Breaking with Slot Cycle Limit Support
z
Undefined Burst Length Support
One Address Decoder provided per Master
z
Three different slaves may be assigned to each decoded memory area: one for internal boot, one for
external boot, one after remap
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
15
z
z
7.3
Boot Mode Select
z
Non-volatile Boot Memory can be internal or external
z
Selection is made by BMS pin sampled at reset
Remap Command
z
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
z
Allows Handling of Dynamic Exception Vectors
Matrix Masters
The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with
others to an available slave peripheral or memory.
Each master has its own decoder, which is defined specifically for each master.
Table 7-1.
7.4
List of Bus Matrix Masters
Master 0
OHCI USB Host Controller
Master 1
Image Sensor Interface
Master 2
Two D Graphic Controller
Master 3
DMA Controller
Master 4
Ethernet MAC
Master 5
LCD Controller
Master 6
Peripheral DMA Controller
Master 7
ARM926 Data
Master 8
ARM926™ Instruction
Matrix Slaves
The Bus Matrix of the AT91SAM9263 manages eight slaves. Each slave has its own arbiter, thus allowing to program a
different arbitration per slave.
The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a slave on
the Matrix. They share the same layer, as programming them does not require a high bandwidth.
Table 7-2.
List of Bus Matrix Slaves
Slave 0
Internal ROM
Slave 1
Internal 80 Kbyte SRAM
Slave 2
Internal 16 Kbyte SRAM
LCD Controller User Interface
Slave 3
DMA Controller User Interface
USB Host User Interface
Slave 4
External Bus Interface 0
Slave 5
External Bus Interface 1
Slave 6
Peripheral Bridge
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
16
7.5
Master to Slave Access
In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing
access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and are
shown as “-” in Table 7-3.
Table 7-3.
Masters to Slaves Access
Master
0
1
2
Slave
OHCI USB
Host
Controller
Image
Sensor
Interface
Two D
Graphics
Controller
3
4
5
6
7&8
DMA
Controller
Ethernet
MAC
LCD
Controller
Peripheral
DMA
Controller
ARM926
Data &
Instruction
0
Internal ROM
X
X
X
X
X
X
X
X
1
Internal 80 Kbyte
SRAM
X
X
X
X
X
X
X
X
2
Internal 16 Kbyte
SRAM Bank
X
X
X
X
X
X
X
X
LCD Controller
User Interface
-
-
-
-
-
-
-
X
DMA Controller
User Interface
-
-
-
-
-
-
-
X
USB Host User
Interface
-
-
-
-
-
-
-
X
4
External Bus
Interface 0
X
X
X
X
X
X
X
X
5
External Bus
Interface 1
X
X
X
X
X
X
X
X
6
Peripheral Bridge
-
-
-
X
-
-
X
X
3
7.6
Peripheral DMA Controller
z
Acts as one Matrix Master
z
Allows data transfers between a peripheral and memory without any intervention of the processor
z
Next Pointer support, removes heavy real-time constraints on buffer management.
z
Twenty channels
z
Two for each USART
z
Two for the Debug Unit
z
Two for each Serial Synchronous Controller
z
Two for each Serial Peripheral Interface
z
Two for the AC97 Controller
z
One for each Multimedia Card Interface
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (low to
high priorities):
z
DBGU Transmit Channel
z
USART2 Transmit Channel
z
USART1 Transmit Channel
z
USART0 Transmit Channel
z
AC97 Transmit Channel
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
17
7.7
z
SPI1 Transmit Channel
z
SPI0 Transmit Channel
z
SSC1 Transmit Channel
z
SSC0 Transmit Channel
z
DBGU Receive Channel
z
USART2 Receive Channel
z
USART1 Receive Channel
z
USART0 Receive Channel
z
AC97 Receive Channel
z
SPI1 Receive Channel
z
SPI0 Receive Channel
z
SSC1 Receive Channel
z
SSC0 Receive Channel
z
MCI1 Transmit/Receive Channel
z
MCI0 Transmit/Receive Channel
DMA Controller
z
Acts as one Matrix Master
z
Embeds 2 unidirectional channels with programmable priority
z
Address Generation
z
z
z
z
z
Source/destination address programming
z
Address increment, decrement or no change
z
DMA chaining support for multiple non-contiguous data blocks through use of linked lists
z
Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of
data into non-contiguous fields in system memory.
z
Gather support for extracting fields from a system memory area into a contiguous transfer
z
User enabled auto-reloading of source, destination and control registers from initially programmed values at
the end of a block transfer
z
Auto-loading of source, destination and control registers from system memory at end of block transfer in
block chaining mode
z
Unaligned system address to data transfer width supported in hardware
Channel Buffering
z
Two 8-word FIFOs
z
Automatic packing/unpacking of data to fit FIFO width
Channel Control
z
Programmable multiple transaction size for each channel
z
Support for cleanly disabling a channel without data loss
z
Suspend DMA operation
z
Programmable DMA lock transfer support.
Transfer Initiation
z
Supports four external DMA Requests
z
Support for software handshaking interface. Memory mapped registers can be used to control the flow of a
DMA transfer in place of a hardware handshaking interface
Interrupt
z
Programmable interrupt generation on DMA transfer completion, Block transfer completion, Single/Multiple
transaction completion or Error condition
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
18
7.8
Debug and Test Features
z
z
z
z
ARM926 Real-time In-circuit Emulator
z
Two real-time Watchpoint Units
z
Two Independent Registers: Debug Control Register and Debug Status Register
z
Test Access Port Accessible through JTAG Protocol
z
Debug Communications Channel
Debug Unit
z
Two-pin UART
z
Debug Communication Channel Interrupt Handling
z
Chip ID Register
Embedded Trace Macrocell: ETM9™
z
Medium+ Level Implementation
z
Half-rate Clock Mode
z
Four Pairs of Address Comparators
z
Two Data Comparators
z
Eight Memory Map Decoder Inputs
z
Two 16-bit Counters
z
One 3-stage Sequencer
z
One 45-byte FIFO
IEEE1149.1 JTAG Boundary-scan on All Digital Pins
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
19
8.
Memories
Figure 8-1. AT91SAM9263 Memory Mapping
Internal Memory Mapping
Address Memory Space
0x0000 0000
0x0000 0000
Internal Memories
Boot Memory (1)
0x0010 0000
256M Bytes
ITCM (2)
0x0020 0000
0x0FFF FFFF
DTCM (2)
0x1000 0000
EBI0
Chip Select 0
0x0030 0000
256M Bytes
SRAM (2)
0x0040 0000
ROM
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
EBI0
Chip Select 1/
EBI0 SDRAMC
0x0050 0000
16K SRAM0
256M Bytes
0x0060 0000
LCD Controller
EBI0
Chip Select 2
0x0080 0000
256M Bytes
DMAC
0x0090 0000
0x3FFF FFFF
EBI0
Chip Select 3/
NANDFlash
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
Reserved
0x00A0 0000
256M Bytes
USB HOST
0x00B0 0000
0x4FFF FFFF
0x5000 0000
Reserved
0x0070 0000
0x3000 0000
0x4000 0000
Notes:
(1) Can be ROM, EBI0_NCS0 or SRAM
depending on BMS and REMAP
(2) Software programmable
Reserved
EBI0
Chip Select 4/
Compact Flash
Slot 0
EBI0
Chip Select 5/
Compact Flash
Slot 1
Peripheral Mapping
256M Bytes
0xF000 0000
Reserved
16K Bytes
UDP
16K Bytes
0xFFF7 8000
256M Bytes
0x7000 0000
0xFFF7 C000
System Controller Mapping
0xFFFF C000
TCO, TC1, TC2
16K Bytes
MCI0
16K Bytes
0xFFFF E000
MCI1
16K Bytes
0xFFFF E200
TWI
16K Bytes
0xFFFF E400
USART0
16K Bytes
0xFFFF E600
USART1
16K Bytes
USART2
16K Bytes
SSC0
16K Bytes
SSC1
16K Bytes
AC97C
16K Bytes
SPI0
16K Bytes
SPI1
16K Bytes
CAN0
16K Bytes
Reserved
0xFFF8 0000
EBI1
Chip Select 0
256M Bytes
0x7FFF FFFF
0x8000 0000
0xFFF8 8000
EBI1
Chip Select 1/
EBI1 SDRAMC
256M Bytes
0x8FFF FFFF
EBI1
Chip Select 2/
NANDFlash
256M Bytes
0xFFF9 4000
0xFFF9 8000
0x9FFF FFFF
0xA000 0000
0xFFFA 8000
0xFFFF EA00
0xFFFF EC00
0xFFFF F200
512 Bytes
SMC1
512 Bytes
PWMC
0xFFFF F800
512 Bytes
AIC
512 bytes
PIOA
512 bytes
PIOB
512 Bytes
PIOC
512 bytes
PIOD
512 bytes
PIOE
512 bytes
PMC
256 Bytes
0xFFFF FD00
RSTC
16 Bytes
0xFFFF FD10
SHDWC
16 Bytes
RTT0
16 Bytes
0xFFFF FD30
PIT
16 Bytes
0xFFFF FD40
WDT
16 Bytes
0xFFFF FD50
0xFFFF FD60
RTT1
16 Bytes
GPBR
80 Bytes
0xFFFF FC00
EMAC
16K Bytes
Reserved
16K Bytes
0xFFFC 0000
0xFFFC 4000
ISI
16K Bytes
2DGE
16K Bytes
0xFFFC 8000
0xFFFC C000
Reserved
0xFFFF C000
SYSC
DBGU
16K Bytes
0xFFFB C000
0xFFFF FFFF
512 Bytes
0xFFFF F600
0xFFFB 8000
0xEFFF FFFF
MATRIX
0xFFFF F400
0xFFFB 0000
256M Bytes
512 bytes
SDRAMC1
0xFFFF F000
0xFFFF FA00
Internal Peripherals
512 Bytes
ECC1
CCFG
0xFFFA C000
Reserved
0xFFFF FFFF
SMC0
0xFFFF E800
0xFFFA 4000
0xF000 0000
512 Bytes
0xFFFF EE00
0xFFFA 0000
1,280M Bytes
SDRAMC0
0xFFFF ED10
0xFFF9 C000
Undefined
(Abort)
512 Bytes
0xFFF8 C000
0xFFF9 0000
0x9000 0000
ECC0
0xFFF8 4000
16K Bytes
0xFFFF FD20
0xFFFF FDB0
Reserved
0xFFFF FFFF
SAM9263 [Summary]
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20
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High
Performance Bus (AHB) for its master and slave interfaces with additional features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 9 are directed to the
EBI0 that associates these banks to the external chip selects EBI0_NCS0 to EBI0_NCS5 and EBI1_NCS0 to
EBI1_NCS2. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding
provides 1M bytes of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced
Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master requesting such an
access.
Each master has its own bus and its own decoder, thus allowing a different memory mapping for each master. However,
in order to simplify the mappings, all the masters have a similar address decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different slaves are assigned to the memory
space decoded at address 0x0: one for internal boot, one for external boot and one after remap. Refer to Table 8-1,
“Internal Memory Mapping,” on page 21 for details.
A complete memory map is presented in Figure 8-1 on page 20.
8.1
Embedded Memories
z
128 Kbyte ROM
z
z
z
One 80 Kbyte Fast SRAM
z
Single Cycle Access at full matrix speed
z
Supports ARM926EJ-S TCM interface at full processor speed
z
Allows internal Frame Buffer for up to 1/4 VGA 8 bpp screen
16 Kbyte Fast SRAM
z
8.1.1
Single Cycle Access at full matrix speed
Single Cycle Access at full matrix speed
Internal Memory Mapping
Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap status and the BMS state at reset.
Table 8-1.
Internal Memory Mapping
REMAP = 0
Address
0x0000 0000
REMAP = 1
BMS = 1
BMS = 0
ROM
EBI0_NCS0
SRAM C
8.1.1.1 Internal 80 Kbyte Fast SRAM
The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split into three areas. Its
memory mapping is presented in Figure 8-1 on page 20.
z
Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the
ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in the Chip
Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB
Masters through the AHB bus at address 0x0010 0000.
z
Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926
data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and
by the AHB Masters through the AHB bus at address 0x0020 0000.
z
Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is
performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters.
After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926
Instruction and the ARM926 Data Masters.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
21
Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is software programmable as a
multiple of 16 Kbytes as shown in Table 8-2. This table provides the size of the Internal SRAM C according to the size of
the internal SRAM A and the internal SRAM B.
Table 8-2.
Internal SRAM Block Size
Internal SRAM A (ITCM) Size
0
16 Kbytes
32 Kbytes
0
80 Kbytes
64 Kbytes
48 Kbytes
16 Kbytes
64 Kbytes
48 Kbytes
32 Kbytes
32 Kbytes
48 Kbytes
32 Kbytes
16 Kbytes
Internal SRAM C
Internal SRAM B
(DTCM) size
Note that among the five 16 Kbyte blocks making up the Internal SRAM, one is permanently assigned to Internal SRAM
C.
At reset, the whole memory (80 Kbytes) is assigned to Internal SRAM C.
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user
dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous
configuration from a software point of view.
Table 8-3 illustrates different configurations and the related 16 Kbyte blocks assignments (RB0 to RB4).
Table 8-3.
16 Kbyte Block Allocation
Configuration examples and related 16 Kbyte block assignments
Decoded
Area
Address
ITCM = 0 Kbyte
DTCM = 0 Kbyte
AHB = 80 Kbytes (1)
ITCM = 32 Kbytes
DTCM = 32
Kbytes
AHB = 16 Kbytes
ITCM = 16 Kbytes
DTCM = 32 Kbytes
AHB = 32 Kbytes
ITCM = 32 Kbytes
DTCM = 16 Kbytes
AHB = 32 Kbytes
ITCM = 16 Kbytes
DTCM = 16 Kbytes
AHB = 48 Kbytes
RB1
RB1
RB1
Internal
SRAM A
(ITCM)
0x0010 0000
RB1
0x0010 4000
RB0
Internal
SRAM B
(DTCM)
0x0020 0000
RB3
RB3
0x0020 4000
RB2
RB2
RB4
Internal
SRAM C
(AHB)
Note:
0x0030 0000
RB4
0x0030 4000
RB3
0x0030 8000
RB2
0x0030 C000
RB1
0x0031 0000
RB0
RB0
RB3
RB3
RB4
RB4
RB4
RB0
RB2
RB2
RB0
1. Configuration after reset.
When accessed from the Bus Matrix, the internal 80 Kbytes of Fast SRAM is single cycle accessible at full matrix speed
(MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor
speed.
8.1.1.2 Internal 16 Kbyte Fast SRAM
The AT91SAM9263 integrates a 16 Kbyte SRAM, mapped at address 0x0050 0000. This SRAM is single cycle
accessible at full Bus Matrix speed.
8.1.2
Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with
two parameters.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
22
REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once the system has booted.
Refer to the section “AT91SAM9263 Bus Matrix” in the product datasheet for more details.
When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is done via
hardware at reset.
Note:
Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the
complete memory map presented in Figure 8-1 on page 20.
The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal
memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface.
8.1.2.1 BMS = 1, Boot on Embedded ROM
The system boots on Boot Program.
z
Boot at slow clock
z
Auto baudrate detection
z
Downloads and runs an application from external storage media into internal SRAM
z
Downloaded code size depends on embedded SRAM size
z
Automatic detection of valid application
z
Bootloader on a non-volatile memory
z
z
SD Card
z
NAND Flash
z
SPI DataFlash® and Serial Flash connected on NPCS0 of the SPI0
Interface with SAM-BA® Graphic User Interface to enable code loading via:
z
Serial communication on a DBGU
z
USB Bulk Device Port
8.1.2.2 BMS = 0, Boot on External Memory
z
Boot at slow clock
z
Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write
controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI0 CS0 (BMS=0) the user must:
8.2
1.
Program the PMC (main oscillator enable or bypass mode).
2.
Program and Start the PLL.
3.
Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock.
4.
Switch the main clock to the new value.
External Memories
The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256
Mbyte memory area assigned.
Refer to Figure 8-1 on page 20.
8.2.1
External Bus Interfaces
The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent
bottlenecks while accessing external memories.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
23
8.2.1.1 External Bus Interface 0
z
Integrates three External Memory Controllers:
z
Static Memory Controller
z
SDRAM Controller
z
ECC Controller
z
Additional logic for NAND Flash and CompactFlash
z
Optional Full 32-bit External Data Bus
z
Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
z
Up to 6 Chip Selects, Configurable Assignment:
z
z
Static Memory Controller on NCS0
z
SDRAM Controller or Static Memory Controller on NCS1
z
Static Memory Controller on NCS2
z
Static Memory Controller on NCS3, Optional NAND Flash support
z
Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
Optimized for Application Memory Space
8.2.1.2 External Bus Interface 1
z
Static Memory Controller
z
SDRAM Controller
z
ECC Controller
Additional logic for NAND Flash
z
Optional Full 32-bit External Data Bus
z
Up to 23-bit Address Bus (up to 8 Mbytes linear)
z
Up to 3 Chip Selects, Configurable Assignment:
z
Static Memory Controller on NCS0
z
SDRAM Controller or Static Memory Controller on NCS1
z
Static Memory Controller on NCS2, Optional NAND Flash support
Allows supporting an external Frame Buffer for the embedded LCD Controller without impacting processor
performance.
Static Memory Controller
z
8-, 16- or 32-bit Data Bus
z
Multiple Access Modes supported
z
z
z
8.2.3
z
z
z
8.2.2
Integrates three External Memory Controllers:
z
Byte Write or Byte Select Lines
z
Asynchronous read in Page Mode supported (4- up to 32-byte page size)
Multiple device adaptability
z
Compliant with LCD Module
z
Control signals programmable setup, pulse and hold time for each Memory Bank
Multiple Wait State Management
z
Programmable Wait State Generation
z
External Wait Request
z
Programmable Data Float Time
Slow Clock mode supported
SDRAM Controller
z
Supported devices
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
24
z
z
z
Numerous configurations supported
z
2K, 4K, 8K Row Address Memory Parts
z
SDRAM with two or four Internal Banks
z
SDRAM with 16- or 32-bit Data Path
Programming facilities
z
Word, half-word, byte access
z
Automatic page break when Memory Boundary has been reached
z
Multibank Ping-pong Access
z
Timing parameters specified by software
z
Automatic refresh operation, refresh rate is programmable
z
Energy-saving capabilities
z
Error detection
z
SDRAM Power-up Initialization by software
z
CAS Latency of 1, 2 and 3 supported
z
Auto Precharge Command not used
z
z
8.2.4
Self-refresh, power down and deep power down modes supported
Refresh Error Interrupt
Error Corrected Code Controller
z
Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
z
Single-bit error correction and two-bit random detection
z
Automatic Hamming Code Calculation while writing
z
Automatic Hamming Code Calculation while reading
z
9.
Standard and Low-power SDRAM (Mobile SDRAM)
ECC value available in a register
z
Error Report, including error flag, correctable error flag and word address being detected erroneous
z
Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages
System Controller
The System Controller is a set of peripherals that allow handling of key elements of the system, such as power, resets,
clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds registers that are used to configure the Bus Matrix and a set of
registers for the chip configuration. The chip configuration registers can be used to configure:
z
EBI0 and EBI1 chip select assignment and voltage range for external memories
z
ARM Processor Tightly Coupled Memories
The System Controller peripherals are all mapped within the highest 16 Kbytes of address space, between addresses
0xFFFF C000 and 0xFFFF FFFF.
However, all the registers of the System Controller are mapped on the top of the address space. This allows all the
registers of the System Controller to be addressed from a single pointer by using the standard ARM instruction set, as
the Load/Store instructions have an indexing mode of ± 4 Kbytes.
Figure 9-1 on page 26 shows the System Controller block diagram.
Figure 8-1 on page 20 shows the mapping of the User Interfaces of the System Controller peripherals.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
25
9.1
System Controller Block Diagram
Figure 9-1. AT91SAM9263 System Controller Block Diagram
System Controller
DDCORE Powered
ir 0-ir 1
fi
nir
nfi
Advanced
Interrupt
Controller
periph ir 2..29
pit ir
rtt0 ir
rtt1 ir
wdt ir
dbgu ir
pmc ir
rstc ir
MC
periph nreset
int
MC
debug
periph nreset
PC
dbgu txd
debug
Periodic
Interval
Timer
pit ir
Watchdog
Timer
wdt ir
tag nreset
SLC
debug
idle
proc nreset
NRST
periph nreset
DDCORE
Reset
Controller
periph nreset
proc nreset
backup nreset
battery save
DDBU
DDBU
POR
DDBU Powered
SLC
SLC
backup nreset
Real-Time
Timer 0
SLC
backup nreset
Real-Time
Timer 1
rtt0 ir
UDPC
rtt0 alarm
rtt1 ir
periph clk 24
rtt1 alarm
periph nreset
SLC
Shut-Down
Controller
W UP
oltage
Controller
battery save
U PC
backup nreset
SLOW
CLOC
OSC
rtt0 alarm
rtt1 alarm
20 General-Purpose
Backup Registers
SLC
periph clk 2..29
pck 0-3
int
PLLRCA
PLLRCB
USB
Device
Port
periph ir 24
S DN
OUT
Bus Matrix
rstc ir
por ntrst
tag nreset
DDCORE
POR
IN
Boundary Scan
TAP Controller
MC
wdt fault
WDRPROC
OUT32
ARM926EJ-S
proc nreset
dbgu ir
Debug
Unit
dbgu rxd
IN32
ntrst
por ntrst
MAIN
OSC
MAINC
PLLA
PLLAC
PLLB
Power
Management
Controller
PC
OTGC
UDPC
periph clk 29
periph nreset
USB ost
Port
periph ir 29
periph clk 26
periph nreset
LCD
Controller
periph ir 26
MC
PLLBC
pmc ir
periph nreset
periph clk 7..27
idle
periph nreset
periph nreset
periph clk 2..6
dbgu rxd
PA0-PA31
PB0-PB31
PC0-PC31
PD0-PD31
PIO
Controllers
periph ir 2..6
ir 0-ir 1
fi
dbgu txd
Embedded
Peripherals
periph ir 7..27
in
out
enable
PE0-PE31
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
26
9.2
Reset Controller
z
Based on two Power-on-Reset cells
z
z
Status of the last reset
z
z
Allows shaping a reset signal for the external devices
Shutdown Controller
z
9.4
Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or
watchdog reset
Controls the internal resets and the NRST pin output
z
9.3
One on VDDBU and one on VDDCORE
Shutdown and Wake-up logic
z
Software programmable assertion of the SHDN pin (SHDN is push-pull)
z
Deassertion programmable on a WKUP pin level change or on alarm
Clock Generator
z
Embeds the low-power 32768 Hz Slow Clock Oscillator
z
z
z
Provides the permanent Slow Clock SLCK to the system
Embeds the Main Oscillator
z
Oscillator bypass feature
z
Supports 3 to 20 MHz crystals
Embeds 2 PLLs
z
Output 80 to 240 MHz clocks
z
Integrates an input divider to increase output accuracy
z
1 MHz Minimum input frequency
Figure 9-2. Clock Generator Block Diagram
Clock Generator
IN32
Slow Clock
Oscillator
Slow Clock
SLC
Main
Oscillator
Main Clock
MAINC
PLLRCA
PLL and
Divider A
PLLA Clock
PLLAC
PLLRCB
PLL and
Divider B
PLLB Clock
PLLBC
OUT32
IN
OUT
Status
Control
Power
Management
Controller
9.5
Power Management Controller
z
Provides:
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
27
z
z
the Processor Clock PCK
z
the Master Clock MCK, in particular to the Matrix and the memory interfaces
z
the USB Device Clock UDPCK
z
the USB Host Clock UHPCK
z
independent peripheral clocks, typically at the frequency of MCK
z
four programmable clock outputs: PCK0 to PCK3
Five flexible operating modes:
z
Normal Mode with processor and peripherals running at a programmable frequency
z
Idle Mode with processor stopped while waiting for an interrupt
z
Slow Clock Mode with processor and peripherals running at low frequency
z
Standby Mode, mix of Idle and Backup Mode, with peripherals running at low frequency, processor stopped
waiting for an interrupt
z
Backup Mode with Main Power Supplies off, VDDBU powered by a battery
Figure 9-3. AT91SAM9263 Power Management Controller Block Diagram
Processor
Clock
Controller
int
Master Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
Prescaler
/1,/2,/4,...,/64
PCK
Idle Mode
Divider
/1,/2,/4
MCK
Peripherals
Clock Controller
periph_clk[..]
ON/OFF
Programmable Clock Controller
SLCK
MAINCK
PLLACK
PLLBCK
ON/OFF
Prescaler
/1,/2,/4,...,/64
pck[..]
USB Clock Controller
PLLBCK
Divider
/1,/2,/4
ON/OFF
UDPCK
UHPCK
9.6
9.7
9.8
Periodic Interval Timer
z
Includes a 20-bit Periodic Counter, with less than 1 μs accuracy
z
Includes a 12-bit Interval Overlay Counter
z
Real-time OS or Linux®/WindowsCE® compliant tick generator
Watchdog Timer
z
16-bit key-protected Counter, programmable only once
z
Windowed, prevents the processor deadlocking on the watchdog access
Real-time Timer
z
Two Real-time Timers, allowing backup of time with different accuracies
z
32-bit Free-running back-up counter
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
28
9.9
z
Alarm Register capable of generating a wake-up of the system through the Shutdown Controller
Twenty 32-bit general-purpose backup registers
Backup Power Switch
z
9.11
Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz oscillator
General-purpose Backup Registers
z
9.10
z
Automatic switch of VDDBU to VDDCORE guaranteeing very low power consumption on VDDBU while
VDDCORE is present
Advanced Interrupt Controller
z
Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
z
Thirty-two individually maskable and vectored interrupt sources
z
Source 0 is reserved for the Fast Interrupt Input (FIQ)
z
Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
z
Programmable Edge-triggered or Level-sensitive Internal Sources
z
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
z
Four External Sources plus the Fast Interrupt signal
z
8-level Priority Controller
z
z
z
Drives the Normal Interrupt of the processor
z
Handles priority of the interrupt sources 1 to 31
z
Higher priority interrupts can be served during service of lower priority interrupt
Vectoring
z
Optimizes Interrupt Service Routine Branch and Execution
z
One 32-bit Vector Register per interrupt source
z
Interrupt Vector Register reads the corresponding current Interrupt Vector
Protect Mode
z
z
Fast Forcing
z
9.12
Easy debugging by preventing automatic operations when protect models are enabled
Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
Debug Unit
z
Composed of two functions
z
Two-pin UART
z
z
Implemented features are 100% compatible with the standard Atmel USART
z
Independent receiver and transmitter with a common programmable Baud Rate Generator
z
Even, Odd, Mark or Space Parity Generation
z
Parity, Framing and Overrun Error Detection
z
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
z
Support for two PDC channels with connection to receiver and transmitter
z
Mode for general purpose Two-wire UART serial communication
Debug Communication Channel Support
z
Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE
Interface
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
29
9.13
9.14
Chip Identification
z
Chip ID: 0x019607A0
z
JTAG ID: 0x05B0C03F
z
ARM926 TAP ID: 0x0792603F
PIO Controllers
z
Five PIO Controllers, PIOA to PIOE, controlling a total of 160 I/O Lines
z
Each PIO Controller controls up to 32 programmable I/O Lines
z
PIOA has 32 I/O Lines
z
PIOB has 32 I/O Lines
z
PIOC has 32 I/O Lines
z
PIOD has 32 I/O Lines
z
PIOE has 32 I/O Lines
z
Fully programmable through Set/Clear Registers
z
Multiplexing of two peripheral functions per I/O Line
z
For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O)
z
z
Input change interrupt
z
Glitch filter
z
Multi-drive option enables driving in open drain
z
Programmable pull-up on each I/O line
z
Pin data status register, supplies visibility of the level on the pin at any time
Synchronous output, provides Set and Clear of several I/O lines in a single write
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
30
10.
Peripherals
10.1
User Interface
The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and
0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space.
A complete memory map is presented in Figure 8-1 on page 20.
10.2
Identifiers
Table 10-1 defines the Peripheral Identifiers. A peripheral identifier is required for the control of the peripheral interrupt
with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 10-1. AT91SAM9263 Peripheral Identifiers
Peripheral ID
Peripheral Mnemonic
Peripheral Name
External Interrupt
0
AIC
Advanced Interrupt Controller
FIQ
1
SYSC
System Controller Interrupt
2
PIOA
Parallel I/O Controller A
3
PIOB
Parallel I/O Controller B
4
PIOC to PIOE
Parallel I/O Controller C, D and E
5
reserved
6
reserved
7
US0
USART 0
8
US1
USART 1
9
US2
USART 2
10
MCI0
Multimedia Card Interface 0
11
MCI1
Multimedia Card Interface 1
12
CAN
CAN Controller
13
TWI
Two-Wire Interface
14
SPI0
Serial Peripheral Interface 0
15
SPI1
Serial Peripheral Interface 1
16
SSC0
Synchronous Serial Controller 0
17
SSC1
Synchronous Serial Controller 1
18
AC97C
AC97 Controller
19
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
20
PWMC
Pulse Width Modulation Controller
21
EMAC
Ethernet MAC
22
reserved
23
2DGE
2D Graphic Engine
24
UDP
USB Device Port
25
ISI
Image Sensor Interface
26
LCDC
LCD Controller
27
DMA
DMA Controller
28
reserved
29
UHP
USB Host Port
30
AIC
Advanced Interrupt Controller
IRQ0
AIC
Advanced Interrupt Controller
IRQ1
31
Note:
Setting AIC, SYSC, UHP and IRQ0 - 1 bits in the clock set/clear registers of the PMC has no effect.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
31
10.2.1 Peripheral Interrupts and Clock Control
10.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
z
the SDRAM Controller
z
the Debug Unit
z
the Periodic Interval Timer
z
the Real-Time Timer
z
the Watchdog Timer
z
the Reset Controller
z
the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt
Controller.
10.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated
Peripheral ID. However, there is no clock control associated with these peripheral IDs.
10.2.1.3 Timer Counter Interrupts
The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the
Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching
the right Interrupt Service Routine.
The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19
disables the clock of the 3 channels.
10.3
Peripherals Signals Multiplexing on I/O Lines
The AT91SAM9263 device features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines
of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The
multiplexing tables define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two
columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral functions which are output only may be duplicated within both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is specified, the
PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is
released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets
low.
If a signal name is specified in the “Reset State” column, the PIO Line is assigned to this function and the corresponding
bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require
the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
32
10.3.1 PIO Controller A Multiplexing
Table 10-2. Multiplexing on PIO Controller A
PIO Controller A
Application Usage
I/O Line
Peripheral A
Peripheral B
Reset
State
Power
Supply
PA0
MCI0_DA0
SPI0_MISO
I/O
VDDIOP0
PA1
MCI0_CDA
SPI0_MOSI
I/O
VDDIOP0
SPI0_SPCK
I/O
VDDIOP0
PA2
PA3
MCI0_DA1
SPI0_NPCS1
I/O
VDDIOP0
PA4
MCI0_DA2
SPI0_NPCS2
I/O
VDDIOP0
PA5
MCI0_DA3
SPI0_NPCS0
I/O
VDDIOP0
PA6
MCI1_CK
PCK2
I/O
VDDIOP0
PA7
MCI1_CDA
I/O
VDDIOP0
PA8
MCI1_DA0
I/O
VDDIOP0
PA9
MCI1_DA1
I/O
VDDIOP0
PA10
MCI1_DA2
I/O
VDDIOP0
PA11
MCI1_DA3
I/O
VDDIOP0
PA12
MCI0_CK
I/O
VDDIOP0
PA13
CANTX
PCK0
I/O
VDDIOP0
PA14
CANRX
IRQ0
I/O
VDDIOP0
PA15
TCLK2
IRQ1
I/O
VDDIOP0
PA16
MCI0_CDB
EBI1_D16
I/O
VDDIOM1
PA17
MCI0_DB0
EBI1_D17
I/O
VDDIOM1
PA18
MCI0_DB1
EBI1_D18
I/O
VDDIOM1
PA19
MCI0_DB2
EBI1_D19
I/O
VDDIOM1
PA20
MCI0_DB3
EBI1_D20
I/O
VDDIOM1
PA21
MCI1_CDB
EBI1_D21
I/O
VDDIOM1
PA22
MCI1_DB0
EBI1_D22
I/O
VDDIOM1
PA23
MCI1_DB1
EBI1_D23
I/O
VDDIOM1
PA24
MCI1_DB2
EBI1_D24
I/O
VDDIOM1
PA25
MCI1_DB3
EBI1_D25
I/O
VDDIOM1
PA26
TXD0
EBI1_D26
I/O
VDDIOM1
PA27
RXD0
EBI1_D27
I/O
VDDIOM1
PA28
RTS0
EBI1_D28
I/O
VDDIOM1
PA29
CTS0
EBI1_D29
I/O
VDDIOM1
PA30
SCK0
EBI1_D30
I/O
VDDIOM1
PA31
DMARQ0
EBI1_D31
I/O
VDDIOM1
Function
Comments
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
33
10.3.2 PIO Controller B Multiplexing
Table 10-3. Multiplexing on PIO Controller B
PIO Controller B
Application Usage
I/O Line
Peripheral A
Peripheral B
Reset
State
Power
Supply
PB0
AC97FS
TF0
I/O
VDDIOP0
PB1
AC97CK
TK0
I/O
VDDIOP0
PB2
AC97TX
TD0
I/O
VDDIOP0
PB3
AC97RX
RD0
I/O
VDDIOP0
PB4
TWD
RK0
I/O
VDDIOP0
PB5
TWCK
RF0
I/O
VDDIOP0
PB6
TF1
DMARQ1
I/O
VDDIOP0
PB7
TK1
PWM0
I/O
VDDIOP0
PB8
TD1
PWM1
I/O
VDDIOP0
PB9
RD1
LCDCC
I/O
VDDIOP0
PB10
RK1
PCK1
I/O
VDDIOP0
PB11
RF1
SPI0_NPCS3
I/O
VDDIOP0
PB12
SPI1_MISO
I/O
VDDIOP0
PB13
SPI1_MOSI
I/O
VDDIOP0
PB14
SPI1_SPCK
I/O
VDDIOP0
PB15
SPI1_NPCS0
I/O
VDDIOP0
PB16
SPI1_NPCS1
PCK1
I/O
VDDIOP0
PB17
SPI1_NPCS2
TIOA2
I/O
VDDIOP0
PB18
SPI1_NPCS3
TIOB2
I/O
VDDIOP0
PB19
I/O
VDDIOP0
PB20
I/O
VDDIOP0
PB21
I/O
VDDIOP0
PB22
I/O
VDDIOP0
PB23
I/O
VDDIOP0
I/O
VDDIOP0
PB25
I/O
VDDIOP0
PB26
I/O
VDDIOP0
PB24
DMARQ3
PB27
PWM2
I/O
VDDIOP0
PB28
TCLK0
I/O
VDDIOP0
PB29
PWM3
I/O
VDDIOP0
PB30
I/O
VDDIOP0
PB31
I/O
VDDIOP0
Function
Comments
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
34
10.3.3 PIO Controller C Multiplexing
Table 10-4. Multiplexing on PIO Controller C
PIO Controller C
Application Usage
Reset
State
Power
Supply
LCDVSYNC
I/O
VDDIOP0
PC1
LCDHSYNC
I/O
VDDIOP0
PC2
LCDDOTCK
I/O
VDDIOP0
PC3
LCDDEN
PWM1
I/O
VDDIOP0
PC4
LCDD0
LCDD3
I/O
VDDIOP0
PC5
LCDD1
LCDD4
I/O
VDDIOP0
PC6
LCDD2
LCDD5
I/O
VDDIOP0
PC7
LCDD3
LCDD6
I/O
VDDIOP0
PC8
LCDD4
LCDD7
I/O
VDDIOP0
PC9
LCDD5
LCDD10
I/O
VDDIOP0
PC10
LCDD6
LCDD11
I/O
VDDIOP0
PC11
LCDD7
LCDD12
I/O
VDDIOP0
PC12
LCDD8
LCDD13
I/O
VDDIOP0
PC13
LCDD9
LCDD14
I/O
VDDIOP0
PC14
LCDD10
LCDD15
I/O
VDDIOP0
PC15
LCDD11
LCDD19
I/O
VDDIOP0
PC16
LCDD12
LCDD20
I/O
VDDIOP0
PC17
LCDD13
LCDD21
I/O
VDDIOP0
PC18
LCDD14
LCDD22
I/O
VDDIOP0
PC19
LCDD15
LCDD23
I/O
VDDIOP0
PC20
LCDD16
ETX2
I/O
VDDIOP0
PC21
LCDD17
ETX3
I/O
VDDIOP0
PC22
LCDD18
ERX2
I/O
VDDIOP0
PC23
LCDD19
ERX3
I/O
VDDIOP0
PC24
LCDD20
ETXER
I/O
VDDIOP0
PC25
LCDD21
ERXDV
I/O
VDDIOP0
PC26
LCDD22
ECOL
I/O
VDDIOP0
PC27
LCDD23
ERXCK
I/O
VDDIOP0
PC28
PWM0
TCLK1
I/O
VDDIOP0
PC29
PCK0
PWM2
I/O
VDDIOP0
PC30
DRXD
I/O
VDDIOP0
PC31
DTXD
I/O
VDDIOP0
I/O Line
Peripheral A
PC0
Peripheral B
Function
Comments
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
35
10.3.4 PIO Controller D Multiplexing
Table 10-5. Multiplexing on PIO Controller D
PIO Controller D
Application Usage
I/O Line
Peripheral A
Peripheral B
Reset
State
Power
Supply
PD0
TXD1
SPI0_NPCS2
I/O
VDDIOP0
PD1
RXD1
SPI0_NPCS3
I/O
VDDIOP0
PD2
TXD2
SPI1_NPCS2
I/O
VDDIOP0
PD3
RXD2
SPI1_NPCS3
I/O
VDDIOP0
PD4
FIQ
DMARQ2
I/O
VDDIOP0
PD5
EBI0_NWAIT
RTS2
I/O
VDDIOM0
PD6
EBI0_NCS4/CFCS0
CTS2
I/O
VDDIOM0
PD7
EBI0_NCS5/CFCS1
RTS1
I/O
VDDIOM0
PD8
EBI0_CFCE1
CTS1
I/O
VDDIOM0
PD9
EBI0_CFCE2
SCK2
I/O
VDDIOM0
SCK1
I/O
VDDIOM0
PD10
PD11
EBI0_NCS2
TSYNC
I/O
VDDIOM0
PD12
EBI0_A23
TCLK
A23
VDDIOM0
PD13
EBI0_A24
TPS0
A24
VDDIOM0
PD14
EBI0_A25_CFRNW
TPS1
A25
VDDIOM0
PD15
EBI0_NCS3/NANDCS
TPS2
I/O
VDDIOM0
PD16
EBI0_D16
TPK0
I/O
VDDIOM0
PD17
EBI0_D17
TPK1
I/O
VDDIOM0
PD18
EBI0_D18
TPK2
I/O
VDDIOM0
PD19
EBI0_D19
TPK3
I/O
VDDIOM0
PD20
EBI0_D20
TPK4
I/O
VDDIOM0
PD21
EBI0_D21
TPK5
I/O
VDDIOM0
PD22
EBI0_D22
TPK6
I/O
VDDIOM0
PD23
EBI0_D23
TPK7
I/O
VDDIOM0
PD24
EBI0_D24
TPK8
I/O
VDDIOM0
PD25
EBI0_D25
TPK9
I/O
VDDIOM0
PD26
EBI0_D26
TPK10
I/O
VDDIOM0
PD27
EBI0_D27
TPK11
I/O
VDDIOM0
PD28
EBI0_D28
TPK12
I/O
VDDIOM0
PD29
EBI0_D29
TPK13
I/O
VDDIOM0
PD30
EBI0_D30
TPK14
I/O
VDDIOM0
PD31
EBI0_D31
TPK15
I/O
VDDIOM0
Function
Comments
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
36
10.3.5 PIO Controller E Multiplexing
Table 10-6. Multiplexing on PIO Controller E
PIO Controller E
Application Usage
Reset
State
Power
Supply
ISI_D0
I/O
VDDIOP1
PE1
ISI_D1
I/O
VDDIOP1
PE2
ISI_D2
I/O
VDDIOP1
PE3
ISI_D3
I/O
VDDIOP1
PE4
ISI_D4
I/O
VDDIOP1
PE5
ISI_D5
I/O
VDDIOP1
PE6
ISI_D6
I/O
VDDIOP1
PE7
ISI_D7
I/O
VDDIOP1
PE8
ISI_PCK
TIOA1
I/O
VDDIOP1
PE9
ISI_HSYNC
TIOB1
I/O
VDDIOP1
PE10
ISI_VSYNC
PWM3
I/O
VDDIOP1
PE11
PCK3
I/O
VDDIOP1
PE12
ISI_D8
I/O
VDDIOP1
PE13
ISI_D9
I/O
VDDIOP1
PE14
ISI_D10
I/O
VDDIOP1
PE15
ISI_D11
I/O
VDDIOP1
PE16
I/O
VDDIOP1
PE17
I/O
VDDIOP1
I/O Line
Peripheral A
PE0
Peripheral B
PE18
TIOA0
I/O
VDDIOP1
PE19
TIOB0
I/O
VDDIOP1
PE20
EBI1_NWAIT
I/O
VDDIOM1
PE21
ETXCK
EBI1_NANDWE
I/O
VDDIOM1
PE22
ECRS
EBI1_NCS2/NANDCS
I/O
VDDIOM1
PE23
ETX0
EB1_NANDOE
I/O
VDDIOM1
PE24
ETX1
EBI1_NWR3/NBS3
I/O
VDDIOM1
PE25
ERX0
EBI1_NCS1/SDCS
I/O
VDDIOM1
PE26
ERX1
I/O
VDDIOM1
PE27
ERXER
EBI1_SDCKE
I/O
VDDIOM1
PE28
ETXEN
EBI1_RAS
I/O
VDDIOM1
PE29
EMDC
EBI1_CAS
I/O
VDDIOM1
PE30
EMDIO
EBI1_SDWE
I/O
VDDIOM1
PE31
EF100
EBI1_SDA10
I/O
VDDIOM1
Function
Comments
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
37
10.4
System Resource Multiplexing
10.4.1 LCD Controller
The LCD Controller can interface with several LCD panels. It supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without
limitation. Interfacing 24 bpp TFT panels prevents using the Ethernet MAC. 16 bpp TFT panels are interfaced through
peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23.
Intensity bit is output on LCDD10. Using the peripheral B does not prevent using MAC lines. 16 bpp STN panels are
interfaced through peripheral A and color data is output on LCDD0 to LCDD15, thus MAC lines can be used on
peripheral B.
Mapping the LCD signals on peripheral A and peripheral B makes is possible to use 24 bpp TFT panels in 24 bits
(peripheral A) or 16 bits (peripheral B) by reprogramming the PIO controller and thus without hardware modification.
10.4.2 ETM™
Using the ETM prevents the use of the EBI0 in 32-bit mode. Only 16-bit mode (EBI0_D0 to EBI0_D15) is available,
makes EBI0 unable to interface CompactFlash and NAND Flash cards, reduces EBI0’s address bus width which makes
it unable to address memory ranges bigger than 0x7FFFFF and finally it makes impossible to use EBI0_NCS2 and
EBI0_NCS3.
10.4.3 EBI1
Using the following features prevents using EBI1 in 32-bit mode:
z
the second slots of MCI0 and/or MCI1
z
USART0
z
DMA request 0 (DMARQ0)
10.4.4 Ethernet 10/100MAC
Using the following features of EBI1 prevents using Ethernet 10/100MAC:
z
SDRAM
z
NAND (unless NANDCS, NANDOE and NANDWE are managed by PIO)
z
SMC 32 bits (SMC 16 bits is still available)
z
NCS1, NCS2 are not available in SMC mode
10.4.5 SSC
Using SSC0 prevents using the AC97 Controller and Two-wire Interface.
Using SSC1 prevents using DMA Request 1, PWM0, PWM1, LCDCC and PCK1.
10.4.6 USART
Using USART2 prevents using EBI0’s NWAIT signal, Chip Select 4 and CompactFlash Chip Enable 2.
Using USART1 prevents using EBI0’s Chip Select 5 and CompactFlash Chip Enable1.
10.4.7 NAND Flash
Using the NAND Flash interface on EBI1 prevents using Ethernet MAC.
10.4.8 CompactFlash
Using the CompactFlash interface prevents using NCS4 and/or NCS5 to access other parallel devices.
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
38
10.4.9 SPI0 and MCI Interface
SPI0 signals and MCI0 signals are multiplexed, as the DataFlash Card is hardware-compatible with the SDCard. Only
one can be used at a time.
10.4.10 Interrupts
Using IRQ0 prevents using the CAN controller.
Using FIQ prevents using DMA Request 2.
10.4.11 Image Sensor Interface
Using ISI in 8-bit data mode prevents using timers TIOA1, TIOB1.
10.4.12 Timers
Using TIOA2 and TIOB2, in this order, prevents using SPI1’s Chip Selects [2-3].
10.5
Embedded Peripherals Overview
10.5.1 Serial Peripheral Interface
z
z
z
Supports communication with serial external devices
z
Four chip selects with external decoder support allow communication with up to 15 peripherals
z
Serial memories, such as DataFlash and 3-wire EEPROMs
z
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
z
External co-processors
Master or slave serial peripheral bus interface
z
8- to 16-bit programmable data length per chip select
z
Programmable phase and polarity per chip select
z
Programmable transfer delays between consecutive transfers and between clock and data per chip select
z
Programmable delay between consecutive transfers
z
Selectable mode fault detection
Very fast transfers supported
z
Transfers with baud rates up to MCK
z
The chip select line may be left active to speed up transfers on the same device
10.5.2 Two-wire Interface
z
Master Mode only
z
Compatibility with standard two-wire serial memory
z
One, two or three bytes for slave address
z
Sequential read/write operations
10.5.3 USART
z
Programmable Baud Rate Generator
z
5- to 9-bit full-duplex synchronous or asynchronous serial communications
z
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
z
Parity generation and error detection
z
Framing error detection, overrun error detection
z
MSB- or LSB-first
z
Optional break generation and detection
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
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z
By 8 or by-16 over-sampling receiver frequency
z
Hardware handshaking RTS-CTS
z
Receiver time-out and transmitter timeguard
z
Optional Multi-drop Mode with address generation and detection
z
Optional Manchester Encoding
z
RS485 with driver control signal
z
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
z
NACK handling, error counter with repetition and iteration limit
z
IrDA modulation and demodulation
z
Test Modes
z
z
Communication at up to 115.2 Kbps
Remote Loopback, Local Loopback, Automatic Echo
10.5.4 Serial Synchronous Controller
z
Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master
or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
z
Contains an independent receiver and transmitter and a common clock divider
z
Offers a configurable frame sync and data length
z
Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame
sync signal
z
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.5.5 AC97 Controller
z
Compatible with AC97 Component Specification V2.2
z
Can interface with a single analog front end
z
Three independent RX Channels and three independent TX Channels
z
One RX and one TX channel dedicated to the AC97 analog front end control
z
One RX and one TX channel for data transfers, associated with a PDC
z
One RX and one TX channel for data transfers with no PDC
z
Time Slot Assigner that can assign up to 12 time slots to a channel
z
Channels support mono or stereo up to 20-bit sample length
z
Variable sampling rate AC97 Codec Interface (48 kHz and below)
10.5.6 Timer Counter
z
Three 16-bit Timer Counter Channels
z
Wide range of functions including:
z
z
Frequency Measurement
z
Event Counting
z
Interval Measurement
z
Pulse Generation
z
Delay Timing
z
Pulse Width Modulation
z
Up/down Capabilities
Each channel is user-configurable and contains:
z
Three external clock inputs
z
Five internal clock inputs
z
Two multi-purpose input/output signals
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
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z
Two global registers that act on all three TC Channels
10.5.7 Pulse Width Modulation Controller
z
4 channels, one 16-bit counter per channel
z
Common clock generator, providing thirteen different clocks
z
z
Modulo n counter providing eleven clocks
z
Two independent Linear Dividers working on modulo n counter outputs
Independent channel programming
z
Independent Enable Disable commands
z
Independent clock selection
z
Independent period and duty cycle, with double bufferization
z
Programmable selection of the output waveform polarity
z
Programmable center or left aligned output waveform
10.5.8 Multimedia Card Interface
z
Two double-channel Multimedia Card Interfaces, allowing concurrent transfers with 2 cards
z
Compatibility with MultiMediaCard Specification Version 3.31
z
Compatibility with SD Memory Card Specification Version 1.0
z
Compatibility with SDIO Specification Version V1.1
z
Cards clock rate up to Master Clock divided by 2
z
Embedded power management to slow down clock rate when not used
z
Each MCI has two slots, each supporting
z
z
One slot for one MultiMediaCard bus (up to 30 cards) or
z
One SD Memory Card
Support for stream, block and multi-block data read and write
10.5.9 CAN Controller
z
Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers
z
Bit rates up to 1Mbit/s.
z
Object-oriented mailboxes, each with the following properties:
z
CAN Specification 2.0 Part A or 2.0 Part B programmable for each message
z
Object Configurable as receive (with overwrite or not) or transmit
z
Local Tag and Mask Filters up to 29-bit Identifier/Channel
z
32 bits access to Data registers for each mailbox data object
z
Uses a 16-bit time stamp on receive and transmit message
z
Hardware concatenation of ID unmasked bitfields to speedup family ID processing
z
16-bit internal timer for Time Stamping and Network synchronization
z
Programmable reception buffer length up to 16 mailbox object
z
Priority Management between transmission mailboxes
z
Autobaud and listening mode
z
Low power mode and programmable wake-up on bus activity or by the application
z
Data, Remote, Error and Overload Frame handling
10.5.10 USB Host Port
z
Compliant with Open HCI Rev 1.0 Specification
z
Compliant with USB V2.0 full-speed and low-speed specification
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
41
z
Supports both low-speed 1.5 Mbps and full-speed 12 Mbps devices
z
Root hub integrated with two downstream USB ports
z
Two embedded USB transceivers
z
Supports power management
z
Operates as a master on the matrix
10.5.11 USB Device Port
z
USB V2.0 full-speed compliant, 12 Mbits per second
z
Embedded USB V2.0 full-speed transceiver
z
Embedded 2,432-byte dual-port RAM for endpoints
z
Suspend/Resume logic
z
Ping-pong mode (two memory banks) for isochronous and bulk endpoints
z
Six general-purpose endpoints
z
Endpoint 0 and 3: 64 bytes, no ping-pong mode
z
Endpoint 1 and 2: 64 bytes, ping-pong mode
z
Endpoint 4 and 5: 512 bytes, ping-pong mode
10.5.12 LCD Controller
z
Single and Dual scan color and monochrome passive STN LCD panels supported
z
Single scan active TFT LCD panels supported
z
4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
z
Up to 24-bit single scan TFT interfaces supported
z
Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
z
1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
z
1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
z
1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
z
Single clock domain architecture
z
Resolution supported up to 2048x2048
z
2D DMA Controller for management of virtual Frame Buffer
z
z
Allows management of frame buffer larger than the screen size and moving the view over this virtual frame
buffer
Automatic resynchronization of the frame buffer pointer to prevent flickering
10.5.13 Two D Graphics Controller
z
Acts as one Matrix Master
z
Commands are passed through the APB User Interface
z
Operates directly in the frame buffer of the LCD Controller
z
z
Line draw
z
Block transfer
z
Clipping
Commands queuing through a FIFO
10.5.14 Ethernet 10/100 MAC
z
Compatibility with IEEE Standard 802.3
z
10 and 100 Mbits per second data throughput capability
z
Full- and half-duplex operations
z
MII or RMII interface to the physical layer
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
42
z
Register Interface to address, data, status and control registers
z
DMA Interface, operating as a master on the Memory Controller
z
Interrupt generation to signal receive and transmit completion
z
28-byte transmit and 28-byte receive FIFOs
z
Automatic pad and CRC generation on transmitted frames
z
Address checking logic to recognize four 48-bit addresses
z
Support promiscuous mode where all valid frames are copied to memory
z
Support physical layer management through MDIO interface control of alarm and update time/calendar data in
10.5.15 Image Sensor Interface
z
ITU-R BT. 601/656 8-bit mode external interface support
z
Support for ITU-R BT.656-4 SAV and EAV synchronization
z
Vertical and horizontal resolutions up to 2048 x 2048
z
Preview Path up to 640*480
z
Support for packed data formatting for YCbCr 4:2:2 formats
z
Preview scaler to generate smaller size image
z
Programmable frame capture rate
SAM9263 [Summary]
6249IS–ATARM–28-Jan-13
43
11.
Package Drawings
11.1
Package Drawing AT91SAM9263B-CU
Figure 11-1. 324-ball TFBGA Package Drawing
Table 11-1.
Soldering Information
Ball Land
0.4 mm +/- 0.05
Soldering Mask Opening
0.275 mm +/- 0.03
Table 11-2.
Device and 324-ball TFBGA Package Maximum Weight
572
Table 11-3.
mg
324-ball TFBGA Package Characteristics
Moisture Sensitivity Level
Table 11-4.
3
Package Reference
JEDEC Drawing Reference
MO-210
JESD97 Classification
e1
This package respects the recommendations of the NEMI User Group.
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44
11.2
Package Drawing (AT91SAM9263B-CU-100)
Figure 11-2. 324-ball TFBGA Package Drawing
Table 11-5.
Soldering Information
Ball Land
0.4 mm +/- 0.05
Solder Mask Opening
0.275 mm +/- 0.03
Table 11-6.
Device and 324-ball TFBGA Package Maximum Weight
572
Table 11-7.
mg
324-ball TFBGA Package Characteristics
Moisture Sensitivity Level
Table 11-8.
3
Package Reference
JEDEC Drawing Reference
MO-275
JESD97 Classification
e8
This package respects the recommendations of the NEMI User Group.
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12. AT91SAM9263 Ordering Information
Table 12-1.
AT91SAM9263 Ordering Information
Marketing Revision Level B
Ordering Code
Temperature Operating
Range
Package
Package Type
AT91SAM9263B-CU
TFBGA 324
Green
Industrial
-40°C to 85°C
AT91SAM9263B-CU-100
TFBGA 324
Green
Industrial
-40°C to 85°C
SAM9263 [Summary]
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46
13.
Revision History
Table 13-1. Revision History
Document
Ref.
6459IS
Change
Request
Ref.
Comments
Ordering Code:
Table 12-1, ”AT91SAM9263 Ordering Information”,
Removed all reference to Marketing Revision Level A, AT91SAM9263-CU
Added AT91SAM9263B-CU-100 to Marketing Revision Level B Ordering Code.
8456
(msg3)
Package Drawings:
Section 11. ”Package Drawings”
Old Package Drawing removed.
Existing package described in: Section 11.1 ”Package Drawing AT91SAM9263B-CU”
Package drawings and related information added for SAM9263B-CU-100. Section 11.2 ”Package Drawing
(AT91SAM9263B-CU-100)”
Document format updated with subsequent change to pagination.
6249HS
8456
(msg3)
EBI0_NCS3 restriction added to Section 10.4.2 “ETM™” on page 38
6053
Second paragraph in Section 5.3 “Programmable I/O Lines Power Supplies” on page 13 edited.
6395
Overview:
”Features”
6249GS
Debug Unit (DBGU) updated.
5846
Section 10.4.3 ”EBI1”, updated
5903
Section 10.4.4 ”Ethernet 10/100MAC”, added to datasheet
Section 6.5 ”Shutdown Logic Pins”, updated, “SHDN pin is tri state output.......”
rfo
Section 5.1 ”Power Supplies”, VDDCORE and VDDBU updated.
Section 5.2, “Power Sequence Requirements removed from datasheet.
5791/5793
New Ordering Code: AT91SAM9263B-CU added to Table 12-1, ”AT91SAM9263 Ordering Information”.
5560
Section 8.1.2.1 ”BMS = 1, Boot on Embedded ROM”, changes to list under “Bootloader on a non-volatile
memory”
5425
Section 5.2 ”Power Sequence Requirements”, section added to datasheet.
5643
Section 10.4.3 ”EBI1”, System Resource Multiplexing, Ethernet 10/100 MAC limitation on EBI1 updated.
5713
Section 10.5.8 ”Multimedia Card Interface”, protocol specification compatibilities updated.
5282
Section 10.5.13 ”Two D Graphics Controller”, removed reference to Polygon Fill, removed from Features
also.
5206
Table 3-1, ”Signal Description List”, Image Sensor Interface, ISI_MCK is provided by PCK3.
5329
6249FS
6249ES
Table 10-6, ”Multiplexing on PIO Controller E”, ISI_MCK removed from PE11 line of the table.
SAM9263 [Summary]
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Table 13-1. Revision History
Document
Ref.
6249DS
Comments
Change
Request
Ref.
”Features”, SPI: Synchronous Communications feature removed.
4910
Section 5.1 ”Power Supplies”, VDDIO and VDDBU slope alignment described.
4967
Section 5.2 ”Power Consumption”, paragraph beginning with “On VDDBU...” updated.
4505
Section 10.5.8 ”Multimedia Card Interface”, “When REMAP = 1.....” removed from 2nd paragraph.
5029
Section 10.5.8 ”Multimedia Card Interface”, MMC and SDMC compatibility updated.
4945
Section 8.2.1.1 ”External Bus Interface 0”, feature added.
4146
Section 8.2.1.1 ”External Bus Interface 0”, feature added.
“Package and Pinout” , references to package are “324-TFBGA.
4664
Figure 9-3 ”AT91SAM9263 Power Management Controller Block Diagram” on page 28, /3 divider removed. 4834
Figure 11-1 ”324-ball TFBGA Package Drawing” on page 44, updated.
4668
SAM9263 [Summary]
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Table 13-1. Revision History
Document
Ref.
Comments
Change
Request
Ref.
In Section 4.1 “324-ball TFBGA Package Outline” on page 10 corrected package top view.
4463
All new information for Table 7-1, “List of Bus Matrix Masters,” on page 16, Table 7-2, “List of Bus Matrix
Slaves,” on page 16 and Table 7-3, “Masters to Slaves Access,” on page 17.
4466
In Section 9.3 “Shutdown Controller” on page 27, corrected reference to shutdown pin.
3870
6249CS
In Section 5.2 “Power Consumption” on page 13, specified static current consumption as worst case.
Corrected Section 10.4.7 “NAND Flash” on page 38, with information on EMAC.
3825
In Section 10.4.3 “EBI1” on page 38, added Ethernet 10/100 MAC to the System Resource Multiplexing list of
4064
EBI1.
In Section 10.4.11 “Image Sensor Interface” on page 39 and Section 10.4.12 “Timers” on page 39, removed
4407
mention of keyboard interfaces.
6249BS
6249AS
Corrected typo to IDE hard disk in Section “Description” on page 1.
3804
Corrected ordering code in Section “” on page 46.
3805
First issue.
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