Power Matters.TM RTG4 Board Level Considerations Microsemi Space Forum 2015 Bassam Youssef, Senior Staff Applications Engineer Jim Steward, Application Engineering © 2015 Microsemi Corporation. Company Proprietary. 1 Objectives Provide an overview of PCB design considerations for RTG4 designs focusing on: • Power Supplies • Memory Controller Interfaces • SERDES Interfaces Highlight information currently available in Microsemi documents © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 2 Power Supplies Supply Voltage Description VDD 1.2 V Core supply voltage VPP 3.3 V Power supply for device charge pumps VDDPLL 3.3 V Power for eight corner PLLs, PLLs in SERDES PCIe/PCS blocks, and FDDR PLL VDDIx 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V Bank supplies VREFx 0.5 * VDDIx SERDES_x_Lyz_VDDAIO 1.2 V SERDES_x_Lyz_VDDAPLL 2.5 V SERDES_VDDI 1.8 V, 2.5 V, or 3.3 V FDDR reference voltage TX/RX analog I/O voltage for SERDES lanes. Analog power for SERDES TXPLL and CDRPLL Power for SERDES reference clock receiver supply. SERDES_VREF 0.5 * SERDES_VDDI © 2015 Microsemi Corporation. Company Proprietary. External differential receiver reference voltage for SERDES Reference Clocks Power Matters.TM 3 Analog Supplies SERDES VDDAPLL Supply 2.5V 3.3W SERDES_x_Lyz_VDDAPLL 33uF 0.1uF SERDES_x_Lyz_REFRET 1.21KW 1% SERDES_x_Lyz_REXT FPGA PLL Supply External R-C filters provide filtering to sensitive analog PLL supplies. SERDES PLL = 2.5V • SERDES TXPLL and CDRPLL supply • SERDES Calibration resistor(REXT). 1.21KW – Impedance calibration (transmit, receive, and receiver equalization) FPGA PLLs = 3.3V Place all passive components as close to device as possible 3.3V 5W VDDPLL 22uF 47uF VSS © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 4 Power Supplies Specifications Key power supplies must comply to the specifications including operating range, POR trip points, and power supply ramping Monotonicity of VDD/VPP/VDDIx is required through its rise time Preliminary Data Symbol Description VDD Core Supply Voltage VPP Flash operating voltage VDDt VPPt Power ON Reset Threshold for VDD supply Power ON Reset Threshold for VPP supply VDD Power supply ramp rates ( from GND/0V) for all power supplies VDDr Tvddpor Power Up to Functional time (From VDD/VPP/VDDIx ramp to beginning of device ready © 2015 Microsemi Corporation. Company Proprietary. Min Typ Max Units 1.14 1.2 1.26 V 3 3.3 3.45 V 0.8 2.6 0.006 V V 24 60 mV/ms ms Power Matters.TM 5 Power-up/down Sequence There is no power-up/down sequence required for RTG4 if one of the following conditions is met: • All PLLs are held in reset until VDDPLL supply reaches its minimum recommended Operating Conditions level (shown below) • The device is held in reset by asserting DEVRST_N until VDDPLL supply reaches its minimum recommended level as stated above If none of the above conditions is met, VDDPLL must start ramping up and reach its minimum recommend level (as stated above) before VDD, VPP, or VDDIx starts ramping up • In other words, VDDPLL must not be the last supply to ramp up, and must reach its minimum recommended level before the last supply starts ramping up All I/O banks supplies must be powered for the RTG4 to power up • You can bring up the I/O banks in any order and before or after the core voltage © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 6 Power Supply Decoupling Capacitors To reduce any potential fluctuation on the power supply lines, proper onboard power supply decoupling caps is required • Keep decoupling caps close to pin (use 402’s where possible on underside of device BGA) • Distribute overall decoupling capacitance around the device perimeter • Use blind vias to remove crosstalk risk and cap surface mount area • Use larger power vias to reduce inductance- especially for high layer count boards. Pin Name PME (Precious Metal Electrode) decoupling caps within the package enhance overall PCB decoupling Internal PME capacitance available for LG/CG1657 package VDD 0.18uF/6.3V VDDI0 0.18uF/6.3V VDDI1 0.18uF/6.3V VDDI2 0.18uF/6.3V VDDI4 0.18uF/6.3V VDDI5 0.18uF/6.3V VDDI6 0.18uF/6.3V VDDI7 0.18uF/6.3V VDDI8 0.18uF/6.3V VDDI9 0.18uF/6.3V VDDPLL 0.8uF/6.3V © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 7 Radiation Tolerant Power Supplies Microsemi provides many Radiation-Tolerant components that can be used with RTG4 PCB designs Engineers should consider the following when selecting power supply components • Calculate required power of the RTG4 device – Power Calculator spreadsheet – SmartPower tool in Libero SoC • Select an appropriate Radiation-Tolerant regulator that can supply the required power and meet all the unique power requirements of the FPGA, using either of the below: – Radiation-Tolerant Linear-Regulator (Microsemi) – Radiation-Tolerant Switching regulator (Microsemi) © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 8 DDR3 Memory Interface DDR3 Characteristics • SSTL15 interface • RTG4 On-Die termination • RTG4 IMP_CALIB resistor • • • • • – 240W CMD/ADDR require external termination to VTT(0.75V) CLK_P/CLK_N requires differential resistor at memory clk input Match ADDR/CMD/CTRL to CLK Tightly match DQ/DM/DQS delays TMATCH DQS compensation © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 9 DDR2 Memory Interface DDR2 Characteristics • SSTL18 • RTG4 On-Die termination • RTG4 IMP_CALIB resistor – 150W • CMD/ADDR require external • • • • • termination to VTT(0.9V) CLK_P/CLK_N requires differential resistor at memory clk input Match ADDR/CMD/CTRL to CLK Tightly matched DQ/DM/DQS delays Loosely match DQS to CLK TMATCH DQS compensation © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 10 LPDDR Memory Interface LPDDR Characteristics • • • • • LVCMOS18 Match ADDR/CMD/CTRL to CLK Tightly matched DQ/DM/DQS Loosely match DQS to CLK TMATCH DQS compensation © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 11 SERDES Routing Proper differential pair routing is needed for proper common-mode rejection and noise immunity • Pair-to-pair spacing is 2X greater than trace-to-trace spacing Avoid Routing Discontinuities: • • No Plane Split Crossing Do not route High-Speed signals close to the edge of a plane © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 12 SERDES Differential Skew "Differential skew" refers to the time difference between the two singleended signals in a differential pair (LANE) Skew limits the bandwidth, adds data-dependent jitter, and limits the possibility of properly equalizing lanes © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 13 SERDES Skew Matching P & N trace skew matching “meandering” is used to balance the skew of the pair, it should be distributed throughout the trace length Immediately compensating will result in better skew distribution Keep traces matched throughout routing, not at the end © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 14 AC-Coupling RTG4 requires AC-Coupling for all SERDES applications including PCI Express for link detection AC-coupling provides common-mode independence Tx Rx Use symmetrical routing and placement for best performance. Creates wider trace spacing resulting in more discontinuity © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 15 AC-Coupling Minimize reflections from the mounting structures with cut-outs in the reference plane Clearing of the reference plane underneath the ac-coupling cap produces less discontinuities of the routing path © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 16 SpaceWire: ES/MS to PROTO/Flight Silicon RTG4 ES device supports 12 SpaceWire ports • RTG4 ES Dev board supports 12 SpaceWire ports The SpaceWire package pin assignment will be updated in the next silicon revision for PROTO and flight units to support 16 SpaceWire ports • RTG4 Production Dev board will support 13 SpaceWire ports Going from the current silicon revision to the next silicon revision, refer to the pin mapping of the device on the Dev board SpaceWire Pin Mapping from RTG4 ES/MS Silicon to PROTO/Flight Silicon for RTG4 Development Kit © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 17 CG1657 Package Pins Two devices are available in Libero SoC Software • RT4G150_ES CG1657 • RT4G150 (production) CG1657 Software generated package pins for RT4G150_ES are not compatible with pins generated for RT4G150 device • Due to SpaceWire enhancements The following pin mapping tables are provided to help you start designing your board SpaceWire Pin Mapping from RTG4 ES/MS Silicon to PROTO/Flight Silicon SpaceWire Pin Mapping from RTG4 ES/MS Silicon to PROTO/Flight Silicon for RTG4 Development Kit © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 18 Take-Aways Understand key points of the RTG4 power supplies and requirements Recognize the different PCB topologies and features for the memory controllers available with the RTG4 Awareness of SERDES layout methods needed for PCB first-time success © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 19 Appendix © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 20 Thank You Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiationhardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Ethernet solutions; Power-overEthernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,600 employees globally. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 email: [email protected] Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. ©2015 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. © 2015 Microsemi Corporation. Company Proprietary. Power Matters.TM 21