Application Note AC393 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table of Contents Purpose . . . . . . . Introduction . . . . . References . . . . . Designing the Board Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 2 3 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Sequencing and Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Behavior During Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 7 8 9 Limiting Surge Current During Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Main Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Auxiliary (RTC) Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset Circuit . . . . JTAG . . . . . . . . Special Pins . . . . . Device Programming SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes Reference Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 19 19 19 20 20 21 21 LPDDR, DDR2, and DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MDDR/FDDR Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VREF Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VTT Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LPDDR and DDR2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR3 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O and Clock Pins 22 23 23 24 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Internal Clamp Diode Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Achieving a Two-Rail Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Configuring Pins in Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Brownout Detection (BOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Purpose This application note provides board-level design guidelines for SmartFusion®2 and IGLOO®2 devices. This document acts as a companion to AC394: Layout Guidelines for SmartFusion2/IGLOO2-Based Board Design Application Note which covers the details of PCB design. May 2016 © 2016 Microsemi Corporation Revision 10 1 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Introduction Good board design practices are required to achieve expected performance from both the PCB and SmartFusion2/IGLOO2 devices. High quality and reliable results depend on minimizing noise levels, preserving signal integrity, meeting impedance and power requirements, and using appropriate SerDes protocols. These guidelines should be treated as a supplement to standard board-level design practices. This document assumes that the reader has a good understanding of the SmartFusion2/IGLOO2 device, is experienced in digital and analog board design, and knowledgeable in the electrical characteristics of systems. Background information on the key theories and concepts of board-level design is available in High Speed Digital Design: A Handbook of Black Magic1, and other industry literature. References The following documents are referenced in this application note: • AC394: Layout Guidelines for SmartFusion2/IGLOO2-Based Board Design App Note • CL0034: SmartFusion2/IGLOO2 Hardware Board Design Checklist • DS0120: Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet • DS0115: SmartFusion2 Pin Descriptions Datasheet • DS0124: IGLOO2 Pin Descriptions Datasheet • UG0445: SmartFusion2 SoC and IGLOO2 FPGA Fabric User Guide • UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide • UG0451: IGLOO2 and SmartFusion2 Programming User Guide • UG0450: SmartFusion2 SoC and IGLOO2 FPGA System Controller User Guide • SmartFusion2 FPGA Fabric DDR Controller Configuration Guide • SmartFusion2 MSS DDR Controller Configuration Guide • AC396: SmartFusion2 and IGLOO2 in Hot Swapping and Cold Sparing App Note Designing the Board The SmartFusion2/IGLOO2 device supports various high-speed interfaces using both double data rate input/output (DDRIO) and SerDes I/O. DDRIO is a multi-standard I/O optimized for low-power DDR, DDR2, and DDR3 performance. SerDes I/O are dedicated to high-speed serial communication protocols. The SerDes I/O supports protocols such as PCI Express 2.0, 10 Gbps attachment unit interface (XAUI), serial gigabit media independent interface (SGMII), JESD204B, as well as user-defined high-speed serial protocol implementation in fabric. Routing high-speed serial data over a PCB is a challenge as losses, dispersion, and crosstalk effects increase with speed. Channel losses and crosstalk decrease the signal-to-noise ratio and limit the data rate on the channel. Subsequent sections discuss the following: • Power Supplies • Limiting Surge Current During Device Reset • Clocks • Reset Circuit • JTAG • Special Pins • Device Programming • SerDes • LPDDR, DDR2, and DDR3 • User I/O and Clock Pins 1. 2 Johnson, Howard, and Martin Graham, High Speed Digital Design: A Handbook of Black Magic. Prentice Hall PTR, 1993. ISBN-10 0133957241 or ISBN-13: 978-0133957242 Revision 10 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs • Achieving a Two-Rail Design • SerDes • Brownout Detection (BOD) See CL0034: SmartFusion2/IGLOO2 Hardware Board Design Checklist to verify the design. Power Supplies Figure 1 illustrates the typical power supply requirements, including PLL RC filter values, for SmartFusion2/IGLOO2 devices. For information on decoupling capacitors associated with individual power supplies, see Table 1 on page 5. SmartFusion2/IGLOO2 1.2 / 1.5 / 1.8 / 2.5 V I/O Bank Supply VDDI (MSIOD & DDRIO) 1.2 / 1.5 / 1.8 / 2.5 / 3.3 V 1.2 V Tx/Rx Analog I/O Supply SERDES_x_L01_VDDAIO SERDES_x_L23_VDDAIO VDDI (MSIO & JTAG) PCIe/PCS Supply SERDES_x_VDD 120 Ω 10 μF SerDes PLL Analog Supply 2.5 / 3.3 V Charge Pump VPP* SERDES_x_VDD 2. 5 V 3.3 SERDES_x_L01_VDDAPLL 0.1 μF 33 μF SERDES_x_L01_REFRET 1.21kΩ ,1% SERDES_x_L01_REXT 2.5 V 3.3 2.5 / 3.3 V eNVM Supply VPPNVM* VSSNVM SERDES_x_L23_VDDAPLL 0.1 μF 33 μF SERDES_x_L23_REFRET 1.21kΩ ,1% SERDES_x_L23_REXT Aux. PLL PCIe Supply SERDES_x_PLL_VDDA VDD Core Supply VDD 2.5 / 3.3 V 50 0.1 μF 22 μF SERDES_x_PLL_VSSA VSS PLL Analog Supply 1 2.5 / 3.3 V CCC_xyz_PLL_VDDA 0.1 μF VDDIx 1 kΩ, 1% 22 μF CCC_xyz_PLL_VSSA MDDR/FDDR VREFx DDR PLL Supply 1 2.5 / 3.3 V MSS/HPMS_xDDR_PLL_VDDA 0.1 μF 1 kΩ, 1% 22 μF MSS/HPMS_xDDR_PLL_VSSA Figure 1 • Power Supplies R ev i si o n 1 0 3 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Notes: • *For M2S090T(S), M2GL090T(S), M2S150T(S),and M2GL150T(S) devices, the VPP and VPPNVM must be connected to a +3.3 V supply. • For the CCC_xyz_PLL supplies, xy refers to the location of the PLL in the device (NE/ NW/ SW) and z refers to the number associated with the PLL (0 or 1). • The PLL RC values shown in the figure are applicable to all variants of SmartFusion2/IGLOO2 devices. For the device to operate successfully, power supplies must be free from unregulated spikes and the associated grounds must be free from noise. All overshoots and undershoots must be within the absolute maximum ratings provided in the corresponding datasheet (DS0120: Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet). The various power supplies needed for IGLOO2 and SmartFusion2 FPGAs are as follows: VDD and VPP: The main power supplies for the device. These must be connected to the appropriate power rail based upon system requirements. VDDIx: I/O bank supplies for the device. For recommendations for unused I/O bank supplies, see Table 4 on page 10 and Table 5 on page 12. VPPNVM: eNVM supply for the device. This pin must be connected to the VPP supply. VREFx: Reference voltage for MDDR/FDDR signals, which is powered through the corresponding bank supply (VDDIx).Can be DNC or grounded (VSS) when unused. SERDES_x_VDD: The PCIe/PCS supply for the device. If the SERDES_x_VDD supply is powered by a separate LDO, a ferrite bead is not required for noise filtering at this supply. However, if SERDES_x_VDD and the core VDD supply are sharing the same power source, then a ferrite bead is required for SERDES_x_VDD, as shown in Figure 1 on page 3. SERDES_x_Lyz_VDDAIO: The +1.2 V SerDes PMA supply for Tx/Rx analog I/O. CCC_xyz_PLL_VDDA and MSS_xDDR_PLL_VDDA: If the associated PLL is used as a clock multiplier, these supplies must be connected over the RC filter circuitry between the common PLL supply and the corresponding onboard PLL return path. If the PLL is unused or used as a clock divider, these supplies can be connected directly to either 2.5 V or 3.3 V without filter circuitry. SERDES_x_Lyz_REFRET: This pin provides the internal PLL current return path for SERDES_x_Lyz_VDDAPLL. This pin must be connected to the corresponding SerDes VDDA PLL through an RC filter circuit, as shown in Figure 1 on page 3. REFRET and digital ground (VSS) are shorted internally in the silicon. Therefore, to filter noise and control long-term jitter, REFRET must not be connected to an external ground. SERDES_x_PLL_VSSA: This pin provides the internal PLL current return path for SERDES_x_PLL_VDDA. This pin must be connected to the corresponding PLL_VDDA through an RC filter circuit, as shown in Figure 1 on page 3. PLL_VSSA and VSS are shorted internally in the silicon. Therefore, to filter noise and control long-term jitter, PLL_VSSA must not be connected to an external ground. CCC_xyz_PLL_VSSA: This pin provides the internal PLL current return path for CCC_xyz_PLL_VDDA. This pin must be connected to the corresponding PLL_VDDA through an RC filter circuit, as shown in Figure 1 on page 3. PLL_VSSA and VSS are shorted internally in the silicon. Therefore, to filter noise and control long-term jitter, PLL_VSSA must not be connected to an external ground. MSS/HPMS_xDDR_PLL_VSSA: This pin provides the internal PLL current return path for MSS/HPMS_xDDR_PLL_VDDA. This pin must be connected to the corresponding PLL_VDDA through an RC filter circuit, as shown in Figure 1 on page 3. PLL_VSSA and VSS are shorted internally in the silicon. Therefore, to filter noise and control long-term jitter, PLL_VSSA must not be connected to an external ground. For detailed pin descriptions, see DS0115: SmartFusion2 Pin Descriptions Datasheet or DS0124: IGLOO2 Pin Descriptions Datasheet. 4 Revision 10 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Power Supply Decoupling To reduce any potential fluctuation on the power supply lines, decoupling capacitors, bypass capacitors, and other power supply filtering techniques must be used. To save board space, fewer, larger-value bulk capacitors can be used instead of a large number of smaller capacitors. However, care must be taken to ensure that the electrical characteristics of the consolidated capacitors (ESR and ESL) match those of the parallel combination of the recommended capacitors. Ceramic capacitors are preferred for high-frequency noise elimination and tantalum capacitors for low-frequency noise elimination. • For values ranging from 1 nF to 100 µF, use X7R or X5R (dielectric material) type capacitors. • For values ranging from 100 µF to 1000 µF, use tantalum capacitors. Figure 2 shows an impedance versus frequency graph for effective combinations of three values of capacitors. From the graph it is evident that impedance is less for wider frequency band when different capacitors are in parallel. Figure 2 • Impedance of Three Capacitors in Parallel Table 1 lists the recommended number of PCB decoupling capacitors for an M2S050T/M2GL050T-FG896 device: Table 1 • Power Supply Decoupling Capacitors Pin Name No. of Pins Ceramic Caps Tantalum Caps 0.01 µF 0.1 µF 10 µF 33 µF 22 µF 47 µF 100 µF 220 µF3 330 µF VDD 24 12 12 – – – – 1 3 1 VDDI0 29 14 14 – – – 2 – – – VDDI1 4 2 2 1 – – – – – – VDDI2 4 2 2 1 – – – – – – Notes: 1. Single ceramic decoupling capacitor is required for both pins at the device. 2. Single ceramic decoupling capacitor is required for four pins at the device. 3. 220 µF is used to limit surge current for the VDD supply. R ev i si o n 1 0 5 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 1 • Power Supply Decoupling Capacitors Pin Name No. of Pins Ceramic Caps Tantalum Caps 0.01 µF 0.1 µF 10 µF 33 µF 22 µF 47 µF 100 µF 220 µF3 330 µF VDDI3 5 2 3 1 – – – – – – VDDI4 3 2 1 1 – – – – – – VDDI5 29 14 14 – – – 2 – – – VDDI6 1 1 – 1 – – – – – – VDDI7 6 3 3 1 – – – – – – VDDI8 5 2 3 1 – – – – – – VDDI9 1 1 1 – – – – – – – VPP 4 2 2 1 – – – – – – VREF0 3 2 1 1 – – – – – – VREF5 3 2 1 1 – – – – – – VPPNVM 1 1 1 – – – – – – SERDES_0_VDD 2 1 1 – – – – – – SERDES_1_VDD 2 1 1 – – – – – – SERDES_0_L01_VDDAIO 1 – – – – – 1 11 – SERDES_0_L23_VDDAIO 11 – – – – – – SERDES_1_L01_VDDAIO 1 – – – – – – SERDES_1_L23_VDDAIO 1 – – – – – – CCC_NE0_PLL_VDDA 11 12 11 11 1 – 1 – – 1 – – – – CCC_NE1_PLL_VDDA 1 – 1 – – 1 – – – – CCC_NW0_PLL_VDDA 1 – 1 – – 1 – – – – CCC_NW1_PLL_VDDA 1 – 1 – – 1 – – – – CCC_SW0_PLL_VDDA 1 – 1 – – 1 – – – – CCC_SW1_PLL_VDDA 1 – 1 – – 1 – – – – MSS_FDDR_PLL_VDDA 1 – 1 – – 1 – – – – MSS_PLL_MDDR_VDDA 1 – 1 – – 1 – – – – PLL_SERDES_0_VDDA 1 – 1 – – 1 – – – – PLL_SERDES_1_VDDA 1 – 1 – – 1 – – – – SERDES_0_L01_VDDAPLL 1 – 1 – 1 – – – – – SERDES_0_L23_VDDAPLL 1 – 1 – 1 – – – – – SERDES_1_L01_VDDAPLL 1 – 1 – 1 – – – – SERDES_1_L23_VDDAPLL 1 – 1 – 1 – – – – Notes: 1. Single ceramic decoupling capacitor is required for both pins at the device. 2. Single ceramic decoupling capacitor is required for four pins at the device. 3. 220 µF is used to limit surge current for the VDD supply. 6 Revision 10 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Decoupling capacitors other than those listed in Table 1 can be used if sized to meet or exceed the performance of the network given in this example. However, substitution requires analysis of the resulting power distribution system’s impedance versus frequency to ensure that no resonant impedance spikes result. See Figure 1 on page 3 for power supply schematics design. Table 2 lists the recommended decoupling capacitors for the SmartFusion2/IGLOO2 devices. For placement and routing details, see AC394: Layout Guidelines for SmartFusion2/IGLOO2-Based Board Design App Note. Table 2 • Recommended Capacitors Part Number Manufacturer Description GRM155R71C103KA01D Murata Ceramic 0.01 µF, 16 V, 10%, X7R, 0402 GRM155R71C104KA88D Murata Ceramic 0.1 µF, 16 V, 10%, X7R, 0402 GRM188R60J106ME47D Murata Ceramic 10 µF, 6.3 V, X5R, 0603 T491B475M016AT KEMET Tantalum 4.7 µF, 16 V, 20%, 1411 T491B226M016AT KEMET Tantalum 22 µF, 16 V, 20%, 1411 T491B476M010AT KEMET Tantalum 47 µF, 10 V, 20%SMD T520V107M010ATE050 KEMET Tantalum 100 µF, 10 V, 20%, 2917 AVX Tantalum 330 µF, 10 V, 10%, 2917 TPSD337K010R0050 Power Supply Sequencing and Power-on Reset Sophisticated power-up management circuitry is designed into each SmartFusion2/IGLOO2 device. These circuits ensure easy transition from the power-off to power-up states of the device. The embedded system controller is responsible for systematic power-on reset whenever the device is powered on or reset. All the I/O are held in a high-impedance state by the system controller until all power supplies are at their required levels and the system controller has completed the reset sequence. The power-on reset circuitry requires the VDD and VPP supplies to ramp monotonically from 0 V to the minimum recommended operating voltage within a predefined time. There is no mandatory sequencing requirement for VDD, VDDI, and VPP. Four power-on reset delay options are available in the Libero® SoC software during design generation: 50 µs, 1 ms, 10 ms, and 100 ms. I/O Behavior During Power-Down Device reset (DEVRST_N) is an asynchronous signal powered through VPP. If a device gets reset during normal operation or if VPP is powered down while the other supplies are still up, glitch is observed on fabric I/O only if the fabric I/O is driven low or is tristated (configured as output). Table 3 • Glitch Occurrence During Various Power-Down Scenarios Scenario Fabric I/O output driving low Fabric I/O output driving high Device Reset Condition Power Supply Condition Glitch Occurs on I/O (Yes/No) VPP and DEVRST_N are VDD and VDDI are stable. ramped down. Yes VPP and DEVRST_N are VDD and VDDI are ramped stable. down. No DEVRST_N is ramped down. VPP, VDD, VDDI are stable. Yes DEVRST_N is ramped down. VPP, VDD, VDDI are stable. No DEVRST_N is ramped up. No VPP, VDD, VDDI are stable. R ev i si o n 1 0 7 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 3 • Glitch Occurrence During Various Power-Down Scenarios (continued) Scenario Fabric I/O tristated Power Supply Condition Glitch Occurs on I/O (Yes/No) VPP, VDD, VDDI are stable. No DEVRST_N is ramped down. VPP, VDD, VDDI are stable. Yes Device Reset Condition DEVRST_N is ramped up. To minimize glitch on fabric I/O during power-down, any one of the following solutions can be used: • The device should enter Flash*Freeze mode before a device reset is asserted. • In the power-down sequence, VDDI should be powered down first, followed by DEVRST_N assertion. • An external pull-down resistor (for example, a 1K resistor) should be used for the fabric I/O. • Critical outputs should be driven high before DEVRST_N assertion. Power Supply Flow SmartFusion2/IGLOO2 FPGA devices require multiple power supplies. Figure 3 illustrates one topology for generating the required power supplies from a single 12 V source. This example power supply topology is based on SmartFusion2 M2S050T-FG896 device with two SerDes channels (SERDES0 and SERDES1) and a DDR3 interface. +12 V VDD SERDES_x_VDD SERDES_x_L01VDDAIO SERDES_x_L23VDDAIO +1.2 V PTH08T230WAZ Texas Instruments +5 V NX7102 Microsemi +3.3 V MIC37102YM Micrel +2.5 V MIC37102YM Micrel +2.5 V PLL_SERDES_x_VDDA PLL_xDDR_VDDA PLLMDDRVDDA CCC_Sxy_PLL_VDDA VPPNVM VPP VDDIO6_2P5 VDDIO9_2P5 SERDES_x_L01_VDDAPLL SERDES_x_L23_VDDAPLL VDDIO5_2P5 MIC69502WR Micrel +3.3 V NX9415CMTR Microsemi VDDIO1_3P3 VDDIO2_3P3 VDDIO3_3P3 VDDIO4_3P3 VDDIO8_3P3 DDR3_1P5 MIC69502WR Micrel +1.8 V MIC69502WR Micrel Figure 3 • Example Power Supply Topology 8 VDDIO0_1P5 Revision 10 VDDIO7_1P8 TPS51200 Texas Instruments DDR3_VTT Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Unused Pin Configurations In cases where certain interfaces are not used, the associated pins need to be configured properly. For example, the pins of an unused crystal oscillator can be left floating (DNC) and should not be grounded. If a PLL is not used or bypassed, and only the divider circuitry is used, then the PLL’s pins can be powered without RC filter circuitry. For SmartFusion2/IGLOO2 devices with multiple SerDes blocks, designers should tie off unused SerDes blocks, as shown in Figure 4 on page 9. For banks configured as LPDDR or single-ended I/O (and MDDR or FDDR functionalities are not being used), VREFx can be left floating (DNC) even though the corresponding bank supply is still powered. To allow a SmartFusion2/IGLOO2 device to exit from reset, some of the bank supplies (VDDIx) must always be powered, even if associated bank I/O are unused (as shown in Table 4 on page 10 and Table 5 on page 12). For details on bank locations for all the devices, see DS0115: SmartFusion2 Pin Descriptions Datasheet or DS0124: IGLOO2 Pin Descriptions Datasheet. SmartFusion2/IGLOO2 1.2 V VDD SERDES_x_VDD 1.2 V SERDES_x_L01_VDDAIO VDD 2.5/3.3 V SERDES_x_L23_VDDAIO 1 VPP 1.2 V/2.5 V SERDES_x_L01_VDDAPLL 1 SERDES_x_L 23_VDDAPLL VPPNVM 2.5 V/3.3 V 1.2 / 1.5 / 1.8 / 2.5 / 3.3 V SERDES_x_PLL_VDDA VDDIx 2 SERDES_x_L01_REFRET SERDES_x_L23_REFRET SERDES_x_RXD[3:0]_P SERDES_x_RXD[3:0]_N SERDES_x_PLL_VSSA 2.5 V/3.3 V CCC_xyz_PLL _VDDA SERDES_x_TXD[3:0]_P MSS/HPMS_xDDR_PLL_VDDA CCC_ xyz_PLL _ VSSA MSS/HPMS_xDDR_PLL_VSSA SERDES_x_TXD[3:0]_N SERDES_x_L01_REXT SERDES_x_L23_REXT DNC or VSS VREFx VDDI(JTAG) 1 kΩ JTAGSEL 1 kΩ JTAGTCK DNC XTLOSC_[MAIN/AUX]_EXTAL DNC XTLOSC_[MAIN/AUX]_XTAL MSIO MSIOD Libero Defined * DNC 3 DDRIO VSS VSSNVM Figure 4 • Recommendations for Unused Pin Configurations Notes: 1. For M2S090T(S), M2GL090T(S), M2S150T(S), and M2GL150T(S) devices, the VPP and VPPNVM must be connected to a +3.3 V supply. 2. For recommendations on unused VDDI supplies, see Table 4 on page 10 and Table 5 on page 12. 3. For details on Libero Defined * DNC, see the device pinout spreadsheets. R ev i si o n 1 0 9 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs SmartFusion2/IGLOO2 devices have multiple bank supplies. In cases where specific banks are not used, Microsemi recommends connecting them as listed in Table 4 and Table 5. Table 4 • Recommendation for Bank Supplies for Packages FC1152, FG896, FG676, FCS536, FCV484, and FG484 FC1152 FG896 FCS536 FCV484 M2S150T/ M2GL050T M2S050T/ M2GL050T M2S090T/ M2GL090T M2S060T/ M2GL060T M2S150T/ M2GL150T M2S150T/ M2GL150 M2S090T/ M2GL090T M2S060T M2GL060T M2S050T/ M2GL050T M2S025T/ M2GL025T M2S010T/ M2GL010T M2S005/ M2GL005 VDDI0 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating – – – Can be left floating Can be left floating Can be left floating Can be left floating VDDI1 Can be left floating Must connect to VDDI1 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 VDDI2 Can be left floating Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Can be left floating Can be left floating Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 VDDI3 Can be left floating Must connect to VDDI3 Must connect to VDDI3 Must connect to VDDI3 Can be left floating Can be left floating Must connect to VDDI3 – Must connect to VDDI3 Can be left floating Can be left floating Can be left floating VDDI4 Can be left floating Can be left floating Can be left floating Must connect to VDDI4 Can be left floating Can be left floating Can be left floating Must connect to VDDI4 Can be left floating Must connect to VDDI4 Must connect to VDDI4 Must connect to VDDI4 VDDI5 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating VDDI6 Must connect to VDDI6 Can be left floating Can be left floating Can be left floating Must connect to VDDI6 Must connect to VDDI6 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating VDDI7 Must connect to VDDI7 Can be left floating Can be left floating Can be left floating Must connect to VDDI7 Must connect to VDDI7 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating – VDDI8 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating – Can be left floating Can be left floating Can be left floating – – – VDDI9 Can be left floating Can be left floating – Can be left floating Can be left floating Can be left floating – Can be left floating – – – – VDDI10 Can be left floating – – – Can be left floating Can be left floating – – – – – – VDDI11 Can be left floating – – – Can be left floating Can be left floating – – – – – – Bank Supply Names 10 FG676 FG484 Re vis i o n 10 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 4 • Recommendation for Bank Supplies for Packages FC1152, FG896, FG676, FCS536, FCV484, and FG484 (continued) FC1152 FG896 FCS536 FCV484 M2S150T/ M2GL050T M2S050T/ M2GL050T M2S090T/ M2GL090T M2S060T/ M2GL060T M2S150T/ M2GL150T M2S150T/ M2GL150 M2S090T/ M2GL090T M2S060T M2GL060T M2S050T/ M2GL050T M2S025T/ M2GL025T M2S010T/ M2GL010T M2S005/ M2GL005 VDDI12 Can be left floating – – – Can be left floating Can be left floating – – – – – – VDDI13 Can be left floating – – – Can be left floating Can be left floating – – – – – – VDDI14 Can be left floating – – – Can be left floating Can be left floating – – – – – – VDDI15 Can be left floating – – – Can be left floating – – – – – – – VDDI16 Can be left floating – – – Can be left floating Can be left floating – – – – – – VDDI17 Can be left floating – – – Can be left floating Can be left floating – – – – – – VDDI18 Can be left floating – – – Can be left floating – – – – – – – Bank Supply Names FG676 FG484 Note: If there is no recommendation provided for a device-bank supply combination, it means the bank is not pinned out. R ev i si o n 1 0 11 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 5 • Recommendation for Bank Supplies for Packages VF400, FCS325, VF256, and TQ144 Bank Supply Names VF400 M2S060T/ M2S050T/ M2GL060T M2GL050T FCS325 VF256 TQ144 M2S025T/ M2GL025T M2S010T/ M2GL010T M2S005/ M2GL005 M2S090T/ M2GL090T M2S060T/ M2GL060T M2S050T/ M2GL050T M2S025T/ M2GL025T M2S025T/ M2S010T/ M2GL025T M2GL010T M2S005S/ M2GL005S M2S010T/ M2GL010T M2S005S/ M2GL005S VDDI0 – Can be left floating Can be left floating Can be left floating Can be left floating – – Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating VDDI1 Can be left floating Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 Can be left floating Can be left floating Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 Must connect to VDDI1 – VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 Must connect to VDDI2 VDDI3 Must connect to VDDI3 Must connect to VDDI3 Can be left floating Can be left floating Can be left floating Must connect to VDDI3 Must connect to VDDI3 Must connect to VDDI3 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating VDDI4 Must connect to VDDI4 Can be left floating Must connect to VDDI4 Must connect to VDDI4 Must connect to VDDI4 Can be left floating Must connect to VDDI4 Can be left floating Must connect to VDDI4 Must connect to VDDI4 Must connect to VDDI4 Must connect to VDDI4 Must connect to VDDI4 Must connect to VDDI4 VDDI5 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating – Can be left floating VDDI6 Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating VDDI7 Can be left floating Can be left floating Can be left floating Can be left floating – Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating Can be left floating – Can be left floating – VDDI8 Can be left floating Can be left floating – – – Can be left floating Can be left floating Can be left floating – – – – – – VDDI9 Can be left floating – – – – – Can be left floating – – – – – – – 12 Re vis i o n 10 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Limiting Surge Current During Device Reset After device power-up, if the application asserts the DEVRST_N pin and there are no decoupling capacitors on the board, additional surge current on VDD may be observed during assertion of DEVRST_N or during a digest check operation. This section describes how to minimize additional surge current during SmartFusion2/IGLOO2 device reset operation. Note that this additional surge current does not occur during device power-up; it is applicable only when DEVRST_N is asserted. SmartFusion2/IGLOO2 device reset can be activated either directly through an external DEVRST_N pin or indirectly through the tamper macro IP. When the device reset is asserted, the system controller immediately puts the FPGA core in inactive state. During this operation, depending on the board design layout and decoupling capacitors used, there may be additional surge current on the VDD power rail. The additional surge current has no effect on device reliability. This surge current is for a very short duration and is normally handled by bulk decoupling capacitors on the power plane in a typical system. In cases where Microsemi-recommended board design guidelines cannot be implemented for decoupling capacitors for VDD (due to limited board spacing or other reasons), higher-than-expected surge current may occur during device reset. Table 6 provides characterized surge current data for VDD during DEVRST_N assertion. This data represents the worst-case condition with no decoupling capacitors on the board. Table 6 • Surge Current on VDD during DEVRST_N Assertion (No Decoupling Capacitors on Board) Surge Current on VDD Device Width of Surge at 50% of Pulse (µS) 0°C to 85°C -40°C to 100°C -55°C to 125°C Units M2S005/M2GL005 2 0.5 0.6 0.6 A M2S010/M2GL010 3 0.9 0.9 0.9 A M2S025/M2GL025 6 1.7 1.7 1.7 A M2S050/M2GL050 12 3.2 3.2 3.2 A M2S060/M2GL060 12 3.2 3.2 3.2 A M2S090/M2GL090 22 4.4 4.6 4.6 A M2S150/M2GL150 42 7.0 7.3 7.3 A However, the surge current data in Table 6 does not represent a typical system. To illustrate this, surge current during device reset was measured at room temperature separately for the M2S090 security evaluation kit and the M2S150 advanced development kit. These kits have decoupling capacitors as per Microsemi-recommended board design guidelines. Table 7 shows the surge currents observed on the M2S090 security evaluation kit and the M2S150 advanced development kit. The surge current values were found to be within acceptable limits. Table 7 • M2S090 and M2S150 Surge Current During DEVRST_N Assertion (With Recommended Decoupling Capacitors on Board) Width of Surge at 50% of Pulse Surge Current M2S090 Security Evaluation Kit 5 µs 150 mA M2S150 Advanced Development Kit 40 µs 1.5 A Kit • The digest check system service performs on-chip NVM data integrity check on SmartFusion2 devices. The use of system services by digest check may cause additional surge current on VDD. For more information on digest check service, see UG0450: SmartFusion2 SoC and IGLOO2 FPGA System Controller User Guide. R ev i si o n 1 0 13 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 8 provides surge current data recorded for VDD when system services were being used by the digest check service. To limit surge current during digest check, follow the Microsemi-recommended board design guidelines. Table 8 • Surge Current on VDD During Digest Check using System Services (No Decoupling Capacitors on Board) Width of Surge at 50% of Pulse (µS) Device Surge Current on VDD 0°C to 85°C -40°C to 100°C -55°C to 125°C Units M2S005/M2GL005 12 0.2 0.2 0.2 A M2S010/M2GL010 12 0.5 0.5 0.5 A M2S025/M2GL025 13 0.6 0.6 0.6 A M2S050/M2GL050 13 0.9 0.9 0.9 A M2S060/M2GL060 13 0.9 0.9 0.9 A M2S090/M2GL090 20 1.0 1.0 1.0 A M2S150/M2GL150 26 1.0 1.0 1.0 A Clocks SmartFusion2 devices have two on-chip RC oscillators and up to two crystal oscillators for generating clocks for the on-chip resources and logic in the FPGA fabric (Table 9). RC Oscillators: • 1-MHz RC oscillator • 50-MHz RC oscillator Crystal Oscillators: • Main crystal oscillator • Auxiliary (RTC) crystal oscillator. Table 9 • Clock Circuit M2S025 M2S050* M2S150 M2GL005 M2GL010 M2GL025 M2GL050* M2GL150 IGLOO2 Part Number M2S010 On-Chip Oscillators SmartFusion2 SoC Part Number M2S005 Resource RC Oscillators 2 2 2 2 2 2 2 2 2 2 Crystal Oscillators 2 2 2 1 2 1 1 1 1 1 Note: *All IGLOO2 devices and the M2S050 SmartFusion2 device only have a main crystal oscillator; they do not have an auxiliary (RTC) crystal oscillator. Main Crystal Oscillator The main crystal oscillator works with an external crystal, ceramic resonator, or a resistor-capacitor network to generate a high-precision clock in the range of 32 kHz to 20 MHz and is connected via the pins XTLOSC_[MAIN/AUX]_EXTAL and XTLOSC_[MAIN/AUX]_XTAL. 14 R ev i sio n 1 0 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 10 lists the output frequency range of the main crystal oscillator with different possible sources. Table 10 • Crystal Oscillator Output Frequency Range Source Output Frequency Range Crystal 32 kHz to 20 MHz Ceramic Resonator 500 kHz to 4 MHz RC Circuit 32 kHz to 4 MHz The main crystal oscillator is operated in medium gain mode when a ceramic resonator is connected between the XTLOSC_[MAIN/AUX]_EXTAL and XTLOSC_[MAIN/AUX]_XTAL pins. When a crystal is used (Figure 5), the load capacitance is determined by the external capacitors C1 and C2, internal capacitance, and stray capacitance (CS). XTLOSC_[MAIN/AUX]_EXTAL Crystal Oscillator SmartFusion2/IGLOO2 XTLOSC_[MAIN/AUX]_XTAL C2 C1 Figure 5 • Crystal Oscillator Typically, designers choose the values of capacitors C1 and C2 to match the crystal’s capacitance CL using the following equation: C 1 C 2C L = --------------------+ Cs C1 + C2 EQ 1 where: CL is the load capacitance provided in manufacturer datasheet. CS is stray capacitance on the PCB; this can be assumed to be in the range of 2 to 5 pF. Usually C1 and C2 are selected such that they are equal. Note: Equation (EQ 1) is only a guideline, and selection of capacitors depends on design requirements such as cost, availability, frequency accuracy, PPM, and type of application. Large values of C1 and C2 increase the frequency stability but decrease the loop gain and may cause oscillator startup problems. The basic rule of thumb is the values of C1 and C2 should be twice as that of CL. Table 11 • Suggested Crystal Oscillator CRYSTAL 32.768 kHz 12.5 pF SMD Citizen R ev i si o n 1 0 CM519-32.768KEZF-UT 15 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs The frequency generated by an RC network is determined by the RC time constant of the selected components (Figure 7). The R and C components are connected to the XTLOSC_[MAIN/AUX]_EXTAL pin, with the XTLOSC_[MAIN/AUX]_XTAL pin connected to the power pin VPP (Figure 6). VPP VPP XTLOSC_[MAIN/AUX]_XTAL R SmartFusion2/IGLOO2 XTLOSC_[MAIN/AUX]_EXTAL C Figure 6 • RC Oscillator Figure 7 • RC Time Constant The operating mode of the main crystal oscillator is configured by the oscillator's macro available in the Libero System-on-Chip (SoC) design software. Auxiliary (RTC) Crystal Oscillator The SmartFusion2 devices, except M2S050, have an auxiliary crystal oscillator dedicated to real-time clocking as an alternative source for the 32 kHz clock. The RTC can take its 32 kHz clock source from the auxiliary crystal oscillator when the main crystal oscillator is being used. Similar to the main crystal oscillator, the auxiliary crystal oscillator can work with an external crystal, ceramic resonator, or an RC circuit to generate a high-precision clock in the range of 32 kHz to 20 MHz. There are two I/O pads for connecting the external frequency source to the auxiliary crystal oscillator: XTLOSC_AUX_EXTAL and XTLOSC_AUX_XTAL. The output frequency range, operating modes, and characteristics for the auxiliary crystal oscillator are the same as those for the main crystal oscillator. Note: Auxiliary (RTC) crystal oscillator is not available in the IGLOO2 device. For detailed information, see UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide. 16 R ev i sio n 1 0 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Reset Circuit SmartFusion2/IGLOO2 devices have a dedicated asynchronous Schmitt-trigger reset input pin (DEVRST_N) with a maximum slew rate not exceeding 1 µs. This active-low signal should be asserted only when the device is unresponsive due to some unforeseen circumstances. It is not recommended to assert this pin during a programming (including eNVM) operation as it may cause severe consequences including corruption of the device configuration. Asserting this signal tristates all user I/O and resets the system. De-asserting DEVRST_N enables the system controller to begin its startup sequence. Figure 8 shows an example of a reset circuit using the Maxim DS1818 reset device, which maintains reset for 150 ms after the 3.3 V supply returns to an in-tolerance condition. If unused, DEVRST_N must be pulled up to VPP through 10 k resistor. Adding a capacitor to ground on DEVRST_N avoids high-frequency noise and unwanted glitches that could reset the device. VPP 10 kΩ DS1818 Reset DEVRST_N 1 μF SmartFusion2/ IGLOO2 Push-Button Switch Figure 8 • Reset Circuit If the user logic needs to be reset, any FPGA I/O can be used as an asynchronous reset for the user logic, as shown in Figure 9. SmartFusion2/IGLOO2 Fabric Fabric Logic CLKINT A Fabric I/O Y Reset Figure 9 • Fabric Logic Reset JTAG The JTAG interface (Table 12) is used for device programming and testing or for debugging Cortex-M3 firmware. These functions are enabled depending on the state of the JTAGSEL input. When the device reset is asserted, JTAG I/O are still enabled but cannot be used as the TAP controller is in reset. JTAG I/O are powered by VDDI in the I/O bank where they reside. JTAG pins should be connected as shown in Figure 10 on page 18. Table 12 • JTAG Pins Pin Names Direction Weak Pull-up Description JTAG_TMS Input Yes JTAG test mode select. JTAG_TRSTB Input Yes JTAG test reset. Must be held low during device operation. R ev i si o n 1 0 17 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 12 • JTAG Pins (continued) Pin Names Direction Weak Pull-up JTAG_TDI Input Yes JTAG test data in. JTAG_TCK Input No JTAG test clock. Microsemi recommends that TCK be tied to VSS or VDDI through a resistor on the board when unused per IEEE 1532 requirements. This prevents totempole current on the input buffer. JTAG_TDO Output No JTAG test data out. Input Connect the JTAGSEL pin to an external pull-up resistor. The default configuration should enable the FPGA fabric TAP. JTAGSEL Description JTAG controller selection. Depending on the state of the JTAGSEL pin, an external JTAG controller connects to either the FPGA fabric TAP (high) or the Cortex-M3 JTAG debug interface (low). For SmartFusion2-based designs, this signal should be held high or low through jumper settings. For IGLOO2-based designs, this signal should be held high through a pull-up resistor. VDDI (JTAG) 1k SmartFusion2/IGLOO2 VDDI (JTAG) VDDI (JTAG) 1 JTAGSEL 2 3 1k JTAG_TCK FP4 Header JTAG_TDO 3 JTAG_TMS 5 6 7 8 9 10 JTAG_TDI JTAG_TRSTB 1 kΩ 1 kΩ Figure 10 • JTAG Programming 18 2 1 R ev i sio n 1 0 4 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Special Pins The SmartFusion2/IGLOO2 devices have dedicated pins for programming the device and probing the fabric I/O (Table 13). The embedded system controller contains a dedicated SPI block for programming which can operate in master or slave mode. In master mode, the SmartFusion2/IGLOO2 device interfaces with external SPI flash, from which programming data is downloaded. In slave mode, the SPI block communicates with a remote device that initiates download of programming data to the device. Table 13 • Special Pins Special Pins Description SC_SPI_SS SPI slave select SC_SPI_SDO SPI data output SC_SPI_SDI SPI data input SC_SPI_CLK SPI clock FLASH_GOLDEN_N* If pulled low, indicates that the device is to be re-programmed from an image contained in the external SPI flash. If pulled high, the SPI is placed into slave mode. Requires an external pull-up resistor value of 10 k to VDDIx. NC No connect. Indicates the pin is not connected to circuitry within the device. NC pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DNC Do not connect. Should not be connected to any signals on the PCB. DNC pins should be left unconnected. PROBE_A The two live probe I/O pins are dual-purpose: PROBE_B • Live probe functionality • User I/O If unused, it must be connected to GND via a 10 kΩ resistor. Note: *This pin may not be available on certain low pin count packages. For more information, see DS0115: SmartFusion2 Pin Descriptions Datasheet and DS0124: IGLOO2 Pin Descriptions Datasheet. Device Programming The SmartFusion2/IGLOO2 device can be programmed via one of two dedicated interfaces: JTAG or SPI. These two interfaces support the following programming modes: • Auto-programming (master) mode • In-system programming: • – JTAG programming mode – SPI Slave programming mode In-application update: – Cortex-M3 update mode (only for SmartFusion2 devices) – Auto update mode For detailed information on hardware connections for each programming mode, see UG0451: IGLOO2 and SmartFusion2 Programming User Guide. SerDes SmartFusion2/IGLOO2 SerDes I/O reside in dedicated I/O banks. The number of SerDes I/O depends on the device size and pin count. For example, the M2S050T/M2GL050T device has two SerDes blocks (SERDES0 and SERDES1), which reside in bank 6 and bank 9 out of 10 I/O banks. The M2S010T/M2GL010T device has a single SerDes block (SERDES0), which resides in I/O bank 5. R ev i si o n 1 0 19 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs PCI Express (PCIe) PCIe is a point-to-point serial differential low-voltage interconnect supporting up to four channels. Each lane consists of two pairs of differential signals: a transmit pair, TXP/TXN, and receive pair, RXP/RXN. Figure 11 illustrates the connectivity between the SmartFusion2/IGLOO2 SerDes interface and the PCIe edge connector. SmartFusion2/ IGLOO2 0.1 μF SerDes Lane0 / TXD Tx SerDes Lane1 / TXD Tx SerDes Lane2 / TXD Tx SerDes Lane3 / TXD Tx 0.1 μF PCIe Edge Connector +12 V Rx +3.3 V 0.1 μF 0.1 μF Rx 0.1 μF 0.1 μF Rx 0.1 μF 0.1 μF Rx SerDes Lane0 / RXD Rx Tx SerDes Lane1 / RXD Rx Tx SerDes Lane2 / RXD Rx Tx SerDes Lane3 / RXD Rx Tx SerDes REFCLK0 Rx Tx Reset # Fabric I/O SerDes REFCLK1 Rx Tx On-board 100 MHz Differential Clock Source Figure 11 • SerDes Schematics AC Coupling Each transmit channel of a PCIe lane must be AC coupled to allow link detection. Capacitors used for AC coupling must be external to the device and large enough to avoid excessive low-frequency drops when the data signal contains a long string of consecutive identical bits. For non-PCIe applications, the SmartFusion2/IGLOO2 device requires the receive inputs to be AC coupled to prevent common-mode mismatches between devices. Suitable values (for example, 0.1 µF) for AC-coupling capacitors must be used to maximize link signal quality and must conform to DS0120: Military Grade IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet electrical specifications. 20 R ev i sio n 1 0 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs SerDes Reference Clock Requirements The selection of the reference clock source or clock oscillator is driven by many parameters such as frequency range, output voltage swing, jitter (deterministic, random, and peak-to-peak), rise and fall times, supply voltage and current, noise specification, duty cycle and duty cycle tolerance, and frequency stability. For SerDes reference clock pins, the internal ODT option should be enabled, and therefore, external termination is not required. Following are the requirements for the SerDes reference clock: • Must be within the range of 100 MHz to 160 MHz. • Must be within the tolerance range of the I/O standard. • The input clock for PCIe is typically a 100 MHz reference clock provided by the host slot for an end point device through the PCIe connector of the motherboard. If two components connected through the PCIe bus use the same 100 MHz clock source, it is called common clock mode. In any other case, the PCIe device is in separated clock mode where one component either does not use a 100 MHz reference clock or uses a 100 MHz reference clock that does not have the same source and phase as the one used by the connected component. See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also see the PCIe Add-in Card Electro-Mechanical (CEM) specifications. PLL Filter To achieve a reasonable level of long-term jitter, it is vital to supply the PLL with analog-grade power. Typically, an RC or RLC filter is used, where C is composed of multiple devices to achieve a wide spectrum of noise absorption. Although the circuit is simple, its effectiveness depends on specific board layout requirements. See Figure 1 on page 3 for an illustration of a typical power supply connection. • The DC series resistance of this filter should be limited. Microsemi recommends limiting the voltage drop across this device to less than 5% under worst-case conditions. • Place a main ceramic or tantalum capacitor (see Figure 1 on page 3), in the filter design to achieve good lowfrequency cut-off. At least one low equivalent series inductance (ESL) and low ESR capacitor in parallel (~0.1 µF ceramic capacitor in 0402 package) enables the filter to maintain its attenuation through moderately high frequencies. • The package ball grid array (BGA) pattern allows the placement of 0402 or 0201 components across the SERDES_x_Lyz_VDDAPLL and SERDES_x_Lyz_REFRET pins on the backside of the board. • For the SerDes block, SERDES_x_Lyz_REFRET serves as the local on-chip ground return path for SERDES_x_Lyz_VDDAPLL. Therefore, the external board ground must not short with SERDES_x_Lyz_REFRET under any circumstances. • High-quality series inductors should not be used without a series resistor when there is a high-gain series resonator. In general, avoid using inductive chokes in any supply path unless care is taken to manage resonance. See Figure 1 on page 3 for SerDes analog power connections. A high-precision 1.21K_1% resistor in either a 0402 or 0201 package is required for the external reference resistor connected between SERDES_x_Lyz_REXT and SERDES_x_Lyz_REFRET. LPDDR, DDR2, and DDR3 DDRIO is a multi-standard I/O buffer optimized for LPDDR, DDR2, and DDR3 performance. The SmartFusion2/IGLOO2 devices include two DDR subsystems: the fabric DDR controllers (FDDR) and microcontroller subsystem (MSS) DDR (MDDR) controllers. All DDRIO can be configured as differential I/O or two single-ended I/O. DDRIO can be connected to the respective DDR sub-system PHYs or can be used as user I/O. • For more information on FDDR and MDDR, see the SmartFusion2 FPGA Fabric DDR Controller Configuration Guide and SmartFusion2 MSS DDR Controller Configuration Guide. R ev i si o n 1 0 21 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 14 lists the differences between LPDDR, DDR2, and DDR3. Table 14 • LPDDR/DDR2/DDR3 Parameters Parameter LPDDR DDR2 DDR3 1.8 V 1.8 V 1.5 V – 0.9 V 0.75 V Asymmetrical tree branch Symmetrical tree branch Daisy chained (fly-by) Single-ended Differential Differential None Static Dynamic Match Addr/CMD/Ctrl to clock tightly Yes Yes Yes Match DQ/DM/DQS tightly Yes Yes Yes Match DQS to clock loosely Yes Yes Not required LVCMOS_18 SSTL_18 SSTL_15 LVCMOS18 - Not required 150_1% 240_1% VDDQ VTT, VREF Clock, address, and command (CAC) layout Data strobe ODT Interface Impedance Calibration One major difference between DDR2 and DDR3 SDRAM is the use of data leveling. To improve signal integrity and support higher frequency operations, a fly-by termination scheme is used with the clocks, command, and address bus signals. Fly-by termination reduces simultaneous switching noise by deliberately causing flight-time skew between the data strobes at every DDR3 chip. Fly-by termination requires controllers to compensate for this skew by adjusting the timing per byte lane. To achieve length matching, short TMATCH_OUT to TMATCH_IN with shortest loop. For more information on DDR memories, refer to the following documents: • JESD209B-JEDEC STANDARD—Low Power Double Data Rate (LPDDR) SDRAM Standard • JESD79-2F-JEDEC STANDARD—DDR2 SDRAM Specification • JESD79-3F-JEDEC STANDARD—DDR3 SDRAM Standard MDDR/FDDR Impedance Calibration The MDDR and FDDR have a DDRIO calibration block. DDRIO can use fixed impedance calibration for different drive strengths, and these values can be programmed using the Libero SoC software for the selected I/O standard. Before initiating DDRIO impedance calibration, either of the following must be done: 22 • Power sequencing where the DDRIO bank VDDIx supply should be up and stable before VDD core supply • DDRIO re-calibration through the APB interface after DDRIO- VDDIx and VDD are up and stable • For more information on impedance calibration, see UG0445: SmartFusion2 SoC and IGLOO2 FPGA Fabric User Guide. R ev i sio n 1 0 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs VREF Power VREF is a low-power reference voltage equal to half of VDDQ. It must also be equal to VTT ± 40 mV. Following are the guidelines for connecting VREF power: • For light loads (less than four DDR components), connect VDDQ to VSSQ through a simple resistor divider composed of two equivalent 1% 1 k resistors (Figure 12). • Generate a local VREF at every device, rather than generating a single VREF with one divider and routing it from the controller to the memory devices. • Decouple at each device or connector to minimize noise. Note: Use discrete resistors, not a resistor pack, to generate VREF. VDDQ 1 kΩ, 1% VREF 1 kΩ, 1% 0.1 μF VSSQ Figure 12 • VREF Generation VTT Power VTT is memory bus termination voltage. To maintain noise margins, VTT must be equal to VDDQ/2, with an accuracy of ± 3%. VTT terminates command and address signals to VDDQ/2 using a parallel resistor (RT) tied to a low impedance source. VTT is not used to terminate any DDR clock pairs. Rather, the xDDR_CLK and xDDR_CLK_N termination consists of a parallel 100-121 resistor between the two lines. • VTT islands require at least two additional decoupling capacitors (4.7 µF) and two bulk capacitors (100 µF) at each end. • Since each data line is connected to VTT with relatively low impedance, this supply must be extremely stable. Any noise on this supply directly affects the data lines. • Sufficient bulk and bypass capacitance must be provided to keep this supply at VDDQ/2. VREF power should not be derived from VTT, but must be derived from VDDQ with a 1% or better resistor divider. R ev i si o n 1 0 23 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs LPDDR and DDR2 Design This document assumes that the designer is familiar with the specification and the basic electrical operation of the LPDDR/DDR2 interface. Data bus, data strobe, and data mask (byte enable) signals are point-to-point, whereas all other address, control, and clock signals are not point-to-point. Figure 13 shows the connectivity of SmartFusion2/IGLOO2 LPDDR interface and Figure 14 on page 25 shows a 32-bit DDR2 interface. SmartFusion2/IGLOO2 xDDR_DQS [1:0] xDDR_DM_RDQS [1:0] xDDR_DQ [15:0] xDDR_BA [2:0] xDDR_ADDR [14:0] x16 LPDDR SDRAM Control lines CKE, CS, WE, RAS, CAS 100Ω xDDR_CLK xDDR_CLK_N x16 LPDDR SDRAM xDDR_DQS [3:2] xDDR_DM_RDQS [3:2] xDDR_DQ [31:16] xDDR_TMATCH_OUT xDDR_TMATCH_IN xDDR_TMATCH_ECC_OUT xDDR_TMATCH_ECC_IN 150_1% xDDR_IMP_CALIB_ECC Figure 13 • LPDDR Interface Note: Impedance calibration is optional for LPDDR operating in LVCMOS mode. 24 R ev i sio n 1 0 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs SmartFusion2/IGLOO2 xDDR_DQS [1:0] xDDR_DQS [1:0]_N xDDR_DM_RDQS [1:0] xDDR_DQ [15:0] DDR 2 SDRAM x16-bit xDDR_CLK 100 xDDR_CLK_N Rt Address lines [13:0] VTT Bank address [2:0] Control lines CKE, CS, WE, RAS, CAS xDDR_DQS [3:2] DDR2 SDRAM x16-bit xDDR_DQS [3:2]_N xDDR_DM_RDQS [3:2] xDDR_DQ [31:16] xDDR_TMATCH_OUT xDDR_TMATCH_IN xDDR_TMATCH_ECC_OUT xDDR_TMATCH_ECC_IN 150_1% xDDR_IMP_CALIB_ECC Figure 14 • DDR2 Interface With short traces, the address, control, and command signals may not require both parallel (RT) and series (RS) termination. In a worst-case scenario, a small series resistor (RS) of about 10 or less is required. This series termination is not used for impedance matching, but for dampening the signals. Note: To get length matching, short the TMATCH_OUT to TMATCH_IN with shortest loop. DDR3 Guidelines Following are the guidelines for connecting to DDR3 memory: • DDR3 data nets have dynamic on-die termination (ODT) built into the controller and SDRAM. The configurations are 40, 60, and 140 . VTT pull-up is not necessary. • Characteristic impedance: Zo is typically 50 and Zdiff (differential) is 100 . R ev i si o n 1 0 25 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs DDR3 interfacing with SmartFusion2/IGLOO2 devices is shown in Figure 15 and Figure 16 for 8-bit and 16-bit interfaces respectively. VTT SmartFusion2/IGLOO2 Clock DDR3 SDRAM Address and Command DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DQ group 0 DQ group1 DQ group 2 DQ group 3 DDR_TMATCH_OUT DDR_TMATCH_IN DDR_TMATCH_ECC_OUT DDR_TMATCH_ECC_IN 240_1% DDR_IMP_CALIB_ECC Figure 15 • 8-Bit DDR3 Interface SmartFusion2/IGLOO2 x16 xDDR_DQS [1:0] xDDR_DQS [1:0]_N xDDR_DM_RDQS [1:0] xDDR_DQ [15:0] DDR3 SDRAM x16 xDDR_BA [2:0] VTT 49.9 Ω 100 Ω VDD xDDR_CLK xDDR_CLK_N 240 Ω ZQ xDDR_DQS [3:2] xDDR_DQS [3:2]_N xDDR_DM_RDQS [3:2] xDDR_DQ [31:16] 240 Ω ZQ xDDR_TMATCH_OUT xDDR_TMATCH_IN xDDR_TMATCH_ECC_OUT xDDR_TMATCH_ECC_IN 240_1% xDDR_IMP_CALIB_ECC Figure 16 • 16-Bit DDR3 Interface 26 49.9 Ω 49.9 Ω xDDR_ADDR [13:0] Control lines CKE, CS, WE, RAS, CAS, ODT DDR3 SDRAM R ev i sio n 1 0 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs User I/O and Clock Pins Table 15 lists recommendations for unused I/O and clock pins in a SmartFusion2/IGLOO2 device. Table 15 • Recommendations for Unused I/O and Clock Pins I/O Unused Condition Remarks MSIO MSIOD Libero-Defined DNC* Internal weak pull-up is available DDRIO Programming SPI pins Crystal oscillator pins Must be left floating and should not connect to ground (VSS) Internal weak nominal 50 k pull-up to VPP Note: *Libero configures unused user I/O (MSIO, MSIOD, DDRIO) as: Input Buffer Disabled, Output Buffer tristated with weak pull-up. Internal Clamp Diode Circuitry All user I/O have an internal clamp diode control circuitry. A pull-up clamp diode must not be present in the I/O circuitry if the hot-swap feature is used. The 3.3 V PCI standard requires a pull-up clamp diode and, therefore, cannot be selected if hot-swap capability is required. VDDI Pull‐Up Clamp diode presents in 3.3V PCI,MSIOD and DDRIOs Buffer Pad Pull‐Down Clamp diode presents in all user IO standards Figure 17 • Internal Clamp Diode Control Circuitry For more information on hot swapping and cold sparing applications, see AC396: SmartFusion2 and IGLOO2 in Hot Swapping and Cold Sparing App Note. Achieving a Two-Rail Design SmartFusion2/IGLOO2 devices require multiple power supplies for functional operation, programming, and high-speed serial interfaces. It is possible to design an application with only two voltage rails using SmartFusion2/IGLOO2 devices. I/O banks in SmartFusion2 and IGLOO2 devices support a wide range of I/O standards. I/O bank supplies can operate at +1.2 V, +1.5 V, +1.8 V, +2.5 V, or +3.3 V. To achieve a two-voltage-rail design, the core voltage should be connected to +1.2 V, and the mandatory I/O bank supplies and VPP supplies can be connected to +2.5 V or +3.3 V. R ev i si o n 1 0 27 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Operating Voltage Rails SmartFusion2/IGLOO2 devices require +1.2 V for the core supply and either +2.5 V or +3.3 V for I/O and analog supplies. Table 16 lists operating voltage requirements for the devices. Table 16 • Operating Voltage Rails Pin Name Description Operating Voltage VDD DC core supply voltage. +1.2 V VDDIx I/O bank supply. SERDES_x_VDD PCIe/PCS supply. +1.2 V SERDES_x_L[01/23]_VDDAIO Tx/Rx analog I/O voltage. Low-voltage power for lanes 0, 1, 2 and 3 of the SerDes interface. +1.2 V VPP* Power supply for charge pump. +2.5 V or +3.3 V VPPNVM* Analog sense-circuit supply for the embedded non-volatile memory (eNVM). +2.5 V or +3.3 V CCC_xyz_PLL_VDDA Analog power pad for CCC PLL. +2.5 V or +3.3 V +1.2 V, +1.5 V, +1.8 V, +2.5 V, or +3.3 V MSS/HPMS_xDDR_PLL_VDDA Analog power pad for xDDR PLL. +2.5 V or +3.3 V SERDES_x_PLL_VDDA +2.5 V or +3.3 V High supply voltage for SerDes PLL. SERDES_x_L[01/23]_VDDAPLL Analog power for SerDes PLL of lanes 0, 1, 2, and 3. +1.2 V or +2.5 V Note: *For M2S090T(S), M2S150T(S) devices, VPP and VPPNVM must be connected to +3.3 V. Configuring Pins in Open Drain To configure fabric pins in open-drain mode, the input port of the tristate buffer must be tied low, and the enable port of the buffer must be driven from the user logic via the fabric port (Figure 18). VDDIx 10 k: SmartFusion2/IGLOO2 IN OUT EN Fabric Port Figure 18 • Configuring Pins in Open Drain 28 R ev i sio n 1 0 I/O Pin Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 17 provides the truth table for configuring pins in open-drain mode. Table 17 • Truth Table Buffer Enable Port Buffer In Port Buffer Out Port 0 (low) 0 (low) 0 (low) 1 (high) 0 (low) VDDIX Brownout Detection (BOD) SmartFusion2/IGLOO2 functionality is guaranteed only if VDD is above the recommended level specified in the datasheet. Brownout occurs when VDD drops below the minimum recommended operating voltage. As a result, it is not possible to ensure proper or predictable device operation. The design might continue to malfunction even after the supply is brought back to the recommended values as parts of the device might have lost functionality during brownout. The VDD supply must be protected by a brownout detection circuit. To recover from VDD brownout, the device must either be power-cycled, or an external brownout detection circuit must be used to reset the device for correct operation. The recommended guideline for the threshold voltage of brownout detection is a minimum of 1 V. The brownout detection circuit should be designed such that if the VDD falls below 1 V, the device should be held in power-down mode via the DEVRST_N pin. Note: Brownout detection must be implemented through a standalone or included as part of power management circuitry. The SmartFusion2/IGLOO2 devices do not have a built-in brownout detection circuitry, but an external brownout detection circuitry can be implemented as shown in Figure 19. Supply VDD Sense +1.2 V Supply Brownout Reset Device 10 kΩ Reset# SmartFusion2/ IGLOO2 DEVRST_n GND Figure 19 • BOD Circuit Implementation The BOD device should have an open-drain output to connect to VPP through 10 k resistor externally. During poweron, the brownout reset keeps the device powered down until the supply voltage reaches the threshold value. Thereafter, the brownout reset device monitors VDD and keeps RESET# output active as long as VDD remains below the threshold voltage. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time is in milliseconds and starts after VDD has risen above the threshold voltage. When the supply voltage drops below the threshold voltage, the output becomes active (low) again. R ev i si o n 1 0 29 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs List of Changes The following table shows the important changes made in this document for each revision. Revision Changes Page Revision 10 Updated "Power Supplies" section (SAR 77745 and SAR 79670). 3 (May 2016) Updated Table 4 (SAR 78887). 10 Updated "Special Pins" section (SAR 75910). 19 Updated "SerDes" section (SAR 78504). 19 Updated "User I/O and Clock Pins" section (SAR 61314). 27 Updated Figure 1 (SAR 72533). 3 Added CCC_PLL_VDDA and MSS_xDDR_PLL_VDDA details under "Power Supplies" on page 3 (SAR 72533). 3 Revision 9 (December 2015) Revision 8 (August 2015) Revision 7 (April 2015) Deleted the RC Values for Filter Circuitry table (SAR 72533). NA Added the M2S060T/M2GL060T device column in Table 5 (SAR 70484). 12 Updated Figure 1 (SAR 66682). 3 Updated the RC Values for Filter Circuitry table (SAR 66682 and SAR 65367). 5 Updated Table 4 (SAR 70545). 10 Updated Table 5 (SAR 67599). 12 Updated Table 13 to replace pin SC_SPI_SS with SC_SPI_SDO. 19 Updated "PLL Filter" section (SAR 60798). 21 Updated Figure 13 (SAR 65438, SAR 69743 and SAR 69580). 24 Updated Figure 14 (SAR 65438). 25 Updated Figure 16 (SAR 65438). 26 Added Figure 17 (SAR 64377). 27 Updated Figure 1 and Figure 4 (SAR 62858). Updated "Power Supply Sequencing and Power-on Reset" section (SAR 64117). 7 Updated "To minimize glitch on fabric I/O during power-down, any one of the following solutions can be used:" section. 8 Added Table 5. 12 Updated Table 4, Table 16, and Table 9 (SAR 62858). 10, 28, 14 Updated "Reset Circuit" section. 17 Updated "AC Coupling" section. 20 Updated Figure 13, Figure 14, Figure 15, and Figure 16 (SAR 65438). 24, 25, 26 Replaced all instances of VQ144 with TQ144 Package. NA Removed all instances of and references to M2S100 and M2GL100 device (SAR 62858). NA Revision 6 Updated "Designing the Board" section (SAR 58055). (September 2014) Updated "Power Supplies" section and Figure 1 (SAR 52580). 30 3 and 9 R ev i sio n 1 0 2 3 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Revision Revision 5 (March 2014) Changes Page Updated "Power Supply Sequencing and Power-on Reset" section (SAR 59593 and SAR 57004). 7 Updated Figure 4 (SAR 52580). 9 Added M2S090T/M2GL090T-FCS325 information for power supplies in Table 4 (SAR 58241). 10 Updated Figure 2 (SAR 56291). 5 Added a foot note to Table 13 (SAR 59563). 19 Updated "SerDes Reference Clock Requirements" section (SAR 60213). 21 Updated Table 14 (SAR 58085). N/A Updated "Brownout Detection (BOD)" section and Figure 19 (SAR 56598). 29 Updates made to maintain the style and consistency of the document. N/A Updated "Power Supply Sequencing and Power-on Reset" section, Figure 1, Figure 4, and Table 4 (SAR 52580). Updated main crystal oscillator pins naming convention (SAR 53177). Updated Figure 1 (SAR 54177). 7, 3, 9, 10 NA 3 Updated Figure 1, Figure 4, and Table 16 (SAR 55659). Updated Figure 1, and Figure 4 (SAR 55705). Updated Figure 13, Figure 14, Figure 15, and Figure 16 (SAR 53161). 3, 9, 28 3, 9 24, 25, 26 Updated Table 13 (SAR 53348). 19 Corrected the Ramp Rate description to 50 us in the "Power Supply Sequencing and Power-on Reset" section (SAR 50245) (SAR 50844). 7 Updated Figure 10. (SAR 50725) 18 Added Section “Configuring Pins in Open Drain". 19 Revision 3 (June 2013) Updated the content for IGLOO2 devices (SAR 48630). N/A Revision 2 (May 2013) Modified the "SmartFusion2 Unused Pin Configurations" section (SAR 47904). 5 Updated Table 15 (SAR 47548). 27 Updated the "Brownout Detection (BOD)" section (SAR 47904). 29 Added Figure 19 (SAR 47904). 29 Added "Power Supply Sequencing and Power-on Reset" section (SAR 47223). 7 Revision 4 (November 2013) Revision 1 (April 2013) Updated Figure 4 (previously Figure 2) and added Figure 4 (SAR 47223). Updated Table 4 and Table 15, and added Table 16 (SAR 47223). Revision 0 (March 2013) Initial Release. 9, N/A 10, 27, and 28 N/A R ev i si o n 1 0 31 Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: [email protected] www.microsemi.com Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at www.microsemi.com. © 2015–2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 51900261-10/05.16