AC439: Board Design Guidelines for RTG4 FPGA Application Note

Application Note AC439
Board Design Guidelines for RTG4 FPGAs
Table of Contents
Purpose . . . . . . .
Introduction . . . . .
References . . . . .
Designing the Board
Power Supplies . . .
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2
2
2
2
3
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Sequencing and PoR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
7
8
9
Clocks . . . . . . . . .
Reset Circuit . . . . .
JTAG . . . . . . . . .
System Controller SPI
Device Programming .
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10
10
11
12
12
JTAG Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI Slave Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O State During Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fabric I/O Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PCI Express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SerDes Reference Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connections in Unused Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
16
16
16
17
LPDDR, DDR2, and DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FDDR Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VREF Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VTT Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LPDDR and DDR2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR3 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DQ Line Interchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SpaceWire Interface . . . . .
Temperature Sensing . . . . .
Additional Pins . . . . . . . .
Configuring Pins in Open Drain
Cold Sparing . . . . . . . . .
Brownout Detection (BOD) . .
List of Changes . . . . . . . .
June 2016
© 2016 Microsemi Corporation
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17
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25
27
1
Board Design Guidelines for RTG4 FPGAs
Purpose
This application note provides board-level design guidelines for RTG4™ FPGAs. This document acts as
a companion to AC453: Layout Guidelines for RTG4-Based Board Design Application Note, which
covers the details of PCB design.
Introduction
Good board design practices are required to achieve expected performance from the PCB and RTG4
devices. High quality and reliable results depend on minimizing noise levels, preserving signal integrity,
meeting impedance and power requirements, and using appropriate transceiver protocols. These
guidelines should be treated as a supplement to the standard board-level design practices.
This document assumes that the reader has a good understanding of the RTG4 device, and is
experienced in digital and analog board design and knowledgeable in the electrical characteristics of
systems. Background information on the key theories and concepts of board-level design is available in
High Speed Digital Design: A Handbook of Black Magic1 and other industry literature.
References
The following documents are the referenced in this application note:
•
AC453: Layout Guidelines for RTG4-Based Board Design Application Note
•
DS0130: RTG4 FPGA Pin Descriptions
•
DS0131: RTG4 FPGA Datasheet
•
CG1657 Package Pin Assignment Table
•
UG0574: RTG4 FPGA Fabric User Guide
•
UG0586: RTG4 FPGA Clocking Resources User Guide
•
AC387: Designing Radiation-Tolerant Power-Supplies for the RTAX-S/SL/DSP FPGA App Note
•
UG0602: RTG4 FPGA Programming User Guide
Designing the Board
RTG4 is a radiation-tolerant flash-based FPGA that supports high-speed interfaces such as double-data
rate (DDR), serializer/deserializer (SerDes), and SpaceWire using high-speed fabric I/O such as MSIO,
MSIOD, and DDRIO.
DDRIO is a multi-standard I/O optimized for low-power DDR, DDR2, and DDR3 performance. SerDes I/O
are dedicated to high-speed serial communication protocols such as PCI Express (PCIe) 2.0,
10-gbps attachment unit interface (XAUI), extended physical code sublayer (EPCS), multiprotocols
(PCIe and EPCS), serial-gigabit media independent interface (SGMII), and JESD204B, as well as userdefined high-speed serial protocol implementation in fabric.
Routing high-speed serial data over a PCB is a challenge as losses, dispersion, and crosstalk effects
increase with speed. Channel losses and crosstalk decrease the signal-to-noise ratio and limit the data
rate on the channel.
Subsequent sections discuss the following:
1.
2
•
Power Supplies
•
Cold Sparing
•
Clocks
•
Reset Circuit
•
JTAG
•
System Controller SPI
Johnson, Howard, and Martin Graham, High Speed Digital Design: A Handbook of Black Magic. Prentice Hall PTR, 1993.
ISBN-10 0133957241 or ISBN-13: 978-0133957242
Power Supplies
•
Temperature Sensing
•
Device Programming
•
Fabric I/O Configurations
•
SerDes
•
LPDDR, DDR2, and DDR3
•
SpaceWire Interface
•
Additional Pins
•
Configuring Pins in Open Drain
•
Cold Sparing
Note: Microsemi RTG4 development board is intended for hardware functional verification only. It must
not be used for space flight applications. It must also not be used for applications or activities that
require components of the same quality as space flights. (For example, it should not be used for
qualification of space flight hardware.)
Power Supplies
Figure 1 illustrates typical power supply requirements, including PLL RC values, for RTG4 devices. For
information on decoupling capacitors associated with individual power supplies, seeTable 1 on page 5.
9
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Figure 1 • Power Supplies
3
Board Design Guidelines for RTG4 FPGAs
Notes:
•
RC values vary depending on the board layout and the application.
•
VDD, VPP, and all I/O bank supplies must be powered even in unused condition for the device to
exit from power-on-reset (PoR).
For the device to operate successfully, power supplies must be free from unregulated spikes and the
associated grounds must be free from noise. All overshoots and undershoots must be within the absolute
maximum ratings provided in the DS0131: RTG4 FPGA Datasheet.
For detailed description of various power supplies in an RTG4 device, see DS0130: RTG4 FPGA Pin
Descriptions.
Power Supply Decoupling
To reduce any potential fluctuation on the power supply lines, decoupling capacitors, bypass capacitors,
and other power supply filtering techniques must be used.
To save board space, fewer, larger-value bulk capacitors can be used instead of a large number of
smaller capacitors. However, care must be taken to ensure that the electrical characteristics of the
consolidated capacitors (ESR and ESL) match those of the parallel combination of the recommended
capacitors.
The capacitors selected must be suitable for the end application. For example, if the RTG4 FPGA is to be
used in a military application, the capacitors used must be certified for military-grade applications.
Similarly, high-reliability, space-grade capacitors must be used for space applications.
The following additional guidelines should be followed when selecting capacitors:
•
For values ranging from 1 nF to 100 µF, use X7R or X5R (dielectric material) type capacitors.
•
For values ranging from 100 µF to 1000 µF, use tantalum capacitors.
Figure 2 shows an impedance-versus-frequency graph for effective combinations of three values of
capacitors. From the graph, it is evident that impedance is lower for a wider frequency band when
capacitors of different values are in parallel.
Figure 2 • Impedance of Three Capacitors in Parallel
4
Board Design Guidelines for RTG4 FPGAs
Table 1 lists the recommended number of PCB decoupling capacitors for an RT4G150-CG1657 device.
Table 1 • Power Supply Decoupling Capacitors
Pin Name
VDD
5
Internal
Package
Capacitance for
CG1657
Number
of Pins
External on Board Capacitors
0.01
µF
0.1 µF 10 µF 4.7 µF 22 µF 33 µF 47 µF 100 µF 330 µF
Ceramic Caps
Tantalum Caps
0.18uF/6.3V (2)
82
41
41
11
–
2
–
1
1
1
VDDI0
0.18uF/6.3V
20
10
10
1
–
–
–
–
–
–
VDDI1
0.18uF/6.3V
16
8
8
3
–
–
–
–
–
–
VDDI2
0.18uF/6.3V
16
8
8
1
–
–
–
–
–
–
VDDI3
-
1
1
1
1
–
–
–
–
–
–
VDDI4
0.18uF/6.3V
15
7
7
1
–
–
–
–
–
–
VDDI5
0.18uF/6.3V
16
8
8
1
–
–
–
–
–
–
VDDI6
0.18uF/6.3V
15
8
8
1
–
–
–
–
–
–
VDDI7
0.18uF/6.3V
16
8
8
1
–
–
–
–
–
–
VDDI8
0.18uF/6.3V
16
8
8
1
–
–
–
–
–
–
VDDI9
0.18uF/6.3V
20
10
10
1
–
–
–
–
–
–
VDDPLL
0.18uF/6.3V
13
13
13
1
–
1
–
–
–
–
VPP
–
9
9
9
1
–
–
–
–
–
–
VREF0
–
2
2
2
–
–
–
–
–
–
–
VREF9
–
2
2
2
–
–
–
–
–
–
–
SERDES_VDDI
–
4
2
2
1
–
–
–
–
–
–
SERDES_VREF
–
2
–
2
–
–
–
–
–
–
–
SERDES_PCIE_0_L01_VDDAIO
–
6
–
6
–
–
–
–
–
–
–
SERDES_PCIE_0_L23_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_1_L01_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_1_L23_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_2_L01_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
Power Supplies
Table 1 • Power Supply Decoupling Capacitors (continued)
SERDES_2_L23_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_3_L01_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_3_L23_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_4_L01_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_4_L23_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_PCIE_5_L01_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_PCIE_5_L23_VDDAIO
–
6
–
6
1
–
–
–
–
–
–
SERDES_PCIE_0_L01_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_PCIE_0_L23_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_1_L01_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_1_L23_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_2_L01_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_2_L23_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_3_L01_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_3_L23_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_4_L01_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_4_L23_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_PCIE_5_L01_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
SERDES_PCIE_5_L23_VDDAPLL
–
1
–
1
–
–
–
1
–
–
–
Notes:
•
Internal precious-metal-electrode (PME) and base-metal-electrode (BME) decoupling capacitors within the package enhance overall PCB decoupling for
production silicon and ES silicon respectively.
•
ES silicon uses BME caps; however, PROTO and Flight silicon use PME caps because of its proven reliability and performance, which help with QML
qualification of RTG4.
•
The RTG4 Evaluation Kit contains commercial grade capacitors for decoupling.
Decoupling capacitors other than those listed in Table 1 on page 5 can be used if sized to meet or exceed the performance of the network given in this example.
However, substitution requires analysis of the resulting power distribution system’s impedance versus frequency to ensure that no resonant impedance spikes
result. See Figure 1 on page 3 for a typical power supply schematics design. For placement and layout details, see AC453: Layout Guidelines for RTG4-Based
Board Design App Note.
6
Power Supplies
Power Supply Sequencing and PoR
Sophisticated power-up management circuitry is designed into each RTG4 device. The embedded
system controller is responsible for systematic power-on reset whenever the device is powered on or
reset. All the I/O are held in a high-impedance state by the system controller until all power supplies are
at their required levels and the system controller has completed the reset sequence.
As specified in DS0131: RTG4 FPGA Datasheet, no specific power-up and power-down sequence is
required if the device is held in reset by asserting DEVRST_N until the VPP and VDDPLL supplies reach
their minimum recommended level. If, however, the device cannot be held in reset, the following power
supply sequencing requirements apply.
VPP Requirements
•
VPP must not be the last supply to ramp up and must reach its minimum recommended level
before the last supply (VDD or VDDIx) starts ramping up.
and
•
VPP must have a minimum ramp time of 5 ms to reach from 10% of the VPP to the minimum
recommended level of VPP.
VDDPLL Requirements
•
VDDPLL must not be the last supply to ramp up and must reach its minimum recommended level
before the last supply (VDD or VDDIx) starts ramping up.
•
All PLLs are held in reset until the VDDPLL supply reaches its minimum recommended level.
or
If none of the above conditions is met, VDDPLL must start ramping up and reach its minimum
recommended level before VDD, VPP, and VDDIx start ramping up. In other words, VDDPLL must not be
the last supply to ramp-up, and it must reach its minimum recommended level before the last supply
starts ramping up.
The SERDES_x_Lyz_VDDAIO supply must be powered up at the same time as VDD to prevent high
current from flowing between the two supplies. The VDDIx supply must be driven down first, all the way
to 0 V, to avoid I/O glitch at output buffers that are driven low.
A PoR delay of 60 ms is typical for generating any design. (PoR delay represents the maximum ramp
time allowed for VDD and VPP.)
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Figure 3 • Power Supply Sequencing
7
Board Design Guidelines for RTG4 FPGAs
Power Supply Flow
RTG4 devices require multiple power supplies (Table 2). All the supplies can be generated through LDOs
or DC-DC converters. See DS0131: RTG4 FPGA Datasheet for more information about operating ranges
(minimum and maximum values) for various power supplies.
Table 2 • Power Supplies in RTG4 Devices
Power Supply Name
Voltage
Description
VDD
1.2 V
DC core supply voltage
VPP
3.3 V
Power supply for charge pumps
VDDPLL
3.3 V
Power for eight PLLs, PLLs in SerDes PCIe/EPCS blocks,
and FDDR PLLs
VDDIx
1.2, 1.5, 1.8, 2.5, or 3.3 V I/O bank supplies
VREFx
0.5 × VDDIx
Reference voltage for DDR signals, powered through the
corresponding bank supply (VDDIx).
SERDES_x_Lyz_VDDAIO
1.2 V
TX/RX analog I/O voltage for SerDes lanes. Should be
shorted to the device’s core supply.
SERDES_x_Lyz_VDDAPLL 2.5 V
Analog power for SerDes TXPLL and CDRPLL
SERDES_VDDI
1.8, 2.5, or 3.3 V
Power for SerDes reference clock receiver supply
SERDES_VREF
0.5 × SERDES_VDDI
Supply for the SerDes reference clocks on the board use a
single ended reference standard. Not used with differential
clock signals.
Figure 4 illustrates one topology for generating the required power supplies from a single 12 V source.
+12 V
PTH08T240WAZ
Core VDD
SERDES_x_Lyz_VDDAIO
1.2 V/10 A
3.3 V/10 A
PTH08T240WAZ
Bank voltages
MIC69502WR
DDRIO Banks
Bank 0 and Bank 9
1.5 V/ 5 A
DDR -VTT
TPS51200
VTT supply for FDDR
MIC69502WR
LDO for SERDES
PLLs & Bank voltages
2.5 V/ 5 A
LX13043CLD
LDO for PLL and VPP
supplies
3.3 V/ 1 A
5 V/6 A
PTH08T231WAZ
Figure 4 • Example Power Supply Topology
8
Power Supplies
Radiation Tolerant Power Supplies
Microsemi provides several radiation-tolerant components that can be used with RTG4 PCB designs.
When selecting the power supply components, consider the following:
•
Calculate required power of the RTG4 device using the power calculator spreadsheet and the
SmartPower tool in the Libero® SoC software
•
Select the appropriate Microsemi radiation-tolerant LDO/switching regulators (DC-DC) that can
supply the required power and meet the power requirements of the FPGA.
See AC387: Designing Radiation-Tolerant Power-Supplies for the RTAX-S/SL/DSP FPGA Application
Note for information on recommended DC-DC converters.
Unused Pin Configurations
In cases where certain interfaces are not used, the associated pins need to be configured properly. For
example, if a PLL is not used or is bypassed, and only the divider circuitry is used, then the PLL’s pins
can be powered without RC filter circuitry.
For RTG4 devices with multiple SerDes blocks, designers should tie off SerDes blocks, as shown in
Figure 5 on page 10.
For I/O banks configured for use as user I/O (DDR functionality is not used), VREF0 and VREF9 can be
left floating (DNC) even though the VDDI0 and VDDI9 are still powered
For RTG4 devices, all of the bank supplies (VDDIx) must always be powered, even if the associated
bank I/O are unused.
Unused I/O banks must be powered-on for device initialization.They can be powered off after the device
is initialized. For unused banks, bulk capacitors must be placed on the associated VDDI rail; the use of
high-frequency capacitors can be reduced or even completely avoided, as long as no I/O activity is
planned.
9
Board Design Guidelines for RTG4 FPGAs
For details on bank locations for RTG4 devices, see DS0130: RTG4 FPGA Pin Descriptions Datasheet.
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Note: *Libero SoC configures unused user I/O (MSIO, MSIOD, DDRIO) and SPI pins as input bufferdisabled and output buffer-tristated with weak pull-up.
Clocks
RTG4 devices have one on-chip RC oscillator operating at 50 MHz. For detailed information on clocking
in RTG4 devices, see UG0586: RTG4 FPGA Clocking Resources User Guide.
Reset Circuit
RTG4 devices have a dedicated asynchronous Schmitt-trigger reset input pin (DEVRST_N) with a
maximum slew rate not exceeding 1 µs. This active-low signal should be asserted only when the device
is unresponsive due to some unforeseen circumstances. It is not recommended to assert this pin during
programming operation as this may cause severe consequences, including corruption of the device
configuration. Asserting the DEVRST_N signal tristates all user I/O and resets the system. De-asserting
this signal enables the system controller to begin its startup sequence.
10
JTAG
If unused, DEVRST_N must be pulled up to VPP through a 10 kΩ resistor. Adding a capacitor to ground
on DEVRST_N prevents high-frequency noise and unwanted glitches that could reset the device.
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Figure 6 • Reset Circuit
For additional information on device reset, see DS0131: RTG4 FPGA Datasheet. For information on
GRESET, see UG0574: RTG4 FPGA Fabric User Guide.
JTAG
The JTAG interface (Table 3) is used for device programming and testing or for debugging Cortex-M3
firmware. JTAG I/O are powered by the VDDI3 supply associated with the bank where the I/O reside.
Table 3 • JTAG Pins
Pin Names
Direction
Weak Pull-up
Description
JTAG_TMS
Input
Yes
JTAG test mode select.
JTAG_TRSTB
Input
Yes
JTAG test reset. Must be held low during device operation.
JTAG_TDI
Input
Yes
JTAG test data in.
JTAG_TCK
Input
No
JTAG test clock. Microsemi recommends that when unused,
TCK be tied to VSS (GND) or VDDI3 through a resistor on the
board, per IEEE 1532 requirements. This prevents totem-pole
current on the input buffer.
JTAG_TDO
Output
No
JTAG test data out.
The JTAG_TRSTB pin must be held low and SC_SPI_SS pin held high for device operation in flight
mode (if system controller SPI is used).
11
Board Design Guidelines for RTG4 FPGAs
System Controller SPI
The SPI interface (Table 4) is used for device programming. Figure 8 on page 13 shows the interface
between R TG4 and programming external SPI flash. System controller contains a dedicated SPI block
for programming. SPI can operate in slave mode, during which the SPI block communicates with a
remote device that initiates download of the programming data to the RTG4 device.
Table 4 • SPI Pins
Pin Name
Description
SC_SPI_SS
SPI slave select
SC_SPI_SDO
SPI data output
SC_SPI_SDI
SPI data input
SC_SPI_SCK
SPI clock
Device Programming
The RTG4 device can be programmed via one of two dedicated interfaces: JTAG or SPI.
JTAG Programming Mode
The RTG4 device supports programming through a dedicated JTAG port (Figure 7) using the Libero SoC
software or a standalone FlashPro software (FlashPro4 or FlashPro5). The power supplies and the
toggling of the JTAG signals must meet the specifications provided in DS0131: RTG4 FPGA Datasheet.
Proper signal integrity measures must be used to ensure that the power supplies and JTAG signals are
free from noise. While programming in JTAG mode, all I/O (MSIO, MSIOD, and DDRIO) are controlled by
boundary scan registers. JTAG pins should be connected as shown in Figure 7.
VDDI (JTAG)
VDDI (JTAG)
JTAG_TCK
JTAG_TDO
JTAG_TMS
RTG4
JTAG_TDI
JTAG_TRSTB
1 kΩ
Figure 7 • JTAG Programming
12
1 kΩ
1
2
3
4
5
FlashPro
Header
6
7
8
9
10
Device Programming
SPI Slave Programming Mode
In SPI slave programming mode, the device is programmed by an external SPI master, which can either
be an external microprocessor or an external FPGA. The SPI master interfaces with the system
controller through a dedicated SPI port.
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Figure 8 • SPI Slave Programming Configuration
For detailed information on hardware connections for each programming mode, see UG0602: RTG4
FPGA Programming User Guide.
I/O State During Programming
If the RTG4 device is already programmed, the I/O must either be held in the previous state or disabled
during programming. This applies to all I/O except the JTAG pins and the dedicated SPI pins.
Recommended Operating Conditions during Programming
The following operating conditions are recommended for programming:
•
VDD: 1.2 V
•
VPP: 3.3 V
•
Tj: 0 °C to 85 °C
Note: Programming should be done on earth. It is currently not recommended to reprogram the device
during space flight.
13
Board Design Guidelines for RTG4 FPGAs
Fabric I/O Configurations
Table 5 lists the supported voltage standards for various I/O types.
Table 5 • Supported I/O Standards
Single-ended
Differential
MSIO
(Max 3.3 V)
MSIOD
(Max 2.5 V)
DDRIO
(Max 2.5 V)
LVTTL
Yes
–
Yes
–
–
PCI
Yes
–
Yes
–
–
LVPECL (input only)
–
Yes
Yes
–
–
LVDS33
–
Yes
Yes
–
–
LVCMOS33
Yes
–
Yes
–
–
LVCMOS25
Yes
–
Yes
Yes
Yes
LVCMOS18
Yes
–
Yes
Yes
Yes
LVCMOS15
Yes
–
Yes
Yes
Yes
LVCMOS12
Yes
–
Yes
Yes
Yes
SSTL2I
Yes
Yes
Yes
Yes
Yes (DDR1)
SSTL2II
Yes
Yes
Yes
–
Yes (DDR1)
SSTL18I
Yes
Yes
–
–
Yes (DDR2)
SSTL18II
Yes
Yes
–
–
Yes (DDR2)
SSTL15I (only for I/O
used by DDR)
Yes
Yes
–
–
Yes (DDR3)
SSTL15II (only for I/O
used by DDR)
Yes
Yes
–
–
Yes (DDR3)
HSTLI
Yes
Yes
–
–
Yes
HSTLII
Yes
Yes
–
–
Yes
LVDS
–
Yes
Yes
Yes
–
RSDS
–
Yes
Yes
Yes
–
Mini LVDS
–
Yes
Yes
Yes
–
BUSLVDS
–
Yes
Yes
Yes (input only)
–
MLVDS
–
Yes
Yes
Yes (input only)
–
SUBLVDS (output only)
–
Yes
Yes
Yes
–
I/O Standard
Notes:
14
•
If the P pad in the I/O pair is configured as an HSTL or SSTL input, output, or bidirectional pin, it
must be terminated. The associated N pad, if used, must be also be configured as an HSTL or
SSTL input, output, or bidirectional pin, and terminated. If unused, the N pad must be tristated
with a weak pull-up, and must not be driven low. If the N pad is configured to a non-terminated
standard (such as such as LVCMOS, LVTTL, or PCI), the pin is toggled to 0 V, leading to leakage
current flowing from the N pad to the VREF.
•
MSIO pins are capable of low-speed LVDS operation and MSIOD pins capable of high-speed
LVDS operation. For more information about maximum LVDS data rates, see DS0131: RTG4
FPGA Datasheet.
•
For I/O pin naming and assignments to specific banks, see DS0130: RTG4 FPGA Pin Descriptions
Datasheet.
SerDes
Table 6 lists the hardening features supported for each I/O type.
Table 6 • Supported Hardening Features
Support Per I/O Type
Feature
MSIO
MSIOD
DDRIO
SET hard clock receiver
Yes
Yes
–
SET hard boundary scan controls lockout
Yes
Yes
Yes
SET hard global controls lockout
Yes
Yes
Yes
SerDes
RT4G150-CG1657 device has six SerDes blocks (SERDES_PCIE_0, SERDES_1, SERDES_2,
SERDES_3, SERDES_4, and SERDES_PCIE_5), each residing in a dedicated bank with the same
name as the block that it contains.
PCI Express (PCIe)
PCIe is a point-to-point serial differential low-voltage interconnect supporting up to four channels. Each
lane consists of two pairs of differential signals: a transmit pair, TXDy_P/N, and a receive pair,
RXDy_P/N. Each signal has a 2.5 GHz embedded clock. Figure 9 illustrates the connectivity between the
RTG4 SerDes interface and PCIe edge connector.
RTG4
0.1 μF
SerDes Lane0 / TXD
Tx
0.1 μF
PCIe Edge
Connector
+12 V
Rx
+3.3 V
0.1 μF
SerDes Lane1 / TXD
Tx
SerDes Lane2 / TXD
Tx
SerDes Lane3 / TXD
Tx
0.1 μF
Rx
0.1 μF
0.1 μF
Rx
0.1 μF
0.1 μF
Rx
SerDes Lane0 / RXD
Rx
Tx
SerDes Lane1 / RXD
Rx
Tx
SerDes Lane2 / RXD
Rx
Tx
SerDes Lane3 / RXD
Rx
Tx
SerDes REFCLK0
Rx
Fabric I/O
Fabric I/O
Tx
Reset #
ȍ2SWLRQDO
Wake#
Tx
SerDes REFCLK1
Rx
On-board
100 MHz
Tx Differential
Clock
Source
Figure 9 • SerDes Schematics
15
Board Design Guidelines for RTG4 FPGAs
AC Coupling
Each transmit channel of a PCIe lane must be AC coupled to allow detection. Capacitors used for AC
coupling must be external to the device and large enough to avoid excessive low-frequency drops when
the data signal contains a long string of consecutive identical bits.
For non-PCIe applications, the RTG4 device requires the receive inputs to be AC coupled to prevent
common-mode mismatches between devices. Suitable values (for example, 0.1 µF) for AC-coupling
capacitors must be used to maximize link signal quality and must conform to the electrical specifications
available in DS0131: RTG4 FPGA Datasheet.
SerDes Reference Clock Requirements
The selection of the reference clock source or clock oscillator is driven by many parameters such as
frequency range, output voltage swing, jitter (deterministic, random, and peak-to-peak), rise and fall
times, supply voltage and current, noise specification, duty cycle and duty cycle tolerance, and frequency
stability.
For SerDes reference clock pins, the internal on-die termination (ODT) option should be enabled, and
therefore, external termination is not required.
The following are the requirements for the SerDes reference clock:
•
Must be within the range of 100 MHz to 160 MHz.
•
Must be within the tolerance range of the I/O standard.
•
The input clock for PCIe is typically a 100-MHz reference clock provided by the host slot for an
endpoint device through the PCIe connector of the motherboard. If two components connected
through the PCIe bus use the same 100-MHz clock source, it is called common clock mode. In
any other case, the PCIe device is in separated clock mode, where one component does not use
a 100-MHz reference clock or uses a 100-MHz reference clock that does not have the same
source and phase as the one used by the connected component.
See the PCI Express Base specification Rev 2.1 for detailed PHY specifications. Also see the PCIe
Add-in Card Electro-Mechanical (CEM) specifications.
PLL Filter
To achieve a reasonable level of long-term jitter, it is vital to supply the PLL with analog-grade power.
Typically, an RC or RLC filter is used, where C is composed of multiple devices to achieve a wide
spectrum of noise absorption. Although the circuit is simple, its effectiveness depends on the specific
board layout requirements. See Figure 1 on page 3 for an illustration of a typical power supply
connection.
•
The DC series resistance of this filter should be limited. Microsemi recommends limiting the
voltage drop across this device to less than 5% under worst-case conditions.
•
Place a main ceramic or tantalum capacitor (see Figure 1 on page 3) in the filter design to achieve
a good low-frequency cut-off. At least one low ESL and low ESR capacitor in parallel to enable
the filter to maintain its attenuation through moderately high frequencies.
•
For the SerDes block, SERDES_x_Lyz_REFRET serves as the local on-chip ground return path
for SERDES_x_Lyz_VDDAPLL. Therefore, the external board ground must not be short with
SERDES_x_Lyz_REFRET under any circumstances.
•
High-quality series inductors must not be used without a series resistor when there is a high-gain
series resonator. In general, avoid using inductive chokes in any supply path unless care is taken
to manage resonance.
See Figure 1 on page 3 for SerDes analog power connections. A high-precision 1.21K_1% resistor is
required for the external reference resistor connected between SERDES_x_Lyz_REXT and
SERDES_x_Lyz_REFRET.
16
LPDDR, DDR2, and DDR3
Connections in Unused Condition
When unused, SerDes pins must be connected as follows:
•
Receive pins must be connected to VSS through a 10 kΩ resistor. If board space is a constraint,
designer can combine up to eight RXD pads to share an external 10 kΩ pull-down resistor. To
avoid reliability issues, RXD pins must not be shorted to VSS directly.
•
Transmit pins must be left floating.
•
Reference clock pins must be connected to SERDES_VDDI through a 10 kΩ resistor.
LPDDR, DDR2, and DDR3
DDRIO is a multi-standard I/O buffer optimized for LPDDR, DDR2, and DDR3 performance. All DDRIO
can be configured as differential I/O or two single-ended I/O. DDRIO can be connected to the respective
DDR subsystem PHY or used as user I/O.
Table 7 lists the differences between LPDDR, DDR2, and DDR3 interfaces.
Table 7 • LPDDR/DDR2/DDR3 Parameters
Parameter
LPDDR
DDR2
DDR3
VDDQ
1.8 V
1.8 V
1.5 V
VTT, VREF
–
0.9 V
0.75 V
Clock, address, and command Asymmetrical tree branch
(CAC) layout
Symmetrical tree branch
Daisy chained (fly-by)
Data strobe
Single-ended
Differential
Differential
ODT
None
Static
Dynamic
Match Addr/CMD/Ctrl to clock Yes
tightly
Yes
Yes
Match DQ/DM/DQS tightly
Yes
Yes
Yes
Match DQS to clock loosely
Yes
Yes
Not required
Interface
LVCMOS_18
SSTL_18
SSTL_15
Impedance calibration
Optional
150_1%
240_1%
Note: Using an impedance calibration resistor is a must for DDR2 and DDR3 memory interfaces, though
optional for LPDDR memory. If an impedance calibration resistor is not set for DDR2 and DDR3
interfaces, the RTG4 device will not initialize.
A major difference between DDR2 and DDR3 SDRAM is the use of data leveling. To improve signal
integrity and support higher frequency operations, a fly-by termination scheme is used with the clock,
command, and address bus signals. Fly-by termination reduces simultaneous switching noise by
deliberately causing flight-time skew between the data strobes at every DDR3 chip. This requires
controllers to compensate for this skew by adjusting the timing per byte lane.
For more information on DDR memories, refer to the following documents:
•
JESD209B-JEDEC Standard—Low Power Double Data Rate (LPDDR) SDRAM Standard
•
JESD79-2F-JEDEC Standard—DDR2 SDRAM Specification
•
JESD79-3F-JEDEC Standard—DDR3 SDRAM Standard
FDDR Impedance Calibration
The FDDR has a DDRIO calibration block. DDRIO can use fixed impedance calibration for different drive
strengths, and these values can be programmed using the Libero SoC software for the selected I/O
standard. If DDR interface is not used, impedance calibration pin can be left floating or pulled to VSS via
a 1 kΩ resistor.
17
Board Design Guidelines for RTG4 FPGAs
Before initiating DDRIO impedance calibration, either of the following must be done:
•
Power sequencing where the DDRIO bank VDDIx supply should be up and stable before VDD
core supply
•
DDRIO re-calibration through the APB interface after VDDIx (DDRIO banks) and VDD are up and
stable
For more information on impedance calibration, see UG0574: RTG4 FPGA Fabric User Guide. For
information on restrictions applicable to FDDR use models, see the CG1657 Package Pin Assignment
Table.
VREF Power
Voltage reference (VREF) is a low-power reference voltage equal to half of VDDQ. It must also be equal
to VTT ± 40 mV.
The following are the guidelines for connecting VREF power:
•
For light loads (less than four DDR components), connect VDDQ to VSSQ through a simple
resistor divider composed of two equivalent 1% 1 kΩ resistors (Figure 10).
•
Generate a local VREF at every device, rather than generating a single VREF with one divider
and routing it from the controller to the memory devices.
•
Decouple at each device or connector to minimize noise.
•
If more than four DDR devices are used in a design, use a separate voltage regulator to generate
the reference voltage for DDR memory.
Note: Use discrete resistors, not a resistor pack, to generate VREF.
VDDIx
1 kΩ, 1%
VREF
1 kΩ, 1%
0.1 μF
Figure 10 • VREF Generation
VTT Power
VTT is memory bus termination voltage. To maintain noise margins, VTT must be equal to VDDQ/2, with
an accuracy of ± 3%. VTT terminates command and address signals to VDDQ/2 using a parallel resistor
(RT) tied to a low-impedance source.
VTT does not terminate any DDR clock pairs. Rather, the xDDR_CLK and xDDR_CLK_N termination
consists of a parallel 100-121 Ω resistor between the two lines.
18
•
VTT islands require at least two additional decoupling capacitors (4-7 µF) and two bulk capacitors
(100 µF) at each end.
•
Each data line is connected to VTT with relatively low impedance. This supply must be extremely
stable. Any noise on this supply directly affects the data lines.
LPDDR, DDR2, and DDR3
•
Sufficient bulk and bypass capacitance must be provided to keep this supply at VDDQ/2. VREF
power must not be derived from VTT, but must be derived from VDDQ with a 1% or better resistor
divider.
LPDDR and DDR2 Design
This document assumes the designer must be familiar with the specifications and basic electrical
operation of the LPDDR/DDR2 interface. Data bus, data strobe, and data mask (byte enable) signals are
point-to-point, whereas all other address, control, and clock signals are not.
Figure 11 shows the connectivity of the RTG4 LPDDR interface, and Figure 12 on page 20 shows a
32-bit DDR2 interface.
RTG4
FDDR_x_DQS [1:0]
FDDR_x_DM_RDQS [1:0]
FDDR_x_DQ [15:0]
FDDR_x_BA [2:0]
FDDR_x_ADDR [14:0]
LPDDR SDRAM
x16-bit
Control lines
CKE, CS, WE, RAS, CAS
100 Ω
FDDR_x_CLK
FDDR_x_CLK_N
LPDDR SDRAM
x16-bit
FDDR_x_DQS [3:2]
FDDR_x_DM_RDQS [3:2]
FDDR_x_DQ [31:16]
FDDR_x_TMATCH_y_OUT
FDDR_x_TMATCH_y_IN
FDDR_x_TMATCH_ECC_OUT
FDDR_x_TMATCH_ECC_IN
150 Ω_1% (Optional)
FDDR_x_IMP_CALIB
Figure 11 • LPDDR Interface
19
Board Design Guidelines for RTG4 FPGAs
RTG4
FDDR_x_DQS [1:0]
FDDR_x_DQS [1:0]_N
FDDR_x_DM_RDQS [1:0]
FDDR_x_DQ [15:0]
DDR 2 SDRAM
x16-bit
FDDR_x_CLK
100 Ω
FDDR_x_CLK_N
Rt
VTT
FDDR_x_ADDR [13:0]
Rt
FDDR_x_BA [2:0]
Rt
Control lines
CKE, CS, WE, RAS, CAS
DDR2 SDRAM
x16-bit
FDDR_x_DQS [3:2]
FDDR_x_DQS [3:2]_N
FDDR_x_DM_RDQS [3:2]
FDDR_x_DQ [31:16]
FDDR_x_TMATCH_y_OUT
FDDR_x_TMATCH_y_IN
FDDR_x_TMATCH_ECC_OUT
FDDR_x_TMATCH_ECC_IN
150 Ω_1%
FDDR_x_IMP_CALIB
Figure 12 • DDR2 Interface
With short traces, the address, control, and command signals may not require both parallel (RT) and
series (RS) termination. In a worst-case scenario, a small series resistor (RS) of about 10 . or less is
required. The series termination is not used for impedance matching, but for dampening the signals.
Note: To ensure signal length matching, short the TMATCH_OUT to TMATCH_IN pins with shortest loop.
DDR3 Guidelines
The following are the guidelines for connecting to DDR3 memory:
20
•
DDR3 data nets have dynamic ODT built in the controller and SDRAM. For configurations with 40,
60, and 140 . terminations, VTT pull-up is not required.
•
Characteristic impedance (Zo) is typically 50  and Zdiff (differential) is 100 .
LPDDR, DDR2, and DDR3
DDR3 interfacing with RTG4 devices for 8-bit and 16-bit interfaces is shown in Figure 13 and Figure 14
respectively.
VTT
RTG4
Clock
DDR3
SDRAM
Address and
Command
DDR3
SDRAM
DDR3
SDRAM
DDR3
SDRAM
DQ group 0
DQ group1
DQ group 2
DQ group 3
FDDR_x_TMATCH_y_OUT
FDDR_x_TMATCH_y_IN
FDDR_x_TMATCH_ECC_OUT
FDDR_x_TMATCH_ECC_IN
240 Ω_1%
FDDR_x_IMP_CALIB
Figure 13 • 8-Bit DDR3 Interface
RTG4
x16
FDDR_x_DQS [1:0]
FDDR_x_DQS [1:0]_N
FDDR_x_DM_RDQS [1:0]
FDDR_x_DQ [15:0]
DDR3 SDRAM
x16
FDDR_x_BA [2:0]
DDR3 SDRAM 49.9 Ω VTT
49.9 Ω
FDDR_x_ADDR [13:0]
49.9 Ω
Control lines
CKE, CS, WE, RAS, CAS, ODT
FDDR_x_CLK
VDD
100 Ω
FDDR_x_CLK_N
ZQ
240 Ω
FDDR_x_DQS [3:2]
FDDR_x_DQS [3:2]_N
FDDR_x_DM_RDQS [3:2]
FDDR_x_DQ [31:16]
240 Ω
ZQ
FDDR_x_TMATCH_y_OUT
FDDR_x_TMATCH_y_IN
FDDR_x_TMATCH_ECC_OUT
FDDR_x_TMATCH_ECC_IN
240 Ω_1%
FDDR_x_IMP_CALIB
Figure 14 • 16-Bit DDR3 Interface
21
Board Design Guidelines for RTG4 FPGAs
DQ Line Interchange
For 4-bit or 8-bit DRAM, data (DQ) lines are interchangeable on the board. For example, if DQ5 of the
FPGA is connected to DQ0 of the DRAM, and DQ0 of the FPGA is connected to DQ5 of the DRAM,
neither the DRAM nor the FPGA will get affected.
For 16-bit DRAM, DQ0 through DQ7 can be interchanged within a byte lane. Similarly, DQ8 through
DQ15 can be interchanged within a byte lane. However, DQ0 through DQ7 signals or pins must not be
interchanged with any of the DQ8 through DQ15 signals.
SpaceWire Interface
The RTG4 device has a built-in RX clock recovery block with the jitter required for SpaceWire
applications. SpaceWire links operate from 2 to 400 Mbps over a full-duplex, point-to-point serial link.
SpaceWire uses a data-strobe (DS)-encoding scheme that encodes the transmission clock and data
from the transmitter into data (D) and strobe (S).The clock can then be recovered at the receiver end by
simply XORing the data (D) and strobe (S) lines together. SpaceWire uses low-voltage differential
signaling (LVDS) for the D and S signals. LVDS employs balanced signals to provide very high-speed
interconnection using a low-voltage swing (350 mV typical). The two dedicated D and S input pads for
can be configured as either single-ended or differential.
The optional ODT capability within the FPGA I/O provides good signal integrity without any external
resistors on the PCB. If ODT is not used, external termination resistors (100 Ω) may be required to
compensate for the unwanted impedance mismatches.
Temperature Sensing
A temperature sensing diode is located internally in the RTG4 device. It acts as an internal thermometer
providing the voltage drop (VBE), based on which the temperature (TJ) can be calculated.
The temperature sensing diode has a dedicated input pin, TEMP_MONITOR, connected to the anode of
the diode. The cathode of the diode is connected to VSS of the die.
7(03B021,725
57*
,GLRGH
7HPSHUDWXUH
VHQVH
GLRGH
966
Figure 15 • RTG4 Temperature Sensing
22
Additional Pins
Measure the temperature using the following steps:
1. With no power supplied to the RTG4 device, apply a known current (I diode) at a known
temperature to the TEMP_MONITOR pin.
2. Measure the VBE between the TEMP_MONITOR pin and the VSS pins
3. Determine the junction temperature (TJ) during operation using the equation:
TJ = m  VBE + T0
EQ1
where,
m = (TJ2-TJ1) / (VBE2-VBE1)
T0 = TJ1 - m * VBE1
Table 8 • Example Temperature (TJ) Calculation
Known Current
(I Diode)
Known
Temperature
VBE
m
T0
TJ
125
0.63936
-735.25
595.09
125.00056
0
0.80937
200 µA
0.0007075
Additional Pins
RTG4 devices have the following additional (special) pins.
Table 9 • Special Pins
Pin Name
Description
NC
"No connect" pin. Indicates the pin is not connected to circuitry within the device. NC
pins can be driven to any voltage or can be left floating with no effect on the operation
of the device.
DNC
"Do not connect" pin. DNC must not be connected to any signals on the PCB. DNC
pins must be left unconnected.
PROBE_CAPTURE
Specifies an internal signal for probing (oscilloscope-like feature).The two live probe
I/O cells function as either of the following:
PROBE_READ_DATA
•
Live probe
•
User I/O (MSIO)
If not used for probing or as user I/O, must be connected to GND through a 10 kΩ
resistor.
23
Board Design Guidelines for RTG4 FPGAs
Configuring Pins in Open Drain
To configure fabric pins in open-drain mode, the input pin of the tristate buffer must be tied low, and the
enable port of the buffer must be driven from the user logic via the fabric port (Figure 16).
VDDIx
10 kΩ
RTG4
IN
OUT
I/O Pin Status
EN
Fabric Port
Figure 16 • Configure Pins in Open Drain
Table 10 provides the truth table of configuring pins in open-drain mode.
Table 10 • Truth Table
Buffer Enable Port
Buffer In Port
Buffer Out Port
0 (low)
0 (low)
0 (low)
1 (high)
0 (low)
VDDIx
Cold Sparing
RTG4 devices support cold sparing for all I/O standards, including PCI 3.3 V. Cold sparing can be
implemented by connecting the devices as shown in Figure 17. The spare device must have its power
supplies set in a specific way so that the device retains its programming in a radiation environment and
does not cause issues in the system. The VPP and VDDI supplies of the spare device are powered up to
the required voltage while the VDD is powered down to save power.
The system integrates two parallel devices with shared I/O connections, one of which is an RTG4 device;
the other device can be any other (RTG4 or non-RTG4) active device.
24
Brownout Detection (BOD)
In cold sparing applications, voltage can be supplied to the device I/O before and during power-up. The
devices must be connected as follows:
•
The primary RTG4 device core and I/O bank supplies must be powered and fully functional until a
time is reached where a swap of devices is determined to be necessary.
•
The spare device I/O banks and VPP must be powered to prevent I/O leakage through the ESD
diodes, and the fabric core must be grounded. This arrangement establishes a low-power,
protected state for the spare device.
•
At any point, cold swap can be made by powering down the core supply of the primary RTG4
device and powering up the core supply of the spare device while following the configuration
sequence for each device.
9''
9'',
&RUH
9''
9''
9'',
,2
9'',
3ULPDU\
'HYLFH
9'',
933
6SDUH
'HYLFH
933
6KDUHG,2V
2WKHU&KLSV
Figure 17 • Cold Sparing
Brownout Detection (BOD)
RTG4 functionality is guaranteed only if VDD is above the recommended voltage level specified in the
data sheet. Brownout occurs when VDD drops below the minimum recommended operating voltage. As
a result, it is not possible to ensure proper or predictable device operation. The design may continue to
malfunction even after the supply is brought back to the recommended values as parts of the device may
have lost functionality during brownout. The VDD supply must be protected by a BOD circuit.
To recover from VDD brownout, the device must either be power-cycled or an external BOD circuit must
be used to reset the device for correct operation. The recommended guideline for the threshold voltage
of BOD is a minimum of 1 V. The BOD circuit must be designed such that if the VDD falls below 1 V, the
device should be held in power-down mode via the DEVRST_N pin.
Note: BOD must be implemented standalone or included as part of the power management circuitry.
25
Board Design Guidelines for RTG4 FPGAs
The RTG4 device does not have built-in BOD circuitry, but an external BOD circuitry can be
implemented, as shown in Figure 18.
VPP
Sense
+1.2 V
VDD
VCC
Brownout Reset
Device
Reset#
RTG4
10 kΩ
DEVRST_n
GND
Figure 18 • BOD Circuit Implementation
The BOD device must have an open-drain output to connect to VPP through 10 kΩ resistor externally.
During power-on, the brownout reset keeps the device powered down until the supply voltage reaches
the threshold voltage. Thereafter, the brownout reset device monitors VDD and keeps RESET# output
active as long as VDD remains below the threshold voltage. An internal timer delays the return of the
output to the inactive state (high) to ensure proper system reset.
The delay time is in milliseconds and it starts after the VDD has risen above the threshold voltage. When
the supply voltage drops below the threshold voltage, the output becomes active (low) again.
26
List of Changes
List of Changes
The following table shows the important changes made in this document for each revision.
Revision
Revision 4
(June 2016)
Changes
Page
Updated "Fabric I/O Configurations" section (SAR 80460)
14
Updated "Power Supply Sequencing and PoR" section (SAR 79727, 80024)
7
Updated "DDR3 Guidelines" section (SAR 80592)
20
Updated "DDR3 Guidelines" section (SAR 80103)
20
Added "Temperature Sensing" section (SAR 79513)
22
Revision 3
(April 2016)
Updated "Cold Sparing" section (SAR 75706)
24
Revision 2
(December 2015)
Updated Figure 5 (SAR 71193, 72422)
10
Updated Table 1 for the capacitance values (SAR 71844, 71049)
5
Updated "PLL Filter" section information on SerDes unused conditions (SAR 72340)
16
Revision 1
Initial release
(September 2015)
N/A
27
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