NVMFS4C03N D

NVMFS4C03N
Power MOSFET
30 V, 1.7 mW, 159 A, Single N−Channel
Logic Level, SO−8FL
Features
•
•
•
•
•
•
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Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS4C03NWF − Wettable Flanks Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V(BR)DSS
RDS(on) MAX
ID MAX
1.7 mW @ 10 V
30 V
159 A
2.4 mW @ 4.5 V
D (5,6)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
"20
V
Parameter
Continuous Drain Current RqJC (Notes 1, 2,
3)
TC = 25°C
TC = 25°C
A
PD
77
MARKING
DIAGRAM
W
D
TA = 25°C
ID
34.9
A
Steady
State
Power Dissipation
RqJA (Notes 1, 2)
Pulsed Drain Current
159
S (1,2,3)
N−CHANNEL MOSFET
Steady
State
Power Dissipation
RqJC (Notes 1, 2)
Continuous Drain Current RqJA (Notes 1, 2,
3)
ID
G (4)
TA = 25°C
PD
3.71
W
TA = 25°C, tp = 10 ms
IDM
900
A
TJ, Tstg
−55 to
175
°C
Operating Junction and Storage Temperature
Source Current (Body Diode)
IS
64
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 11 A)
EAS
549
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
Symbol
Value
Unit
Junction−to−Case − Steady State (Note 2)
RqJC
1.95
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
40
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
April, 2016 − Rev. 2
D
D
4C03N = Specific Device Code for
NVMFS4C03N
4C03WF= Specific Device Code of
NVMFS4C03NWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceabililty
Package
Shipping†
NVMFS4C03NT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
NVMFS4C03NT3G
SO−8 FL
(Pb−Free)
5000 /
Tape & Reel
NVMFS4C03NWFT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
NVMFS4C03NWFT3G
SO−8 FL
(Pb−Free)
5000 /
Tape & Reel
Device
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
© Semiconductor Components Industries, LLC, 2016
D
4C03xx
AYWZZ
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Parameter
S
S
S
G
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NVMFS4C03N/D
NVMFS4C03N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
18.2
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
100
mA
nA
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
1.3
2.2
4.8
V
mV/°C
VGS = 10 V
ID = 30 A
1.4
1.7
VGS = 4.5 V
ID = 30 A
2.0
2.4
mW
Forward Transconductance
gFS
VDS = 3 V, ID = 30 A
136
S
Gate Resistance
RG
TA = 25 °C
1.0
W
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
67
Total Gate Charge
QG(TOT)
20.8
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
3071
VGS = 0 V, f = 1 MHz, VDS = 15 V
1673
pF
4.9
VGS = 4.5 V, VDS = 15 V; ID = 30 A
nC
8.5
4.7
QG(TOT)
VGS = 10 V, VDS = 15 V,
ID = 30 A
45.2
nC
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
14
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
32
ns
27
17
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.75
TJ = 125°C
0.6
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 10 A
1.1
V
47
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
QRR
23
ns
24
39
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS4C03N
TYPICAL CHARACTERISTICS
250
250
4.5 V
TJ = 25°C
3.8 V
200
3.6 V
3.4 V
175
VGS = 10 V
150
3.2 V
125
100
3.0 V
75
50
2.8 V
25
2.6 V
200
175
150
125
100
75
TJ = 25°C
TJ = −55°C
25
0
0.5
1.0
1.5
2.0
2.5
1.5
3.0
3
3.5
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
2.9
TJ = 25°C
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
Figure 3. On−Resistance vs. VGS
4.5
3.1
TJ = 25°C
2.9
2.7
2.5
2.3
VGS = 4.5 V
2.1
1.9
1.7
1.5
VGS = 10 V
1.3
0
25
50
75
100 125 150 175 200
225 250
ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.8
10000
VGS = 0 V
ID = 30 A
VGS = 10 V
IDSS, LEAKAGE (nA)
1.6
2.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
3.1
3
2
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
0.0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
TJ = 150°C
50
0
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
VDS = 3 V
225
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
225
1.4
1.2
1.0
TJ = 125°C
1000
TJ = 100°C
TJ = 85°C
100
0.8
0.6
−50 −25
10
0
25
50
75
100
125
150
175
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NVMFS4C03N
VGS, GATE−TO−SOURCE VOLTAGE (V)
10000
C, CAPACITANCE (pF)
Ciss
Coss
1000
100
Crss
VGS = 0 V
TJ = 25°C
f = 1 MHz
10
0.1
1
10
12
QT
10
15
9
8
VDS
7
12
VGS
6
9
5
4
Qgs
Qgd
6
3
TJ = 25°C
VDS = 15 V
ID = 30 A
2
1
0
100
0
5
10
15
20
25
30
35
40
45
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
3
0
50
1000
1000
VGS = 0 V
IS, SOURCE CURRENT (A)
VDD = 15 V
ID = 15 A
VGS = 4.5 V
td(off)
tf
100
tr
td(on)
100
TJ = 150°C
10
TJ = 25°C
1
TJ = −55°C
0.1
10
0.1
1
10
0.3
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
ID, DRAIN CURRENT (A)
t, TIME (ns)
18
11
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
100
10 ms
10 ms
10
1
0.1
VGS ≤ 10 V
TC = 25°C
100 ms
RDS(on) Limit
Thermal Limit
Package Limit
1 ms
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NVMFS4C03N
TYPICAL CHARACTERISTICS
R(t) (°C/W)
100
RqJA Steady State = 40°C/W
Duty Cycle = 50%
10 20%
10%
5%
1 2%
1%
PCB Cu Area = 650 mm2
PCB Cu Thk = 2 oz
0.1
0.01
Single Pulse
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
PULSE TIME (sec)
Figure 12. Thermal Impedance
(Junction−to−Ambient)
100
IPEAK, (A)
0.001
1E−06
TJ(initial) = 25°C
10
TJ(initial) = 100°C
1
1.00E−04
1.00E−03
TIME IN AVALANCHE (s)
Figure 13. Avalanche Characteristics
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5
1.00E−02
1E+01
1E+02
1E+03
NVMFS4C03N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
DETAIL A
2X
0.10
b
C A B
0.05
c
0.495
8X
4.560
MILLIMETERS
MIN
NOM
MAX
1.10
0.90
1.00
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.30
5.15
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
1.530
e/2
e
L
1
4
3.200
K
4.530
E2
PIN 5
(EXPOSED PAD)
L1
M
1.330
2X
0.905
1
G
0.965
D2
4X
1.000
4X 0.750
BOTTOM VIEW
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
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NVMFS4C03N/D