NVMFS5C645NL D

NVMFS5C645NL
Power MOSFET
60 V, 4.0 mW, 100 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C645NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
4.0 mW @ 10 V
60 V
100 A
5.7 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
ID
100
A
Parameter
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
TC = 100°C
TC = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Pulsed Drain Current
Steady
State
PD
N−CHANNEL MOSFET
A
22
PD
A
TJ, Tstg
−55 to
+175
°C
IS
100
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 5 A)
EAS
185
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
D
1
1.8
820
Source Current (Body Diode)
MARKING
DIAGRAM
W
3.7
IDM
Operating Junction and Storage Temperature
S (1,2,3)
15
TA = 100°C
TA = 25°C, tp = 10 ms
W
79
40
ID
TA = 100°C
TA = 25°C
G (4)
71
TC = 100°C
TA = 25°C
D (5)
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
1.9
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
41
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
5C645L
A
Y
W
ZZ
S
S
S
G
D
5C645L
AYWZZ
D
D
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 0
1
Publication Order Number:
NVMFS5C645NL/D
NVMFS5C645NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
15.5
VGS = 0 V,
VDS = 48 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
100
nA
2.0
V
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
−4.9
mV/°C
VGS = 10 V
ID = 50 A
3.3
4.0
VGS = 4.5 V
ID = 50 A
4.6
5.7
gFS
VDS = 15 V, ID = 50 A
105
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
2200
VGS = 0 V, f = 1 MHz, VDS = 50 V
CRSS
900
pF
17
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 30 V; ID = 50 A
16
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 30 V; ID = 50 A
34
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
1.5
nC
5.6
VGS = 4.5 V, VDS = 30 V; ID = 50 A
Gate−to−Drain Charge
QGD
5.1
Plateau Voltage
VGP
2.8
td(ON)
10
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 30 V,
ID = 50 A, RG = 2.5 W
tf
15
ns
24
5.0
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.88
TJ = 125°C
0.78
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
41
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
21
ns
20
32
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C645NL
3.8 V
140 10 V to
4.5 V
120
3.6 V
100
3.4 V
80
3.2 V
60
3.0 V
40
2.8 V
TJ = −55°C
100
80
60
40
20
0
0
0.5
1.0
1.5
2.0
2.5
0
3.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
TJ = 25°C
120
20
10
TJ = 25°C
ID = 50 A
9
8
7
6
5
4
3
3
4
5
6
7
8
9
10
4.0
8
TJ = 25°C
7
6
VGS = 4.5 V
5
4
VGS = 10 V
3
2
10
30
50
70
90
110
130
150
VGS, GATE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.5
100,000
TJ = 125°C
VGS = 10 V
ID = 50 A
2.0
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
TJ = 125°C
140
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
TYPICAL CHARACTERISTICS
1.5
1.0
10,000
TJ = 85°C
1000
100
0.5
0
−50 −25
10
0
25
50
75
100
125
150
175
5
15
25
35
45
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
55
NVMFS5C645NL
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
2400
CISS
2000
1600
VGS = 0 V
TJ = 25°C
f = 1 MHz
COSS
1200
800
400
CRSS
0
0
10
20
30
40
50
30
QT
25
8
20
6
15
QGD
QGS
4
10
VDS = 30 V
TJ = 25°C
ID = 25 A
2
5
0
0
0
60
4
8
12
16
20
24
28
32
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
1000
t, TIME (ns)
IS, SOURCE CURRENT (A)
45
VGS = 4.5 V
VDD = 30 V
ID = 25 A
td(off)
tf
100
tr
td(on)
10
40
TJ = 125°C
35
30
TJ = 25°C
25
20
15
TJ = −55°C
10
5
1
0
1
10
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
TC = 25°C
VGS ≤ 10 V
0.01 ms
0.1 ms
10
TJ(initial) = 25°C
IPEAK (A)
IDS (A)
100
1 ms
10 ms
10
TJ(initial) = 100°C
1
RDS(on) Limit
Thermal Limit
Package Limit
1
0.1
0.1
1
10
1E−04
100
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMFS5C645NL
100
RqJA(t) (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
NVMFS5C646NL 650 mm2, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C645NLT1G
5C645L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C645NLWFT1G
645LWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C645NLT3G
5C645L
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C645NLWFT3G
645LWF
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5C645NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE L
2X
0.20 C
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
A
2
B
D1
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
0.10 C
3X
C
e
SEATING
PLANE
DETAIL A
A
0.10 C
SIDE VIEW
8X
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
b
0.10
C A B
0.05
c
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.00
5.30
5.15
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.30
6.15
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
0.495
4.560
e/2
L
1
2X
1.530
4
K
3.200
4.530
E2
PIN 5
(EXPOSED PAD)
L1
M
1.330
2X
G
D2
0.905
1
BOTTOM VIEW
0.965
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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For additional information, please contact your local
Sales Representative
NVMFS5C645NL/D