NVMFS5C604NL D

NVMFS5C604NL
Power MOSFET
60 V, 1.2 mW, 287 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C604NLWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
1.2 mW @ 10 V
60 V
287 A
1.7 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
Pulsed Drain Current
Value
Unit
VDSS
60
V
VGS
±20
V
ID
287
A
TC = 100°C
TC = 25°C
Steady
State
PD
ID
Operating Junction and Storage Temperature
Source Current (Body Diode)
W
200
S (1,2,3)
N−CHANNEL MOSFET
A
40
28
PD
TA = 100°C
TA = 25°C, tp = 10 ms
G (4)
100
TA = 100°C
TA = 25°C
D (5,6)
203
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Symbol
MARKING
DIAGRAM
W
3.9
D
1.9
1
IDM
900
A
TJ, Tstg
−55 to
+175
°C
IS
203
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 22 A)
EAS
776
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C604L
XXXXXX = (NVMFS5C604NL) or
XXXXXX = 604LWF
XXXXXX = (NVMFS5C604NLWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Junction−to−Case − Steady State
Junction−to−Ambient − Steady State (Note 2)
Symbol
Value
Unit
RqJC
0.75
°C/W
RqJA
39
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NVMFS5C604NL/D
NVMFS5C604NL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
22.9
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
10
TJ = 125°C
250
IGSS
VDS = 0 V, VGS = ±16 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.0
V
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
1.2
−5.9
mV/°C
VGS = 10 V
ID = 50 A
0.93
1.2
VGS = 4.5 V
ID = 50 A
1.25
1.7
gFS
VDS = 15 V, ID = 50 A
180
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
8900
VGS = 0 V, f = 1 MHz, VDS = 25 V
CRSS
3750
pF
40
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 30 V; ID = 50 A
52
Total Gate Charge
QG(TOT)
VGS = 10 V, VDS = 30 V; ID = 50 A
120
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
6.4
nC
21.4
VGS = 4.5 V, VDS = 30 V; ID = 50 A
Gate−to−Drain Charge
QGD
12.7
Plateau Voltage
VGP
2.8
td(ON)
21.8
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 4.5 V, VDS = 30 V,
ID = 50 A, RG = 2.5 W
tf
79.1
ns
57.8
81.3
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.78
TJ = 125°C
0.64
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
98
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
45
ns
53
190
nC
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
NVMFS5C604NL
TYPICAL CHARACTERISTICS
200
10 V to 3.4 V
3.2 V
160
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
180
140
3.0 V
120
100
80
2.8 V
60
40
20
0
0.5
1.0
1.5
TJ = 125°C
TJ = −55°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.004
TJ = 25°C
ID = 50 A
0.003
0.002
0.001
0
2
TJ = 25°C
0
2.0
3
4
5
6
7
8
9
10
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
4.0
0.0020
TJ = 25°C
0.0015
VGS = 4.5 V
VGS = 10 V
0.0010
0.0005
10
30
50
70
90
110
130
150
VGS, GATE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
VGS = 10 V
ID = 40 A
1.9
TJ = 125°C
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
2.1
1.7
1.5
1.3
1.1
10,000
TJ = 85°C
0.9
0.7
−50 −25
10
0
25
50
75
100
125
150
175
5
15
25
35
45
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
55
NVMFS5C604NL
10
CISS
COSS
VGS = 0 V
TJ = 25°C
f = 1 MHz
CRSS
0
10
20
30
40
50
30
QT
25
8
20
6
15
4
QGD
QGS
10
VDS = 30 V
TJ = 25°C
ID = 50 A
2
5
0
0
0
60
20
40
60
80
100
120
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
9600
8800
8000
7200
6400
5600
4800
4000
3200
2400
1600
800
0
VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
TYPICAL CHARACTERISTICS
1000
td(off)
40
100
IS, SOURCE CURRENT (A)
t, TIME (ns)
tf
tr
td(on)
10
VGS = 4.5 V
VDD = 30 V
ID = 50 A
1
30
20
10
TJ = 125°C
TJ = 25°C
0
1
10
100
0.3
0.4
0.5
0.6
0.7
0.8
TJ = −55°C
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
1000
TC = 25°C
VGS ≤ 10 V
0.01 ms
TJ(initial) = 25°C
0.1 ms
IPEAK (A)
IDS (A)
100
1 ms
dc
10 ms
TJ(initial) = 100°C
10
10
RDS(on) Limit
Thermal Limit
Package Limit
1
1
0.1
1
10
1E−04
100
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMFS5C604NL
100
RqJA(t) (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
NVMFS5C604NL 650 mm2, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C604NLT1G
5C604L
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C604NLWFT1G
604LWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C604NLT3G
5C604L
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C604NLWFT3G
604LWF
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5C604NL
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
0.20 C
D
A
2
B
D1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
0.10
8X b
C A B
0.05
c
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
e/2
1
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
0.495
e
L
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15
5.00
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.15
6.30
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
4.560
2X
1.530
4
K
3.200
E2
PIN 5
(EXPOSED PAD)
G
L1
4.530
M
D2
1.330
2X
0.905
1
BOTTOM VIEW
0.965
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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Sales Representative
NVMFS5C604NL/D