NVMFS5C410N D

NVMFS5C410N
Power MOSFET
40 V, 0.92 mW, 300 A, Single N−Channel
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS5C410NWF − Wettable Flank Option for Enhanced Optical
Inspection
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
ID MAX
40 V
0.92 mW @ 10 V
300 A
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJC
(Notes 1, 3)
TC = 25°C
Power Dissipation
RqJC (Note 1)
Continuous Drain
Current RqJA
(Notes 1, 2, 3)
Steady
State
Pulsed Drain Current
Value
Unit
VDSS
40
V
VGS
±20
V
ID
300
A
TC = 100°C
TC = 25°C
Steady
State
PD
ID
W
166
N−CHANNEL MOSFET
A
46
PD
1.9
D
900
TJ, Tstg
−55 to
+ 175
°C
IS
158
A
Single Pulse Drain−to−Source Avalanche
Energy (IL(pk) = 34 A)
EAS
578
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Source Current (Body Diode)
MARKING
DIAGRAM
W
3.9
IDM
Operating Junction and Storage Temperature
S (1,2,3)
32
TA = 100°C
TA = 25°C, tp = 10 ms
G (4)
83
TA = 100°C
TA = 25°C
D (5,6)
212
TC = 100°C
TA = 25°C
Power Dissipation
RqJA (Notes 1 & 2)
Symbol
A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
S
S
S
G
D
XXXXXX
AYWZZ
D
D
XXXXXX = 5C410N
XXXXXX = (NVMFS5C410N) or
XXXXXX = 410NWF
XXXXXX = (NVMFS5C410NWF)
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction−to−Case − Steady State
RqJC
0.9
°C/W
Junction−to−Ambient − Steady State (Note 2)
RqJA
39
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 1
1
Publication Order Number:
NVMFS5C410N/D
NVMFS5C410N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
5
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25 °C
10
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = 20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
100
nA
3.5
V
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
2.5
−8.6
VGS = 10 V
gFS
ID = 50 A
VDS =15 V, ID = 50 A
0.76
mV/°C
0.92
190
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
6100
VGS = 0 V, f = 1 MHz, VDS = 25 V
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
QGD
Plateau Voltage
VGP
pF
70
Total Gate Charge
Gate−to−Drain Charge
3400
VGS = 10 V, VDS = 32 V; ID = 50 A
86
18
nC
28
VGS = 10 V, VDS = 32 V; ID = 50 A
14
4.9
V
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
54
tr
162
td(OFF)
VGS = 10 V, VDS = 32 V,
ID = 50 A, RG = 2.5 W
tf
ns
227
173
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.8
TJ = 125°C
0.65
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 50 A
1.2
V
91
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 50 A
QRR
42
ns
49
159
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
NVMFS5C410N
TYPICAL CHARACTERISTICS
VDS = 10 V
4.8 V
5.2 V
240
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
300
10 V to 6.0 V
280
200
160
4.4 V
120
80
150
TJ = 25°C
100
TJ = 125°C
0
0.5
1.0
2.0
1.5
2.5
3.0
0
3
4
5
6
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
Figure 1. On−Region Characteristics
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
7
1.00
0.95
TJ = 25°C
0.90
0.85
0.80
VGS = 10 V
0.75
0.70
0.65
0.60
0.55
0.50
0
50
100
150
200
250
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.E−03
2.0
1.8
2
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 25°C
ID = 50 A
3
1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
5.0
VGS = 10 V
ID = 50 A
1.E−04
TJ = 150°C
IDSS, LEAKAGE (A)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE
TJ = −55°C
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
200
50
VGS = 4.0 V
40
250
1.6
TJ = 125°C
1.E−05
1.4
1.2
TJ = 85°C
1.E−06
1.0
0.8
−50 −25
1.E−07
0
25
50
75
100
125
150
175
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFS5C410N
TYPICAL CHARACTERISTICS
VGS, GATE−TO−SOURCE VOLTAGE (V)
1E+4
C, CAPACITANCE (pF)
CISS
COSS
1E+3
1E+2
CRSS
VGS = 0 V
TJ = 25°C
f = 1 MHz
1E+1
5
0
15
10
25
20
30
35
8
7
6
QGS
QGD
5
4
3
VDS = 20 V
TJ = 25°C
ID = 50 A
2
1
0
0
10
20
30
40
50
60
70
80
90
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source Voltage vs. Charge
100
VGS = 0 V
IS, SOURCE CURRENT (A)
td(off)
tf
tr
t, TIME (ns)
9
40
1000
td(on)
100
VGS = 10 V
VDS = 20 V
ID = 50 A
10
TJ = 150°C
TJ = 125°C
1
10
1
1000
10
10
0.3
100
0.4
0.5
0.6
TJ = 25°C TJ = −55°C
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
TC = 25°C
VGS ≤ 10 V
0.01 ms
0.1 ms
100
IPEAK (A)
100
ID (A)
1 ms
dc
10 ms
TJ(initial) = 25°C
TJ(initial) = 100°C
10
10
RDS(on) Limit
Thermal Limit
Package Limit
1
1
0.1
1
10
1E−04
100
1E−03
VDS (V)
TIME IN AVALANCHE (s)
Figure 11. Safe Operating Area
Figure 12. IPEAK vs. Time in Avalanche
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4
1E−02
NVMFS5C410N
100
RqJA(t) (°C/W)
50% Duty Cycle
10
20%
10%
5%
1
2%
1%
NVMFS5C410N 650 mm2, 2 oz., Cu Single Layer Pad
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
PULSE TIME (sec)
Figure 13. Thermal Characteristics
DEVICE ORDERING INFORMATION
Device
Marking
Package
Shipping†
NVMFS5C410NT1G
5C410N
DFN5
(Pb−Free)
1500 / Tape & Reel
NVMFS5C410NWFT1G
410NWF
DFN5
(Pb−Free, Wettable Flanks)
1500 / Tape & Reel
NVMFS5C410NT3G
5C410N
DFN5
(Pb−Free)
5000 / Tape & Reel
NVMFS5C410NWFT3G
410NWF
DFN5
(Pb−Free, Wettable Flanks)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS5C410N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE M
2X
0.20 C
D
A
2
B
D1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
2X
0.20 C
4X
E1
2
q
E
c
1
2
3
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
A1
4
TOP VIEW
C
SEATING
PLANE
DETAIL A
0.10 C
A
0.10 C
SIDE VIEW
0.10
8X b
C A B
0.05
c
DETAIL A
RECOMMENDED
SOLDERING FOOTPRINT*
e/2
1
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
2X
0.495
e
L
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15
5.00
5.30
4.70
4.90
5.10
3.80
4.00
4.20
6.00
6.15
6.30
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.575
0.71
1.20
1.35
1.50
0.51
0.575
0.71
0.125 REF
3.00
3.40
3.80
0_
−−−
12 _
4.560
2X
1.530
4
K
3.200
E2
PIN 5
(EXPOSED PAD)
G
L1
4.530
M
D2
1.330
2X
0.905
1
BOTTOM VIEW
0.965
4X
1.000
4X 0.750
1.270
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
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NVMFS5C410N/D