Freescale Semiconductor, Inc. Data Sheet: Technical Data Document Number: WPR1516 Rev 2, 1/2015 MWPR1516 16 KB Flash MWPR1516CFM(R) MWPR1516CALR 24 MHz Cortex-M0+ Based Microcontroller Higher integration receiver controller MCU for wireless power transfer application. Targeting battery powered products are smart phone, tablet, portable medical devices, power tools etc. This product offers: • AC/DC conversion and modulation/demodulation circuit for bi-directional communication to support industrial standards with foreign object detection (FOD) • USB/adapter power switcher to charge products with wire and wireless with priority. • Up to 15 W with proper external transistors • QFN package for industrial application and WLCSP package for space constrained consumer applications 32-pin QFN (FM) 36-pin WLCSP (AL) 5 x 5 x 0.58 Pitch 0.5 3.1 x 3.0 x 0.6 Pitch 0.4 mm mm Performance • 24 MHz ARM® Cortex®-M0+ core • Single cycle 32-bit x 32-bit multiplier Human-machine interface • One interrupt module (IRQ) • Up to 13 general-purpose input/output (GPIO) Memories and memory interfaces • 16 KB program flash memory • 4 KB SRAM Communication interfaces • One UART module • One I2C module System peripherals • LDO provides 5 V and 3 A output to down system • CNC controls the communication and provides AC protection • High voltage input PMC module with three power modes: Run, Wait, Stop • LVR with reset or interrupt, selectable trip points • WDOG with independent clock source • Serial wire debug interface Analog Modules Clocks • 32.768 kHz or 4 MHz to 24 MHz crystal oscillator • Internal 20 kHz low-power oscillator (LPO) • Internal clock source (ICS) • Internal FLL with internal or external reference, precision trimming Operating Characteristics • Input from rectifier voltage range: 3.5 to 20 V • Temperature range (ambient): -40 to 85°C • One 12-bit analog-to-digital converters (ADC) with up to 4 external channels • One programmable gain amplifier (PGA) with differential input and output • One analog comparator (ACMP) containing a 6-bit DAC and programmable reference input Timers • Two 2-channel FTMs with basic TPM function • One periodic interrupt timers (PIT) • One FSK demodulation timer (FSKDT) • System tick timer (SysTick) • One real time clock (RTC) Security and integrity modules • 80-bit unique identification number per chip Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2014–2015 Freescale Semiconductor, Inc. All rights reserved. Ordering Information Part Number1 Memory Maximum number of I\O's Flash (KB) SRAM (KB) MWPR1516CFM(R) 16 4 13 MWPR1516CALR 16 4 13 1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to WPR1516PB1 enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. WPR1516RM1 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. WPR1516_0N49M1 Package drawing Package dimensions are provided in package drawings. QFN 32-pin: 98ASA00615D1 WLCSP 36-pin: 98ASA00789D1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. Figure 1 shows the functional modules in the chip. 2 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. WPR1516 Family ARM ® Cortex™-M0+ Core System Internal watchdogs Memories and Memory Interfaces Program flash Debug interfaces Interrupt controller PMC Security Analog Timers UHV Watchdog 12-bit ADC x1 FSKDT x1 CNC x1 Analog comparator x1 FTM x2 and Integrity 6-bit DAC RAM Clocks External clock ICS Communication Human-Machine Interface (HMI) Interfaces LDO x1 UART x1 NMI I2C x1 GPIO PIT x1 Figure 1. Functional block diagram MWPR1516 16 KB Flash, Rev2, 1/2015. 3 Freescale Semiconductor, Inc. Table of Contents 1 Ratings................................................................................................5 1.1 Thermal handling ratings........................................................... 5 1.2 Moisture handling ratings.......................................................... 5 1.3 ESD handling ratings................................................................. 5 1.4 Voltage and current operating ratings........................................6 2 General............................................................................................... 7 2.1 Nonswitching electrical specifications...................................... 7 2.1.1 DC electrical characteristics.........................................7 2.1.2 Supply current characteristics...................................... 11 2.1.3 EMC performance........................................................ 12 2.2 Switching specifications............................................................ 13 2.2.1 Control timing.............................................................. 13 2.2.2 FTM module timing..................................................... 14 2.3 Thermal specifications...............................................................14 2.3.1 Thermal operating requirements.................................. 14 2.3.2 Thermal characteristics.................................................15 3 Peripheral operating requirements and behaviors.............................. 16 3.1 UHV modules............................................................................ 16 3.1.1 LDO electrical characteristics...................................... 16 3.1.2 Programmable gain amplifier (PGA) electronic characterizations...........................................................17 3.1.3 Communication and clamp controller (CNC) electronic characterizations.......................................... 18 3.2 Core modules............................................................................. 19 3.2.1 SWD electricals ...........................................................19 3.3 Clock modules........................................................................... 20 3.3.1 External oscillator (OSC) and ICS characteristics....... 20 3.4 Memories and memory interfaces..............................................22 3.4.1 NVM specifications......................................................22 4 Freescale Semiconductor, Inc. 4 5 6 7 8 9 3.5 Analog........................................................................................23 3.5.1 IFR measurement conditions........................................23 3.5.2 ADC characteristics......................................................24 3.5.3 Analog comparator (ACMP) electricals.......................26 3.6 Communication interfaces......................................................... 26 3.6.1 Inter-Integrated Circuit Interface (I2C) timing............ 27 Dimensions.........................................................................................28 4.1 Obtaining package dimensions.................................................. 28 Pinout................................................................................................. 28 5.1 Signal multiplexing and pin assignments.................................. 28 5.2 Device pin assignment............................................................... 30 Ordering Parts.................................................................................... 31 6.1 Determining valid orderable parts............................................. 31 Part Identification...............................................................................31 7.1 Description.................................................................................31 7.2 Format........................................................................................31 7.3 Fields..........................................................................................32 7.4 Example..................................................................................... 32 Terminology and guidelines...............................................................32 8.1 Definition: Operating requirement.............................................32 8.2 Definition: Operating behavior..................................................33 8.3 Definition: Attribute.................................................................. 33 8.4 Definition: Rating...................................................................... 34 8.5 Result of exceeding a rating.......................................................34 8.6 Relationship between ratings and operating requirements........ 35 8.7 Guidelines for ratings and operating requirements....................35 8.8 Definition: Typical value........................................................... 35 8.9 Typical value conditions............................................................36 Revision history................................................................................. 37 MWPR1516 16 KB Flash, Rev2, 1/2015. Ratings 1 Ratings 1.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 1.3 ESD handling ratings Symbol Description1 Min Typ. Max Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 — +2000 V 2 VCDM Electrostatic discharge voltage, charged-device model -500 — +500 V 3 Latch-up current at ambient temperature of 85 °C -100 — +100 mA 4 ILAT 1. Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions, unless otherwise noted. 2. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 4. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. MWPR1516 16 KB Flash, Rev2, 1/2015. 5 Freescale Semiconductor, Inc. Ratings 1.4 Voltage and current operating ratings Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Table 1. Voltage and current operating ratings Symbol VREC VAC1/AC2 Description Supply voltage from wireless receiver rectifier AC voltage input from wireless receiver coil IVREC Maximum current into VREC VDIO Digital input voltage (except RESET_b, EXTAL, and XTAL) VAD_IN VAIO ID Wired power input voltage • Analog1, RESET, VOUT_FB, EXTAL, and XTAL input voltage • VOUT and ISENS input voltage Instantaneous maximum current single pin limit • for GPIO pins • for other pins except power pins Min. Max. Unit 0 20 V -0.3 21 V 0 120 mA -0.3 VDD+0.3 0 12 -0.3 VDD+0.3 -0.3 5.5 -25 25 -10 10 V mA 1. Analog pins are defined as pins that do not have an associated general-purpose I/O port function. 6 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. General 2 General 2.1 Nonswitching electrical specifications 2.1.1 DC electrical characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 2. DC characteristics Symbol — Descriptions Operating voltage — Min. Typical1 Max. Unit 3.13 — 5.5 V VDD – 0.8 — — V — — -100 mA — — 0.8 V 5V — — 100 mA All digital inputs VDD > 4.5 V 0.70 × VDD — — V Input high voltage All digital inputs 3.13 V <VDD ≤ 4.5 V 0.75 × VDD — — V VIL Input low voltage All digital inputs 3.13 V <VDD ≤ 4.5 V — — 0.30 × VDD V VIL Input low voltage All digital inputs VDD > 3.3 V — — 0.35 × VDD V Vhys Input hysteresis All digital inputs — 0.06 × VDD — — mV VOH Output high voltage All I/O pins, standard- 5 V, Iload = -5 drive strength mA IOHT Output high current VOL Output low voltage IOLT Output low current Max total IOL for all ports VIH Input high voltage VIH Max total IOH for all ports 5V All I/O pins, standard- 5 V, Iload = 5 drive strength mA |IIn| Input leakage All input only pins (per VIN = VDD or current pin) VSS — 0.1 1 µA |IOZ| Hi-Z (off-state) All input / output (per leakage pin) current VIN = VDD or VSS — 0.1 1 µA Total leakage combined for all inputs and Hi-Z pins VIN = VDD or VSS — — 2 µA |IOZTOT| All input only and I/O Table continues on the next page... MWPR1516 16 KB Flash, Rev2, 1/2015. 7 Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 2. DC characteristics (continued) Symbol Descriptions Min. Typical1 Max. Unit RPU Pullup resistors All digital inputs, when enabled (all I/O pins other than PTA6 or PTA7 — 30.0 — 50.0 kΩ RPU2 Pullup resistors PTA6 and PTA7 — 30.0 — 60.0 kΩ IIC DC injection current3, 4, 5, 6 Single pin limit VIN < VSS, VIN > VDD -0.2 — 2 mA -5 — 25 Total MCU limit, includes sum of all stressed pins CIn Input capacitance, all pins — — — 7 pF VRAM RAM retention voltage — 2.0 — — V 1. Typical values are measured at 25 °C. Characterized, not tested. 2. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. 3. This item applies to the GPIO share pads only. 4. All functional non-supply pins, except for PTA6 and PTA7, are internally clamped to VDD. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). Table 3. Power supply electrical characteristics Symbol Description VDD1.8 Output voltage core Full performance mode VDD3 Output Voltage Flash Output voltage VDD Load current VDD Output voltage VREFH Unit 1.83 1.98 V — 1.6 — V Full performance mode 2.6 2.81 2.9 V mode2 — 1.69 — V Reduced power Full performance mode 3.5 V≤VREC<4.5 V 3.13 — 4.5 V Full performance mode 4.5 V≤ VREC<5.3 V 4.19 — 5.25 V Full performance mode VREC≥5.3 V 4.75 4.99 5.25 V mode2 2.5 — 5.75 V Full performance mode 3.5 V ≤ VREC<4.5 V 0 — 28 mA Full performance mode 4.5V ≤ VREC<5.3 V 0 — 28 mA Full performance mode VREC≥5.3 V 0 — 50 mA mode2 0 — 5 mA 3.8 3.819 V 4.5 V≤VREC<4.9 V 3.781/ 3.8/ 4.24 3.819/ 4.179 4.221 V Reduced power VREFH Max. 1 1.72 Reduced power IDD Typical mode2 Reduced power VDDF Min. 4.1 V≤VREC<4.5 V 3.781 Table continues on the next page... 8 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Nonswitching electrical specifications Table 3. Power supply electrical characteristics (continued) Symbol — Description VREFH accuracy IREFH Output current VREFH VLVWA VDD Low voltage warning assert level VLVWD VDD Low voltage warning deassert level VLVRA VDD low voltage reset assert VLVRD VDD low voltage reset deassertl VLVWREFHA VLVWREFHA Min. Typical Max. Unit VREC ≥ 4.9 V 3.781/ 4.179/ 4.577 3.8/ 4.2/ 4.64 3.819/ 4.221/ 4.623 V 1 VREC≥VREFH + 0.3, 0—70 °C — — 0.5 % VREC≥VREFH + 0.3, -40—85 °C — — 0.8 % VREC≥VREFH + 0.3 0 — 5 mA PMC_LVCTLSTAT1[SLVWSEL] = 0b 3.43 3.63 3.83 V PMC_LVCTLSTAT1[SLVWSEL] = 1b 3.94 4.14 4.34 PMC_LVCTLSTAT1[SLVWSEL] = 0b 3.54 3.74 3.94 PMC_LVCTLSTAT1[SLVWSEL] = 1b 4.08 4.28 4.48 2.97 3.02 — V — — 3.13 V PMC_VREFHLVW[LVWCFG]=00b 3.34 3.54 3.74 V PMC_VREFHLVW[LVWCFG]=01b 3.43 3.63 3.83 V PMC_VREFHLVW[LVWCFG]=10b 3.86 4.06 4.26 V PMC_VREFHLVW[LVWCFG]=11b 4.11 4.31 4.51 V PMC_VREFHLVW[LVWCFG]=00b 3.45 3.65 3.85 V PMC_VREFHLVW[LVWCFG]=01b 3.55 3.75 3.95 V PMC_VREFHLVW[LVWCFG]=10b 4.00 4.20 4.40 V PMC_VREFHLVW[LVWCFG]=11b 4.27 4.47 4.67 V Low voltage warning for VREFH assert level Low voltage warning for VREFH deassert level V VLVR1.8A Low voltage reset for VDD1.8 assert level 1.49 1.69 1.89 V VLVR1.8D Low voltage reset for VDD1.8 deassert level 1.56 1.76 1.96 V VLVRDDFA Low voltage reset for VDDF assert level 2.44 2.64 2.84 V VLVRDDFD Low voltage reset for VDDF deassert level 2.52 2.72 2.92 V — 20 — kHz -5 — 5 % fLPOCLK dfLPOCLK Trimmed LPOCLK output frequency Trimmed LPOCLK internal clock ∆f / fNOMINAL 5 tSDEL LPOCLK start up delay — 25 50 µs dVHT Temperature sensor slope — 5.07 — mV/° C VHT Temperature sensor output voltage THTIA THTID VBG VHCBG tSTP_REC — 1.57 — V High temperature interrupt assert6 95 110 125 °C High temperature interrupt deassert6 85 100 115 °C Bandgap output voltage 1.13 1.2 1.32 V HC Bandgap output voltage 1.14 1.15 1.16 V not including VREFH — 15 — µs including VREFH — 1 — ms Recovery time from Stop 1. Typical values are measured at 25 °C. MWPR1516 16 KB Flash, Rev2, 1/2015. 9 Freescale Semiconductor, Inc. Nonswitching electrical specifications 2. 3. 4. 5. 6. Power supply enters reduced power mode when MCU is in Stop mode. VDD is from VDD1. This typical value is configurable based on VREC. User need to trim the LPOCLK in order to get ±5% LPOCLK This is junction temperature. NOTE Unless noted, VDD1 and VDD2 must be shorted on the application board. 0.4 0.35 0.3 0.25 VD D - VO H (V ) 0.2 ‐40 C 25 C 85 C 0.15 0.1 0.05 0 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0.004 0.0045 0.005 I O H(A ) Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V) 10 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Nonswitching electrical specifications 0.35 0.3 0.25 0.2 ‐40 C VO L(V) 25 C 85 C 0.15 0.1 0.05 0 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0.004 0.0045 0.005 I OL ( A ) Figure 3. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V) 2.1.2 Supply current characteristics This section includes information about power supply current in various operating modes. Table 4. Supply current characteristics (at 5.5 V) Parameter Symbol Bus Freq. Typical1 Max. Unit Temp. Run supply current FEI mode, all modules clocks enabled; run from flash RIDD 24 MHz 13.17 — mA -40―85 °C 12 MHz 9.37 — 6 MHz 7.49 — Run supply current FEI mode, all modules clocks disabled; run from flash RIDD 24 MHz 11.17 — mA -40―85 °C 12 MHz 8.37 — Run supply current FBE mode, all modules clocks enabled; run from RAM RIDD mA -40―85 °C Run supply current FBE mode, all modules clocks disabled; run from RAM RIDD mA -40―85 °C Wait mode current FBE mode, all modules clocks enabled WIDD mA -40―85 °C 6 MHz 6.99 — 24 MHz 14.01 17 12 MHz 8.65 — 6 MHz 6.60 — 24 MHz 10.61 13 12 MHz 7.65 — 6 MHz 6.09 — 24 MHz 8.23 10 Table continues on the next page... MWPR1516 16 KB Flash, Rev2, 1/2015. 11 Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 4. Supply current characteristics (at 5.5 V) (continued) Parameter Stop mode supply current no clocks active (except CNC clock) Symbol Bus Freq. Typical1 Max. 12 MHz 6.52 — 6 MHz 5.53 — — 700 — SIDD Unit Temp. µA -40―85 °C 1. Data in Typical column was characterized at 25 °C or is typical recommended value. 2.1.3 EMC performance Electromagnetic compatibility (EMC) performance is highly dependent on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation play a significant role in EMC performance. The system designer must consult the following Freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing EMC performance. • AN2321: Designing for Board Level Electromagnetic Compatibility • AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers • AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers • AN2764: Improving the Transient Immunity Performance of MicrocontrollerBased Applications • AN1259: System Design and Layout Techniques for Noise Reduction in MCUBased Systems 2.1.3.1 Radiated Emissions Table 5. EMC radiated emissions operating behaviors for 32-pin QFN package Symbol Description Frequency band (MHz) Typ. Unit Notes 1, 2 VRE1 Radiated emissions voltage, band 1 0.15–50 4 dBμV VRE2 Radiated emissions voltage, band 2 50–150 6 dBμV VRE3 Radiated emissions voltage, band 3 150–500 16 dBμV VRE4 Radiated emissions voltage, band 4 500–1000 5 dBμV IEC level 0.15–1000 M — VRE_IEC 12 Freescale Semiconductor, Inc. 2, 3 MWPR1516 16 KB Flash, Rev2, 1/2015. Switching specifications 1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. VRECT = 5.0 V, TA = 25 °C, fOSC = 32.768 kHz (crystal), fSYS = 24 MHz, fBUS = 24 MHz 3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method 2.2 Switching specifications 2.2.1 Control timing Table 6. Control Timing Rating Bus frequency (tCYC = 1 / fBus) Internal low power oscillator frequency2 External reset pulse width Max. Unit DC Typical1 — 24 MHz fLPO 16 20 26 KHz tEXTRST 1.5 × — — ns Symbol Min. fBus tCYC Reset low drive External NMI pin interrupt pulse width Asynchronous path IRQ pulse width Asynchronous path3 tRSTDRV 34 × tCYC — — ns tNMI 100 — — ns 100 — — ns 1.5 × tCYC — — ns tILIH Synchronous path tIHIL — tRise — 10.2 — ns tFall — 9.5 — ns Port rise and fall time Normal drive strength (load = 50 pF) 1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. 2. It can be configured by PMC_RC20KTRM[OSCOT]. 3. This is the shortest pulse that is guaranteed to be recognized as a IRQ pin request. textrst RESET_b pin Figure 4. Reset Timing MWPR1516 16 KB Flash, Rev2, 1/2015. 13 Freescale Semiconductor, Inc. Thermal specifications tIHIL IRQ IRQ tILIH Figure 5. IRQ Timing 2.2.2 FTM module timing Synchronizer circuits determine the shortest input pulses that can be recognized. These synchronizers operate from the timer clock. Table 7. FTM Input Timing Function Symbol Min. Max. Unit Input capture pulse width tICPW 1.5 — tTimer1 1. tTimer = 1/fTimer tICPW FTMCHn FTMCHn tICPW Figure 6. Timer Input Capture Pulse 2.3 Thermal specifications 2.3.1 Thermal operating requirements Table 8. Thermal operating requirements of WLCSP package Symbol Description Min. Max Unit TJ Die junction temperature -40 95 °C TA Ambient temperature -40 85 °C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + θJA × chip power dissipation. 14 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Thermal specifications Table 9. Thermal operating requirements of QFN package Symbol Description Min. Max Unit TJ Die junction temperature -40 105 °C TA Ambient temperature -40 85 °C Notes 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + θJA × chip power dissipation. 2.3.2 Thermal characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 10. Thermal Attributes Board type Symbol Single-layer (1S) RθJA Four-layer (2s2p) Description 32 QFN 36 WLCSP Unit Notes Thermal resistance, junction to ambient (natural convection) 97 129.8 °C/W 1, 2 RθJA Thermal resistance, junction to ambient (natural convection) 33 71.4 °C/W 1, 3 Single-layer (1S) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 81 116.5 °C/W 1, 3 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 27 68.0 °C/W 1, 3 — RθJB Thermal resistance, junction to board 12 48.6 °C/W 4 — RθJC Thermal resistance, junction to case 1.3 8.1 °C/W 5 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 3 0.2 °C/W 6 — ΨJB Thermal characterization parameter, junction to package bottom outside center (natural convection) — 14.3 °C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. MWPR1516 16 KB Flash, Rev2, 1/2015. 15 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 2. JESD51-2 with the single layer board (JESD51-3) horizontal. 3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = PINT + PI/O PINT = IDD × VDD, Watts - chip internal power PI/O = Power dissipation on input and output pins - user determined For most applications, PI/O << PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273 °C) Solving the equations above for K gives: K = PD × (TA + 273 °C) + θJA × (PD)2 Where K is a constant pertaining to the particular part. K can be determined by measuring PD (at equilibrium) for an known TA. Using this value of K, the values of PD and TJ can be obtained by solving the above equations iteratively for any value of TA. 3 Peripheral operating requirements and behaviors 3.1 UHV modules 16 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Peripheral operating requirements and behaviors 3.1.1 LDO electrical characteristics This section provides data about the LDO module electrical characteristics. Table 11. LDO electrical characteristics Sy mb ol Description Min. Typical Max. Unit VOUT Regulated output voltage 4.2 5 5.2 V VOUT Output voltage accuracy — 22 — % — 4.27 — V — V N x 1.4/(511 x 10 x Rsense)3 — A 1.05/(10 x Rsense) — A 1 A VTH1 Over voltage protection deassert LDO_CR[OVTHLD]=00b LDO_CR[OVTHLD]=01b 4.62 LDO_CR[OVTHLD]=10b 5.33 LDO_CR[OVTHLD]=11b 5.78 VTH2 Over voltage protection assert LDO_CR[OVTHLD]=00b — 4.8 LDO_CR[OVTHLD]=01b 5.2 LDO_CR[OVTHLD]=10b 6.0 LDO_CR[OVTHLD]=11b 6.5 ILIM Current limit threshold, with sample resistor: 33 mΩ 0.3 100 mΩ 0.1 ITH1 Over current protection threshold LDO_CR[OCTHLD]=000b — LDO_CR[OCTHLD]=001b 1.10/(10 x Rsense) LDO_CR[OCTHLD]=010b 1.15/(10 x Rsense) LDO_CR[OCTHLD]=011b 1.20/(10 x Rsense) LDO_CR[OCTHLD]=100b 1.25/(10 x Rsense) LDO_CR[OCTHLD]=101b 1.30/(10 x Rsense) LDO_CR[OCTHLD]=110b 1.35/(10 x Rsense) LDO_CR[OCTHLD]=111b 1.40/(10 x Rsense) 1. VOUT is configurable by LDO_VTRM[VTRM], it must be lower than 5.2 V. User can check the voltage dropout of MOSFET to avoid over power consumption. 2. This value is affected by the precision of the output voltage divider resistor. 3. N is configured by LDO_VTRM[VTRM]. 3.1.2 Programmable gain amplifier (PGA) electronic characterizations This section includes information about PGA. MWPR1516 16 KB Flash, Rev2, 1/2015. 17 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 12. PGA electrical characteristics (4.5 V ≤ VDDA ≤ 5.5 V) Symbol Description Gain Programmable gain dGain/dT PGA_CTRL[GAIN]=00b Min. Typical Max. — 8 — PGA_CTRL[GAIN]=01b 10 PGA_CTRL[GAIN]=10b 15 PGA_CTRL[GAIN]=11b 20 Gain versus temperature Unit — 10 — ppm/°C voltage1 -12 — 12 mV dVOS/dT Input referred offset voltage versus temperature — 20 — µV/°C IIN_BIAS Input BIAS current — — 250 µA — — 2.0 MHz VOS Input referred offset Bw(-3 dB) PGA -3 dB bandwidth PGA_CTRL[GAIN]=00b PGA_CTRL[GAIN]=01b 1.6 PGA_CTRL[GAIN]=10b 1.0 PGA_CTRL[GAIN]=11b 0.8 PSRR Power supply rejection ratio — -60 — dB CMRR Common mode rejection ratio — -60 — dB VR_CM_IN Input common mode voltage VR_DM_IN Input differential mode voltage PGA_CTRL[GAIN]=00b 4.5 5 5.5 V — — 250 mV PGA_CTRL[GAIN]=01b 200 PGA_CTRL[GAIN]=10b 130 PGA_CTRL[GAIN]=11b 100 1. The output referred offset of PGA is digitized by the on-chip ADC and stored in certain memory of each chip, customer can access the data to perform system level calibration. 3.1.3 Communication and clamp controller (CNC) electronic characterizations This section includes information about FSK Zero-Crossing, VREC and VAD analog comparators. Table 13. FSK analog comparator electrical specifications Symbol Characteristic Min. Typical Max. Unit VDDA Supply voltage 3.5 — 5.5 V IDDA Power consumption — 270 — µA VAIN Analog input range VSS — VDD - 1.4 V VAIO Analog input offset voltage — — 20 mV Analog comparator hysteresis — 0 — mV VH 18 Freescale Semiconductor, Inc. CNC_ANACFG1[ZCDHYST] = 00b CNC_ANACFG1[ZCDHYST] = 01b 18 MWPR1516 16 KB Flash, Rev2, 1/2015. Peripheral operating requirements and behaviors Table 13. FSK analog comparator electrical specifications Symbol Characteristic Min. Typical CNC_ANACFG1[ZCDHYST] = 10b 40 CNC_ANACFG1[ZCDHYST] = 11b 60 Max. Unit Table 14. CNC over-voltage protect (OVP) and low-voltage protect (LVP) electrical specifications Symbol VREC-OVP VREC-OVPR Characteristic VREC OVP assert VREC OVP deassert Min. Typical Max. Unit CNC_ANACFG1[VRECOVLVL]=00b — 25.7 — V CNC_ANACFG1[VRECOVLVL]=01b 21.5 22.5 23.2 CNC_ANACFG1[VRECOVLVL]=10b 19.3 20.3 21.2 CNC_ANACFG1[VRECOVLVL]=11b 16.4 17.1 18 CNC_ANACFG1[VRECOVLVL]=00b — 20.4 — CNC_ANACFG1[VRECOVLVL]=01b 17 17.8 18.4 CNC_ANACFG1[VRECOVLVL]=10b 15.2 16.2 16.8 CNC_ANACFG1[VRECOVLVL]=11b 12.8 13.5 14 V VREC-LVP VREC LVP assert 4.3 4.5 4.7 V VREC-LVPR VREC LVP de-assert 4.9 5.1 5.3 V VAD-OVP VAD OVP assert 5.5 5.7 5.9 V VAD-OVPR VAD OVP de-assert 5.15 5.3 5.5 V VAD-OK VAD LVP assert 4.15 4.3 4.55 V VAD-OK VAD LVP de-assert 3.95 4.0 4.25 V 3.2 Core modules 3.2.1 SWD electricals Table 15. SWD full voltage range electricals Symbol J1 Description Max. Unit 0 24 MHz 1/J1 — ns 20 — ns — 3 ns SWD_CLK frequency of operation • Serial wire debug J2 SWD_CLK cycle period J3 SWD_CLK clock pulse width • Serial wire debug J4 Min. SWD_CLK rise and fall times Table continues on the next page... MWPR1516 16 KB Flash, Rev2, 1/2015. 19 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 15. SWD full voltage range electricals (continued) Symbol Description Min. Max. Unit J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 3 — ns J11 SWD_CLK high to SWD_DIO data valid — 35 ns J12 SWD_CLK high to SWD_DIO high-Z 0 — ns J2 J3 J3 SWD_CLK (input) J4 J4 Figure 7. Serial wire clock input timing SWD_CLK J9 SWD_DIO J10 Input data valid J11 SWD_DIO Output data valid J12 SWD_DIO J11 SWD_DIO Output data valid Figure 8. Serial wire data timing 3.3 Clock modules 20 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Peripheral operating requirements and behaviors 3.3.1 External oscillator (OSC) and ICS characteristics Table 16. OSC and ICS specifications (temperature range = -40 to 85 °C ambient) Symbol Min Typical1 Max Unit Low range (RANGE = 0) flo 31.25 32.768 39.0625 kHz High range (RANGE = 1) fhi 4 — 24 MHz Characteristic Crystal or resonator frequency Load capacitors Feedback resistor See Note2 C1, C2 Low Frequency, Low-Power Mode3 — — — MΩ Low Frequency, High-Gain Mode — 10 — MΩ High Frequency, Low-Power Mode — 1 — MΩ High Frequency, High-Gain Mode — 1 — MΩ — 0 — kΩ — 200 — kΩ — 0 — kΩ 3 RF Series resistor Low Frequency Low-Power Mode RS Series resistor High Frequency Low-Power Mode3 Series resistor High Frequency, High-Gain Mode 4 MHz — 0 — kΩ 8 MHz — 0 — kΩ 16 MHz — 0 — kΩ — 0 — kΩ — 1000 — ms — 800 — ms — 3 — ms — 1.5 — ms High-Gain Mode RS 24 MHz Crystal start-up time low range = 32.768 kHz crystal; High range = 24 MHz crystal4,5 Low range, low power tCSTL Low range, high gain High range, low power tCSTH High range, high gain Internal reference start-up time tIRST — 20 50 µs Internal reference clock (IRC) frequency trim range fint_t 31.25 — 39.0625 kHz Internal reference clock frequency, factory trimmed T = 25 °C, VDD = 5 V fint_ft — 37.5 — kHz DCO output frequency range FLL reference = fint_t, flo, or fhi/RDIV fdco 40 — 50 MHz Factory trimmed internal oscillator accuracy T = 25 °C, VDD = 5 V Δfint_ft -0.5 — 0.5 % Deviation of IRC over temperature when trimmed at T = 25 °C, VDD = 5V Over temperature range from -40 °C to 85°C Δfint_t -1 — 0.5 % Over temperature range from 0 °C to 85°C Δfint_t -0.5 — 0.5 Frequency accuracy of DCO output using factory trim value Over temperature range from -40 °C to 85°C Δfdco_ft -2 — 1.5 Over temperature range from 0 °C to 85°C Δfdco_ft -1 — 1.5 % Table continues on the next page... MWPR1516 16 KB Flash, Rev2, 1/2015. 21 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 16. OSC and ICS specifications (temperature range = -40 to 85 °C ambient) (continued) Characteristic Symbol Min Typical1 Max Unit FLL acquisition time4,6 tAcquire — — 2 ms Long term jitter of DCO output clock (averaged over 2 ms interval)7 CJitter — 0.02 0.2 %fdco 1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. 2. See crystal or resonator manufacturer's recommendation. 3. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 4. This parameter is characterized and not tested on each device. 5. Proper PC board layout procedures must be followed to achieve specifications. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. OSC XTAL EXTAL RF C1 RS Crystal or Resonator C2 Figure 9. Typical crystal or resonator circuit 3.4 Memories and memory interfaces 22 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Peripheral operating requirements and behaviors 3.4.1 NVM specifications This section provides details about program / erase times, program / erase endurance for the flash memory. Table 17. Flash characteristics Characteristic Symbol Min.1 Typical2 Max.3 Unit4 NVM Bus frequency fNVMBUS 1 — 25 MHz NVM Operating frequency fNVMOP 0.8 1 1.05 MHz Erase Verify All Blocks tVFYALL — — 4653 tCYC Erase Verify Flash Block tRD1BLK — — 4626 tCYC Erase Verify Flash Section tRD1SEC — — 482 tCYC Read Once tRDONCE — — 464 tCYC Program Flash (2 words) tPGM2 0.14 0.14 0.35 ms Program Flash (4 words) tPGM4 0.23 0.23 0.56 ms Program Once tPGMONCE 0.22 0.23 0.23 ms Erase All Blocks tERSALL 95.54 100.31 100.56 ms Erase Flash Block tERSBLK 95.54 100.31 100.56 ms Erase Flash Sector tERSPG 19.11 20.06 20.10 ms Unsecure Flash tUNSECU 95.55 100.31 100.57 ms Configure NVM tCONFNVM — — 381 tCYC Verify Backdoor Access Key tVFYKEY — — 482 tCYC Set User Margin Level tMLOADU — — 420 tCYC FLASH Program/erase endurance TL to TH = -40 °C to 105 °C nFLPE 10 k 100 k — Cycles Data retention at an average junction temperature of TJAVG = 85 °C after up to 10,000 program / erase cycles tD_RET 15 100 — years 1. 2. 3. 4. Minimum times are based on maximum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and maximum fNVMBUS Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging tCYC = 1 / fNVMBUS Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program and erase operations, see the Memory section. 3.5 Analog MWPR1516 16 KB Flash, Rev2, 1/2015. 23 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors 3.5.1 IFR measurement conditions The value stored in the IFR is measured under the conditions of the following table. Table 18. IFR measurement conditions Symbol Descriptions Value Unit VREFH ADC reference voltage 5 V VREC Supply voltage from wireless receiver rectifier 5 V VDDX I/O supply voltage 5 V fBUS Bus frequency 24 MHz TA Ambient temperature 25 °C — Code execution From RAM — — NVM activity — — 3.5.2 ADC characteristics This section describes the ADC characteristics. Table 19. ADC Operating Conditions Characteristic Reference potential Symbol Min Typ Max Unit Low VRL VSSA — VDDA / 2 V High VRH VDDA — VDDA V /2 Differential reference voltage1 VRH - VRL 3.13 5.0 5.5 V fATDCLK 0.25 — 8.33 MHz tREC — — 1 µs tDISABLE — — 3 bus clock cycles 12-bit resolution NCONV12 19 — 39 10-bit resolution NCONV10 18 — 38 8-bit resolution NCONV8 16 — 36 ADC Clock Frequency (derived from bus clock via the prescaler bus) Buffer amplifier turn on time (delay after module start / recovery from Stop mode) ADC disable time ADC Conversion Period2 ADC clock cycles 1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V. 2. The minimum time assumes a sample time of four ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock cycles. 24 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Peripheral operating requirements and behaviors SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS R AS z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT ADC SAR ENGINE R ADIN v ADIN C AS v AS R ADIN INPUT PIN R ADIN INPUT PIN R ADIN INPUT PIN C ADIN Figure 10. ADC Input Impedance Equivalency Diagram Table 20. ADC Electrical Characteristics Characteristic Symbol Min Typical Max Unit RS — — 1 KΩ Total input capacitance Non sampling CINN — — 10 pF Total input capacitance sampling CINS — — 16 Input internal Resistance RINA — 5 15 Disruptive analog input current INA 0.25 — 2.5 mA Coupling ratio positive current injection Kp — — 1E-4 A/A Coupling ratio negative current injection Kn — — 5E-3 A/A Max input source resistance KΩ Table 21. ADC Conversion Performance Characteristic1 Symbol Min Typical Max Unit Resolution 12-Bit LSB — 1.25 — mV Differential Nonlinearity 12-Bit DNL -4 ±2 4 counts Integral Nonlinearity 12-Bit INL -5 ±2.5 5 counts Absolute Error2 12-Bit AE -7 ±4 7 counts Resolution 10-Bit LSB — 5 — mV Differential Nonlinearity 10-Bit DNL -1 ±0.5 1 counts Integral Nonlinearity 10-Bit INL -2.5 ±1 2.5 counts 10-Bit AE -3 ±2 3 counts Absolute Error2 Table continues on the next page... MWPR1516 16 KB Flash, Rev2, 1/2015. 25 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 21. ADC Conversion Performance (continued) Characteristic1 Symbol Min Typical Max Unit Resolution 8-Bit LSB — 20 — mV Differential Non-linearity 8-Bit DNL -0.5 ±0.3 0.5 counts Integral Non-linearity 8-Bit INL -1 ±0.5 1 counts 8-Bit AE -1.5 ±1 1.5 counts Absolute Error2 1. The 8-bit and 10-bit mode operation is structurally tested in production test. Absolute values are tested in 12-bit mode. 2. These values include the quantization error which is inherently 1/2 count for any ADC. NOTE Supply voltage VDDA = 5.12 V. External VREF = VRH - VRL = 5.12 V. fADCCLK = 8.0 MHz The values are tested to be valid with no IO PORT output drivers switching simultaneous with conversions. 3.5.3 Analog comparator (ACMP) electricals Table 22. Comparator electrical specifications Characteristic Symbol Min Typical Max Unit Supply current (Operation mode) IDDA — 10 20 µA Supply current, low-speed mode (EN = 1, PMODE = 0) IDDLS — 18 20 μA Analog input voltage VAIN VSS - 0.3 — VDDA V Analog input offset voltage VAIO — — 40 mV Analog comparator hysteresis (HYST=0) VH — 15 20 mV Analog comparator hysteresis (HYST=1) VH — 20 30 mV — — 40 μs IDDAOFF — 60 — nA IDAC6b — 7 — μA tD — 0.4 1 µs 6-bit DAC integral non-linearity INL –0.5 — 0.5 LSB2 6-bit DAC differential non-linearity DNL –0.3 — 0.3 LSB2 Analog comparator initialization delay1 Supply current (Off mode) 6-bit DAC current adder (enabled) Propagation Delay 1. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 2. 1 LSB = Vreference/64 26 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Peripheral operating requirements and behaviors 3.6 Communication interfaces 3.6.1 Inter-Integrated Circuit Interface (I2C) timing Table 23. I2C timing Characteristic Symbol Fast Mode1 Standard Mode Minimum Maximum Minimum Maximum Unit SCL Clock Frequency fSCL 0 100 0 4002 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. tHD; STA 4 — 0.6 — µs LOW period of the SCL clock tLOW 4.7 — 1.3 — µs HIGH period of the SCL clock tHIGH 4 — 0.6 — µs Set-up time for a repeated START condition tSU; STA 4.7 — 0.6 — µs Data hold time for I2C bus devices tHD; DAT 03 3.454 05 0.93 µs Data set-up time tSU; DAT 2506 — 1004, 7 — ns Rise time of SDA and SCL signals tr — 1000 20 +0.1Cb8 300 ns 7 Fall time of SDA and SCL signals tf — 300 20 +0.1Cb 300 ns Set-up time for STOP condition tSU; STO 4 — 0.6 — µs Bus free time between STOP and START condition tBUF 4.7 — 1.3 — µs Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. Fast mode is fully supported on all pins at VDD > 2.7 V. If VDD < 2.7 V, only pins that support high drive strength can support fast mode with maximum bus loading. 2. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V 3. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 4. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. 5. Input signal Slew = 10 ns and Output Load = 50 pF 6. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. 7. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. 8. Cb = total capacitance of the one bus line in pF. MWPR1516 16 KB Flash, Rev2, 1/2015. 27 Freescale Semiconductor, Inc. Dimensions SDA tf tLOW tSU; DAT tr tf tHD; STA tSP tr tBUF SCL S HD; STA tHD; DAT tHIGH tSU; STA tSU; STO SR P S Figure 11. Timing definition for fast and standard mode devices on the I2C bus 4 Dimensions 4.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00615D 36-pin WLCSP 98ASA00789D 5 Pinout 5.1 Signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. NOTE VDD1 and VDD2 must be short on PCB. PTA6 and PTA7 are true open drain pins. The external pullup resistor must be added to make them output correct values in using I2C0, GPIO, and UART0. 28 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Pinout The NC pin must be floating, and do not tie it to the any of the VDD or VSS. 32 QFN 36 WLC SP Pin Name Default — C3 VSS1 VSS1 VSS1 — C4 VSS1 VSS1 VSS1 — D3 VDD1 VDD1 VDD1 — D4 VDD1 VDD1 VDD1 1 A1 VREC VREC VREC 2 A2 VDD1 VDD1 VDD1 3 A3 VSS1 VSS1 VSS1 4 B3 PTA0 DISABLED PTA0 SBAR_IN1 EXTAL 5 B4 PTA1 DISABLED PTA1 SBAR_OUT0 XTAL 6 A4 PTA2 DISABLED PTA2 BUSOUT SBAR_OUT1 FTM0_CH0 7 A5 PTA3 DISABLED PTA3 CLAMP ACMP0_OUT FTM0_CH1 8 A6 PTA4 SWDIO PTA4 SWDIO FTM1_CH0 9 B6 PTA5 SWCLK PTA5 SWCLK FTM1_CH1 10 B5 PTA6 DISABLED PTA6 I2C0_SDA UART0_RX 11 C5 PTA7 DISABLED PTA7 I2C0_SCL UART0_TX 12 C6 VSS2/ VSSA VSS2/ VSSA VSS2/ VSSA 13 D6 VDD2/ VDDA VDD2/ VDDA VDD2/ VDDA 14 E6 PTB0/ RESET_b/ NMI_b RESET_b PTB0 IRQ NMI_b 15 D5 PTB1 DISABLED PTB1 ADCAD0 SBAR_IN0 16 E5 PTB2 DISABLED PTB2 ADCAD1 ACMP0_IN0 17 F6 PTB3 DISABLED PTB3 ADCAD2 ACMP0_IN1 18 E4 PTB4 DISABLED PTB4 ADCAD3 19 F5 VSS3 VSS3 VSS3 20 F4 VREFH VREFH VREFH 21 F3 VOUT_FB VOUT_FB VOUT_FB 23 F2 VOUT VOUT VOUT 24 F1 ISENS ISENS ISENS 25 E2 CLC1 CLC1 CLC1 26 D2 VLC VLC VLC 27 E1 GD GD GD 28 D1 VBOOT VBOOT VBOOT 29 C2 AD_IN AD_IN AD_IN 30 B2 AD_EN AD_EN AD_EN MWPR1516 16 KB Flash, Rev2, 1/2015. ALT0 ALT1 ALT2 ALT3 RESET_b 29 Freescale Semiconductor, Inc. Pinout 32 QFN 36 WLC SP Pin Name Default ALT0 31 C1 AC1 AC1 AC1 32 B1 AC2 AC2 AC2 ALT1 ALT2 ALT3 AC2 AC1 AD_EN AD_IN VBOOT GD VLC CLC1 32 31 30 29 28 27 26 25 5.2 Device pin assignment 21 VOUT_FB PTA1 5 20 VREFH PTA2 6 19 VSS3 PTA3 7 18 PTB4 PTA4 8 17 PTB3 PTA6 PTA5 16 4 PTB2 PTA0 15 NC PTB1 22 14 3 PTB0/RESET_b/NMI_b VSS1 13 VOUT VDD2/VDDA 23 12 2 VSS2/VSSA VDD1 11 ISENS PTA7 24 10 1 9 VREC Figure 12. 32-pin QFN package NOTE The NC pin must be floating, and do not tie it to the VDD or VSS. 30 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Ordering Parts 1 2 3 4 5 6 A VREC VDD1 VSS1 PTA2 PTA3 PTA4 A B AC2 AD_EN PTA0 PTA1 PTA6 PTA5 B C AC1 AD_IN VSS1 VSS1 PTA7 VSS2/ VSSA C D VBOOT VLC VDD1 VDD1 PTB1 VDD2/ VDDA D E GD CLC1 CLC2 PTB4 PTB2 PTB0/ RESET_b/ NMI_b E F ISENS VOUT VOUT_FB VREFH VSS3 PTB3 F 1 2 3 4 5 6 Figure 13. 36-pin WLCSP package 6 Ordering Parts 6.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: WPR1516. 7 Part Identification 7.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 7.2 Format Part numbers for this device have the following format: Q WPR## FFF R T PP N MWPR1516 16 KB Flash, Rev2, 1/2015. 31 Freescale Semiconductor, Inc. Terminology and guidelines 7.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Q Description Values Qualification status • M = Fully qualified, general market flow • P = Prequalification WPR family • WPR15 Program flash memory size • 16 = 16 KB R Silicon revision • (Blank) = Main • A = Revision after main T Temperature range (°C) • C = -40 to 85 °C Package identifier • FM=32 QFN (5 mm x 5 mm) • AL=36 WLCSP (3.1 mm x 3.0 mm) Packaging type • R = Tape and reel • (Blank) = Trays WPR## FFF PP N 7.4 Example This is an example part number: MWPR1516CFM 8 Terminology and guidelines 8.1 Definition: Operating requirement An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 Example This is an example of an operating requirement: 32 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Terminology and guidelines Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 8.2 Definition: Operating behavior Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 8.2.1 Example This is an example of an operating behavior: Symbol IWP Description Min. Digital I/O weak pullup/ 10 pulldown current Max. 130 Unit µA 8.3 Definition: Attribute An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 Example This is an example of an attribute: Symbol CIN_D Description Input capacitance: digital pins MWPR1516 16 KB Flash, Rev2, 1/2015. Min. — Max. 7 Unit pF 33 Freescale Semiconductor, Inc. Terminology and guidelines 8.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 8.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. 1.2 Unit V 8.5 Result of exceeding a rating Failures in time (ppm) 40 30 The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 20 10 0 Operating rating Measured characteristic 34 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Terminology and guidelines 8.6 Relationship between ratings and operating requirements .) ) ) g era Op g tin in rat in. (m in. t (m ax t (m n me g tin era Op e uir req en rem g( i g tin era Op u req g tin era Op in rat .) x ma Fatal range Degraded operating range Normal operating range Degraded operating range Fatal range Expected permanent failure - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Correct operation - No permanent failure - Possible decreased life - Possible incorrect operation Expected permanent failure –∞ ∞ Operating (power on) g lin nd Ha ng i rat .) ) in. (m ng li nd Ha i rat ng ax (m Fatal range Handling range Fatal range Expected permanent failure No permanent failure Expected permanent failure –∞ ∞ Handling (power off) 8.7 Guidelines for ratings and operating requirements Follow these guidelines for ratings and operating requirements: • Never exceed any of the chip’s ratings. • During normal operation, don’t exceed any of the chip’s operating requirements. • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8.8 Definition: Typical value A typical value is a specified value for a technical characteristic that: • Lies within the range of values specified by the operating behavior • Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. MWPR1516 16 KB Flash, Rev2, 1/2015. 35 Freescale Semiconductor, Inc. Terminology and guidelines 8.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. Max. 70 130 Unit µA 8.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 8.9 Typical value conditions Typical values assume you meet the following conditions (or other conditions as specified): 36 Freescale Semiconductor, Inc. MWPR1516 16 KB Flash, Rev2, 1/2015. Revision history Table 24. Typical value conditions Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 9 Revision history The following table provides a revision history for this document. Table 25. Revision history Rev. No. 2 Date 1/2015 MWPR1516 16 KB Flash, Rev2, 1/2015. Substantial Changes Initial public release. 37 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. ©2014-2015 Freescale Semiconductor, Inc. Document Number WPR1516 Revision 2, 1/2015