Exclusive Technology Feature ISSUE: October 2010 The Over-Power Phenomenon In DCM/CCM-Operated Flyback Converters (Part 1) by Christophe Basso, ON Semiconductor, Toulouse, France A flyback converter is usually designed to operate within a certain input-voltage range, characterized by a lowline and a high-line level. Between these two input voltages, the converter must be capable of delivering the nominal power for which it has been designed. To account for the unavoidable production tolerances, the engineer includes a certain margin in his calculations, ensuring the delivery of nominal power in worst-case situations such as low line and high temperature. If the adopted margin benefits the converter at low line, experience shows that the output-power capability of the converter may double under high-line conditions. In this article series, we will explore the origins of this excess power and explain how it can be controlled so that output power remains within a reasonable range. Operating Modes Of A Flyback Converter A flyback converter transmits power in two operating cycles. When the primary switch is closed, energy is absorbed from the input source and stored in the magnetizing inductor of the transformer, Lp. Because of the transformer’s winding configuration, the secondary-side diode is blocked, decoupling its downstream circuitry from the primary side. When the switch opens, the energy stored in the primary is transferred to the secondary side, producing a current that circulates in the output capacitor and the load. Fig. 1. depicts these events occurring during the on time (Fig. 1a) and the off time (Fig. 1b.) Ip 1: N D C Lp Is = 0 Vin 1: N Vout R D Lp Vin SW Vout C Ip R Is SW Ip a b Fig.1. The two operating states of a flyback converter show energy storage in the primary side (a) followed by energy circulation in the secondary side (b). Assuming 100% of the stored energy is transferred to the secondary side during a switching cycle, the primary inductor is fully demagnetized at the beginning of the next cycle. In this case, the converter is said to operate in the discontinuous-conduction mode (DCM): there is no current "memory" from the previous inductor state and the primary current ramps up from zero at the beginning of each switching cycle. On the other hand, if some energy remains in the transformer gap at the beginning of the next switching cycle, the inductor current no longer starts from zero but from an initial value known as the valley current (Ivalley). In that case, the converter is said to operate in the continuous-conduction mode (CCM). © 2010 How2Power. All rights reserved. Page 1 of 13 Exclusive Technology Feature If we plot idealized currents circulating in a CCM flyback converter during the on and off times of the primary switch, we see the waveforms presented in Fig. 2. When the switch turns on, the current in the inductor ramps up linearly with a slope equal to: Son = Vin Lp (1) If we operate in CCM, the value of the initial current in the inductor is not zero but the valley current. As the current ramps up and reaches a value Ipeak imposed by the controller, the switch turns off. To fight against the collapsing magnetic field, the voltage across the primary inductor reverses and the secondary-side diode now conducts: the current circulates in the secondary winding, supplying both the capacitor and the load. The current in the secondary side now decreases with a slope equal to: Soff = Vout + V f (2) Ls where Vf represents the diode’s forward drop; Vout, the output voltage; and Ls, the transformer’s secondary-side inductance. I p (t ) I peak ∆I L ( t ) I valley Vin L p (V out + Vf ) NL p t Is (t ) I peak N (V out + Vf ) Ls I valley N t ton Tsw toff Fig 2. In CCM, the current first ramps up in the primary side until the switch opens and transfers the stored energy to the secondary side. © 2010 How2Power. All rights reserved. Page 2 of 13 Exclusive Technology Feature If we could observe the magnetizing inductor current from the primary side during the off time, we would see the secondary downslope described by equation (2) but reflected on the primary side as: Soff = Vout + V f (3) NL p where N is the turns ratio linking the primary and the secondary windings. In Fig. 2., the inductor current swings between two values, Ivalley and Ipeak. The excursion between these points is called the ripple current and is defined by: ∆I L= I peak − I valley (4) In heavy CCM operation, the ripple current can be very small and the waveforms resemble a square-wave as Ivalley increases. When the load gets lighter, the converter transitions to DCM and the valley current vanishes to zero. The inductor ripple current is then maximum and corresponds to the full swing. The primary- and secondary-current waveforms are updated in Fig. 3 to illustrate DCM operation. I p (t ) I peak ∆I L ( t ) Vin L p (V out + Vf ) NL p t Is (t ) I peak N (V out + Vf ) Ls t ton Tsw toff Fig. 3. When the flyback converter operates in DCM, the inductor current ramps up from zero. © 2010 How2Power. All rights reserved. Page 3 of 13 Exclusive Technology Feature At a similar power level, the circulating ac currents in CCM are smaller than in DCM, leading to lower conduction losses in the first case. Mode transition occurs as a function of the load but also the input voltage. Usually, highpower converters are designed to operate in CCM at low line and enter DCM or light CCM at high line. Power Transfer In A DCM Flyback Converter What we need to calculate, now, is the amount of power transferred from the source to the output during a switching cycle. When the converter is supplied by a dc source Vin, the power delivered by the source is: T Pin 1 sw = I in ( t )Vin ( t ) dt Vin I in , avg Tsw ∫0 (5) By looking at the upper waveform in Fig. 2., we can see that the average input current equals: ∆I L ton I peak + I valley + = I in , avg = I ton Fsw valley 2 Tsw 2 (6) Knowing the primary inductor slope from equation (1), we can obtain a definition for the ripple current ∆IL: V ∆I L =in ton Lp (7) Combining equations (4) and (7), we can extract a definition for the on time: ton = (I peak − I valley ) Lp (8) Vin Substituting equation (8) into (6), we have: I in , avg = (I peak + I valley ) ( I peak − I valley ) 2 Vin L p Fsw (9) If we now multiply both sides of the equation by Vin and re-arrange the expression: = Pin 1 L p ( I peak 2 − I valley 2 ) Fsw 2 (10) This equation describes the power absorbed from the source by a flyback converter operated in CCM. Should the converter operate in DCM, the valley current would drop to zero, simplifying the expression to: Pin = 1 L p I peak 2 Fsw 2 (11) The transmitted output power, available to the load on the secondary side, is simply the absorbed power affected by the overall efficiency, η (eta). = Pout 1 L p ( I peak 2 − I valley 2 ) Fswη 2 © 2010 How2Power. All rights reserved. (12) Page 4 of 13 Exclusive Technology Feature Effect Of Propagation Delay On Maximum Output-Power Level In a current-mode-controlled power supply, the feedback loop adjusts the primary-inductor peak current on a cycle-by-cycle basis as a function of the input/output parameters. In a classical arrangement, a sense resistor converts the primary current into a voltage that is then applied to the current-sense pin of the selected controller. However, there are some situations where the feedback loop is lost, e.g. in output short circuits, at start-up or when the optocoupler is destroyed. In these fault conditions, it is important to keep the acceptable peak current within safe limits. A high peak current could cause transformer saturation, clamping voltage runaway, and possibly smoke. For this reason, it is common to find an internal clamp in the pulse-width modulation (PWM) controller that limits the current-setpoint excursion. As an example, consider the UC384X controller family, which contains a clamp that is set to 1 V. Because of this clamp, the maximum voltage developed on the current-sense resistor can never exceed 1 V, which would correspond to 1 A flowing through a 1-Ω resistor. In the new NCP1250 from ON Semiconductor, this voltage limit has been reduced to 0.8 V, ensuring a slight increase in the converter’s overall efficiency. Fig. 4. depicts the internal implementation of such a circuit. PWM reset 5.3V Skip CS 20 kΩ 2 C7 FB 64 kΩ 300 mV CS LEB 20 kΩ 0.8 V From OPP 3 Rsense Fig. 4. The maximum peak current is set by the 0.8-V reference voltage. In Fig. 4., the feedback voltage reaches the current setpoint after voltage division by a factor of 4.2. In case of loop failure, the feedback voltage jumps to 5.3 V but thanks to the 0.8-V active Zener diode, the current setpoint cannot exceed the following value: = I peak ,max Vsense ,max 0.8 = Rsense Rsense (13) At least, that is the current limit in theory. Unfortunately, the reality is different as illustrated by Fig. 5. © 2010 How2Power. All rights reserved. Page 5 of 13 Exclusive Technology Feature = I peak I peak ,max + ∆I peak , HL I peak ,max Vin ,max Lp t prop 0.8 Rsense S= I Lp ( t ) Vin Lp High line ∆I peak , LL The PWM latch is reset here Low line tdel PWM reset signal VGS ( t ) Gate-source signal t prop Fig. 5. When an overcurrent condition is detected, it takes a certain amount of time before the controller acknowledges the fault and propagates the turn-off signal to the MOSFET gate. In this picture, we can see the current level growing and reaching the maximum value imposed by equation (13). We would expect the comparator to immediately react, however, this device is affected by a response time. Before the reset order reaches the latch and instructs the driver output to go low, a certain amount of time elapses. Furthermore, even when the controller drive pin goes to ground, there will still be an additional delay in the propagation of this drive signal to the MOSFET gate. This second delay is due to the resistive elements in the path from the controller to the MOSFET. During this period of delays, the inductor current keeps increasing according to the slope defined by equation (1). When the MOSFET eventually opens, the current has reached a peak defined by: I= peak ,max Vsense ,max Rsense + Vin t prop Lp (14) As the equation indicates, the variable part depends on the input voltage. At low line, there is a slight current overshoot that barely affects the maximum delivered power before the controller protection trips. On the other hand, in high-line conditions, the overshoot can be quite large, particularly if the driver sink capability is weak and large-QG MOSFETs are selected. If we calculate the percentage of maximum peak-current increase from low line (LL) to high line (HL), we can show that the equation is: I peak ,max, HL − I peak ,max, LL I peak ,max, LL = Vin , HL − Vin , LL L pVsense ,max + Vin , LL t prop Rsense © 2010 How2Power. All rights reserved. (15) Page 6 of 13 Exclusive Technology Feature where Vin , HL Vin , LL is the dc input voltage high line, 370 V is the dc input voltage low line, 120 V Lp is the transformer primary inductor, 200 µH tprop is the total propagation delay, 350 ns Rsense is the sense resistor, 0.33 Ω Vsense is the maximum authorized sense value, 0.8 V If we use the above values, which were derived for a universal mains 30-W DCM-adapter featuring an NCP1250, we have a peak current with a variation from low to high line of: ∆I peak = I peak ,max, LL 370 − 120 = 0.166 or 16.6% 200u × 0.8 + 120 350n × 0.33 (16) Practically speaking, if the low-line maximum current is: I peak ,max, LL = 0.8 120 + × 350n = 2.63A 0.33 200u (17) It increases under high-line conditions to: ∆I peak I peak ,max, HL =I peak ,max, LL 1 + I peak , max, LL =2.63 × 1.166 =3.07 A (18) As a first rough calculation, the extra power available at high line in DCM can thus be quickly extrapolated from equation (16) via (11): ∆I peak ∆Pout = 1 + Pout , LL I peak ,max, LL 2 1.1662 ≈ 36% = (19) However, in this approach, we considered a constant 100% efficiency between low and high-line conditions. In reality, the efficiency at high line is always slightly greater than that of low line. That’s because as the dutyratio decreases, the rms values of the circulating currents also decrease, naturally reducing the associated losses. If we now include the efficiency change in our calculations, we can express the maximum power at low and high lines in a fault condition (the feedback is lost and the internal 0.8-V clamp is activated.) The equations for maximum power are: Pout , LL = 1 L p I peak ,max, LL 2 Fswη LL 2 (20) Pout , HL = 1 L p I peak ,max, HL 2 Fswη HL 2 (21) © 2010 How2Power. All rights reserved. Page 7 of 13 Exclusive Technology Feature If we calculate the power difference between low and high line and compare it to that of low line, we have: I peak ,max, HL 2η HL ∆Pout = −1 Pout , LL I peak ,max, LL 2η LL (22) Considering the respective low- and high-line efficiency numbers of 85% and 89% calculated for the 30-W adapter example, we can refine the previous calculations: ∆Pout 3.07 2 × 0.89 = = − 1 42% Pout , LL 2.632 × 0.85 (23) From equation (20), the maximum power output at low line is estimated to be: 1 Pout , LL = L p I peak ,max, LL 2 Fswη LL = 0.5 × 200u × 2.632 × 65k × 0.85 ≈ 38 W 2 (24) According to equation (23), the high-line power will rise to: Pout ,max, HL =Pout ,max, LL ∆Pout 38 × 1.42 = 54 W = Pout , LL (25) If our example adapter has an output voltage equal to 19 V (which is common), the maximum current circulating in the output diode can differ significantly between low- and high-line operating conditions: I out ,max, = LL Pmax, LL 38 = = 2A 19 Vout (26) I out ,max, HL = Pmax, HL 54 = = 2.8 A 19 Vout (27) Why Limit the Maximum Power? First, let’s consider the output diode. Having a high-line current much larger than the nominal current forces you to oversize the diode or its associated heatsink. It comes at a cost and size/volume increase of course. Second, there’s a compliance issue. In safety document IEC950 [1], the section on Limited Power Sources (LPS) describes a certification for maximum output-power limit. Table 1 describes the maximum power that can be delivered by a power supply fulfilling the LPS requirements. Table 1. Maximum power capability of LPS-compliant power supplies. Output Voltage Output Current Vout ( V ) Apparent Power I out ( A ) S ( VA ) Vrms Vdc ≤ 20 ≤ 20 ≤8 ≤ 5 ⋅ Vout 20 < Vout ≤ 30 20 < Vout ≤ 30 ≤8 ≤ 100 - 20 < Vout ≤ 60 ≤ 150 Vout ≤ 100 © 2010 How2Power. All rights reserved. Page 8 of 13 Exclusive Technology Feature If a power supply manufacturer can show the compliance of his converter with the LPS test, the manufacturer may use less expensive materials for the enclosure. In our example, a 19-V adapter can comply with the LPS definition if its output current is less than 8 A and its maximum power in fault condition stays below 5 x 19, or 95 W. Despite a power runaway at high line, our 30-W adapter does not exceed the LPS limit. Provided the diode can accept the extra current, no special precautions are needed. The problem becomes more challenging with higher-power adapters. How Do We Limit Maximum Power? In our explanation, we saw that the culprit for this extra power is the primary peak-current runaway at high line. For the typical example reflected in equation (16), the difference amounts to almost 17%. A solution to this problem is to reduce the maximum peak-current limit as a function of the input voltage as shown in Fig. 6 (graph on right). At low line, the current limit is unchanged, but as the input voltage grows, the peak current limit is gradually reduced. The final peak-current value could be selected so that the high-line output power roughly matches the low-line level. This technique is called over-power protection or OPP. I peak I peak ,max = f (Vin ) I peak ,max I peak I peak , LL I peak , HL Vin Vin HL LL LL HL Fig. 6. One approach to implementing over-power protection is to limit the peak current as a function of input voltage. To calculate the required peak current limit we must impose at high line, one option is to check what value of this parameter would force the high-line power to equal the low-line power. As our converter operates in DCM over the full range, we can formulate this requirement as follows: 1 1 L p ( I peak ,max, LL 2 ) Fswη LL = L p ( I peak ,max, HL 2 ) Fswη HL 2 2 (28) Extracting the peak-current definition, we obtain: I peak ,max, HL = 2 Pmax, LL (29) L p Fswη HL However, this value corresponds to the final peak current seen by the transformer inductor at high line. The current sensed by the controller on its dedicated pin (scaled in voltage by the sense resistor) must then reflect the propagation delay contribution that appears in equation (14): I sense ,max, HL = I peak ,max, HL − Vin , HL Lp t prop = 2 Pmax, LL L p Fswη HL − Vin , HL Lp t prop © 2010 How2Power. All rights reserved. (30) Page 9 of 13 Exclusive Technology Feature If we use the numerical values given previously and want our power supply delivering 38 W at high line, then applying equation (30) leads us to the following current sensed by the controller: = I sense ,max, HL 2 × 38 370 −= × 350n 1.927 A 200u × 65k × 0.85 200u (31) Given the usage of a 0.33-Ω resistor, the corresponding voltage sensed by the controller dedicated pin will be: Vsense ,max, HL = I sense ,max, HL Rsense = 1.927 × 0.33 = 636 mV (32) In the NCP1250, the maximum sensed voltage is limited to 0.8 V. To reduce this level down to what equation (32) recommends, we must subtract 164 mV from 0.8 V. There are several options to implement peak-current reduction at high line. Two of these options are illustrated in Fig. 7. I ( Lp ) I peak ,max ∆I L , HL ∆I L , LL Offset generation t I ( Lp ) I peak ,max, LL ∆I L , LL ∆I L , HL Clamp reduction I peak ,max, HL High line t Fig. 7. The reduction in the peak-current limit at high line can be obtained by either offsetting the current-sense signal (top graph) or by reducing the internal clamping value (bottom graph). In one approach, an offset is added to the current-sense voltage information. If the offset builds up with the growing input voltage, the available current shrinks dynamically, leading to the expected result. This technique is illustrated in the upper graph of Fig. 7. A possible implementation of the offset method appears in Fig. 8. Experience shows that the obtained results are good and fit the bill in terms of peak-current reduction. However, the permanent presence of the OPP resistors connected to the bulk rail affects the standby power dramatically. Not only is there extra power dissipation in the resistors, there are also additional losses under light or no-load conditions because the permanent offset disturbs skip-cycle operations. © 2010 How2Power. All rights reserved. Page 10 of 13 Exclusive Technology Feature Bulk ROPP1 Q1 DRV ROPP 2 CS R1 C1 Rsense Fig. 8. By generating an offset from the bulk capacitor to the current sense pin, we can create a variable offset affecting the maximum output power of the converter. The lower section of Fig. 7 represents another way of reaching the goal. The ground level is no longer affected, but the maximum allowed value of peak inductor current is reduced as the input voltage rises. This is the technique implemented in the NCP1250 using a new circuit developed by ON Semiconductor. This circuit limits the maximum output power as effectively as the offset-generation technique but without the extra power dissipation associated with that technique. Furthermore, with the alternative method implemented in the NCP1250 (whose technical details appear in Fig. 9), the skip cycle is not affected. © 2010 How2Power. All rights reserved. Page 11 of 13 Exclusive Technology Feature 800 mV on off PWM reset off 0 300-ns blank 0 on 600 mV -200 mV OPP CS + 1 ROPPU . Aux. ROPPL 4 0.8 V 0.8 V Fig. 9. Sensing the auxiliary winding of the flyback converter during the on time is an excellent way to obtain an image of the input voltage without incurring additional power dissipation. The auxiliary winding of the flyback converter swings to -NVin during the on time. This negative voltage is thus representative of the input-voltage variations. If we scale it down via a resistive divider consisting of ROPPU and ROPPL, we can directly sum it with the internal positive 0.8-V reference voltage used for the active clamp. With this adopted technique, we can easily reduce the maximum clamping voltage down to 450 mV. Final Results For OPP Implementation Using the 30-W DCM adapter values, we have entered the formulas we derived in Mathcad and plotted the power variations with and without OPP implementation. In the calculations, the efficiency varies linearly from 85% to 89%. The results appear in Fig. 10. 70 63 W 60 Pout ( W ) 50 46 W 40 100 ∆Pout = 4W 46 W 42 W 200 300 Vin ( V ) 400 Fig. 10. OPP implementation clearly improves the output-power limiting of the flyback converter. © 2010 How2Power. All rights reserved. Page 12 of 13 Exclusive Technology Feature Owing to a linear variation of the compensation level, the delivered power stays within control. It does not exceed 4 W between the two input-voltage extremes. This nondissipative OPP technique has also been implemented in a high-voltage switcher, the NCP1027. Conclusion In this first part of this article, we have explained why a flyback converter operated in the discontinuous conduction mode can deliver more power at high line than at low line. With moderate power adapters, this extra power is not detrimental to converter operation. However, when adapters of higher power levels must comply with the Limited Power Source specifications, it is important to understand the phenomenon at play and minimize its impacts on final performance. Two compensation techniques have been disclosed. The second technique is implemented in the NCP1250 and offers excellent performance without increasing power dissipation. References UL60950-1, Information Technology Equipment – Safety – Part 1: General Requirements. About the Author Christophe Basso is an application engineering director at ON Semiconductor in Toulouse, France. He has originated numerous integrated circuits among which the NCP120X series has set new standards for low standby power converters. SPICE simulation is also one of his favorite subjects and he authored a second book, “Switch-Mode Power Supplies: SPICE Simulations and Practical Designs”, published by McGraw-Hill in 2008. His work was positively reviewed in several magazines and in a recent PELS newsletter. Christophe holds a BSEE-equivalent from the Montpellier University, France and a MSEE from the Institut National Polytechnique de Toulouse, France. He holds 17 patents on power conversion and often publishes papers in conferences and trade magazines. For further reading on power protection, see the How2Power Design Guide, search the Design Area category and select Power Protection as the subcategory. © 2010 How2Power. All rights reserved. Page 13 of 13