NCP1340 D

NCP1340
Product Preview
High-Voltage,
Quasi-Resonant, Controller
Featuring Valley Lock-Out
Switching
The NCP1340 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line power
converters. With an integrated active X2 capacitor discharge feature,
the NCP1340 can enable no−load power consumption below 30 mW.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 6th valley and transitions to a
frequency foldback mode to reduce switching losses. As the load
decreases further, the NCP1340 enters quiet−skip mode to manage the
power delivery.
To help ensure converter ruggedness, the NCP1340 implements
several key protective features such as internal brownout detection, a
non−dissipative Over Power Protection (OPP) for constant maximum
output power regardless of input voltage, a latched over voltage and
NTC−ready overtemperature protection through a dedicated pin, and
line removal detection to safely discharge the X2 capacitors when the
line is removed.
If transient load capability is desired, the NCP1341 offers the same
performance and features with the addition of power excursion mode
(PEM).
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated High−Voltage Startup Circuit with Brownout Detection
Integrated X2 Capacitor Discharge Capability
Wide VCC Range from 9 V to 28 V
28 V VCC Overvoltage Protection
Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Saturation Detection
Internal Temperature Shutdown
Valley Switching Operation with Valley−Lockout for Noise−Free
Operation
Frequency Foldback with 25 kHz Minimum Frequency Clamp for
Increased Efficiency at Light Loads
Skip Mode with Quiet−Skip Technology for Highest Performance
During Light Loads
Minimized Current Consumption for No Load Power Below 30 mW
Frequency Jittering for Reduced EMI Signature
Latching or Auto−Recovery Timer−Based Overload Protection
Adjustable Overpower Protection
Fixed or Adjustable Maximum Frequency Clamp
Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
4−ms Soft−Start Timer
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8
9
1
1
SOIC−9 NB
D SUFFIX
CASE 751BP
SOIC−8 NB
D SUFFIX
CASE 751
MARKING DIAGRAM
9
1340xz
ALYW
G
1
1340xz
x
z
A
L
Y
W
G
= Specific Device Code
= A or B
= 1, 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
1
HV
Fault
FMAX
FB
ZCD/OPP
CS
VCC
DRV
GND
1
HV
Fault
FB
VCC
ZCD/OPP
DRV
GND
CS
(Top Views)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. P1
1
Publication Order Number:
NCP1340/D
NCP1340
TYPICAL APPLICATION SCHEMATIC
Figure 1. NCP1340 8−Pin Typical Application Circuit
Figure 2. NCP1340 9−Pin Typical Application Circuit
Table 1. ORDERABLE PART NUMBERS
Device Marking
Pins
Fault
Pin
FMAX
Pin
PEM
Fault/Overload
Protection
Frequency
Clamp
NCP1340B1DR2G
1340B1
8
Yes
No
No
Auto−Restart
None
NCP1340B3D1R2G
1340B3
9
Yes
Yes
No
Auto−Restart
Adjustable
Ordering Code
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2
NCP1340
FUNCTIONAL BLOCK DIAGRAM
Figure 3. NCP1340 Block Diagram
Table 2. PIN FUNCTIONAL DESCRIPTION
8−Pin
9−Pin
Pin Name
Function
1
1
Fault
The controller enters fault mode if the voltage on this pin is pulled above or below the fault
thresholds. A precise pull up current source allows direct interface with an NTC thermistor.
−
2
FMAX
A resistor to ground sets the value for the maximum switching frequency clamp. If this pin is
pulled above 4 V, the maximum frequency clamp is disabled.
2
3
FB
3
4
ZCD/OPP
4
5
CS
5
6
GND
Ground reference.
6
7
DRV
This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs.
7
8
VCC
This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17 V and
turns off when VCC goes below 9 V (typical values). After start−up, the operating range is 9 V up
to 28 V.
−
9
N/C
Removed for creepage distance.
8
10
HV
This pin is the input for the high voltage startup and brownout detection circuits. It also contains
the line removal detection circuit to safely discharge the X2 capacitors when the line is removed.
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
A resistor divider from the auxiliary winding to this pin provides input to the demagnetization detection comparator and sets the OPP compensation level.
Input to the cycle−by−cycle current limit comparator.
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3
NCP1340
Table 3. MAXIMUM RATINGS
Rating
Symbol
Value
High Voltage Startup Circuit Input Voltage
VHV(MAX)
−0.3 to 700
V
High Voltage Startup Circuit Input Current
IHV(MAX)
20
mA
Supply Input Voltage
VCC(MAX)
−0.3 to 30
V
Supply Input Current
ICC(MAX)
30
mA
Supply Input Voltage Slew Rate
dVCC/dt
1
V/ms
Fault Input Voltage
VFault(MAX)
−0.3 to TBD
V
Fault Input Current
IFault(MAX)
10
mA
Zero Current Detection and OPP Input Voltage
VZCD(MAX)
−0.3 to VCC + 0.7 V
V
Zero Current Detection and OPP Input Current
IZCD(MAX)
−2/+5
mA
Maximum Input Voltage (Other Pins)
VMAX
−0.3 to TBD
V
Maximum Input Current (Other Pins)
IMAX
10
mA
Feedback Input Voltage
VFB
−0.3 to TBD
V
Feedback Input Current
Driver Maximum Voltage (Note 1)
Driver Maximum Current
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (TA = 25°C, 1 Oz Cu, 0.155 Sq Inch Printed Circuit Copper Clad)
TBD Suffix, Plastic Package TBD (SOIC−9)
Thermal Resistance, Junction to Ambient 1 Oz Cu Printed Circuit Copper Clad)
TBD Suffix, Plastic Package TBD (SOIC−9)
ESD Capability (Note 5)
Human Body Model per JEDEC Standard JESD22−A114E.
Machine Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
Unit
IFB
10
mA
VDRV
−0.3 to VDRV(high)
V
IDRV(SRC)
IDRV(SNK)
500
800
mA
TJ
−40 to 125
°C
TSTG
–60 to 150
°C
PD(MAX)
W
TBD
°C/W
R JA
TBD
V
2000
200
2000
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, VDRV(high), when VCC exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is VCC.
2. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
3. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.
4. Low Conductivity Board. As mounted on 80 x 100 x 1.5 mm FR4 substrate with a single layer of 50 mm2 of 2 oz copper trances and heat
spreading area. As specified for a JEDEC51−1 conductivity test PCB. Test conditions were under natural convection of zero air flow.
5. HV Pin is rated to the maximum voltage of the part, or 700 V.
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4
NCP1340
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
VCC(on)
17.0
18.0
9.0
–
5.5
0.70
18.0
19.0
9.5
–
7.5
1.05
Unit
START−UP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Discharge Voltage During Line Removal
Minimum Operating Voltage
Operating Hysteresis
Internal Latch / Logic Reset Level
Transition from Istart1 to Istart2
dV/dt = 0.1 V/ms
VCC increasing
VCC decreasing
VCC decreasing
VCC(on) − VCC(off)
VCC decreasing
VCC increasing, IHV = 650 mA
VCC(X2_reg)
VCC(off)
VCC(HYS)
VCC(reset)
VCC(inhibit)
16.0
17.0
8.5
7.5
4.5
0.40
VCC(off) Delay
VCC decreasing
tdelay(VCC_off)
–
30.0
–
ms
Startup Delay
Delay from VCC(on) to DRV Enable
tdelay(start)
–
–
500
ms
VHV(MIN)
–
–
40
V
Vcc = 0 V
Istart1
0.2
0.5
0.65
mA
Start−Up Current Sourced from VCC Pin
Vcc = Vcc(on) – 0.5 V
Istart2
2.4
3.75
5.0
mA
Start−Up Circuit Off−State Leakage Current
VHV = 162.5 V
VHV = 325 V
VHV = 700 V
IHV(off1)
IHV(off2)
IHV(off3)
–
–
–
–
–
–
15
20
50
mA
VCC = VCC(on) – 0.5 V
VFB = 0 V
fsw = 50 kHz, CDRV = open
ICC1
ICC2
ICC3
0.075
0.185
0.5
0.115
0.230
1.0
0.150
0.315
1.5
VCC(OVP)
27
28
29
V
tdelay(VCC_OVP)
–
30.0
–
ms
tline(removal)
65
100
135
ms
tline(discharge)
21
32
43
ms
tline(detect)
21
32
43
ms
Minimum Voltage for Start−Up Current
Source
Inhibit Current Sourced from VCC Pin
Supply Current
Fault or Latch
Skip Mode (excluding FB current)
Operating Current
V
mA
VCC Overvoltage Protection Threshold
VCC Overvoltage Protection Delay
X2 CAPACITOR DISCHARGE
Line Voltage Removal Detection Timer
Discharge Timer Duration
Line Detection Timer Duration
VCC Discharge Current
VCC = 20 V
HV Discharge Level
ICC(discharge)
13
18
23
mA
VHV(discharge)
–
–
30
V
BROWNOUT DETECTION
System Start−Up Threshold
VHV increasing
VBO(start)
107
112
116
V
Brownout Threshold
VHV decreasing
VBO(stop)
93
98
102
V
Hysteresis
VHV increasing
VBO(HYS)
9.0
14
–
V
Brownout Detection Blanking Time
VHV decreasing
tBO(stop)
40
70
100
ms
Rise Time
VDRV from 10% to 90%
tDRV(rise)
–
40
80
ns
Fall Time
VDRV from 90% to 10%
tDRV(fall)
–
20
60
ns
IDRV(SRC)
IDRV(SNK)
–
–
500
800
–
–
GATE DRIVE
Current Capability
Source
Sink
mA
High State Voltage
VCC = VCC(off) + 0.2 V, RDRV = 10 kW
VCC = 30 V, RDRV = 10 kW
VDRV(high1)
VDRV(high2)
8.0
10
–
12
–
14
V
Low Stage Voltage
VFault = 0 V
VDRV(low)
–
–
0.25
V
VFB(open)
4.9
5.0
5.1
V
KFB
−
4
−
–
RFB
350
400
420
kW
FEEDBACK
Open Pin Voltage
VFB to Internal Current Setpoint Division
Ratio
Internal Pull−Up Resistor
VFB = 0.4 V
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5
NCP1340
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
IFB
92
100
108
mA
V1to2
V2to3
V3to4
V4to5
V5to6
V6to5
V5to4
V4to3
V3to2
V2to1
1.316
1.128
1.034
0.940
0.846
1.410
1.504
1.598
1.692
1.880
1.400
1.200
1.100
1.000
0.900
1.500
1.600
1.700
1.800
2.000
1.484
1.272
1.166
1.060
0.954
1.590
1.696
1.802
1.908
2.120
100
300
60
110
360
75
120
420
85
VFMAX(mode)
3.85
4.00
4.15
V
IFMAX
9.0
10
11
mA
ton(MAX)
28
32
40
ms
FEEDBACK
Internal Pull−Up Current
Valley Thresholds
Transition from 1st to 2nd valley
Transition from 2nd to 3rd valley
Transition from 3rd to 4th valley
Transition from 4th to 5th valley
Transition from 5th to 6th valley
Transition from 6th to 5th valley
Transition from 5th to 4th valley
Transition from 4th to 3rd valley
Transition from 3rd to 2nd valley
Transition from 2nd to 1st valley
Maximum Frequency Clamp
Versions x2
Versions x3
Versions x3
FMAX Secondary Mode Threshold
V
VFB decreasing
VFB decreasing
VFB decreasing
VFB decreasing
VFB decreasing
VFB increasing
VFB increasing
VFB increasing
VFB increasing
VFB increasing
fMAX
VFMAX = 0.7 V
VFMAX = 3.5 V
9−Pin Versions Only
FMAX Pin Source Current
Maximum On Time
kHz
DEMAGNETIZATION INPUT
ZCD threshold voltage
VZCD decreasing
VZCD(trig)
35
55
90
mV
ZCD hysteresis
VZCD increasing
VZCD(HYS)
15
35
55
mV
VZCD step from 4.0 V to −0.3 V
tdemag
–
150
250
ns
IQZCD = 5.0 mA
IQZCD = −2.0 mA
VZCD(MAX)
VZCD(MIN)
12.4
−0.9
12.7
−0.7
13
0
tZCD(blank)
2.25
3.0
3.75
ms
While in soft−start
After soft−start complete
t(tout1)
t(tout2)
80
5.1
100
6.0
120
6.9
ms
Detects open pin fault.
IZCD
–
1.0
–
mA
Current Limit Threshold Voltage
VCS increasing
VILIM1
0.760
0.800
0.840
V
Leading Edge Blanking Duration
DRV minimum width minus
tdelay(ILIM1)
tLEB1
220
275
330
ns
Step VCS 0 V to VILIM1 + 0.5 V,
VFB = 4 V
tdelay(ILIM1)
–
125
175
ns
Step VCS 0 V to 0.7 V, VFB = 2.4
tdelay(PWM)
–
125
175
ns
Vfreeze
170
200
230
mV
Demagnetization Propagation Delay
ZCD Clamp Voltage
Positive Clamp
Negative Clamp
V
Blanking Delay After Turn−Off
Timeout After Last Demagnetization
Detection
Pull−Up Current Source for ZCD Open
Detection
CURRENT SENSE
Current Limit Threshold Propagation Delay
PWM Comparator Propagation Delay
Minimum Peak Current Freeze Setpoint
CURRENT SENSE
Abnormal Overcurrent Fault Threshold
VCS increasing, VFB = 4 V
VILIM2
1.125
1.200
1.275
V
Abnormal Overcurrent Fault Blanking
Duration
DRV minimum width minus
tdelay(ILIM2)
tLEB2
90
120
150
ns
Step VCS 0 V to VILIM2 + 0.5 V,
VFB = 4 V
tdelay(ILIM2)
–
125
175
ns
nILIM2
–
4
–
kOPP(MAX)
–
31.25
–
Abnormal Overcurrent Fault Propagation
Delay
Number of Consecutive Abnormal Overcurrent Faults to Enter Latch Mode
Maximum OPP Reduction
VZCD = −250 mV, VFB = 4 V
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6
%
NCP1340
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VCS dv/dt = 1 V/ms, measured from
VOPP(MAX) to DRV falling edge
tOPP(delay)
–
125
175
ns
tOPP(blank)
100
120
200
ns
ICS
0.7
1.0
1.5
mA
Jitter Frequency
fjitter
1.0
1.3
1.6
kHz
Peak Jitter Voltage Added to PWM
Comparator
Vjitter
90
100
110
mV
tSSTART
2.8
4.0
5.0
ms
CURRENT SENSE
Overpower Protection Delay
Overpower Signal Blanking Delay
Pull−Up Current Source
VCS = 1.5 V
JITTERING
FAULT PROTECTION
Soft−Start Period
Flyback Overload Fault Timer
Overvoltage Protection (OVP) Threshold
Measured from
1st DRV pulse to VCS = VILIM1
VCS = VILIM1
tOVLD
120
160
200
ms
VFault increasing
VFault(OVP)
2.79
3.00
3.21
V
OVP Detection Delay
VFault increasing
tdelay(OVP)
–
30.0
–
ms
Overtemperature Protection (OTP) Threshold
(Note 6)
VFault decreasing
VFault(OTP_in)
0.38
0.40
0.42
V
Overtemperature Protection (OTP) Exiting
Threshold (Note 6)
VFault increasing
Versions B Only
VFault(OTP_out)
0.874
0.920
0.966
V
VFault decreasing
tdelay(OTP)
–
30.0
–
ms
VFault = VFault(OTP_in) + 0.2 V
IOTP
42.5
45.5
48.5
mA
Fault Input Clamp Voltage
VFault(clamp)
1.15
1.7
2.25
V
Fault Input Clamp Series Resistor
RFault(clamp)
1.32
1.55
1.78
kW
trestart
1.7
2.0
2.3
S
fMIN
23.5
25
27.5
kHz
tDT(1)
tDT(2)
tDT(3)
–
−
32
0
18
−
–
−
−
ms
tquiet
1250
−
−
ms
OTP Detection Delay
OTP Pull−Up Current Source
Autorecovery Timer
LIGHT/NO LOAD MANAGEMENT
Minimum Frequency Clamp
Dead−Time Added During Frequency
Foldb ack
VFB = 800 mV
VFB = 600 mV
VFB = 400 mV
Quiet−Skip Timer
Skip Threshold
VFB decreasing
Vskip
350
400
450
mV
Skip Hysteresis
VFB increasing
Vskip(HYS)
−
50
−
mV
Thermal Shutdown
Temperature increasing
TSHDN
–
140
–
°C
Thermal Shutdown Hysteresis
Temperature decreasing
TSHDN(HYS)
–
40
–
°C
tdelay(TSHDN)
–
30
–
ms
THERMAL PROTECTION
Thermal Shutdown Delay
6. NTC with R110 = 8.8 kW
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NCP1340
INTRODUCTION
The NCP1340 implements a quasi−resonant flyback
converter utilizing current−mode architecture where the
switch−off event is dictated by the peak current. This IC is
an ideal candidate where low parts count and cost
effectiveness are the key parameters, particularly in ac−dc
adapters, open−frame power supplies, etc. The NCP1340
incorporates all the necessary components normally needed
in modern power supply designs, bringing several
enhancements such as non−dissipative overpower
protection (OPP), brownout protection, and frequency
reduction management for optimized efficiency over the
entire power range. Accounting for the needs of extremely
low standby power requirements, the controller features
minimized current consumption and includes an automatic
X2 capacitor discharge circuit that eliminates the need to
install power−consuming resistors across the X2 input
capacitors.
• High−Voltage Start−Up Circuit: Low standby power
consumption cannot be obtained with the classic
resistive start−up circuit. The NCP1340 incorporates a
high−voltage current source to provide the necessary
current during start−up and then turns off during normal
operation.
• Internal Brownout Protection: The ac input voltage is
sensed via the high−voltage pin. When this voltage is
too low, the NCP1340 stops switching. No restart
attempt is made until the ac input voltage is back within
its normal range.
• X2−Capacitor Discharge Circuitry: Per the
IEC60950 standard, the time constant of the X2 input
capacitors and their associated discharge resistors must
be less than 1 s in order to avoid electrical shock when
the user unplugs the power supply and inadvertently
touches the ac input cord terminals. By providing an
automatic means to discharge the X2 capacitors, the
NCP1340 eliminates the need to install X2 discharge
resistors, thus reducing power consumption.
• Quasi−Resonant, Current−Mode Operation:
Quasi−Resonant (QR) mode is a highly efficient mode
of operation where the MOSFET turn−on is
synchronized with the point where its drain−source
voltage is at the minimum (valley). A drawback of this
mode of operation is that the operating frequency is
inversely proportional to the system load. The
NCP1340 incorporates a valley lockout (VLO) and
frequency foldback technique to eliminate this
drawback, thus maximizing the efficiency over the
entire power range.
• Valley Lockout: In order to limit the maximum
frequency while remaining in QR mode, one would
traditionally use a frequency clamp. Unfortunately, this
can cause the controller to jump back and forth between
two different valleys, which is often undesirable. The
•
•
•
•
•
•
•
NCP1340 patented VLO circuitry solves this issue by
determining the operating valley based on the system
load, and locking out other valleys unless a significant
change in load occurs.
Frequency Foldback: As the load continues to
decrease, it becomes beneficial to reduce the switching
frequency. When the load is light enough, the NCP1340
enters frequency foldback mode. During this mode, the
peak current is frozen and dead−time is added to the
switching cycle, thus reducing the frequency and
switching operation to discontinuous conduction mode
(DCM). Dead−time continues to be added until skip
mode is reached, or the switching frequency reaches its
minimum level of 25 kHz.
Skip Mode: To further improve light or no−load power
consumption while avoiding audible noise, the
NCP1340 enters skip mode when the operating
frequency reaches its minimum value. foldback isavoid
acoustic noise, the circuit prevents the switching
frequency from decaying below 25 kHz. This allows
regulation via burst of pulses at 25 kHz or greater
instead of operating in the audible range.
Quiet−Skip: To further reduce acoustic noise, the
NCP1340 incorporates a novel circuit to prevent the
skip mode burst period from entering the audible range
as well.
Internal OPP: In order to limit power delivery at high
line, a scaled version of the negative voltage present on
the auxiliary winding during the on−time is routed to
the ZCD/OPP pin. This provides the designer with a
simple and non−dissipative means to reduce the
maximum power capability as the bulk voltage
increases.
Frequency Jittering: In order to reduce the EMI
signature, a low frequency triangular voltage waveform
is added to the iniput of the PWM comparator. This
helps by spreading out the energy peaks during noise
analysis.
Internal Soft−Start: The NCP1340 includes a 4 ms
soft−start to prevent the main power switch from being
overly stressed during start−up. Soft−start is activated
each time a new startup sequence occurs or during
auto−recovery mode.
Dedicated Fault Input: The NCP1340 includes a
dedicated fault input. It can be used to sense an
overvoltage condition and latch off the controller by
pulling the pin above the overvoltage protection (OVP)
threshold. The controller is also disabled if the Fault pin
is pulled below the overtemperature protection (OTP)
threshold. The OTP threshold is configured for use with
a NTC thermistor.
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NCP1340
• Overload/Short−Circuit Protection: The NCP1340
•
HIGH VOLTAGE START−UP
The NCP1340 contains a multi−functional high voltage
(HV) pin. While the primary purpose of this pin is to reduce
standby power while maintaining a fast start−up time, it also
incorporates brownout detection and line removal detection.
The HV pin must be connected directly to the ac line in
order for the X2 discharge circuit to function correctly. Line
and neutral should be diode “ORed” before connecting to the
HV pin as shown in Figure 4. The diodes prevent the pin
voltage from going below ground. A resistor in series with
the pin should be used to protect the pin during EMC or surge
testing. A low value resistor should be used (<5 kW) to
reduce the voltage offset during start−up.
implements overload protection by limiting the
maximum time duration for operation during overload
conditions. The overload timer operates whenever the
maximum peak current is reached. In addition to this,
special circuitry is included to prevent operation in
CCM during extreme overloads, such as an output
short−circuit.
Maximum Frequency Clamp: The NCP1340 includes
a maximum frequency clamp. In all versions, the clamp
is available disabled or fixed at 110 kHz. In the 9−pin
versions, the clamp can be adjusted via an external
resistor from the FMAX Pin to ground. It can also be
disabled by pulling the FMAX pin above 4 V.
AC
CON
EMI
HV
Controller
Figure 4. High−Voltage Input Connection
Start−up and VCC Management
During start−up, the current source turns on and charges
the VCC capacitor with Istart2 (typically 6 mA). When Vcc
reaches VCC(on) (typically 16.0 V), the current source turns
off. If the input voltage is not high enough to ensure a proper
start−up (i.e. VHV has not reached VBO(start)), the controller
will not start. VCC then begins to fall because the controller
bias current is at ICC2 (typically 1 mA) and the auxiliary
supply voltage is not present. When VCC falls to VCC(off)
(typically 10.5 V), the current source turns back on and
charges VCC. This cycle repeats indefinitely until VHV
reaches VBO(start). Once this occurs, the current source
immediately turns on and charges VCC to VCC(on), at which
point the controller starts (see Figure 6).
When VCC is brought below VCC(inhibit), the start−up
current is reduced to Istart1 (typically 0.5 mA). This limits
power dissipation on the device in the event that the VCC pin
is shorted to ground. Once VCC rises back above VCC(inhibit),
the start−up current returns to Istart2.
Once VCC reaches VCC(on), the controller is enabled and
the controller bias current increases to ICC3 (typically
2.0 mA). However, the total bias current is greater than this
due to the gate charge of the external switching MOSFET.
The increase in ICC due to the MOSFET is calculated using
Equation 1.
DI CC + f sw @ Q G @ 10 −3
(eq. 1)
where DICC is the increase in milliamps, fsw is the switching
frequency in kilohertz and QG is the gate charge of the
external MOSFET in nanocoulombs.
CVCC must be sized such that a VCC voltage greater than
VCC(off) is maintained while the auxiliary supply voltage
increases during start−up. If CVCC is too small, VCC will fall
below VCC(off) and the controller will turn off before the
auxiliary winding supplies the IC. The total ICC current after
the controller is enabled (ICC3 plus DICC) must be
considered to correctly size CVCC.
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9
NCP1340
Figure 5. Start−up Circuitry Block Diagram
VHV
VBO(start)
VHV(MIN)
VCC
VCC(on)
VCC(off)
Start−up
Current = Istart2
Start−up
Current = Istart1
VCC(inhibit )
DRV
Figure 6. Start−up Timing
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10
tdelay (start )
NCP1340
DRIVER
The peak current level is clamped during the soft−start
phase. The setpoint is actually limited by a clamp level
ramping from 0 to 0.8 V within 4 ms.
In addition to the PWM comparator, a dedicated
comparator monitors the current sense voltage, and if it
reaches the maximum value, VILIM (typically 800 mV), the
gate driver is turned off and the overload timer is enabled.
This occurs even if the limit imposed by the feedback
voltage is higher than VILIM1. Due to the parasitic
capacitances of the MOSFET, a large voltage spike often
appears on the CS Pin at turn−on. To prevent this spike from
falsely triggering the current sense circuit, the current sense
signal is blanked for a short period of time, tLEB1 (typically
275 ns), by a leading edge blanking (LEB) circuit. Figure 7
shows the schematic of the current sense circuit.
The peak current is also limitied to a minimum level,
Vfreeze (0.2 V, typically). This results in higher efficiency at
light loads by increasing the minimum energy delivered per
switching cycle, while reducing the overall number of
switching cycles during light load.
The NCP1340 maximum supply voltage, VCC(MAX), is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
MOSFETs. The DRV voltage clamp, VDRV(high) is typically
12 V with a maximum limit of 14 V.
REGULATION CONTROL
Peak Current Control
The NCP1340 is a peak current−mode controller, thus the
FB voltage sets the peak current flowing in the transformer
and the MOSFET. This is achieved by sensing the MOSFET
current across a resistor and applying the resulting voltage
ramp to the non−inverting input of the PWM comparator
through the CS pin. The current limit threshold is set by
applying the FB voltage divided by KFB (typically 4) to the
inverting input of the PWM comparator. When the current
sense voltage ramp exceeds this threshold, the output driver
is turned off, however, the peak current is affected by several
functions (see Figure 7):
Figure 7. Peak Current Setpoint
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11
NCP1340
Zero Current Detection
As shown by Figure 12, a valley is detected once the ZCD
pin voltage falls below the demagnetization threshold,
VZCD(trig), typically 55 mV. The controller will either switch
once the valley is detected or increment the valley counter,
depending on the FB voltage.
The NCP1340 is a quasi−resonant (QR) flyback
controller. While the power switch turn−off is determined by
the peak current set by the feedback loop, the switch turn−on
is determined by the transformer demagnetization. The
demagnetization is detected by monitoring the transformer
auxiliary winding voltage.
Turning on the power switch once the transformer is
demagnetized has the benefit of reduced switching losses.
Once the transformer is demagnetized, the drain voltage
starts ringing at a frequency determined by the transformer
magnetizing inductance and the drain lump capacitance,
eventually settling at the input voltage. A QR flyback
controller takes advantage of the drain voltage ringing and
turns on the power switch at the drain voltage minimum or
“valley” to reduce switching losses and electromagnetic
interference (EMI).
Overpower Protection
The average bulk capacitor voltage of the QR flyback
varies with the RMS line voltage. Thus, the maximum
power capability at high line can be much higher than
desired. An integrated overpower protection (OPP) circuit
provides a relatively constant output power limit across the
input voltage on the bulk capacitor, Vbulk. Since it is a
high−voltage rail, directly measuring Vbulk will contribute
losses in the sensing network that will greatly impact the
standby power consumption. The NCP1340 OPP circuit
achieves this without the need for a high−voltage sensing
network, and is essentially lossless.
Figure 8. OPP Circuit Schematic
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12
VAUX (V)
NCP1340
⎛N
− ⎢ AUX . VBULK
⎝ NP
⎛
⎢
⎝
Figure 9. Auxiliary Winding Voltage
The ratio between RZCD and ROPPL is given by
Equation 5. It is obtained by combining Equations 3 and 4.
Since the auxiliary winding voltage during the power
switch on time is a reflection of the input voltage scaled by
the primary to auxiliary winding turns ratio, NP:AUX (see
Figure 9), OPP is achieved by scaling down reflected
voltage during the on−time and applying it to the ZCD pin
as a negative voltage, VOPP. The voltage is scaled down by
a resistor divider comprised of ROPPU and ROPPL. The
maximum internal current setpoint (VCS(OPP)) is simply the
sum of VOPP and the peak current sense threshold, VILIM1.
Figure 8 shows the schematic for the OPP circuit.
The adjusted peak current limit is calculated using
Equation 2. For example, a VOPP of −150 mV results in a
peak current limit of 650 mV in NCP1340.
V CS(OPP) + V OPP ) V ILIM1
V
R ZCD
* V F * V ZCD
+ AUX
R OPPL
V ZCD
A design example is shown below:
System Parameters:
V AUX + 18 V
V F + 0.6 V
N P:AUX + 0.18
The ratio between RZCD and ROPPL is calculated using
Equation 5 for a minimum VZCD of 8 V.
R ZCD
18 V * 0.6 V * 8 V
+
+ 1.2 kW
R OPPL
8V
(eq. 2)
To ensure optimal zero−crossing detection, a diode is
needed to bypass ROPPU during the off−time. Equation 3 is
used to calculate ROPPU and ROPPL.
N
R ZCD ) R OPPU
@ V bulk * V OPP
+ * P:AUX
R OPPL
V OPP
RZCD is arbitrarily set to 1 kW. ROPPL is also set to 1 kW
because the ratio between the resistors is close to 1.
The NCP1340 maximum overpower compensation or
peak current setpoint reduction is 31.25% for a VOPP of
−250 mV. We will use this value for the following example:
Substituting values in Equation 3 and solving for ROPPU
we obtain:
(eq. 3)
ROPPU is selected once a value is chosen for ROPPL.
ROPPL is selected large enough such that enough voltage is
available for the zero−crossing detection during the
off−time. It is recommended to have at least 8 V applied on
the ZCD pin for good detection. The maximum voltage is
internally clamped to VCC. The off−time voltage on the ZCD
Pin is given by Equation 4.
V ZCD +
R OPPL
@ ǒV AUX * V FǓ
R ZCD ) R OPPL
(eq. 5)
R ZCD ) R OPPU
0.18 @ 370 V * (−0.25 V)
+
+ 271
R OPPL
−0.25 V
R OPPU + 271 @ R OPPL * R ZCD
R OPPU + 271 @ 1 kW * 1 kW + 270 kW
(eq. 4)
For optimum performance over temperature, it is
recommended to keep ROPPL below 3 kW.
Where VAUX is the voltage across the auxiliary winding
and VF is the DOPP forward voltage drop.
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13
NCP1340
Soft−Start
in CCM for several cycles until the voltage on the ZCD pin
is high enough to prevent the timer from running. Therefore,
a longer timeout period, ttout1 (typically 100 ms), is used
during soft−start to prevent CCM operation.
Soft−start is achieved by ramping up an internal reference,
VSSTART, and comparing it to the current sense signal.
VSSTART ramps up from 0 V once the controller initially
powers up. The peak current setpoint is then limited by the
VSSTART ramp resulting in a gradual increase of the switch
current during start−up. The soft−start duration, tSSTART, is
typically 4 ms.
During startup, demagnetization phases are long and
difficult to detect since the auxiliary winding voltage is very
small. In this condition, the 6 ms steady−state timeout is
generally shorter than the inductor demagnetization period.
If it is used to restart a switching cycle, it can cause operation
Frequency Jittering
In order to help meet stringent EMI requirements, the
NCP1340 features frequency jittering to average the energy
peaks over the EMI frequency range. As shown in Figure 10,
the function consists of summing a 0 to 100 mV, 1.3 kHz
triangular wave (Vjitter) with the CS signal immediately
before the PWM comparator. This current acts to modulate
the on−time and hence the operation frequency.
Figure 10. Jitter Implementation
LIGHT LOAD MANAGEMENT
Since the jittering function modulates the peak current
level, the FB signal will attempt to compensate for this effect
in order to limit the output voltage ripple. Therefore, the
bandwidth of the feedback loop must be well below the jitter
frequency, or the jitter function will be filtered by the loop.
Due to the frozen peak current, the effect of the jittering
circuit will not be seen during frequency foldback mode.
Valley Lockout Operation
The operating frequency of a traditional QR flyback
controller is inversely proportional to the system load. In
other words, a load reduction increases the operating
frequency. A maximum frequency clamp can be useful to
limit the operating frequency range. However, when used by
itself, such an approach often causes instabilities since when
this clamp is active, the controller tends to jump (or hesitate)
between two valleys, thus generating audible noise.
Instead, the NCP1340 also incorporates a patented valley
lockout (VLO) circuitry to eliminate valley jumping. Once
a valley is selected, the controller stays locked in this valley
until the output power changes significantly. This technique
extends the QR mode operation over a wider output power
range while maintaining good efficiency and limiting the
maximum operating frequency.
Maximum Frequency Clamp
The NCP1340 includes a maximum frequency clamp. In
all versions, the clamp is available disabled or fixed at
110 kHz. In the 9−pin versions, the clamp can be adjusted
via an external resistor from the FMAX Pin to ground. It can
also be disabled by pulling the FMAX pin above 4 V.
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14
NCP1340
The operating valley (1st, 2nd, 3rd, 4th, 5th or 6th) is
determined by the FB voltage. An internal counter
increments each time a valley is detected by the ZCD/OPP
1x10
Fsw (Hz)
8x10
6x10
6th 5th 4th
5
2x10
2nd
1st
VCO
4 mode
4
6th
4x10
3rd
Pin. Figure 11 shows a typical frequency characteristic
obtainable at low line in a 65 W application.
5th
4th
3rd
2nd
1st
4
4
0
VCO
mode
0
20
40
60
Pout (W)
Figure 11. Valley Lockout Frequency vs. Output Power
When an “n” valley is asserted by the valley selection
circuitry, the controller is locked in this valley until the FB
voltage decreases to the lower threshold (“n+1” valley
activates) or increases to the “n valley threshold” + 600 mV
(“n−1” valley activates). The regulation loop adjusts the
peak current to deliver the necessary output power. Each
valley selection comparator features a 600 mV hysteresis
that helps stabilize operation despite the FB voltage swing
produced by the regulation loop.
Table 5. VALLEY FB THRESHOLDS (typical values)
FB Falling
1st
FB Rising
valley
1.400 V
2nd
valley
2.000 V
2nd to 3rd valley
1.200 V
3rd to 2nd valley
1.800 V
valley
1.100 V
4th
valley
1.700 V
4th to 5th valley
1.000 V
5th to 4th valley
1.600 V
0.900 V
6th
1.500 V
3rd
5th
to
to
to
2nd
4th
6th
valley
Valley Timeout
to
to
to
1st
3rd
5th
valley
operation lasts for a few cycles until the voltage on the ZCD
pin is high enough to detect the valleys. A longer timeout
period, ttout1, (typically 100 ms) is set during soft−start to
limit CCM operation.
In VLO operation, the number of timeout periods are
counted instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For example, if
the FB voltage sets VLO mode to turn on at the fifth valley,
and the ZCD ringing is damped such that the ZCD circuit is
only able to detect:
• Valleys 1 to 4: the circuit generates a DRV pulse 6 ms
(steady−state timeout delay) after the 4th valley
detection.
• Valleys 1 to 3: the timeout delay must run twice, and
the circuit generates a DRV pulse 12 ms after the 3rd
valley detection.
In case of extremely damped oscillations, the ZCD
comparator may not be able to detect the valleys. In this
condition, drive pulses will stop while the controller waits
for the next valley or ZCD event. The NCP1340 ensures
continued operation by incorporating a maximum timeout
period after the last demagnetization detection. The timeout
signal acts as a substitute for the ZCD signal to the valley
counter. Figure 12 shows the valley timeout circuit
schematic. The steady state timeout period, ttout2, is set at 6
ms (typical) to limit the frequency step.
During startup, the voltage offset added by the OPP diode,
DOPP, prevents the ZCD Comparator from accurately
detecting the valleys. In this condition, the steady state
timeout period will be shorter than the inductor
demagnetization period causing CCM operation. CCM
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15
NCP1340
Figure 12. Valley Timeout Circuitry
Frequency Foldback
As the output load decreases (FB voltage decreases), the
valleys are incremented from 1 to 6. When the sixth valley
is reached, if the FB voltage further decreases to 0.8 V, the
peak current setpoint becomes internally frozen to Vfreeze
(0.2 V typically), and the controller enters frequency
foldback mode (FF). During this mode, the controller
regulates the power delivery by modulating the switching
frequency.
In frequency foldback mode, the controller reduces the
switching frequency by adding dead−time after the 6th
valley is detected. This dead−time increases as the FB
voltage decreases. There is no discontinuity when the
system transitions from VLO to FF and the frequency
smoothly reduces as FB decreases.
The dead−time circuit is designed to add 0 ms dead−time
when VFB = 0.8 V and linearly increases the total dead−time
to tDT(3) (32 ms minimum) as VFB falls down to 0.4 V. The
minimum frequency clamp prevents the switching
frequency from dropping below 25 kHz to eliminate the risk
of audible noise.
Figure 13 summarizes the VLO to FF operation with
respect to the FB voltage.
Operating Mode
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
V
decreases
FB
FF
V FB increases
Valley 6
Valley 5
Valley 4
Fault !
Valley 3
Valley 2
Valley 1
0.8
0.9
1.0
1.1
1.2
1.4
1.5
1.6
1.7
1.8
Figure 13. Valley Lockout Thresholds
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16
2.0
3.2
V
(V)
FB
NCP1340
Minimum Frequency Clamp and Skip Mode
as the currnet drive pulses ends – it does not stop
immediately.
Once switching stops, FB will rise. As soon as FB crosses
the skip−exit threshold, drive pulses will resume, but the
controller remains in burst mode. At this point, a 1250 ms
(min) timer, tquiet, is started together with a count−to−3
counter. The next time the FB voltage drops below the
skip−in threshold, drive pulses stop at the end of the current
pulse as long as 3 drive pulses have been counted (if not, they
do not stop until the end of the 3rd pulse). They are not
allowed to start again until the timer expires, even if the
skip−exit threshold is reached first. It is important to note
that the timer will not force the next cycle to begin – i.e. if
the natural skip frequency is such that skip−exit is reached
after the timer expires, the drive pulses will wait for the
skip−exit threshold.
This means that during no−load, there will be a minimum
of 3 drive pulses, and the burst−cycle period will likely be
much longer than 1250 ms. This operation helps to improve
efficiency at no−load conditions.
In order to exit burst mode, the FB voltage must rise higher
than 1 V. If this occurs before tquiet expires, the drive pulses
will resume immediately – i.e. the controller won’t wait for
the timer to expire. Figure 14 provides an example of how
Quiet−Skip works, while Figure 15 shows a possible
implementation.
As mentioned previously, the circuit prevents the
switching frequency from dropping below fMIN (25 kHz
typical). When the switching cycle would be longer than
40 ms, the circuit forces a new switching cycle. However, the
fMIN clamp cannot generate a DRV pulse until the
demagnetization is completed. In other words, it will not
cause operation in CCM.
Since the NCP1340 forces a minimum peak current and a
minimum frequency, the power delivery cannot be
continuously controlled down to zero. Instead, the circuit
starts skipping pulses when the FB voltage drops below the
skip level, Vskip, and recovers operation when VFB exceeds
Vskip + Vskip(HYS). This skip−mode method provides an
efficient method of control during light loads.
Quiet−Skip
To further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audible
range by limiting it to a maximum of 800 Hz. This is
achieved via a timer (tquiet) that is activated during
Quiet−Skip. The start of the next burst cycle is prevented
until this timer has expired.
As the output power decreases, the switching frequency
decreases. Once it hits 25 kHz, the skip−in threshold is
reached and burst mode is entered − switching stops as soon
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17
NCP1340
Figure 14. Quiet−Skip Timing Diagram
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18
NCP1340
Figure 15. Quiet−Skip Basic Implementation
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NCP1340
FAULT MANAGEMENT
external latch input. When the NCP1340 detects a latching
fault, the driver is immediately disabled. The operation
during a latching fault is identical to that of a non−latching
fault except the controller will not attempt to restart at the
next VCC(on), even if the fault is removed. In order to clear
the latch and resume normal operation, VCC must first be
allowed to drop below VCC(reset) or a line removal event
must be detected. This operation is shown in Figure 16.
The NCP1340 contains three separate fault modes.
Depending on the type of fault, the device will either latch
off, restart when the fault is removed, or resume operation
after the auto−recovery timer expires.
Latching Faults
Some faults will cause the NCP1340 to latch off. These
include the abnormal OCP (AOCP), VCC OVP, and the
Fault
Fault
Applied
Fault
Removed
time
V CC
V CC (on)
V CC (off)
time
FDRV
time
I HV
Istart 2
I start (off)
time
Figure 16. Operation During Latching Fault
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NCP1340
Non−Latching Faults
re−enabled when VCC reaches VCC(on) according to the
initial power−on sequence, provided VHV is above
VBO(start). This operation is shown in Figure 17. When VHV
is reaches VBO(start), VCC immediately charges to VCC(on).
If VCC is already above VCC(on) when the fault is removed,
the controller will start immediately as long as VHV is above
VBO(start).
When the NCP1340 detects a non−latching fault
(brownout or thermal shutdown), the drivers are disabled,
and VCC falls towards VCC(off) due to the IC internal current
consumption. Once VCC reaches VCC(off), the HV current
source turns on and CVCC begins to charge towards VCC(on).
When VCC, reaches VCC(on), the cycle repeats until the fault
is removed. Once the fault is removed, the NCP1340 is
Fault
Fault
Applied
Fault
Removed
Waits for next
V CC(on) before
starting
VCC
time
V CC (on )
V CC (off )
time
FDRV
time
IHV
Istart 2
Istart (off)
time
Figure 17. Operation During Non−Latching Fault
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NCP1340
Auto−recovery Timer Faults
running, the HV current source turns on and off to maintain
Vcc between Vcc(off) and Vcc(on). Once the auto−recovery
timer expires, the controller will attempt to start normally at
the next VCC(on) provided VHV is above VBO(start). This
operation is shown in Figure 18.
Some faults faults cause the NCP1340 auto−recovery
timer to run. If an auto−recovery fault is detected, the gate
drive is disabled and the auto−recovery timer, tautorec
(typically 1.2 s), starts. While the auto−recovery timer is
Fault
Applied
Fault
Removed
Fault
time
VCC
VCC(on)
VCC(off)
Restarts
At V CC (on )
( new burst
cycle if Fault
still present
)
DRV
time
Controller
stops
Autorecovery
Timer
time
1.2 s
t restart
Figure 18. Operation During Auto−Recovery Fault
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NCP1340
PROTECTION FEATURES
Brownout Protection
Figure 19 shows the brownout detector waveforms during
a brownout.
When a brownout is detected, the controller stops
switching and enters non−latching fault mode (see
Figure 17). The HV current source alternatively turns on and
off to maintain VCC between VCC(on) and VCC(off) until the
input voltage is back above VBO(start).
A timer is enabled once VHV drops below its disable
threshold, VBO(stop) (typically 99 V). The controller is
disabled if VHV doesn’t exceed VBO(stop) before the
brownout timer, tBO (typically 54 ms), expires. The timer is
set long enough to ignore a two cycle dropout. The timer
starts counting once VHV drops below VBO(stop).
V HV
V BO (start )
V BO (stop )
time
Brownout
Timer
Brownout
detected
Starts
Charging
Immediately
V CC
V CC (on)
Fault
Cleared
Restarts at
next V CC(on)
time
V CC (off )
tdelay (start )
time
DRV
Figure 19. Operation During Brownout
Line Removal Detection and X2 Capacitor Discharge
time
discharge circuitry. A novel approach is used to reconfigure
the high voltage startup circuit to discharge the input filter
capacitors upon removal of the ac line voltage. The line
removal detection circuitry is always active to ensure safety
compliance.
The line removal is detected by digitally sampling the
voltage present at the HV pin, and monitoring the slope.
A timer, tline(removal) (typically 100 ms), is used to detect
when the slope of the input signal is negative or below the
resolution level. The timer is reset any time a positive slope
Safety agency standards require the input filter capacitors
to be discharged once the ac line voltage is removed. A
resistor network is the most common method to meet this
requirement. Unfortunately, the resistor network consumes
power across all operating modes and it is a major
contributor of input power losses during light−load and
no−load conditions.
The NCP1340 eliminates the need for external discharge
resistors by integrating active input filter capacitor
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23
NCP1340
is detected. Once the timer expires, a line removal condition
is acknowledged initiating an X2 capacitor discharge cycle,
and the controller is disabled.
If VCC is above VCC(on), it is first discharged to VCC(on).
A second timer, tline(discharge) (typically 32 ms), is used for
the time limiting of the discharge phase to protect the device
against overheating. Once the discharge phase is complete,
tline(discharge) is reused while the device checks to see if the
line voltage is reapplied. During the discharge phase, if VCC
drops to VCC(on), it is quickly recharged to VCC(X2_reg). The
discharging process is cyclic and continues until the ac line
is detected again or the voltage across the X2 capacitor is
lower than VHV(discharge) (30 V maximum). This feature
allows the device to discharge large X2 capacitors in the
input line filter to a safe level.
It is important to note that the HV pin cannot be
connected to any dc voltage due to this feature, i.e.
directly to the bulk capacitor.
X2 Capacitor
Discharge
VHV
VBO(start )
VBO(stop)
X2 Capacitor
Discharge
AC Line Unplug
VHV(discharge )
time
AC
Timer
Starts
Timer
tline(removal )
AC
Timer
Restarts
AC
Timer
Expires
No AC Detection
tline(discharge /detect )
tline(removal )
DRV
tline(discharge )
tline(detect )
X2 Discharge
X2 Discharge
Current
Device is stopped
Istart 2
ICC
ICC(discharge )
0
ICC3
Istart 2
VCC
VCC(X2_reg)
VCC(on)
Figure 20. Line Removal Timing
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24
tline(discharge )
X2 Discharge
time
NCP1340
X2 Capacitor
Discharge
VHV
VBO(start )
VBO(stop )
AC Line Unplug
VHV(discharge )
AC
Timer
Starts
Timer
tline (removal )
AC
Timer
Expires
AC
Timer
Restarts
time
AC Detected
tline(discharge /detect )
time
X2 Discharge
Device is stopped
X2 Discharge
Current
time
tline (discharge )
tline (removal )
DRV
tdelay (start )
Istart 2
time
ICC
ICC(discharge )
0
ICC3
Istart 2
time
VCC
VCC(X2_reg)
VCC(on)
Figure 21. Line Removal Timing with AC Reapplied
the lower fault threshold, VFault(OTP_in) (typically 0.4 V).
The lower threshold is normally used for detecting an
overtemperature fault. The controller operates normally
while the Fault pin voltage is maintained within the upper
and lower fault thresholds. Figure 22 shows the architecture
of the Fault input.
The Fault input signal is filtered to prevent noise from
triggering the fault detectors. Upper and lower fault detector
blanking delays, tdelay(OVP) and tdelay(OTP),are both
typically 30 ms. A fault is detected if the fault condition is
asserted for a period longer than the blanking delay.
An over temperature protection block monitors the
junction temperature during the discharge process to avoid
thermal runaway, in particular during open/short pins safety
tests. Please note that the X2 discharge capability is also
active at all times, including off−mode and before the
controller actually starts to pulse (e.g. if the user unplugs the
converter during the start−up sequence).
Dedicated Fault Input
The NCP1340 includes a dedicated fault input accessible
via the Fault pin (8−pin and 9−pin versions only). The
controller can be latched by pulling up the pin above the
upper fault threshold, VFault(OVP) (typically 3.0 V). The
controller is disabled if the Fault pin voltage is pulled below
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25
NCP1340
OVP
voltage drop across the thermistor. The resistance of the
NTC thermistor decreases at higher temperatures resulting
in a lower voltage across the thermistor. The controller
detects a fault once the thermistor voltage drops below
VFault(OTP_in).
The controller bias current is reduced during power up by
disabling most of the circuit blocks including IFault(OTP).
This current source is enabled once VCC reaches VCC(on). A
filter capacitor is typically connected between the Fault and
GND pins. This will result in a delay before VFault reaches
its steady state value once IFault(OTP) is enabled. Therefore,
the lower fault comparator (i.e. overtemperature detection)
is ignored during soft−start.
Version A latches off the controller after an
overtemperature fault is detected according to Figure 16. In
Version B, the controller is re−enabled once the fault is
removed such that VFault increases above VFault(OTP_out),
the auto−recovery timer expires, and VCC reaches VCC(on)
as shown in Figure 18.
An active clamp prevents the Fault pin voltage from
reaching the upper latch threshold if the pin is open. To reach
the upper threshold, the external pull−up current has to be
higher than the pull−down capability of the clamp (set by
RFault(clamp) at VFault(clamp)), i.e., approximately 1 mA.
The upper fault threshold is intended to be used for an
overvoltage fault using a zener diode and a resistor in series
from the auxiliary winding voltage. The controller is latched
once VFault exceeds VFault(OVP).
Once the controller is latched, it follows the behavior of
a latching fault according to Figure 16 and is only reset if
VCC is reduced to VCC(reset), or X2 discharge is activated. In
the typical application these conditions occur only if the ac
voltage is removed from the system.
OTP
The lower fault threshold is intended to be used to detect
an overtemperature fault using an NTC thermistor. A pull up
current source, IFault(OTP) (typically 45.5 mA), generates a
Figure 22. Fault Pin Internal Schematic
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26
NCP1340
• The controller latches off (version A) or
• Enters a safe, low duty−ratio auto−recovery mode
Overload Protection
The overload timer integrates the duration of the overload
fault. That is, the timer count increases while the fault is
present and reduces its count once it is removed. The
overload timer duration, tOVLD, is typically 160 ms. When
the overload timer expires, the controller detects an overload
condition does one of the following:
(version B).
Figure 23 shows the overload circuit schematic, while
Figure 24 and Figure 25 show operating waveforms for
latched and auto−recovery overload conditions.
Figure 23. Overload Circuitry
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27
NCP1340
Fault
Latch
Event
Latch
time
V CC
V CC(on)
V CC(off)
time
DRV
time
I HV
Istart2
IHV(off)
time
Figure 24. Latched Overload Operation
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28
NCP1340
Output Load
Overcurrent
applied
Fault
disappears
Max Load
time
Fault Flag
Fault
timer
starts
time
V CC
V CC(on)
V CC(off)
Restarts
At V CC ( on
( new burst
cycle if Fault
still present
DRV
)
time
)
Controller
stops
time
Fault timer
160 ms
t OVLD
t restart
Figure 25. Auto−Recovery Overload Operation
www.onsemi.com
29
t delay
time
( start
)
NCP1340
Abnormal Overcurrent Protection (AOCP)
core. Due to the valley timeout feature of the controller, the
flux level will quickly walk up until the core saturates. This
can cause excessive stress on the primary MOSFET and
secondary diode. This is not a problem for the NCP1340,
however, because the valley timeout timer is disabled while
the ZCD Pin voltage is above the arming threshold. Since the
leakage energy is high enough to arm the ZCD trigger, the
timeout timer is disabled and the next drive pulse is delayed
until demagnetization occurs.
Under some severe fault conditions, like a winding
short−circuit, the switch current can increase very rapidly
during the on−time. The current sense signal significantly
exceeds VILIM1, but because the current sense signal is
blanked by the LEB circuit during the switch turn−on, the
power switch current can become huge and cause severe
system damage.
The NCP1340 protects against this fault by adding an
additional comparator for Abnormal Overcurrent Fault
detection. The current sense signal is blanked with a shorter
LEB duration, tLEB2, typically 125 ns, before applying it to
the Abnormal Overcurrent Fault Comparator. The voltage
threshold of the comparator, VILIM2, typically 1.2 V, is set
50% higher than VILIM1, to avoid interference with normal
operation. Four consecutive Abnormal Overcurrent faults
cause the controller to enter latch mode. The count to 4
provides noise immunity during surge testing. The counter
is reset each time a DRV pulse occurs without activating the
Fault Overcurrent Comparator.
VCC Overvoltage Protection
An additional comparator on the VCC pin monitors the
VCC voltage. If VCC exceeds VCC(OVP), the gate drive is
disabled and the NCP1340 follows the operation of a
latching fault (see Figure 16).
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the controller. The controller is
disabled if the junction temperature exceeds the thermal
shutdown threshold, TSHDN (typically 140°C). When a
thermal shutdown fault is detected, the controller enters a
non−latching fault mode as depicted in Figure 17. The
controller restarts at the next VCC(on) once the junction
temperature drops below below TSHDN by the thermal
shutdown hysteresis, TSHDN(HYS), typically 40°C.
The thermal shutdown is also cleared if VCC drops below
VCC(reset), or a line removal fault is detected. A new power
up sequence commences at the next VCC(on) once all the
faults are removed.
Current Sense Pin Failure Protection
A 1 mA (typically) pull−up current source, ICS, pulls up the
CS pin to disable the controller if the pin is left open.
Additionally, the maximum on−time, ton(MAX) (32 ms
typically), prevents the MOSFET from staying on
permanently if the CS Pin is shorted to GND.
Output Short Circuit Protection
During an output short−circuit, there is not enough
voltage across the secondary winding to demagnetize the
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30
NCP1340
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
31
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1340
PACKAGE DIMENSIONS
SOIC−9 NB
CASE 751BP
ISSUE A
2X
0.10 C A-B
D
D
A
0.20 C
2X
0.10 C A-B
4 TIPS
10
F
6
H
E
1
5
0.20 C
9X
B
5 TIPS
L2
b
0.25
A3
L
C
SEATING
PLANE
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DETERMINED AT DATUM F.
5. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM F.
6. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
C A-B D
M
TOP VIEW
9X
h
X 45 _
0.10 C
0.10 C
M
A
A1
e
C
DETAIL A
SEATING
PLANE
END VIEW
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
H
h
L
L2
M
MILLIMETERS
MIN
MAX
1.25
1.75
0.10
0.25
0.17
0.25
0.31
0.51
4.80
5.00
3.80
4.00
1.00 BSC
5.80
6.20
0.37 REF
0.40
1.27
0.25 BSC
0_
8_
RECOMMENDED
SOLDERING FOOTPRINT*
9X
1.00
PITCH
0.58
6.50
9X
1.18
1
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NCP1340/D