21095K.book Page 1 Wednesday, December 5, 2012 2:28 PM Not recommended for new designs – Please use 24LCS21A. 24LC21 1K 2.5V Dual Mode I2C™ Serial EEPROM Features: PDIP 1 8 VCC NC 2 7 VCLK NC 3 6 SCL VSS 4 5 SDA NC 1 8 VCC NC 2 7 VCLK NC 3 5 SCL VSS 4 5 SDA SOIC 24LC21 Description: The Microchip Technology Inc. 24LC21 is a 128 x 8 bit Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-only mode and Bidirectional mode. Upon power-up, the device will be in the Transmit-only mode, sending a serial bit stream of the entire memory array contents, clocked by the VCLK pin. A valid high-to-low transition on the SCL pin will cause the device to enter the Bidirectional mode, with byte selectable read/write capability of the memory array. The 24LC21 is available in a standard 8-pin PDIP and SOIC package, in both commercial and industrial temperature ranges. NC 24LC21 • Single supply with operation down to 2.5V • Completely implements DDC1™/DDC2™ interface for monitor identification • Low-power CMOS technology: - 1 mA active current typical - 10 A standby current typical at 5.5V • 2-wire serial interface bus, I2C™ compatible • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 8 bytes • 100 kHz (2.5V) and 400 kHz (5V) compatibility • Factory programming (QTP) available • 1,000,000 erase/write cycles ensured • Data retention > 200 years • 8-pin PDIP and SOIC package • Available for extended temperature ranges Commercial (C): 0°C to +70°C Industrial (I): -40°C to +85°C Package Types Block Diagram VCLK HV Generator I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches SDA SCL YDEC VCC VSS 1994-2012 Microchip Technology Inc. Sense Amp R/W Control DS21095K-page 1 21095K.book Page 2 Wednesday, December 5, 2012 2:28 PM 24LC21 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C Soldering temperature of leads (10 seconds) .......................................................................................................+300°C ESD protection on all pins 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Parameter SCL and SDA pins: High-level input voltage Low-level input voltage Input levels on VCLK pin: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current Note 1: 2: VCC = +2.5V to 5.5V Commercial (C): TA = 0°C to +70°C Industrial (I): TA = -40°C to +85°C Symbol Min Max Units Conditions VIH VIL .7 VCC — — .3 VCC V V — — VIH VIL VHYS VOL1 VOL2 ILI ILO CIN, COUT 2.0 — .05 VCC — — -10 -10 — .8 .2 VCC — .4 .6 10 10 10 V V V V V A A pF ICC Write ICC Read ICCS — — — — 3 1 30 100 mA mA A A VCC 2.7V (Note 1) VCC < 2.7V (Note 1) (Note 1) IOL = 3 mA, VCC = 2.5V (Note 1) IOL = 6 mA, VCC = 2.5V VIN = .1V to VCC VOUT = .1V to VCC VCC = 5.0V (Note1), TA = 25C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 3.0V, SDA = SCL = VCC VCC = 5.5V, SDA = SCL = VCC (Note 2) This parameter is periodically sampled and not 100% tested. VLCK must be grounded. DS21095K-page 2 1994-2012 Microchip Technology Inc. 21095K.book Page 3 Wednesday, December 5, 2012 2:28 PM 24LC21 TABLE 1-2: AC CHARACTERISTICS Standard Mode Parameter Symbol Vcc= 4.5 - 5.5V Fast Mode Min Max Min Max Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns Start condition setup time TSU:STA 4700 — 600 — ns Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns — 250 250 ns — 50 20 + .1 CB — — — — (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated Start condition (Note 2) — — (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF 50 ns (Note 3) — 10 — 10 ms Byte or Page mode — 4000 4700 — 0 2000 — — 500 — — 600 1300 — 0 1000 — — 500 — ns ns ns ns ns — — — — — 1M — 1M — cycles Output fall time from VIH TOF min. to VIL max. Input filter spike suppresTSP sion (SDA and SCL pins) Write cycle time TWR Transmit-only Mode Parameters Output valid from VCLK TVAA VCLK high time TVHIGH VCLK low time TVLOW Mode transition time TVHZ Transmit-only power-up TVPU time Endurance — Note 1: 2: 3: 4: 25°C, VCC = 5.0V, Block mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise and spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com 1994-2012 Microchip Technology Inc. DS21095K-page 3 21095K.book Page 4 Wednesday, December 5, 2012 2:28 PM 24LC21 2.0 FUNCTIONAL DESCRIPTION The 24LC21 operates in two modes, the Transmit-only mode and the Bidirectional mode. There is a separate two-wire protocol to support each mode, each having a separate clock input and sharing a common data line (SDA). The device enters the Transmit-only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode. The only way to switch the device back to the Transmit-only mode is to remove power from the device. 2.1 Transmit-only Mode The device will power-up in the Transmit-only mode. This mode supports a unidirectional two-wire protocol for transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Transmit-only mode (see Initialization Procedure, below). In this mode, data is trans- FIGURE 2-1: mitted on the SDA pin in 8-bit bytes, each followed by a ninth, null bit (see Figure 2-1). The clock source for the Transmit-only mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The Bidirectional mode Clock (SCL) pin must be held high for the device to remain in the Transmit-only mode. 2.2 Initialization Procedure After VCC has stabilized, the device will be in the Transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit of a byte. The device will power-up at an indeterminate byte address. (Figure 2-2). TRANSMIT-ONLY MODE SCL TVAA TVAA SDA Null Bit Bit 1 (LSB) Bit 1 (MSB) Bit 7 VCLK TVHIGH FIGURE 2-2: TVLOW DEVICE INITIALIZATION VCC SCL SDA TVAA High-impedance for 9 clock cycles TVAA Bit 8 Bit 7 TVPU VCLK DS21095K-page 4 1 2 8 9 10 11 1994-2012 Microchip Technology Inc. 21095K.book Page 5 Wednesday, December 5, 2012 2:28 PM 24LC21 3.0 BIDIRECTIONAL MODE 3.1 The 24LC21 can be switched into the Bidirectional mode (see Figure 3-1) by applying a valid high-to-low transition on the Bidirectional mode clock (SCL). When the device has been switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire bidirectional data transmission protocol. In this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. The bus must be controlled by a master device that generates the Bidirectional mode clock (SCL), controls access to the bus and generates the Start and Stop conditions, while the 24LC21 acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Bidirectional Mode Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (see Figure 3-2). 3.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 3.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 3-1: MODE TRANSITION Transmit-only mode Bidirectional mode SCL TVHZ SDA VCLK FIGURE 3-2: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA 1994-2012 Microchip Technology Inc. Data Allowed to Change Stop Condition DS21095K-page 5 21095K.book Page 6 Wednesday, December 5, 2012 2:28 PM 24LC21 3.1.4 DATA VALID (D) 3.1.5 The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Note: Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first in first out fashion. FIGURE 3-3: ACKNOWLEDGE The 24LC21 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition. BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA Start FIGURE 3-4: Stop BUS TIMING DATA TR TF THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TAA THD:STA TAA TBUF SDA OUT DS21095K-page 6 1994-2012 Microchip Technology Inc. 21095K.book Page 7 Wednesday, December 5, 2012 2:28 PM 24LC21 3.1.6 SLAVE ADDRESS After generating a Start condition, the bus master transmits the slave address consisting of a 7-bit device code ‘1010’ for the 24LC21, followed by three “don’t care” bits. The eighth bit of slave address determines if the master device wants to read or write to the 24LC21 (Figure 3-5). The 24LC21 monitors the bus for its corresponding slave address all the time. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Control Code Chip Select R/W Read 1010 xxx 1 Write 1010 xxx 0 FIGURE 3-5: CONTROL BYTE ALLOCATION Start Read/Write SLAVE ADDRESS R/W A 4.0 WRITE OPERATION 4.1 Byte Write Following the Start signal from the master, the slave address (4 bits), the “don’t care” bits (3 bits) and the R/W bit which is a logic low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC21. After receiving another Acknowledge signal from the 24LC21 the master device will transmit the data word to be written into the addressed memory location. The 24LC21 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24LC21 will not generate Acknowledge signals (Figure 4-1). It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. 4.2 1 0 1 0 x x Page Write x The write control byte, word address and the first data byte are transmitted to the 24LC21 in the same way as in a byte write. But instead of generating a Stop condition the master transmits up to eight data bytes to the 24LC21, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a Stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains constant. If the master should transmit more than eight words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-3). 1994-2012 Microchip Technology Inc. DS21095K-page 7 21095K.book Page 8 Wednesday, December 5, 2012 2:28 PM 24LC21 It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. FIGURE 4-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S Control Byte Word Address S T O P Data P BUS ACTIVITY A C K A C K A C K VCLK FIGURE 4-2: BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S BUS ACTIVITY Control Byte Word Address S T O P Data P A C K A C K A C K VCLK DS21095K-page 8 1994-2012 Microchip Technology Inc. 21095K.book Page 9 Wednesday, December 5, 2012 2:28 PM 24LC21 FIGURE 4-3: PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S Word Address Control Byte BUS ACTIVITY Data (n + 1) Data (n) S T O P Data (n + 15) P A C K A C K A C K A C K A C K VCLK 1994-2012 Microchip Technology Inc. DS21095K-page 9 21095K.book Page 10 Wednesday, December 5, 2012 2:28 PM 24LC21 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for the flow diagram. FIGURE 5-1: 6.0 WRITE PROTECTION When using the 24LC21 in the Bidirectional mode, the VCLK pin operates as the write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array. Connecting the VCLK pin to VSS would allow the 24LC21 to operate as a serial ROM, although this configuration would prevent using the device in the Transmit-only mode. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS21095K-page 10 1994-2012 Microchip Technology Inc. 21095K.book Page 11 Wednesday, December 5, 2012 2:28 PM 24LC21 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read except that after the 24LC21 transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24LC21 to transmit the next sequentially addressed 8-bit word (see Figure 7-3). 7.1 To provide sequential reads the 24LC21 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. Current Address Read The 24LC21 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the 24LC21 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21 discontinues transmission (Figure 7-1). 7.2 Random Read 7.4 Noise Protection The 24LC21 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24LC21 as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a ‘1’. The 24LC21 will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24LC21 discontinues transmission (Figure 7-2). FIGURE 7-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY 1994-2012 Microchip Technology Inc. S T A R T Control Byte S T O P Data (n) S P A C K N O A C K DS21095K-page 11 21095K.book Page 12 Wednesday, December 5, 2012 2:28 PM 24LC21 FIGURE 7-2: RANDOM READ S T BUS ACTIVITY A MASTER R T Control Byte S T A R T Word Address S SDA LINE Control Byte S T O P Data (n) P S A C K BUS ACTIVITY A C K A C K N O A C K FIGURE 7-3: BUS ACTIVITY MASTER SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + X) P SDA LINE BUS ACTIVITY A C K A C K A C K A C K N O A C K DS21095K-page 12 1994-2012 Microchip Technology Inc. 21095K.book Page 13 Wednesday, December 5, 2012 2:28 PM 24LC21 8.0 PIN DESCRIPTIONS TABLE 8-1: 8.1 PIN FUNCTION TABLE Name Function VSS SDA SCL VCLK VCC NC Ground Serial Address/Data I/O Serial Clock (Bidirectional mode) Serial Clock (Transmit-only mode) +2.5V to 5.5V Power Supply No Connection SDA This pin is used to transfer addresses and data into and out of the device, when the device is in the Bidirectional mode. In the Transmit-only mode, which only allows data to be read from the device, data is also transferred on the SDA pin. This pin is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10K for 100 kHz, 2K for 400 kHz). 8.2 SCL This pin is the clock input for the Bidirectional mode, and is used to synchronize data transfer to and from the device. It is also used as the signaling input to switch the device from the Transmit-only mode to the Bidirectional mode. It must remain high for the chip to continue operation in the Transmit-only mode. 8.3 VCLK This pin is the clock input for the Transmit-only mode. In the Transmit-only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability. For normal data transfer in the Bidirectional mode, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 1994-2012 Microchip Technology Inc. DS21095K-page 13 21095K.book Page 14 Wednesday, December 5, 2012 2:28 PM 24LC21 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP Example XXXXXXXX XXXXXNNN YYWW 24LC21 017 0410 8-Lead SOIC (.150”) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21095K-page 14 Example 24LC21 /SN0410 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 1994-2012 Microchip Technology Inc. 21095K.book Page 15 Wednesday, December 5, 2012 2:28 PM 24LC21 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 1994-2012 Microchip Technology Inc. DS21095K-page 15 21095K.book Page 16 Wednesday, December 5, 2012 2:28 PM 24LC21 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21095K-page 16 1994-2012 Microchip Technology Inc. 21095K.book Page 17 Wednesday, December 5, 2012 2:28 PM 24LC21 APPENDIX A: REVISION HISTORY Revision J Added note to page 1 header (Not recommended for new designs). Added Section 9.0: Package Marking Information. Added On-line Support page. Updated document format. Revision K Added a note to each package outline drawing. 1994-2012 Microchip Technology Inc. DS21095K-page 17 21095K.book Page 18 Wednesday, December 5, 2012 2:28 PM 24LC21 NOTES: DS21095K-page 18 1994-2012 Microchip Technology Inc. 21095K.book Page 19 Wednesday, December 5, 2012 2:28 PM 24LC21 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 1994-2012 Microchip Technology Inc. DS21095K-page 19 21095K.book Page 20 Wednesday, December 5, 2012 2:28 PM 24LC21 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 24LC21 Literature Number: DS21095K Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21095K-page 20 1994-2012 Microchip Technology Inc. 21095K.book Page 21 Wednesday, December 5, 2012 2:28 PM 24LC21 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device 24LC21: Dual Mode I2C™ Serial EEPROM 24LC21T: Dual Mode I2C™ Serial EEPROM (Tape and Reel) Temperature Range Blank I = 0C to = -40C to Package P SN = = +70C +85C Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1994-2012 Microchip Technology Inc. DS21095K-page 21 21095K.book Page 22 Wednesday, December 5, 2012 2:28 PM 24LC21 NOTES: DS21095K-page 22 1994-2012 Microchip Technology Inc. 21095K.book Page 23 Wednesday, December 5, 2012 2:28 PM Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 1994-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620767306 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 1994-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21095K-page 23 21095K.book Page 24 Wednesday, December 5, 2012 2:28 PM Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7828 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS21095K-page 24 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 10/26/12 1994-2012 Microchip Technology Inc.